Group iii nitride transistor structure with reduced leakage current and method of fabrication

Abstract

The application discloses a III-nitride transistor structure capable of reducing leakage current and a manufacturing method thereof. The III-nitride transistor structure comprises a first heterojunction and a second heterojunction which are arranged in a stack mode, and the first heterojunction and the second heterojunction are electrically isolated by a high-resistance material and / or an insertion layer; a first electrode, a second electrode and a first gate electrode matched with the first heterojunction, a third semiconductor is arranged between the first gate electrode and the first heterojunction, and the first gate electrode is electrically connected with the first electrode; a source electrode, a drain electrode and a second gate electrode matched with the second heterojunction, the source electrode and the drain electrode are electrically connected with the first gate electrode and the second electrode respectively, and a sixth semiconductor is arranged between the second gate electrode and the second heterojunction. The III-nitride transistor structure provided by the application can effectively reduce the reverse conduction voltage of a device and reduce the area of the device.

Description

Technical Field

[0001] This invention relates to a transistor structure, and more particularly to a group III nitride transistor structure that can reduce leakage current and its fabrication method, belonging to the field of semiconductor technology. Background Technology

[0002] Group III nitrides (such as gallium nitride, GaN) possess excellent material properties, including a large bandgap, high breakdown field strength, high electron mobility, and high electron saturation drift velocity, making them highly suitable for next-generation power electronic systems. In power electronic systems such as synchronous buck or boost converters, transistor devices inevitably operate in reverse conduction mode. For GaN-based high electron mobility transistors (HEMTs), the lack of a body diode results in fast reverse recovery, but the source-to-drain voltage drop depends on the gate bias, leading to higher values ​​compared to Si-based and SiC-based power devices and resulting in power losses. Therefore, improving the reverse conduction capability of GaN HEMTs is crucial for further reducing power losses in GaN-based power electronic systems.

[0003] Several methods have been reported, such as fabricating Schottky diodes (SBDs) on a Si-based GaN HEMT structure, where the drain of the HEMT is shared with the cathode of the SBD. However, Si-based SBDs are limited by material properties and cannot fully utilize the advantages of GaN, leading to reliability issues. Cross-structures of HEMT and SBD or lateral rectifiers are effective, but increased area seems unavoidable. Furthermore, the source-drain voltage drop required for reverse conduction depends on the gate bias and is relatively large, resulting in high power consumption. Lateral integration of SBDs typically leads to increased leakage current or increased forward on-resistance of the HEMT. Vertical integration of SBDs is also difficult to control due to leakage current, and current reports indicate integration with Si Schottky diodes on the substrate, failing to leverage the advantages of GaN materials. Summary of the Invention

[0004] The main objective of this invention is to provide a group III nitride transistor structure and its fabrication method that can reduce leakage current, thereby overcoming the shortcomings of the prior art.

[0005] To achieve the aforementioned objectives, the technical solution adopted by this invention includes:

[0006] One embodiment of the present invention provides a group III nitride transistor structure that can reduce leakage current, comprising:

[0007] A first heterojunction and a second heterojunction are stacked together, and the first heterojunction and the second heterojunction are electrically isolated by a high-resistivity material and / or an intercalation layer.

[0008] The first electrode, the second electrode, and the first gate are in cooperation with the first heterojunction. The first electrode and the second electrode are electrically connected through a first two-dimensional electron gas in the first heterojunction. A third semiconductor is provided between the first gate and the first heterojunction. The third semiconductor is capable of depleting a portion of the first two-dimensional electron gas located below it. The first gate is also electrically connected to the first electrode.

[0009] The source, drain, and second gate are coupled to the second heterojunction. The source and drain are electrically connected through a second two-dimensional electron gas within the second heterojunction. The source and drain are also electrically connected to the first gate and the second electrode, respectively. A sixth semiconductor is disposed between the second gate and the second heterojunction. The sixth semiconductor is capable of depleting a portion of the second two-dimensional electron gas located below it.

[0010] This invention also provides a method for fabricating a group III nitride transistor structure that can reduce leakage current, comprising:

[0011] The step of fabricating a first heterojunction, a high-resistivity material and / or an insertion layer and a second heterojunction stacked along a predetermined direction, wherein the first heterojunction and the second heterojunction are electrically isolated from each other by the high-resistivity material and / or the insertion layer.

[0012] A first electrode, a second electrode, a first gate, and a third semiconductor are fabricated to cooperate with a first heterojunction. The first electrode and the second electrode are electrically connected through a first two-dimensional electron gas within the first heterojunction. The third semiconductor is disposed between the first gate and the first heterojunction. The first gate is also electrically connected to the first electrode. The third semiconductor is capable of depleting a portion of the first two-dimensional electron gas located below it.

[0013] Fabricate a source, drain, second gate, and a sixth semiconductor that cooperate with a second heterojunction. The source and drain are electrically connected via a second two-dimensional electron gas within the second heterojunction. The sixth semiconductor is disposed between the second gate and the second heterojunction and is capable of depleting the portion of the second two-dimensional electron gas located below it.

[0014] The first gate is electrically connected to the source, and the second electrode is electrically connected to the drain.

[0015] Compared with the prior art, the advantages of the present invention include:

[0016] 1) The present invention provides a group III nitride transistor structure that integrates diodes and transistors in a direction perpendicular to the substrate, thereby reducing the wafer area occupied by the group III nitride transistor and facilitating the miniaturization of the device.

[0017] 2) The III-nitride transistor structure provided in this embodiment of the invention has the characteristics of direct growth and process compatibility, which effectively reduces the complexity and fabrication cost of the device;

[0018] 3) The group III nitride transistor structure provided in this embodiment of the invention can effectively reduce the leakage current and power consumption of the device, thereby improving the reliability and stability of the device;

[0019] 4) The group III nitride transistor structure provided in this embodiment of the invention has better process compatibility and is more convenient in design. Attached Figure Description

[0020] Figure 1a This is a schematic diagram of a group III nitride transistor structure that can reduce leakage current, provided in Embodiment 1 of the present invention;

[0021] Figure 1b The results of TCAD simulation test of a group III nitride transistor structure that can reduce leakage current provided in Embodiment 1 of the present invention and a conventional transistor are shown.

[0022] Figures 2a-2g This is a schematic diagram of the fabrication process of a group III nitride transistor structure that can reduce leakage current in Embodiment 1 of the present invention.

[0023] Figure 3 This is a schematic diagram of a group III nitride transistor structure that can reduce leakage current, provided in Embodiment 2 of the present invention;

[0024] Figure 4 This is a schematic diagram of a group III nitride transistor structure that can reduce leakage current, provided in Embodiment 3 of the present invention;

[0025] Figure 5 The results are the performance test results of the device in Comparative Example 1;

[0026] Figure 6 The results are the performance test results of the device in Comparative Example 2;

[0027] Figure 7 This is a schematic diagram of a group III nitride transistor structure that can reduce leakage current, provided in Embodiment 4 of the present invention;

[0028] Figure 8 This is a schematic diagram of a group III nitride transistor structure that can reduce leakage current, provided in Embodiment 5 of the present invention;

[0029] Figure 9 These are the corresponding curves between the hole distribution, H atom distribution, and p-GaN spacing within the P-type layer;

[0030] Figure 10 This is the curve showing the relationship between the electric field intensity within the P-type layer and the p-GaN spacing. Detailed Implementation

[0031] In view of the shortcomings of the prior art, the inventors of this invention, through long-term research and extensive practice, have proposed the technical solution of this invention. The following will further explain and illustrate this technical solution, its implementation process, and its principles.

[0032] This invention provides a Group III nitride transistor structure that reduces leakage current. To improve the conduction characteristics of the transistor structure and reduce the reverse conduction voltage drop, this invention provides a device structure that connects the transistor and diode in parallel. To minimize the wafer area occupied by the device, this invention vertically stacks the transistor and diode to achieve vertical integration, avoiding the problem of increasing the area in the lateral direction. Furthermore, to avoid increasing leakage current, this invention adopts a hybrid anode diode structure similar to and compatible with HEMT devices. This diode has an in-situ high-resistivity passivation layer (which can be understood as a high-resistivity material), greatly reducing the surface leakage current of the device. In addition, to leverage the advantages of GaN devices, this invention adopts a hybrid anode diode structure similar to and compatible with HEMT devices. This diode, as a lateral rectifier, also uses GaN material and an AlGaN / GaN heterojunction as its basic structure.

[0033] In this embodiment of the invention, the first heterojunction and the second heterojunction are electrically isolated through a high-resistivity material and / or an insertion layer, and the insertion layer can also reduce stress. The inventors of this case have found that vertical integration is difficult to achieve for material epitaxy because the material structure to be epitaxial needs to be thick enough, but the thick epitaxial material structure can cause the sample to crack. However, setting an insertion layer between the first heterojunction and the second heterojunction can effectively alleviate the problem of sample cracking.

[0034] One embodiment of the present invention provides a group III nitride transistor structure that can reduce leakage current, comprising:

[0035] A first heterojunction and a second heterojunction are stacked together, and the first heterojunction and the second heterojunction are electrically isolated by a high-resistivity material and / or an intercalation layer.

[0036] The first electrode, the second electrode, and the first gate are in cooperation with the first heterojunction. The first electrode and the second electrode are electrically connected through a first two-dimensional electron gas in the first heterojunction. A third semiconductor is provided between the first gate and the first heterojunction. The third semiconductor is capable of depleting a portion of the first two-dimensional electron gas located below it. The first gate is also electrically connected to the first electrode.

[0037] The source, drain, and second gate are coupled to the second heterojunction. The source and drain are electrically connected through a second two-dimensional electron gas within the second heterojunction. The source and drain are also electrically connected to the first gate and the second electrode, respectively. A sixth semiconductor is disposed between the second gate and the second heterojunction. The sixth semiconductor is capable of depleting a portion of the second two-dimensional electron gas located below it.

[0038] In one specific embodiment, the group III nitride transistor structure includes a first semiconductor, a second semiconductor, a high-resistivity material layer or an insertion layer, a fourth semiconductor, and a fifth semiconductor sequentially grown along a predetermined direction; or, the group III nitride transistor structure includes a fourth semiconductor, a fifth semiconductor, a high-resistivity material layer or an insertion layer, a first semiconductor, and a second semiconductor sequentially grown along a predetermined direction; or, the group III nitride transistor structure includes a first semiconductor, a second semiconductor, a high-resistivity material layer, an insertion layer, a fourth semiconductor, and a fifth semiconductor sequentially grown along a predetermined direction; or, the group III nitride transistor structure includes a fourth semiconductor, a fifth semiconductor, a high-resistivity material layer, an insertion layer, a first semiconductor, and a second semiconductor sequentially grown along a predetermined direction.

[0039] The first semiconductor and the second semiconductor cooperate to form a first heterojunction, and the fourth semiconductor and the fifth semiconductor cooperate to form a second heterojunction.

[0040] In one specific embodiment, the high-resistivity material layer is formed by transforming a first region of a continuous third semiconductor layer, wherein the third semiconductor is distributed in a second region of the third semiconductor layer;

[0041] Alternatively, the third semiconductor may be formed by transforming a second region of a continuous high-resistivity material layer, wherein the high-resistivity material is distributed within a first domain of the high-resistivity material layer.

[0042] In one specific embodiment, the third semiconductor is a p-type semiconductor.

[0043] In one specific embodiment, the material of the third semiconductor includes a p-type wide bandgap semiconductor.

[0044] In one specific embodiment, the p-type wide bandgap semiconductor includes a p-type group III nitride.

[0045] In one specific embodiment, the p-type group III nitride includes p-type GaN, p-type AlGaN, p-type InGaN, or p-type InN, etc.

[0046] In one specific embodiment, the p-type semiconductor includes p-type polycrystalline silicon, p-type amorphous silicon, p-type oxide, p-type diamond, or p-type semiconductor polymer, etc.

[0047] In one specific embodiment, the third semiconductor includes a plurality of spaced-apart strip p-type semiconductors arranged in an array.

[0048] In one specific embodiment, the doping concentration of the third semiconductor is 10. 16 ~10 20 cm -3 .

[0049] In one specific embodiment, the thickness of the third semiconductor is 10 nm to 500 nm.

[0050] In one specific embodiment, the high-resistivity material includes high-resistivity GaN, high-resistivity AlGaN, high-resistivity Ga2O3, high-resistivity InGaN, or high-resistivity InN, etc.

[0051] In one specific embodiment, the high-resistivity material layer is formed by transforming a third region of a continuous sixth semiconductor layer, wherein the sixth semiconductor is distributed in a fourth region of the sixth semiconductor layer;

[0052] Alternatively, the sixth semiconductor may be formed by transforming a fourth region of a continuous high-resistivity material layer, wherein the high-resistivity material is distributed within a third domain of the high-resistivity material layer.

[0053] In one specific embodiment, the sixth semiconductor is a p-type semiconductor.

[0054] In one specific embodiment, the material of the sixth semiconductor includes a p-type wide bandgap semiconductor.

[0055] In one specific embodiment, the p-type wide bandgap semiconductor includes a p-type group III nitride.

[0056] In one specific embodiment, the p-type group III nitride includes p-type GaN, p-type AlGaN, p-type InGaN, or p-type InN, etc.

[0057] In one specific embodiment, the p-type semiconductor includes p-type polycrystalline silicon, p-type amorphous silicon, p-type oxide, p-type diamond, or p-type semiconductor polymer, etc.

[0058] In one specific embodiment, the high-resistivity material includes high-resistivity GaN, high-resistivity AlGaN, high-resistivity Ga2O3, high-resistivity InGaN, or high-resistivity InN, etc.

[0059] In one specific embodiment, the high-resistivity material layer is distributed between the third semiconductor and the second electrode, and the third semiconductor is also electrically isolated from the second electrode via the high-resistivity material;

[0060] Alternatively, the high-resistivity material layer is distributed between the sixth semiconductor and the source and drain, and the sixth semiconductor is electrically isolated from the source and drain via the high-resistivity material.

[0061] In one specific embodiment, the insertion layer includes any one of a metal layer, a dielectric layer, and a two-dimensional material layer.

[0062] In one specific embodiment, the metal layer includes a single metal layer or a multilayer metal layer stacked together, and the material of the metal layer includes any one of Mo, Mg, and Al, but is not limited thereto.

[0063] In one specific embodiment, the thickness of the metal layer is 2 nm to 10 μm.

[0064] In one specific embodiment, the material of the dielectric layer includes any one of AlN, BN, AlBN, AlPN, BCN, high-resistivity AlGaN, and high-resistivity GaN, but is not limited thereto.

[0065] In one specific embodiment, the thickness of the dielectric layer is 0.5 nm to 1 μm.

[0066] In one specific embodiment, the material of the two-dimensional material layer includes any one of BN, graphene, fluorinated graphene, graphene oxide, and black phosphorus, but is not limited thereto.

[0067] In one specific embodiment, the thickness of the two-dimensional material layer is 0.5 nm to 500 nm.

[0068] In one specific embodiment, an insulating dielectric layer is further disposed on the second heterojunction, and the source and drain are disposed on the insulating dielectric layer.

[0069] In one specific embodiment, the thickness of the insulating dielectric layer is 1-1000 nm.

[0070] In one specific embodiment, the material of the insulating dielectric layer includes any one or a combination of two or more of SiO2, AlN, and Si3N4, but is not limited thereto.

[0071] In one specific embodiment, a two-dimensional material is further disposed on the sixth semiconductor, and the source and drain are disposed on the two-dimensional material.

[0072] In one specific embodiment, a two-dimensional material is disposed on the third semiconductor.

[0073] In one specific embodiment, the two-dimensional material has 1 to 100 layers.

[0074] In one specific embodiment, the two-dimensional material is a single type of two-dimensional material or a two-dimensional material heterostructure.

[0075] In one specific embodiment, the two-dimensional material includes any one or a combination of two or more of graphene, MoS2, and WS2, but is not limited thereto.

[0076] In one specific embodiment, a seventh semiconductor is further disposed between the first semiconductor and the second semiconductor and / or between the fourth semiconductor and the fifth semiconductor.

[0077] In one specific embodiment, the materials of the first semiconductor, the second semiconductor, the fourth semiconductor, and the fifth semiconductor are all selected from group III-V compounds.

[0078] In one specific embodiment, the materials of the first semiconductor and the fourth semiconductor include GaN or GaAs, but are not limited thereto.

[0079] In one specific embodiment, the materials of the second and fifth semiconductors include AlGaN or AlGaAs, but are not limited thereto.

[0080] In one specific embodiment, the material of the seventh semiconductor includes AlN, but is not limited thereto.

[0081] In one specific embodiment, the first heterojunction, together with the first electrode and the second electrode, forms a diode, and the second heterojunction, together with the source, drain and gate, forms a transistor (also understood as a triode, the same below). The first electrode can be the anode and the second electrode can be the cathode.

[0082] In one specific embodiment, a lower p-type doping concentration and / or a thinner p-type material thickness can be set in the third semiconductor to weaken its control over the 2DEG channel, thereby reducing the forward voltage drop of the diode. After the forward voltage drop of the diode is reduced, the diode will conduct preferentially when the transistor is reverse-biased, that is, the first channel formed by the first two-dimensional electron gas in the first heterojunction will conduct first, so the reverse-biased source-drain voltage drop of the transistor is reduced.

[0083] In one specific embodiment, the electrical connection between the first electrode and the source electrode can be through a metal interconnect on the chip or through an external circuit metal connection; the electrical connection between the second electrode and the drain electrode can be through a metal interconnect on the chip or through an external circuit metal connection.

[0084] In one specific embodiment, the thickness of the gate is 10-1000 nm, and the material of the gate can be any one or a combination of two or more of Ti, Al, Ni, Au, Cr, Pt, Mo, Pd, etc., for example, it can be selected from the following group: Ni / Au, Mo / Au, Cr / Au, Pd / Au, but is not limited thereto; the thickness of the first electrode, the second electrode, the source electrode, and the drain electrode can be 10-1000 nm, and the material of the first electrode, the second electrode, the source electrode, and the drain electrode can be any one or an alloy formed from two or more of Au, Cr, Pt, Ag, Ti, Al, TiN, for example, it can be selected from the following group: Ti / Al / Ni / Au, Ti / Al / Ti / Au, Ti / Al / Ti / TiN, but is not limited thereto.

[0085] In one specific embodiment, the first heterojunction or the second heterojunction is formed on the substrate, and a buffer layer is distributed between the first heterojunction or the second heterojunction and the substrate.

[0086] It should be noted that the transistor may be stacked on top of the diode in a vertical direction, or the diode may be stacked on top of the transistor in a vertical direction, and their relative positions in the vertical direction may be interchanged.

[0087] This invention also provides a method for fabricating a group III nitride transistor structure that can reduce leakage current, comprising:

[0088] The step of fabricating a first heterojunction, a high-resistivity material and / or an insertion layer and a second heterojunction stacked along a predetermined direction, wherein the first heterojunction and the second heterojunction are electrically isolated from each other by the high-resistivity material and / or the insertion layer.

[0089] A first electrode, a second electrode, a first gate, and a third semiconductor are fabricated to cooperate with a first heterojunction. The first electrode and the second electrode are electrically connected through a first two-dimensional electron gas within the first heterojunction. The third semiconductor is disposed between the first gate and the first heterojunction. The first gate is also electrically connected to the first electrode. The third semiconductor is capable of depleting a portion of the first two-dimensional electron gas located below it.

[0090] Fabricate a source, drain, second gate, and a sixth semiconductor that cooperate with a second heterojunction. The source and drain are electrically connected via a second two-dimensional electron gas within the second heterojunction. The sixth semiconductor is disposed between the second gate and the second heterojunction and is capable of depleting the portion of the second two-dimensional electron gas located below it.

[0091] The first gate is electrically connected to the source, and the second electrode is electrically connected to the drain.

[0092] In one specific embodiment, the manufacturing method specifically includes:

[0093] A first semiconductor, a second semiconductor, a high-resistivity material layer or an insertion layer, a fourth semiconductor, and a fifth semiconductor are sequentially grown in a predetermined direction; or, a fourth semiconductor, a fifth semiconductor, a high-resistivity material layer or an insertion layer, a first semiconductor, and a second semiconductor are sequentially grown in a predetermined direction; or, a first semiconductor, a second semiconductor, a high-resistivity material layer, an insertion layer, a fourth semiconductor, and a fifth semiconductor are sequentially grown in a predetermined direction; or, a fourth semiconductor, a fifth semiconductor, a high-resistivity material layer, an insertion layer, a first semiconductor, and a second semiconductor are sequentially grown in a predetermined direction.

[0094] The first semiconductor and the second semiconductor cooperate to form a first heterojunction, and the fourth semiconductor and the fifth semiconductor cooperate to form a second heterojunction.

[0095] In one specific embodiment, the manufacturing method specifically includes:

[0096] A continuous third semiconductor layer is formed on the second semiconductor, the third semiconductor layer including a first region and a second region, and the first region is transformed to form the high-resistivity material layer; or, a continuous high-resistivity material layer is formed on the second semiconductor, the high-resistivity material layer including a first region and a second region, and the second region is transformed to form the third semiconductor.

[0097] In one specific embodiment, the manufacturing method specifically includes:

[0098] A continuous sixth semiconductor layer is formed on the fifth semiconductor, the sixth semiconductor layer including a third region and a fourth region, and the third region is subjected to a conversion process to form the high-resistivity material layer;

[0099] Alternatively, a continuous high-resistivity material layer is formed on the fifth semiconductor, the high-resistivity material layer including a third region and a fourth region, and the fourth region is transformed to form the sixth semiconductor.

[0100] In one specific embodiment, the method for performing the conversion treatment includes any one or more combinations of H ion implantation, H plasma treatment, H doping annealing, N ion implantation, F ion implantation, Ar ion implantation, Fe ion implantation, O plasma treatment, and thermal oxidation.

[0101] For example, the third and sixth semiconductors are generally made of p-GaN material and can be passivated in situ by selective activation or NH3 annealing, H plasma treatment, H ion implantation, O plasma treatment, thermal oxidation, secondary epitaxy, ion implantation, etc. The in-situ passivation method is selective passivation, which weakens its control over 2DEG and reduces the forward voltage drop of the diode.

[0102] Of course, the third and sixth semiconductors can also be p-type materials such as p-type polycrystalline silicon and p-type oxide. These materials can be deposited by sputtering, LPCVD, PECVD and other methods. Their concentration can be controlled by the deposition conditions, or can be adjusted by subsequent ion implantation, annealing and other methods, thereby controlling the voltage drop of the diode.

[0103] It should be noted that the p-type semiconductor (third semiconductor) below the second part of the first electrode can also be patterned, and then partially passivated in situ or partially removed by means of NH3 annealing, H plasma treatment, H ion implantation, O plasma treatment, thermal oxidation, etc., or by dry etching (ICP, RIE, NLD, etc.) or wet etching (PEC etching, KOH, etc.) to adjust the concentration of electrons in the channel below, thereby controlling the voltage drop of the diode.

[0104] In one specific embodiment, the third semiconductor can be passivated in situ by means of NH3 annealing, H plasma treatment, H ion implantation, O plasma treatment, thermal oxidation, etc., to reduce leakage current; the sixth semiconductor can be activated by post-process annealing, retaining only the sixth semiconductor below the second gate, while the rest is in an inactive state, i.e., a high-resistivity region, to reduce leakage current.

[0105] In one specific embodiment, the manufacturing method further includes: patterning the third semiconductor to form a strip array structure.

[0106] In one specific embodiment, the manufacturing method further includes:

[0107] The third semiconductor and a high-resistivity material layer are selectively epitaxially grown on the second semiconductor.

[0108] Alternatively, the sixth semiconductor and a high-resistivity material layer may be selectively epitaxially grown on the fifth semiconductor.

[0109] In one specific embodiment, the fabrication method further includes: forming an insertion layer on the high-resistivity material layer, and then fabricating a first heterojunction or a second heterojunction on the insertion layer.

[0110] In one specific embodiment, the insertion layer includes any one of a metal layer, a dielectric layer, and a two-dimensional material layer.

[0111] In one specific embodiment, the metal layer includes a single metal layer or a multilayer metal layer stacked together, and the material of the metal layer includes any one of Mo, Mg, and Al, but is not limited thereto.

[0112] In one specific embodiment, the thickness of the metal layer is 2 nm to 10 μm.

[0113] In one specific embodiment, the material of the dielectric layer includes any one of AlN, BN, AlBN, AlPN, BCN, high-resistivity AlGaN, and high-resistivity GaN, but is not limited thereto.

[0114] In one specific embodiment, the thickness of the dielectric layer is 0.5 nm to 1 μm.

[0115] In one specific embodiment, the material of the two-dimensional material layer includes any one of BN, graphene, fluorinated graphene, graphene oxide, and black phosphorus, but is not limited thereto.

[0116] In one specific embodiment, the thickness of the two-dimensional material layer is 0.5 nm to 500 nm.

[0117] In one specific embodiment, the third semiconductor is further electrically isolated from the second electrode via the high-resistivity material, or the sixth semiconductor is further electrically isolated from the source and drain via the high-resistivity material.

[0118] In one specific embodiment, the third semiconductor and the sixth semiconductor are p-type semiconductors.

[0119] In one specific embodiment, the third and sixth semiconductors are made of p-type wide bandgap semiconductors.

[0120] In one specific embodiment, the p-type wide bandgap semiconductor includes a p-type group III nitride.

[0121] In one specific embodiment, the p-type group III nitride includes p-type GaN, p-type AlGaN, p-type InGaN, or p-type InN.

[0122] In one specific embodiment, the p-type semiconductor includes p-type polycrystalline silicon, p-type amorphous silicon, p-type oxide, p-type diamond, or p-type semiconductor polymer, etc.

[0123] In one specific embodiment, the first high-resistivity material and the second high-resistivity material include high-resistivity GaN, high-resistivity AlGaN, high-resistivity Ga2O3, high-resistivity InGaN, or high-resistivity InN, etc.

[0124] It should be noted that the transistor portion and diode portion in the group III nitride transistor with reduced leakage current provided in the embodiments of the present invention can be fabricated on the same wafer or separately on different wafers, and then the diode portion and transistor portion are integrated in the vertical direction by bonding. Among them, the p-type semiconductor of the upper device portion in the vertical direction can be obtained by overall activation first, and then selectively retained by etching or passivation. Of course, the p-type semiconductor can also be obtained by selective epitaxy or lateral epitaxy.

[0125] The following will further explain the technical solution, its implementation process and principle in conjunction with the accompanying drawings and specific implementation examples. Unless otherwise specified, the deposition, epitaxy, etching and other processes used in the embodiments of the present invention are all known to those skilled in the art.

[0126] Example 1

[0127] Please see Figure 1a The structure of a group III nitride transistor may include:

[0128] A first buffer layer, a first channel layer (i.e., the aforementioned first semiconductor, hereinafter the same) 1, a first barrier layer (i.e., the aforementioned second semiconductor, hereinafter the same) 2, a first p-type layer (i.e., the aforementioned third semiconductor, hereinafter the same) 3, a first high-resistivity layer (i.e., the first high-resistivity material or the first high-resistivity material layer, hereinafter the same), an insertion layer (or an insertion layer may be omitted), a second buffer layer, a second channel layer (i.e., the aforementioned fourth semiconductor, hereinafter the same) 4, a second barrier layer (i.e., the aforementioned fifth semiconductor, hereinafter the same) 5, a second p-type layer (i.e., the aforementioned sixth semiconductor, hereinafter the same) 6, and a second high-resistivity layer (i.e., the second high-resistivity material or the second high-resistivity material layer, hereinafter the same) are sequentially stacked on a substrate. The first channel layer 1 and the first barrier layer 2 cooperate to form a first heterojunction, and a first two-dimensional electron gas (2DEG) is formed between the first channel layer 1 and the first barrier layer 2. The second channel layer 4 and the second barrier layer 5 cooperate to form a second heterojunction, and a second two-dimensional electron gas (2DEG) is formed between the second channel layer 4 and the second barrier layer 5.

[0129] An anode (i.e., the aforementioned first electrode, the same below) and a cathode (i.e., the aforementioned second electrode, the same below) are disposed at intervals on the first barrier layer 2. The cathode and the anode are electrically connected through a first 2DEG. A first gate (i.e., gate one in the figure, the same below) is also disposed on the first p-type layer. The first gate is electrically connected to the anode and completely covers the first p-type layer. The first gate is electrically in contact with the first p-type layer. The first p-type layer and the cathode are also electrically isolated through the first high-resistivity layer.

[0130] A source and a drain are spaced apart on the second barrier layer 5, and the source and drain are electrically connected via a second 2DEG. A second gate (gate 2 in the figure) is disposed on the second p-type layer, and the second p-type layer is electrically isolated from the source and drain via a second high-resistivity layer.

[0131] The first heterojunction and the second heterojunction are electrically isolated by the first high-resistivity layer and the insertion layer. The first gate is also electrically connected to the source, and the cathode is also electrically connected to the drain.

[0132] It should be noted that the first heterojunction, together with the anode, cathode, and first gate, forms a diode, and the second heterojunction, together with the source, drain, and second gate, forms a transistor. The surface of the structure of the group III nitride transistor is also covered with a passivation layer.

[0133] Specifically, the insertion layer can be any one of a metal layer, a dielectric layer, or a two-dimensional material layer. The metal layer includes a single metal layer or a multilayer metal layer stacked together. The material of the metal layer includes any one of Mo, Mg, and Al. The thickness of the metal layer is 2 nm to 10 μm.

[0134] Specifically, for the Mg layer, thermal annealing can be performed in a nitrogen environment to alloy it with the underlying material. The annealing temperature can be 400–800℃, and the time can be 5–120 min. For the Al layer, thermal annealing can be performed in an oxygen environment to oxidize it. The temperature can be room temperature to 800℃, and the time can be 5–120 min. Subsequently, the Al layer can be subjected to plasma treatment. The plasma used can be N2, N2O, NH3, NO, etc., and the equipment can be ICP, RIE, PECVD, etc. Alternatively, ultraviolet ozone treatment can be performed on the Al layer for 30–300 min. The intercalated metal can be used as a back electrode, with wide applications including voltage application and temperature detection. Multilayer metals such as Mg / Mo / Mg can also be used to improve the device's heat dissipation capability.

[0135] Specifically, the dielectric layer is made of any one of AlN, BN, AlBN, AlPN, BCN, high-resistivity AlGaN, and high-resistivity GaN, and the thickness of the dielectric layer is 0.5 nm to 1 μm; the two-dimensional material layer is made of any one of BN, graphene, fluorinated graphene, graphene oxide, and black phosphorus, and the thickness of the two-dimensional material layer is 0.5 nm to 500 nm.

[0136] Please see Figures 2a-2g The method for fabricating a group III nitride transistor structure provided in this embodiment may include the following steps:

[0137] 1) Using epitaxial techniques such as metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), or hydride vapor phase epitaxy (HVPE), growth is achieved as follows: Figure 2a The material structure shown is as follows: substrate / first buffer layer / first channel layer / first barrier layer / first high resistivity layer / second buffer layer / second channel layer / second barrier layer / second high resistivity layer;

[0138] The substrate can be a silicon wafer, sapphire, etc.; the material of the first / second channel layer can be GaN or GaAs, etc.; the material of the first / second barrier layer can be AlGaN or AlGaAs, etc.; a first two-dimensional electron gas is formed between the first channel layer and the first barrier layer; a second two-dimensional electron gas is formed between the second channel layer and the second barrier layer; the first / second barrier layer has poor conductivity, such as AlGaN with a conductivity of 10Ω / m or higher; the first / second high-resistivity layer is an unactivated p-type doped layer, which can be made of Mg-doped GaN; the first / second high-resistivity layer has poor conductivity; the material of the first / second buffer layer can be known to those skilled in the art.

[0139] 2) Reactive ion etching is used to remove a portion of the second buffer layer / second channel layer / second barrier layer / second high-resistivity layer in a designated area to expose the first high-resistivity layer, resulting in a material structure as follows: Figure 2b As shown;

[0140] 3) Reactive ion etching technology can be used to remove the second high-resistivity layer in the source region and drain region, as well as the first high-resistivity layer in the cathode region and anode region. It can also remove part or all of the first / second barrier layer located in the source region, drain region / cathode region and anode region, and even etch part of the first / second channel layer.

[0141] Using metal deposition techniques such as electron beam evaporation or sputtering, source, drain, cathode, and anode are fabricated in the source, drain, cathode, and anode regions, respectively. Rapid annealing is then performed at 500-1000℃ for 0.1-100 minutes, forming ohmic contacts between the source, drain, cathode, and anode and the materials they contact. Simultaneously, the source and drain are electrically connected to a second two-dimensional electron gas, while the cathode and anode are electrically connected via a first two-dimensional electron gas. The resulting device structure after electrode formation is shown below. Figure 2c As shown;

[0142] The thickness of the source / drain / cathode / anode is 10-1000 nm, and the material of the source / drain / cathode / anode can be any one of Ti / Al / Ni / Au, Ti / Al / Ti / Au, Ti / Al / Cr / Au, Ti / Al / Pt / Au, Ti / Al / Mo / Au, and Ti / Al / Pd / Au. It should be noted that the anode and cathode are electrically connected by a first two-dimensional electron gas.

[0143] 4) Employing thin film deposition technologies such as PECVD, ALD, and LPCVD in... Figure 2c The device structure shown has a protective layer deposited on its surface. The thickness of the protective layer is 10-1000 nm. The material of the protective layer can be any one or more combinations of SiO2, AlN, and Si3N4, but is not limited to these.

[0144] Subsequently, etching methods such as reactive ion etching or ion beam etching are used to remove part of the protective layer in order to expose the part of the first high-resistivity layer / second high-resistivity layer that needs to be activated.

[0145] The exposed first / second high-resistivity layer is annealed and activated using p-type material in high-temperature equipment such as a rapid annealing furnace or MOCVD, transforming the corresponding regions of the first / second high-resistivity layer into a first / second p-type layer. The annealing temperature is 300–1000℃, resulting in a device structure as shown below. Figure 2d As shown;

[0146] 5) Remove the protective layer and use metal deposition techniques such as electron beam evaporation or sputtering to fabricate a first gate (gate one in the figure) on the first p-type layer and a second gate (gate two in the figure) on the second p-type layer. The first gate is electrically connected to the anode and is electrically in contact with the first p-type layer and completely covers the first p-type layer.

[0147] The thickness of the second gate and the first gate is 10-1000 nm, and the material can be any one or a combination of two or more of Ti, Al, Ni, Au, Cr, Pt, Mo, and Pd, typically Ni / Au; the formed device structure is as follows. Figure 2e As shown;

[0148] 6) Employing thin film deposition technologies such as PECVD, ALD, and LPCVD, in... Figure 2e The device structure shown has a passivation layer deposited on its surface. The passivation layer has a thickness of 10-1000 nm and can be made of any one or more of the following materials: SiO2, AlN, Al2O3, and Si3N4, but is not limited to these. The resulting device structure is as follows: Figure 2f As shown;

[0149] 7) Use etching methods such as reactive ion etching or ion beam etching to remove part of the passivation layer in the region corresponding to the second part of the anode and the source to expose the first gate and the source; then use metal deposition techniques such as electron beam evaporation or sputtering to deposit interconnect metal electrodes, and make the interconnect metal electrodes electrically connected to the first gate and the source respectively.

[0150] The interconnecting metal electrodes have a thickness of 500-3000 nm and are made of any one or more of the following materials: Ti, Al, Ni, Au, Cr, Pt, Mo, Pd, and Cu; typically Cu or Ti / Al is chosen, and the resulting device structure is as follows: Figure 2g As shown.

[0151] Comparative Example 1

[0152] Comparative Example 1 is a commercial EPC device disclosed in Zhang, H., and RS Balog, "Loss analysis during dead time and thermal study of gallium nitride devices," Applied Power Electronics Conference & Exposition IEEE, 2015. The test results of this device are as follows: Figure 5 As shown

[0153] Comparative Example 2

[0154] The figure shows the test data of the p-GaN gate transistor conducted by our research group. Comparative Example 2 is a p-GaN gate transistor disclosed in "Hao Ronghui. Research on Novel Enhancement-Type p-GaN Gate HEMT Power Switching Device [D]. Nanjing University of Science and Technology, 2019.", and its test results are as follows. Figure 6 As shown.

[0155] Example 2

[0156] The embodiment provides a structure of a group III nitride transistor as follows: Figure 3 As shown, the difference between the group III nitride transistor structure provided in this embodiment and the transistor in embodiment 1 is that the diode portion formed by the first heterojunction and the anode, cathode, and first gate is in a different position than the transistor formed by the second heterojunction and the source, drain, and second gate. The preparation method of the group III nitride transistor structure provided in this embodiment is basically the same as that in embodiment 1.

[0157] Example 3

[0158] The embodiment provides a structure of a group III nitride transistor as follows: Figure 4As shown, the difference between this embodiment and the group III nitride transistor of Example 1 is that the second buffer layer can be replaced by a high-resistivity material. The preparation method of the group III nitride transistor structure provided in this embodiment is basically the same as that of Example 1.

[0159] Example 4

[0160] The embodiment provides a structure of a group III nitride transistor as follows: Figure 7 As shown, a group III nitride transistor structure includes a first buffer layer, a first channel layer, a first barrier layer, a first p-type layer and a first high-resistivity layer, a passivation layer, a second p-type layer and a second high-resistivity layer, a second barrier layer, a second channel layer, a second buffer layer and a second substrate, which are sequentially stacked on a first substrate. The first channel layer and the first barrier layer cooperate to form a first heterojunction, and a first two-dimensional electron gas (2DEG) is formed between the first channel layer and the first barrier layer. The second channel layer and the second barrier layer cooperate to form a second heterojunction, and a second two-dimensional electron gas (2DEG) is formed between the second channel layer and the second barrier layer.

[0161] An anode (i.e., the aforementioned first electrode, the same below) and a cathode (i.e., the aforementioned second electrode, the same below) are disposed at intervals on the second barrier layer. The cathode and the anode are electrically connected through a second 2DEG. A second gate (i.e., gate two in the figure, the same below) is also disposed on the second p-type layer. The second gate is electrically connected to the anode and completely covers the second p-type layer. The second gate is electrically in contact with the second p-type layer. The second p-type layer and the cathode are also electrically isolated through a second high-resistivity layer.

[0162] A source and a drain are spaced apart on the first barrier layer, and the source and drain are electrically connected via a first 2DEG. A first gate (gate one in the figure) is disposed on the first p-type layer, and the first p-type layer is electrically isolated from the source and drain via a first high-resistivity layer.

[0163] The second gate is also electrically connected to the source, and the cathode is also electrically connected to the drain via interconnecting metals.

[0164] It should be noted that the second heterojunction, together with the anode, cathode, and second gate, forms a diode, while the first heterojunction, together with the source, drain, and first gate, forms a transistor.

[0165] Example 5

[0166] The embodiment provides a structure of a group III nitride transistor as follows: Figure 8As shown, its structure is basically the same as that of the group III nitride transistor in Example 1. The difference between the two is that: multiple P-type layers are disposed in the first high-resistivity layer or the second high-resistivity layer in the upper diode or transistor. The material of the multiple P-type layers can be the same as the material of the first or second P-type layer in the transistor or diode. The volume and spacing of the multiple P-type layers gradually decrease in the direction away from the first gate or the second gate.

[0167] For example, in this embodiment, the p-type layer is p-GaN, wherein the spacing between multiple p-GaN layers is passivated by H plasma, and the diffusion of the H plasma follows a Gaussian distribution.

[0168]

[0169] Where C is the concentration, x is the interval size, Q is the H content, and L is the diffusion width.

[0170] The inventors in this case discovered that if the spacing between multiple p-GaN layers gradually decreases away from the first or second gate, a concentration gradient can be created in the multiple p-type layers through diffusion. Figure 9 It can be seen that by arranging multiple p-GaN cells at specific intervals, the concentration distribution of the p-type layer can be effectively adjusted. Figure 10 It can be seen that when multiple p-GaN transistors are arranged at specific intervals and their concentrations are distributed in a specified manner, the electric field strength of the group III nitride transistor gradually decreases, but retains the plateau characteristics, thus allowing it to withstand high voltage.

[0171] The present invention provides a group III nitride transistor structure that integrates a diode and a transistor in a direction perpendicular to the substrate, thereby reducing the wafer area occupied by the group III nitride transistor and facilitating miniaturization applications. Furthermore, the overall device structure features direct growth and process compatibility, effectively reducing device complexity and fabrication costs. Additionally, the group III nitride transistor structure provided by the present invention effectively reduces leakage current and power consumption, thereby improving device reliability and stability.

Claims

1. A group III nitride transistor structure that can reduce leakage current, characterized in that... include: A first heterojunction and a second heterojunction are stacked together, and the first heterojunction and the second heterojunction are electrically isolated by a high-resistivity material and / or an intercalation layer. The first electrode, the second electrode, and the first gate are in cooperation with the first heterojunction. The first electrode and the second electrode are electrically connected through a first two-dimensional electron gas in the first heterojunction. A third semiconductor is provided between the first gate and the first heterojunction. The third semiconductor is capable of depleting a portion of the first two-dimensional electron gas located below it. The first gate is also electrically connected to the first electrode. The source, drain, and second gate are coupled to the second heterojunction. The source and drain are electrically connected through a second two-dimensional electron gas within the second heterojunction. The source and drain are also electrically connected to the first gate and the second electrode, respectively. A sixth semiconductor is disposed between the second gate and the second heterojunction. The sixth semiconductor is capable of depleting a portion of the second two-dimensional electron gas located below it.

2. The group III nitride transistor structure according to claim 1, characterized in that: The group III nitride transistor structure includes a first semiconductor, a second semiconductor, a high-resistivity material layer or insertion layer, a fourth semiconductor, and a fifth semiconductor, which are sequentially grown along a predetermined direction. Alternatively, the group III nitride transistor structure includes a fourth semiconductor, a fifth semiconductor, a high-resistivity material layer or insertion layer, a first semiconductor, and a second semiconductor, which are grown sequentially along a set direction. Alternatively, the group III nitride transistor structure includes a first semiconductor, a second semiconductor, a high-resistivity material layer, an insertion layer, a fourth semiconductor, and a fifth semiconductor, which are sequentially grown along a predetermined direction. Alternatively, the group III nitride transistor structure includes a fourth semiconductor, a fifth semiconductor, a high-resistivity material layer, an insertion layer, a first semiconductor, and a second semiconductor, which are grown sequentially along a set direction. The first semiconductor and the second semiconductor cooperate to form a first heterojunction, and the fourth semiconductor and the fifth semiconductor cooperate to form a second heterojunction.

3. The group III nitride transistor structure according to claim 2, characterized in that: The high-resistivity material layer is formed by transforming a first region of a continuous third semiconductor layer, wherein the third semiconductor is distributed in a second region of the third semiconductor layer; Alternatively, the third semiconductor may be formed by transforming a second region of a continuous high-resistivity material layer, wherein the high-resistivity material is distributed within a first domain of the high-resistivity material layer.

4. The group III nitride transistor structure according to claim 3, characterized in that: The third semiconductor is a p-type semiconductor.

5. The group III nitride transistor structure according to claim 3, characterized in that: The material of the third semiconductor includes a p-type wide bandgap semiconductor.

6. The group III nitride transistor structure according to claim 5, characterized in that: The p-type wide bandgap semiconductor includes p-type group III nitrides.

7. The group III nitride transistor structure according to claim 6, characterized in that: The p-type group III nitrides include p-type GaN, p-type AlGaN, p-type InGaN, or p-type InN.

8. The group III nitride transistor structure according to claim 4, characterized in that: The p-type semiconductor includes p-type polycrystalline silicon, p-type amorphous silicon, p-type oxide, p-type diamond, or p-type semiconductor polymer.

9. The group III nitride transistor structure according to claim 3, characterized in that: The third semiconductor includes a plurality of spaced-apart strip p-type semiconductors arranged in an array.

10. The group III nitride transistor structure according to claim 3, characterized in that: The doping concentration of the third semiconductor is 10. 16 cm -3 ~ 10 20 cm -3 .

11. The group III nitride transistor structure according to claim 3, characterized in that: The thickness of the third semiconductor is 10 nm to 500 nm.

12. The group III nitride transistor structure according to claim 3, characterized in that: The high-resistivity material includes high-resistivity GaN, high-resistivity AlGaN, high-resistivity Ga2O3, high-resistivity InGaN, or high-resistivity InN.

13. The group III nitride transistor structure according to claim 2, characterized in that: The high-resistivity material layer is formed by transforming a third region of a continuous sixth semiconductor layer, wherein the sixth semiconductor is distributed in a fourth region of the sixth semiconductor layer; Alternatively, the sixth semiconductor may be formed by transforming a fourth region of a continuous high-resistivity material layer, wherein the high-resistivity material is distributed within a third domain of the high-resistivity material layer.

14. The group III nitride transistor structure according to claim 13, characterized in that: The sixth semiconductor is a p-type semiconductor.

15. The group III nitride transistor structure according to claim 13, characterized in that: The material of the sixth semiconductor includes a p-type wide bandgap semiconductor.

16. The group III nitride transistor structure according to claim 15, characterized in that: The p-type wide bandgap semiconductor includes p-type group III nitrides.

17. The group III nitride transistor structure according to claim 16, characterized in that: The p-type group III nitrides include p-type GaN, p-type AlGaN, p-type InGaN, or p-type InN.

18. The group III nitride transistor structure according to claim 14, characterized in that: The p-type semiconductor includes p-type polycrystalline silicon, p-type amorphous silicon, p-type oxide, p-type diamond, or p-type semiconductor polymer.

19. The group III nitride transistor structure according to claim 13, characterized in that: The high-resistivity material includes high-resistivity GaN, high-resistivity AlGaN, high-resistivity Ga2O3, high-resistivity InGaN, or high-resistivity InN.

20. The group III nitride transistor structure according to claim 2, characterized in that: The high-resistivity material layer is distributed between the third semiconductor and the second electrode, and the third semiconductor is also electrically isolated from the second electrode by the high-resistivity material; Alternatively, the high-resistivity material layer is distributed between the sixth semiconductor and the source and drain, and the sixth semiconductor is electrically isolated from the source and drain via the high-resistivity material.

21. The group III nitride transistor structure according to claim 2, characterized in that: The insertion layer includes any one of a metal layer, a dielectric layer, or a two-dimensional material layer.

22. The group III nitride transistor structure according to claim 21, characterized in that: The metal layer includes a single metal layer or a multi-layer metal layer stacked together, and the material of the metal layer includes any one of Mo, Mg, and Al.

23. The group III nitride transistor structure according to claim 21, characterized in that: The thickness of the metal layer is 2 nm to 10 μm.

24. The group III nitride transistor structure according to claim 21, characterized in that: The dielectric layer is made of any one of AlN, BN, AlBN, AlPN, BCN, high-resistivity AlGaN, and high-resistivity GaN.

25. The group III nitride transistor structure according to claim 21, characterized in that: The thickness of the dielectric layer is 0.5 nm to 1 μm.

26. The group III nitride transistor structure according to claim 21, characterized in that: The material of the two-dimensional material layer includes any one of BN, graphene, fluorinated graphene, graphene oxide, and black phosphorus.

27. The group III nitride transistor structure according to claim 21, characterized in that: The thickness of the two-dimensional material layer is 0.5 nm to 500 nm.

28. The group III nitride transistor structure according to claim 2, characterized in that: An insulating dielectric layer is also disposed on the second heterojunction, and the source and the drain are disposed on the insulating dielectric layer.

29. The group III nitride transistor structure according to claim 28, characterized in that: The thickness of the insulating dielectric layer is 1 nm to 1000 nm.

30. The group III nitride transistor structure according to claim 28, characterized in that: The insulating dielectric layer is made of any one or a combination of two or more of SiO2, AlN, and Si3N4.

31. The group III nitride transistor structure according to claim 13, characterized in that: The sixth semiconductor is further provided with a two-dimensional material, and the source and drain are disposed on the two-dimensional material.

32. The group III nitride transistor structure according to claim 3, characterized in that: The third semiconductor is provided with a two-dimensional material.

33. The group III nitride transistor structure according to claim 31 or 32, characterized in that: The two-dimensional material has 1 to 100 layers.

34. The group III nitride transistor structure according to claim 31 or 32, characterized in that: The two-dimensional material is a single type of two-dimensional material or a two-dimensional material heterostructure.

35. The group III nitride transistor structure according to claim 31 or 32, characterized in that: The two-dimensional material includes any one or a combination of two or more of graphene, MoS2, and WS2.

36. The group III nitride transistor structure according to claim 2, characterized in that: A seventh semiconductor is also disposed between the first semiconductor and the second semiconductor and / or between the fourth semiconductor and the fifth semiconductor.

37. The group III nitride transistor structure according to claim 36, characterized in that: The materials of the first semiconductor, the second semiconductor, the fourth semiconductor, and the fifth semiconductor are all selected from group III-V compounds.

38. The group III nitride transistor structure according to claim 37, characterized in that: The materials of the first semiconductor and the fourth semiconductor include GaN or GaAs.

39. The group III nitride transistor structure according to claim 37, characterized in that: The materials of the second and fifth semiconductors include AlGaN or AlGaAs.

40. The group III nitride transistor structure according to claim 36, characterized in that: The material of the seventh semiconductor includes AlN.

41. A method for fabricating a group III nitride transistor structure that can reduce leakage current, characterized in that... include: The step of fabricating a first heterojunction, a high-resistivity material and / or an insertion layer and a second heterojunction stacked along a predetermined direction, wherein the first heterojunction and the second heterojunction are electrically isolated from each other by the high-resistivity material and / or the insertion layer. A first electrode, a second electrode, a first gate, and a third semiconductor are fabricated to cooperate with a first heterojunction. The first electrode and the second electrode are electrically connected through a first two-dimensional electron gas within the first heterojunction. The third semiconductor is disposed between the first gate and the first heterojunction. The first gate is also electrically connected to the first electrode. The third semiconductor is capable of depleting a portion of the first two-dimensional electron gas located below it. A source, drain, second gate, and sixth semiconductor are fabricated to cooperate with the second heterojunction. The source and drain are electrically connected through a second two-dimensional electron gas in the second heterojunction. The sixth semiconductor is disposed between the second gate and the second heterojunction and is capable of depleting the portion of the second two-dimensional electron gas located below it. as well as The first gate is electrically connected to the source, and the second electrode is electrically connected to the drain.

42. The manufacturing method according to claim 41, characterized in that, Specifically, it includes: A first semiconductor, a second semiconductor, a high-resistivity material layer or intercalation layer, a fourth semiconductor, and a fifth semiconductor are sequentially grown along a predetermined direction and stacked in sequence. Alternatively, a fourth semiconductor, a fifth semiconductor, a high-resistivity material layer or insertion layer, a first semiconductor, and a second semiconductor may be sequentially grown along a predetermined direction. Alternatively, a first semiconductor, a second semiconductor, a high-resistivity material layer, an insertion layer, a fourth semiconductor, and a fifth semiconductor may be sequentially grown along a predetermined direction to form a stacked arrangement. Alternatively, a fourth semiconductor, a fifth semiconductor, a high-resistivity material layer, an insertion layer, a first semiconductor, and a second semiconductor may be sequentially grown along a predetermined direction to form a stacked arrangement. The first semiconductor and the second semiconductor cooperate to form a first heterojunction, and the fourth semiconductor and the fifth semiconductor cooperate to form a second heterojunction.

43. The manufacturing method according to claim 42, characterized in that, Specifically, it includes: A continuous third semiconductor layer is formed on the second semiconductor, the third semiconductor layer including a first region and a second region, and the first region is transformed to form the high-resistivity material layer; or, a continuous high-resistivity material layer is formed on the second semiconductor, the high-resistivity material layer including a first region and a second region, and the second region is transformed to form the third semiconductor.

44. The manufacturing method according to claim 42, characterized in that, Specifically, it includes: A continuous sixth semiconductor layer is formed on the fifth semiconductor, the sixth semiconductor layer including a third region and a fourth region, and the third region is subjected to a conversion process to form the high-resistivity material layer; Alternatively, a continuous high-resistivity material layer is formed on the fifth semiconductor, the high-resistivity material layer including a third region and a fourth region, and the fourth region is transformed to form the sixth semiconductor.

45. The manufacturing method according to claim 43 or 44, characterized in that: The methods for performing the conversion treatment include any one or more combinations of H ion implantation, H plasma treatment, H doping annealing, N ion implantation, F ion implantation, Ar ion implantation, Fe ion implantation, O plasma treatment, and thermal oxidation.

46. ​​The manufacturing method according to claim 42, characterized in that, Also includes: The third semiconductor is patterned to form a strip array structure.

47. The manufacturing method according to claim 42, characterized in that, Also includes: The third semiconductor and a high-resistivity material layer are selectively epitaxially grown on the second semiconductor. Alternatively, the sixth semiconductor and a high-resistivity material layer may be selectively epitaxially grown on the fifth semiconductor.

48. The manufacturing method according to claim 47, characterized in that, The fabrication method further includes: forming an insertion layer on the high-resistivity material layer, and then fabricating a first heterojunction or a second heterojunction on the insertion layer.

49. The manufacturing method according to claim 48, characterized in that: The insertion layer includes any one of a metal layer, a dielectric layer, or a two-dimensional material layer.

50. The manufacturing method according to claim 49, characterized in that: The metal layer includes a single metal layer or a multi-layer metal layer stacked together, and the material of the metal layer includes any one of Mo, Mg, and Al.

51. The manufacturing method according to claim 49, characterized in that: The thickness of the metal layer is 2 nm to 10 μm.

52. The manufacturing method according to claim 49, characterized in that: The dielectric layer is made of any one of AlN, BN, AlBN, AlPN, BCN, high-resistivity AlGaN, and high-resistivity GaN.

53. The manufacturing method according to claim 49, characterized in that: The thickness of the dielectric layer is 0.5 nm to 1 μm.

54. The manufacturing method according to claim 49, characterized in that: The material of the two-dimensional material layer includes any one of BN, graphene, fluorinated graphene, graphene oxide, and black phosphorus.

55. The manufacturing method according to claim 49, characterized in that: The thickness of the two-dimensional material layer is 0.5 nm to 500 nm.

56. The manufacturing method according to claim 42, characterized in that: The third semiconductor is further electrically isolated from the second electrode via the high-resistivity material, or the sixth semiconductor is further electrically isolated from the source and drain via the high-resistivity material.

57. The manufacturing method according to claim 42, characterized in that: The third and sixth semiconductors are p-type semiconductors.

58. The manufacturing method according to claim 42, characterized in that: The materials of the third and sixth semiconductors include p-type wide bandgap semiconductors.

59. The manufacturing method according to claim 58, characterized in that: The p-type wide bandgap semiconductor includes p-type group III nitrides.

60. The manufacturing method according to claim 59, characterized in that: The p-type group III nitrides include p-type GaN, p-type AlGaN, p-type InGaN, or p-type InN.

61. The manufacturing method according to claim 57, characterized in that: The p-type semiconductor includes p-type polycrystalline silicon, p-type amorphous silicon, p-type oxide, p-type diamond, or p-type semiconductor polymer.

62. The manufacturing method according to claim 42 or 56, characterized in that: The high-resistivity material includes high-resistivity GaN, high-resistivity AlGaN, high-resistivity Ga2O3, high-resistivity InGaN, or high-resistivity InN.

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