IGBT device and method of manufacturing the same

Abstract

The application belongs to the technical field of semiconductor power devices, and particularly discloses an IGBT device and a manufacturing method thereof. The IGBT device comprises a cell region and a terminal region. The cell region comprises a p-type collector region, an n-type semiconductor layer located above the p-type collector region, a plurality of gate trenches located in the n-type semiconductor layer, shielding gates located in lower portions of the gate trenches and gates located in upper portions of the gate trenches, the gates, the shielding gates and the n-type semiconductor layer being insulated from each other, a p-type body region located in the n-type semiconductor layer and between adjacent gate trenches, the p-type body region being provided with an n-type emitter region, and an n-type charge storage region located in the n-type semiconductor layer and between adjacent shielding gates. Part of the shielding gates is provided with the n-type charge storage region, the n-type charge storage region is arranged on one side of the p-type body region adjacent to the p-type collector region, and part of the shielding gates is not provided with the n-type charge storage region.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor power device technology, and in particular relates to an IGBT device and its manufacturing method. Background Technology

[0002] An Insulated Gate Bipolar Transistor (IGBT) is a composite device made of a Metal Oxide Semiconductor (MOS) transistor and a bipolar transistor. The input electrode of an IGBT is a MOS transistor, and the output electrode is a PNP transistor. It combines the advantages of both types of transistors: the low drive power and fast switching speed of MOS transistors, and the low saturation voltage drop and large capacitance of bipolar transistors. Existing IGBT devices typically introduce an n-type charge storage region beneath the p-type body region. The introduction of the n-type charge storage region provides a hole barrier, increasing the surface carrier concentration, improving the carrier distribution in the device's drift region, and reducing the on-state voltage drop. However, the presence of the n-type charge storage region prevents holes from being rapidly removed by the emitter during IGBT turn-off, reducing the switching speed and increasing switching losses. Summary of the Invention

[0003] In view of this, the purpose of the present invention is to provide an IGBT device and a method for manufacturing the same, so as to reduce the switching losses of the IGBT device.

[0004] To achieve the above-mentioned objectives of this invention, this invention provides an IGBT device, comprising a cell region and a termination region, wherein the cell region includes:

[0005] p-type collector region;

[0006] An n-type semiconductor layer located above the p-type collector region;

[0007] A plurality of gate trenches are located within the n-type semiconductor layer, a shielding gate is located in the lower part of the gate trenches and a gate is located in the upper part of the gate trenches, wherein the gate, the shielding gate and the n-type semiconductor layer are mutually insulated and isolated from each other;

[0008] A p-type body region is located within the n-type semiconductor layer and between adjacent gate trenches, and an n-type emitter region is provided within the p-type body region;

[0009] n-type charge storage regions located in the n-type semiconductor layer and between adjacent shield gates, wherein the n-type charge storage regions are provided between some of the shield gates, and the n-type charge storage regions are provided on one side of the p-type body region adjacent to the p-type collector region, and some of the shield gates are not provided with the n-type charge storage regions.

[0010] Optionally, the shield gates are located in the lower part of the gate trench and extend upwardly into the upper part of the gate trench.

[0011] Optionally, the width of the upper part of the gate trench is greater than the width of the lower part of the gate trench.

[0012] Optionally, the gate is located in the region of the upper part of the gate trench beyond the lower part of the gate trench.

[0013] Optionally, the n-type charge storage regions are located below the gate, and some of the gate is not provided with the n-type charge storage regions.

[0014] Optionally, further comprising an n-type field stop region located between the p-type collector region and the n-type semiconductor layer.

[0015] Optionally, further comprising an n-type collector region located below the n-type semiconductor layer and alternately spaced apart from the p-type collector region.

[0016] Optionally, the n-type charge storage regions are not provided in the termination region.

[0017] The application also provides a manufacturing method of an IGBT device, characterized in that the method comprises:

[0018] providing a first n-type semiconductor layer;

[0019] defining the position of the n-type charge storage regions by a photolithography process, and then performing ion implantation to form the n-type charge storage regions in the first n-type semiconductor layer;

[0020] forming a second n-type semiconductor layer on the first n-type semiconductor layer;

[0021] forming a gate trench, shield gates and gates in the gate trench in the first n-type semiconductor layer and the second n-type semiconductor layer, and making some of the shield gates provided with the n-type charge storage regions, and some of the shield gates not provided with the n-type charge storage regions.

[0022] The IGBT device of the present application is provided with n-type charge storage regions between partial shield gates to improve drift region carrier distribution and reduce on-state voltage drop of the device, and no n-type charge storage regions are provided between partial shield gates so that holes can be quickly extracted by the collector when the device is turned off, thereby improving switching speed and reducing switching loss. The manufacturing method of the IGBT device of the present application forms n-type charge storage regions in the first n-type semiconductor layer in advance, and can accurately control the position and concentration of the n-type charge storage regions. BRIEF DESCRIPTION OF DRAWINGS

[0023] In order to more clearly illustrate the technical solutions of the exemplary embodiments of the present application, the drawings needed in the description of the embodiments are briefly introduced as follows.

[0024] Figure 1 is a cross-sectional structure schematic diagram of a first embodiment of the IGBT device provided by the present application;

[0025] Figure 2 is a cross-sectional structure schematic diagram of a second embodiment of the IGBT device provided by the present application;

[0026] Figures 3-5 is a cross-sectional structure schematic diagram of main process nodes in an embodiment of the manufacturing method of the IGBT device provided by the present application. DETAILED DESCRIPTION

[0027] The technical solutions of the present application will be described in detail below with reference to the drawings in the embodiments of the present application, by specific means. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. Meanwhile, in order to clearly illustrate the specific embodiments of the present application, the thickness of the layers and regions described in the present application is exaggerated in the schematic diagrams listed in the drawings, and the sizes of the listed diagrams do not represent actual sizes.

[0028] Figure 1 is a cross-sectional structure schematic diagram of a first embodiment of the IGBT device provided by the present application, the IGBT device provided by the present application includes a cell region and a termination region, Figure 1 only the structure of the cell region is exemplarily shown, as Figure 1 as shown, the cell region of the IGBT device of the present application includes a p-type collector region 20, an n-type semiconductor layer 21 located above the p-type collector region 20, and a plurality of gate trenches located in the n-type semiconductor layer 21, Figure 1 only three gate trench structures are exemplarily shown. A shield gate 27 located in the lower part of the gate trench and a gate 25 located in the upper part of the gate trench, the gate 25, the shield gate 27 and the n-type semiconductor layer 21 are mutually insulated and separated, Figure 1In the embodiment, the gate 25 is insulated and separated from the n-type semiconductor layer 21 and the shielding gate 27 by the gate dielectric layer 24, and the shielding gate 27 is separated from the n-type semiconductor layer 21 by the field oxide layer 26, and the thickness of the field oxide layer 26 is usually greater than the thickness of the gate dielectric layer 24.

[0029] The p-type body region 22 is located in the n-type semiconductor layer 21 and between adjacent gate trenches, and the n-type emitter region 23 is arranged in the p-type body region 22.

[0030] The n-type charge storage region 32 is located in the n-type semiconductor layer 21 and between adjacent shielding gates 27, and the n-type charge storage region 32 is arranged on one side of the p-type body region 22 adjacent to the p-type collector region 20, and the n-type charge storage region is not arranged between some of the shielding gates 27. Figure 1 In the embodiment, the n-type charge storage region 32 is arranged between the two shielding gates 27 on the left side as an example.

[0031] The IGBT device of the present application has the n-type charge storage region arranged between some of the shielding gates to improve the carrier distribution in the drift region, thereby reducing the on-state voltage drop of the IGBT device, and the n-type charge storage region is not arranged between some of the shielding gates, so that the holes can be quickly extracted by the collector when the IGBT device is turned off, thereby improving the switching speed of the IGBT device and reducing the switching loss.

[0032] The IGBT device of the present application can not have the n-type charge storage region arranged in the terminal region, which can make the IGBT device have more stable and controllable withstand voltage.

[0033] Figure 2 is a cross-sectional structure schematic diagram of a second embodiment of the IGBT device provided by the present application, as Figure 2 As shown in the figure, the shielding gate 27 is located in the lower part of the gate trench and extends upward to the upper part of the gate trench, at this time, the width of the upper part of the gate trench can be greater than the width of the lower part of the gate trench, and the gate 25 is located in the area of the upper part of the gate trench beyond the lower part of the gate trench, at this time, preferably, the n-type charge storage region 32 is located below the gate 25. And the n-type charge storage region is arranged below part of the gate 25, and the n-type charge storage region is not arranged below part of the gate 25. Figure 2The example illustrates that only the two middle gates 25 have an n-type charge storage region 32 below them, while the other gates 25 do not have an n-type charge storage region below them. The IGBT device of the present invention may further include an n-type collector region 30, which is located below the n-type semiconductor layer 21 and alternately spaced with the p-type collector region 20. Optionally, the IGBT device of the present invention may further include an n-type field-stop region 31, which is located between the p-type collector region 20 and the n-type semiconductor layer 21. Both the n-type field-stop region 31 and the n-type collector region 30 are known technologies and will not be described in detail in the embodiments of the present invention.

[0034] This invention also proposes a method for manufacturing IGBT devices. Figures 3-5 This is a cross-sectional structural diagram of the main process nodes in one embodiment of the manufacturing method of the IGBT device provided by the present invention.

[0035] First, such as Figure 3 As shown, a first n-type semiconductor layer 21a is provided, and then the position of the n-type charge storage region is defined by photolithography. Then, ion implantation is performed in the first n-type semiconductor layer 21a to form the n-type charge storage region 32. Figure 3 The example shows the location of the final formed n-type charge storage region. Optionally, the injection area of ​​the n-type charge storage region can be increased in this step, as long as the portion of the n-type charge storage region that coincides with the location of the gate trench is etched away when the gate trench is formed subsequently.

[0036] Next, as Figure 4 As shown, a second n-type semiconductor layer 21b is formed on the first n-type semiconductor layer 21a, and the first n-type semiconductor layer 21a and the second n-type semiconductor layer 21b together constitute the n-type semiconductor layer in the IGBT device of the present invention.

[0037] Next, as Figure 5 As shown, a gate trench is formed in the n-type semiconductor layer 21, which is composed of the first n-type semiconductor layer and the second n-type semiconductor layer, as well as a shielding gate 27, a gate 25, a gate dielectric layer 24, and a field oxide layer 26 located in the gate trench. This process is a conventional process in the industry and will not be described in detail in this embodiment of the invention. However, it should be noted that the position of the gate trench needs to be controlled in this step so that an n-type charge storage region 32 is provided between some of the shielding gates 27, and no n-type charge storage region is provided between some of the shielding gates 27. At the same time, by pre-controlling the position of the formed n-type charge storage region, it is possible to ensure that no n-type charge storage region is provided in the terminal area of ​​the IGBT device.

[0038] Next, a p-type body region can be formed within the n-type semiconductor layer 21. The p-type body region is located within the n-type semiconductor layer 21 and between adjacent gate trenches. The p-type body region is located on the side of the n-type charge storage region 32 away from the p-type collector region. Then, an n-type emitter region is formed within the p-type body region.

[0039] Finally, the IGBT device can be manufactured using conventional processes.

[0040] The above specific implementation methods and embodiments are specific support for the technical concept of the present invention, and should not be used to limit the scope of protection of the present invention. Any equivalent changes or modifications made on the basis of the technical solution based on the technical concept proposed by the present invention shall still fall within the scope of protection of the technical solution of the present invention.

Claims

1. An IGBT device, characterized in that, It includes a cell region and a terminal region, wherein the cell region includes: p-type collector region; An n-type semiconductor layer located above the p-type collector region; A plurality of gate trenches are located within the n-type semiconductor layer, a shielding gate is located in the lower part of the gate trenches and a gate is located in the upper part of the gate trenches, wherein the gate, the shielding gate and the n-type semiconductor layer are mutually insulated and isolated from each other; A p-type body region is located within the n-type semiconductor layer and between adjacent gate trenches, and an n-type emitter region is provided within the p-type body region; An n-type charge storage region is located within the n-type semiconductor layer and between adjacent shielding gates, wherein the n-type charge storage region is provided between some of the shielding gates, the n-type charge storage region is located on the side of the p-type body region adjacent to the p-type collector region, and the n-type charge storage region is not provided between some of the shielding gates; The shielding grid is located in the lower part of the grid trench and extends upward into the upper part of the grid trench; The width of the upper part of the gate trench is greater than the width of the lower part of the gate trench; The gate is located in the region above the gate trench that extends beyond the lower part of the gate trench; The n-type charge storage region is located below the gate. The n-type charge storage region is provided below some of the gates, while the n-type charge storage region is not provided below some of the gates. The same gate trench includes a shielding gate and two gates respectively disposed on both sides of the shielding gate. The n-type charge storage region is located below the two gates on both sides of the same shielding gate.

2. The IGBT device as described in claim 1, characterized in that, It also includes an n-type field cutoff region, which is located between the p-type collector region and the n-type semiconductor layer.

3. The IGBT device as described in claim 1, characterized in that, It also includes an n-type collector region, which is located below the n-type semiconductor layer and is alternately spaced with the p-type collector region.

4. The IGBT device as described in claim 1, characterized in that, The terminal area does not contain the n-type charge storage area.

5. A method for manufacturing an IGBT device, characterized in that, include: Provide a first n-type semiconductor layer; The location of the n-type charge storage region is defined by photolithography, and then ion implantation is performed to form the n-type charge storage region in the first n-type semiconductor layer; A second n-type semiconductor layer is formed on the first n-type semiconductor layer; A gate trench and a shielding gate and a gate are formed within the first n-type semiconductor layer and the second n-type semiconductor layer, respectively, such that an n-type charge storage region is provided between some of the shielding gates, and no n-type charge storage region is provided between some of the shielding gates; the shielding gate is located in the lower part of the gate trench and extends upward into the upper part of the gate trench; the width of the upper part of the gate trench is greater than the width of the lower part of the gate trench; the gate is located in the region of the upper part of the gate trench that extends beyond the lower part of the gate trench. The n-type charge storage region is located below the gate. The n-type charge storage region is provided below some of the gates, while the n-type charge storage region is not provided below some of the gates. The same gate trench includes a shielding gate and two gates respectively disposed on both sides of the shielding gate. The n-type charge storage region is located below the two gates on both sides of the same shielding gate.

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