A SiC super junction device

Abstract

The application provides a SiC super junction device, which comprises an N-type substrate, an N column region, a P column region, a source electrode, a gate trench oxide, a super junction trench structure, a super junction trench oxide, a polysilicon gate, a P-body region, a P+ contact region, an N+ contact region and a drain electrode. The SiC super junction device provided by the application solves the problem that a conventional ion implantation process or a deep trench etching and filling process is difficult to form a super junction N / P column structure with an ideal depth, that is, it is difficult to obtain a super junction N / P column structure with a high aspect ratio, and that is, it is difficult to realize an ideal breakdown voltage-on resistance compromise.

Description

Technical Field

[0001] This invention belongs to the field of power semiconductor device technology, specifically a SiC superjunction device. Background Technology

[0002] As one of the representatives of third-generation wide-bandgap semiconductor materials, silicon carbide (SiC) boasts advantages over silicon, including a wider bandgap (3 times), a higher critical electric field (10 times), a higher carrier saturation drift velocity (2 times), and higher thermal conductivity (2.5 times). It is an excellent material for fabricating high-voltage power electronic devices and has broad application prospects in high-power, high-temperature, high-voltage, and radiation-resistant power electronics fields. SiC power devices, with their lower switching losses, higher frequency characteristics, lower on-resistance, and excellent high-temperature characteristics, have become a highly competitive new generation of low-loss power devices. However, despite these advantages, SiC devices also present several challenges.

[0003] Despite the industry's efforts to overcome the breakdown voltage (BV) and on-resistance (R) of semiconductor materials ON The one-dimensional limiting relationship between ions and poles led to the development of superjunction structures, which have been widely used in Si-based devices. However, due to the extremely stable chemical and physical properties of SiC, conventional ion implantation or deep trench etching processes are insufficient to form superjunction N / P pillars of ideal depth, i.e., it is difficult to form superjunction N / P pillar structures with high aspect ratios. Therefore, it is difficult to achieve the ideal BV-R structure. ON Compromise.

[0004] In view of this, the present invention designs a SiC superjunction device that can realize a superjunction N / P pillar structure with a high aspect ratio. Summary of the Invention

[0005] The purpose of this invention is to propose a SiC superjunction device that forms a P-pillar region through ion implantation inside the superjunction trench structure. This solves the problem that the extremely stable chemical and physical properties of SiC material make it difficult to form superjunction N / P pillars of ideal depth using conventional ion implantation or deep trench etching processes, thus hindering the achievement of ideal BV-R (Browser-Vehicle-Return) superjunctions. ON The issue involves trade-offs. The width and doping concentration of the P-pillar region can be optimized by adjusting the ion implantation energy, angle, and dose.

[0006] To achieve the above-mentioned objectives, the first SiC superjunction device provided by this invention is:

[0007] A SiC superjunction device includes: an N-type substrate 10, an N-pillar region 9 located above the N-type substrate 10, and P-pillar regions 7 located on both sides of the N-pillar region 9, wherein the P-pillar regions 7 are formed by ion implantation inside a superjunction trench structure 8; a superjunction trench structure 8 located above the P-pillar regions 7, a superjunction trench oxide 12 located inside the superjunction trench structure 8, a source electrode 1 above the superjunction trench oxide 12, a gate trench oxide 6 located between adjacent P-pillar regions 7 above the N-pillar region 9, a polysilicon gate 2 located inside the gate trench oxide 6, a P-body region 3 located between the gate trench oxide 6 and the superjunction trench structure 8 above the N-pillar region 9, a P+ contact region 4 and an N+ contact region 5 located above the P-body region 3 and forming an ohmic contact with the source electrode 1, and a drain electrode 11 located below the N-type substrate 10 and forming an ohmic contact with the N-type substrate 10.

[0008] As a preferred embodiment, a potential shielding region 13 is provided above the P-pillar region 7. The potential shielding region 13 is formed by ion implantation inside the superjunction trench structure 8. The potential shielding region 13 is above the P-pillar region 7 and below the superjunction trench structure 8. The potential shielding region 13, the P-pillar region 7, and the superjunction trench structure 8 are completed under the same mask. The width of the potential shielding region 13 is wider than the width of the P-pillar region 7.

[0009] As a preferred embodiment, the injection depth of the P-pillar region 7 is less than the depth of the N-pillar region 9, forming a semi-superjunction structure.

[0010] To achieve the above-mentioned objectives, the present invention also provides a second SiC superjunction device, comprising: an N-type substrate 10, an N-pillar region 9 located above the N-type substrate 10, and P-pillar regions 7 located on both sides of the N-pillar region 9, wherein the P-pillar regions 7 are formed by ion implantation inside a superjunction trench structure 8; a superjunction trench structure 8 located above the P-pillar regions 7, and a source electrode 1 located above the superjunction trench structure 8, a gate trench oxide 6 located between adjacent P-pillar regions 7 above the N-pillar region 9, a polysilicon gate 2 located inside the gate trench oxide 6, a P-body region 3 located between the gate trench oxide 6 and the superjunction trench structure 8 above the N-pillar region 9, a P+ contact region 4 and an N+ contact region 5 located above the P-body region 3 and forming an ohmic contact with the source electrode 1, and a drain electrode 11 located below the N-type substrate 10 and forming an ohmic contact with the N-type substrate 10; wherein the source electrode 1 is in direct contact with the P-body region 3 and the P-pillar regions 7 and forms an ohmic contact.

[0011] As a preferred embodiment, a Schottky contact region 14 is formed by ion implantation above the P-pillar region 7, below the P-body region 3, and on the side of the source electrode 1, and the Schottky contact region 14 forms a Schottky contact with the source electrode 1.

[0012] To achieve the above-mentioned objectives, the present invention also provides a third type of SiC superjunction device, comprising: an N-type substrate 10, an N-pillar region 9 located above the N-type substrate 10, and P-pillar regions 7 located on both sides of the N-pillar region 9, wherein the P-pillar regions 7 are formed by ion implantation inside a superjunction trench structure 8; a superjunction trench structure 8 located above the P-pillar regions 7, a superjunction trench oxide 12 located inside the superjunction trench structure 8, a source electrode 1 located above the superjunction trench structure 8, a gate trench oxide 6 located between adjacent P-pillar regions 7 above the N-pillar region 9, a polysilicon gate 2 located inside the gate trench oxide 6, a P-body region 3 located between the gate trench oxide 6 and the superjunction trench structure 8 above the N-pillar region 9, a P+ contact region 4 and an N+ contact region 5 located above the P-body region 3 and forming an ohmic contact with the source electrode 1, and a drain electrode 11 located below the N-type substrate 10 and forming an ohmic contact with the N-type substrate 10; wherein the source electrode 1 is in direct contact with the P-body region 3 and the P-pillar regions 7 and forms an ohmic contact.

[0013] The P-pillar region 7 is not grounded by connecting to the P-body region 3. Instead, the superjunction trench oxide layer 12 at the bottom of the superjunction trench structure 8 is etched away. A second P+ contact region 15 is provided in the P-pillar region 7. The second P+ contact region (15) is located above the inside of the P-pillar region 7 and below the source metal 1, and forms an ohmic contact with the source metal 1. The P-pillar region 7 is electrically connected and grounded through the second P+ contact region 15 and the source metal 1.

[0014] As a preferred embodiment, a second N+ contact area 16 is provided within the P-pillar region 7, the second N+ contact area 16 is located on the side of the second P+ contact area 15, and a channel diode 17 is provided above the second N+ contact area 16.

[0015] As a preferred embodiment, the P-pillar region 7 can be completed under the same mask as the superjunction trench structure 8.

[0016] As a preferred embodiment, the gate trench oxide 6 and the superjunction trench oxide 12 are SiO2.

[0017] As a preferred embodiment, the doping types in the device are correspondingly reversed, that is, P-type doping is changed to N-type doping while N-type doping is changed to P-type doping.

[0018] The device is made of SiC material, but other semiconductor materials may also be used.

[0019] The device has a polysilicon terminal as the gate, an N+ substrate terminal as the drain, and an N+ contact region and a P+ contact region as the source.

[0020] The beneficial effects of this invention are as follows:

[0021] By combining trench etching with ion implantation, the problem of difficulty in forming superjunction N / P pillars of ideal depth and high aspect ratio due to the extremely stable chemical and physical properties of SiC material, which makes it difficult to achieve the ideal breakdown voltage-on resistance tradeoff, is solved. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of the device structure in Embodiment 1 of the present invention;

[0023] Figure 2 This is a schematic diagram of the device structure in Embodiment 2 of the present invention;

[0024] Figure 3 This is a schematic diagram of the device structure in Embodiment 3 of the present invention;

[0025] Figure 4 This is a schematic diagram of the device structure in Embodiment 4 of the present invention;

[0026] Figure 5 This is a schematic diagram of the device structure in Embodiment 5 of the present invention;

[0027] Figure 6 This is a schematic diagram of the device structure in Embodiment 6 of the present invention;

[0028] Figure 7 This is a schematic diagram of the device structure in Embodiment 7 of the present invention.

[0029] In this diagram, 1 is the source electrode, 2 is the polysilicon gate, 3 is the P-body region, 4 is the P+ contact region, 5 is the N+ contact region, 6 is the gate trench oxide, 7 is the P-pillar region, 8 is the superjunction trench structure, 9 is the N-pillar region, 10 is the N-type substrate, 11 is the drain electrode, 12 is the superjunction trench oxide, 13 is the potential shielding region, 14 is the Schottky contact region, 15 is the second P+ contact region, 16 is the second N+ contact region, and 17 is the channel diode. Detailed Implementation

[0030] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0031] Example 1

[0032] like Figure 1As shown, a SiC superjunction device according to this embodiment includes: an N-type substrate 10, an N-pillar region 9 located above the N-type substrate 10, and P-pillar regions 7 located on both sides of the N-pillar region 9. The P-pillar regions 7 are formed by ion implantation inside a superjunction trench structure 8. The superjunction trench structure 8 is located above the P-pillar regions 7. The superjunction trench oxide 12 is located inside the superjunction trench structure 8. The source electrode 1 is located above the superjunction trench oxide 12. The gate trench oxide 6 is located between adjacent P-pillar regions 7 above the N-pillar region 9. The polysilicon gate 2 is located inside the gate trench oxide 6. The P-body region 3 is located between the gate trench oxide 6 and the superjunction trench structure 8 above the N-pillar region 9. The P+ contact region 4 and N+ contact region 5 are located above the P-body region 3 and form an ohmic contact with the source electrode 1. The drain electrode 11 is located below the N-type substrate 10 and forms an ohmic contact with the N-type substrate 10.

[0033] Preferably, the P-pillar region 7 can be completed under the same mask as the superjunction trench structure 8.

[0034] Preferably, the gate trench oxide 6 and the superjunction trench oxide 12 are SiO2.

[0035] Preferably, the doping types in the device are changed to opposite doping types, that is, P-type doping is changed to N-type doping while N-type doping is changed to P-type doping.

[0036] The beneficial effects of this example are:

[0037] By forming the P-pillar region 7 through ion implantation inside the superjunction trench structure 8, the problem of difficulty in forming superjunction N / P pillars of ideal depth due to the extremely stable chemical and physical properties of SiC material, which makes it difficult to obtain a superjunction N / P pillar structure with a high aspect ratio and thus difficult to achieve the ideal breakdown voltage-on resistance tradeoff is solved.

[0038] Example 2

[0039] like Figure 2 As shown, the difference between this embodiment and Embodiment 1 is that: a potential shielding region 13 is provided above the P-pillar region 7; the potential shielding region 13 is formed by ion implantation inside the superjunction trench structure 8; the potential shielding region 13 is above the P-pillar region 7 and below the superjunction trench structure 8; the potential shielding region 13, the P-pillar region 7, and the superjunction trench structure 8 are completed under the same mask; the width of the potential shielding region 13 is wider than the width of the P-pillar region 7. This improves the gate oxide reliability of the device.

[0040] Example 3:

[0041] like Figure 3As shown, the difference between this embodiment and Embodiment 1 is that the implantation depth of the P-pillar region 7 is less than the depth of the N-pillar region 9, forming a semi-superjunction structure. The advantage of this approach is that it balances the difficulty of fabrication with device performance, reducing the fabrication difficulty and cost of the device.

[0042] Example 4:

[0043] like Figure 4 As shown, this embodiment provides a SiC superjunction device, including: an N-type substrate 10, an N-pillar region 9 located above the N-type substrate 10, and P-pillar regions 7 located on both sides of the N-pillar region 9. The P-pillar regions 7 are formed by ion implantation inside a superjunction trench structure 8; a superjunction trench structure 8 located above the P-pillar regions 7, and a source electrode 1 located above the superjunction trench structure 8; a gate trench oxide 6 located between adjacent P-pillar regions 7 above the N-pillar region 9; a polysilicon gate 2 located inside the gate trench oxide 6; a P-body region 3 located between the gate trench oxide 6 and the superjunction trench structure 8 above the N-pillar region 9; a P+ contact region 4 and an N+ contact region 5 located above the P-body region 3 and forming an ohmic contact with the source electrode 1; and a drain electrode 11 located below the N-type substrate 10 and forming an ohmic contact with the N-type substrate 10. The source electrode 1 is in direct contact with the P-body region 3 and the P-pillar regions 7 and forms an ohmic contact.

[0044] Preferably, the P-pillar region 7 can be completed under the same mask as the superjunction trench structure 8.

[0045] Preferably, the gate trench oxide 6 and the superjunction trench oxide 12 are SiO2.

[0046] Preferably, the doping types in the device are changed to opposite doping types, that is, P-type doping is changed to N-type doping while N-type doping is changed to P-type doping.

[0047] The difference between this embodiment and Embodiment 1 is that: there is no superjunction trench oxide 12 in the superjunction trench structure 8, and the source electrode 1 is in direct contact with the P-body region 3 and the P-pillar region 7 to form an ohmic contact. The advantage of doing so is that the resistance between the P-pillar region 7 and the source metal 1 is reduced, thereby improving the switching performance of the device.

[0048] Example 5:

[0049] like Figure 5 As shown, the difference between this embodiment and Embodiment 4 is that a Schottky contact region 14 is formed by ion implantation above the P-pillar region 7, below the P-body region 3, and on the side of the source electrode 1. The Schottky contact region 14 forms a Schottky contact with the source electrode 1. The advantage of doing this is to improve the third quadrant capability of the device.

[0050] Example 6:

[0051] like Figure 6 As shown, this embodiment provides a SiC superjunction device, including: an N-type substrate 10, an N-pillar region 9 located above the N-type substrate 10, and P-pillar regions 7 located on both sides of the N-pillar region 9. The P-pillar regions 7 are formed by ion implantation inside a superjunction trench structure 8; a superjunction trench structure 8 located above the P-pillar regions 7, a superjunction trench oxide 12 located inside the superjunction trench structure 8, a source electrode 1 located above the superjunction trench structure 8, a gate trench oxide 6 located between adjacent P-pillar regions 7 above the N-pillar region 9, a polysilicon gate 2 located inside the gate trench oxide 6, a P-body region 3 located between the gate trench oxide 6 and the superjunction trench structure 8 above the N-pillar region 9, a P+ contact region 4 and an N+ contact region 5 located above the P-body region 3 and forming an ohmic contact with the source electrode 1, and a drain electrode 11 located below the N-type substrate 10 and forming an ohmic contact with the N-type substrate 10; the source electrode 1 is in direct contact with the P-body region 3 and the P-pillar regions 7 and forms an ohmic contact.

[0052] The P-pillar region 7 is not grounded by connecting to the P-body region 3. Instead, the superjunction trench oxide layer 12 at the bottom of the superjunction trench structure 8 is etched away. A second P+ contact region 15 is provided inside the P-pillar region 7. The second P+ contact region (15) is located above the inside of the P-pillar region 7 and below the source metal 1, and forms an ohmic contact with the source metal 1. The P-pillar region 7 is electrically connected to and grounded through the second P+ contact region 15 and the source metal 1. The advantage of this is that it avoids the problem of the P-pillar region 7 becoming detached due to discontinuous ion implantation on the trench sidewall, which would lead to a decrease in the blocking ability of the superjunction structure.

[0053] Preferably, the P-pillar region 7 can be completed under the same mask as the superjunction trench structure 8.

[0054] Preferably, the gate trench oxide 6 and the superjunction trench oxide 12 are SiO2.

[0055] Preferably, the doping types in the device are changed to opposite doping types, that is, P-type doping is changed to N-type doping while N-type doping is changed to P-type doping.

[0056] Example 7:

[0057] like Figure 7 As shown, the difference between this embodiment and embodiment 6 is that a second N+ contact region 16 is provided within the P-pillar region 7. The second N+ contact region 16 is located on the side of the second P+ contact region 15, and a channel diode 17 is provided above the second N+ contact region 16. The channel diode 17 is turned on when the device is operating in freewheeling mode, which improves the device's third quadrant capability.

Claims

1. A SiC superjunction device, characterized in that: include: An N-type substrate (10), an N-pillar region (9) located above the N-type substrate (10), and P-pillar regions (7) located on both sides of the N-pillar region (9), wherein the P-pillar regions (7) are formed by ion implantation inside a superjunction trench structure (8); a superjunction trench structure (8) located above the P-pillar regions (7), and a source electrode (1) located above the superjunction trench structure (8); a gate trench oxide (6) located between adjacent P-pillar regions (7) above the N-pillar region (9); and polysilicon located inside the gate trench oxide (6). The gate (2), the P-body region (3) located above the N-pillar region (9) between the gate trench oxide (6) and the superjunction trench structure (8), the P+ contact region (4) and the N+ contact region (5) located above the P-body region (3) and forming an ohmic contact with the source electrode (1), and the drain electrode (11) located below the N-type substrate (10) and forming an ohmic contact with the N-type substrate (10); the source electrode (1) is in direct contact with the P-body region (3) and the P-pillar region (7) and forms an ohmic contact. A Schottky contact region (14) is formed by ion implantation above the P-pillar region (7), below the P-body region (3), and on the side of the source electrode (1). The Schottky contact region (14) forms a Schottky contact with the source electrode (1).

2. A SiC superjunction device, characterized in that: include: An N-type substrate (10), an N-pillar region (9) located above the N-type substrate (10), and P-pillar regions (7) located on both sides of the N-pillar region (9), wherein the P-pillar regions (7) are formed by ion implantation inside a superjunction trench structure (8); a superjunction trench structure (8) located above the P-pillar regions (7), a superjunction trench oxide (12) located inside the superjunction trench structure (8), and a source electrode (1) above the superjunction trench structure (8), a gate trench oxide (6) located between adjacent P-pillar regions (7) above the N-pillar region (9), and a gate trench oxide (6) located between adjacent P-pillar regions (7) above the N-pillar region (9). The polysilicon gate (2) inside the trench oxide (6), the P-body region (3) between the gate trench oxide (6) and the superjunction trench structure (8) above the N-pillar region (9), the P+ contact region (4) and the N+ contact region (5) above the P-body region (3) and forming an ohmic contact with the source electrode (1), and the drain electrode (11) below the N-type substrate (10) and forming an ohmic contact with the N-type substrate (10); the source electrode (1) is in direct contact with the P-body region (3) and the P-pillar region (7) and forms an ohmic contact; The P-pillar region (7) is not grounded by connecting to the P-body region (3). Instead, the superjunction trench oxide (12) at the bottom of the superjunction trench structure (8) is etched away. A second P+ contact region (15) is provided in the P-pillar region (7). The second P+ contact region (15) is located above the inside of the P-pillar region (7) and below the source electrode (1), and forms an ohmic contact with the source electrode (1). The P-pillar region (7) is electrically connected and grounded through the second P+ contact region (15) and the source electrode (1).

3. A SiC superjunction device according to claim 2, characterized in that: The second N+ contact region (16) is provided in the P-pillar region (7). The second N+ contact region (16) is on the side of the second P+ contact region (15). A channel diode (17) is provided above the second N+ contact region (16). The channel diode (17) is turned on when the device is in freewheeling mode, thereby improving the third quadrant capability of the device. The channel diode (17) is located on the top of the second N+ contact region (16) and on the side of the superjunction trench oxide (12).

4. A SiC superjunction device according to claim 1 or 2, characterized in that: The P-column region (7) can be completed under the same mask as the superjunction trench structure (8).

5. A SiC superjunction device according to claim 1 or 2, characterized in that: The gate trench oxide (6) and the superjunction trench oxide (12) are SiO2.

6. A SiC superjunction device according to claim 1 or 2, characterized in that: The doping types in the device are reversed accordingly, that is, P-type doping becomes N-type doping while N-type doping becomes P-type doping.

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