Single photon avalanche diode integrated with quenching resistor and method of manufacturing the same

Abstract

The application relates to a single photon avalanche diode integrated with a quenching resistor and a manufacturing method thereof, which comprises the following steps: obtaining a wafer; patterning and etching the front surface of a base to form a quenching resistor groove and an isolation groove; the width of the isolation groove is greater than that of the quenching resistor groove; forming an insulating layer on the inner surface of the quenching resistor groove; depositing polysilicon on the front surface of the base, the polysilicon fills the quenching resistor groove and seals the quenching resistor groove, and the polysilicon fills the isolation groove without sealing the isolation groove; oxidizing the polysilicon in the isolation groove; and filling the isolation groove with light-shielding conductive material. The application is compatible with the CMOS process. Since the quenching resistor groove can share a photoetching plate with the isolation groove, the manufacturing of the quenching resistor does not need to use a photoetching plate alone, thereby reducing the production cost.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor manufacturing, in particular to a single photon avalanche diode integrated with quenching resistance and a manufacturing method of the single photon avalanche diode integrated with quenching resistance. BACKGROUND

[0002] At present, the intelligentization of automobiles is the trend, and the assisted driving and automatic driving technologies are increasingly equipped on new vehicle models. The core hardware related thereto is LiDAR (Laser Radar), and the devices constituting the signal collection part of the LiDAR are APD (Avalanche Photon Diode), SPAD (Single Photon Avalanche Diode) and other discrete optoelectronic devices. Compared with the APD technology, the SPAD technology is like digital circuit to analog circuit. It has the advantages of high gain, easy integration, low power consumption, small temperature influence, etc., so that its application prospect is more extensive.

[0003] In order to be able to continuously detect and respond to the next photon signal in time, the SPAD needs to be configured with a quenching circuit to quickly quench the avalanche after the avalanche occurs, so that the SPAD returns to the state of accepting photons. Among the many quenching methods, passive quenching circuit is the simplest one. Its principle is shown in Figure 4 The SPAD has a quenching resistance R L .

[0004] The exemplary SPAD process needs to introduce tungsten plug DTI (Deep Trench Isolation) process to isolate the APD sub-cell, but because the quenching resistance needs to be formed, it needs to deposit polysilicon for the quenching resistance after the tungsten plug DTI metal process, which is contrary to the metal process control rules of the traditional semiconductor factory, resulting in that the process cannot be compatible with the traditional semiconductor process production line. SUMMARY

[0005] Therefore, it is necessary to provide a manufacturing method of a single photon avalanche diode integrated with quenching resistance which can be compatible with CMOS (Complementary Metal Oxide Semiconductor) process.

[0006] A method for manufacturing a single photon avalanche diode integrated with quenching resistance, comprising: obtaining a wafer; the wafer comprising a substrate and an avalanche photodiode cell formed in the substrate; patterning and etching a first surface of the substrate to form a quenching resistance trench and an isolation trench; the width of the isolation trench is greater than the width of the quenching resistance trench; forming an insulating layer on the inner surface of the quenching resistance trench; depositing polysilicon on the first surface of the substrate, the polysilicon fills the quenching resistance trench and seals the quenching resistance trench, and the polysilicon fills the isolation trench without sealing the isolation trench; performing oxidation treatment on the exposed structure in the isolation trench; filling the isolation trench with light-shielding conductive material; wherein the isolation trench is located outside the avalanche photodiode cell and the quenching resistance trench, and is used to isolate the avalanche photodiode cell and the quenching resistance.

[0007] The above-mentioned method for manufacturing a single photon avalanche diode integrated with quenching resistance forms a polysilicon quenching resistance in the quenching resistance trench. Since the width of the isolation trench is greater than the width of the quenching resistance trench, when the quenching resistance trench is filled with polysilicon, there is still space in the isolation trench for subsequent filling of light-shielding conductive material. The polysilicon in the isolation trench will be oxidized as an insulating layer when the isolation trench is subjected to oxidation treatment, and since the quenching resistance trench is filled with polysilicon, only the surface of the polysilicon in the quenching resistance trench will be oxidized when the polysilicon in the isolation trench is oxidized, and the polysilicon in the quenching resistance trench can remain as a polysilicon quenching resistance. In summary, the above-mentioned method for manufacturing a single photon avalanche diode integrated with quenching resistance can realize the deposition of a polysilicon quenching resistance before the deposition of light-shielding conductive material, and is compatible with CMOS technology.

[0008] In one of the embodiments, the avalanche photodiode cell comprises an avalanche photodiode cathode region, and the method further comprises: forming a dielectric layer covering the light-shielding conductive material on the first surface of the substrate; forming a cathode contact hole and a quenching resistance contact hole; the bottom of the cathode contact hole extends to the avalanche photodiode cathode region, and the bottom of the quenching resistance contact hole extends to the polysilicon in the quenching resistance trench; the cathode contact hole and the quenching resistance contact hole are filled with a first conductive material; forming a metal layer on the dielectric layer, and part of the structure of the metal layer is electrically connected to the first conductive material in the cathode contact hole and the quenching resistance contact hole; forming a light incident window on the first surface of the substrate by removing the dielectric layer above part of the area of the avalanche photodiode cathode region, so that external light can be incident on the avalanche photodiode cathode region through the light incident window.

[0009] In one of the embodiments, the first conductive material comprises tungsten.

[0010] In one embodiment, the step of forming the cathode contact hole and the quench resistance contact hole, the cathode contact hole includes a first contact hole on one side of the light entrance window and a second contact hole on the other side.

[0011] In one embodiment, the step of patterning and etching the first side of the substrate to form the quench resistance trench and the isolation trench includes: forming a quench resistance trench etching window and an isolation trench etching window in a photoresist on the first side of the substrate by a first photomask, the isolation trench etching window having a width greater than the width of the quench resistance trench etching window; etching the substrate through the quench resistance trench etching window and the isolation trench etching window to form the quench resistance trench and the isolation trench; wherein the depth of the isolation trench is greater than the depth of the quench resistance trench.

[0012] In one embodiment, the light blocking conductive material has a light transmittance lower than that of silicon and silicon dioxide.

[0013] In one embodiment, the light blocking conductive material includes tungsten.

[0014] In one embodiment, the step of obtaining the wafer, the substrate of the obtained wafer includes a substrate of a second conductivity type and an epitaxial layer on the substrate, the epitaxial layer having the second conductivity type, the avalanche photodiode cathode region being located in the epitaxial layer and having a first conductivity type; the first conductivity type and the second conductivity type are opposite conductivity types.

[0015] In one embodiment, the step of obtaining the wafer, the avalanche photodiode cell of the obtained wafer further includes: a second conductivity type well region located on both sides of the avalanche photodiode cathode region; a second conductivity type buried layer located in the epitaxial layer below the avalanche photodiode cathode region; wherein the doping concentration of the epitaxial layer is less than the doping concentration of the substrate and the second conductivity type buried layer.

[0016] In one embodiment, the step of obtaining the wafer, the avalanche photodiode cell of the obtained wafer further includes a ring-shaped doped region located in the epitaxial layer, the ring-shaped doped region being located inside the second conductivity type well regions on both sides of the avalanche photodiode cathode region, the ring-shaped doped region having the first conductivity type.

[0017] In one of the embodiments, before the step of patterning and etching the first surface of the substrate, the method further comprises the steps of forming a light-transmissive silicon nitride layer on the first surface of the substrate, and forming a hard mask on the light-transmissive silicon nitride layer; the step of patterning and etching the first surface of the substrate to form the quenching resistance trench and the isolation trench comprises the steps of photoetching on the hard mask, and etching the hard mask, the light-transmissive silicon nitride layer and the substrate to form the quenching resistance trench and the isolation trench.

[0018] In one of the embodiments, the material of the hard mask comprises silicon oxide; after the step of forming the quenching resistance trench and the isolation trench, and before the step of forming the insulating layer on the inner surface of the quenching resistance trench, the method further comprises the steps of: oxidizing the inner surface of the quenching resistance trench and the inner surface of the isolation trench; and wet-removing the oxide layer on the inner surface of the quenching resistance trench and the inner surface of the isolation trench, while removing the hard mask.

[0019] In one of the embodiments, the first conductive type is N-type, and the second conductive type is P-type.

[0020] In one of the embodiments, the step of forming the insulating layer on the inner surface of the quenching resistance trench comprises the step of thermally oxidizing and growing an oxide layer on the inner surface of the quenching resistance trench and the inner surface of the isolation trench.

[0021] In one of the embodiments, before the step of oxidizing the polysilicon in the isolation trench, the method further comprises the step of doping the polysilicon in the quenching resistance trench to adjust the resistivity.

[0022] In one of the embodiments, the step of oxidizing the polysilicon in the isolation trench also oxidizes the polysilicon on the first surface of the substrate.

[0023] An integrated quenching resistance single photon avalanche diode, comprising: a substrate; an avalanche photodiode cell arranged in the substrate; a quenching resistance trench and an isolation trench outside the avalanche photodiode cell and the quenching resistance trench are formed in the substrate, the width of the isolation trench is greater than the width of the quenching resistance trench, and an insulating layer is formed on the inner surface of the quenching resistance trench and the inner surface of the isolation trench; the integrated quenching resistance single photon avalanche diode further comprises a polysilicon quenching resistance in the quenching resistance trench, and a light-shielding conductive material in the isolation trench; the isolation trench is used to isolate the avalanche photodiode cell and the quenching resistance.

[0024] The single photon avalanche diode integrated with quenching resistor, the polysilicon quenching resistor is formed in the quenching resistor groove, and the width of the quenching resistor groove is less than the width of the isolation groove, so that the quenching resistor does not need to use a separate photoetching plate (the quenching resistor groove and the isolation groove share a photoetching plate), thereby reducing the production cost.

[0025] In one of the embodiments, the substrate comprises a substrate of a second conductivity type and an epitaxial layer of the second conductivity type on the substrate, the avalanche photodiode cell comprises an avalanche photodiode cathode region in the epitaxial layer, the avalanche photodiode cathode region has a first conductivity type; the first conductivity type and the second conductivity type are opposite conductivity types; the single photon avalanche diode integrated with quenching resistor further comprises: a dielectric layer on the epitaxial layer and covering the light-shielding conductive material; a metal layer on the dielectric layer; wherein a cathode contact hole is formed between the metal layer and the avalanche photodiode cathode region, a quenching resistor contact hole is formed between the metal layer and the polysilicon quenching resistor, the cathode contact hole and the quenching resistor contact hole are filled with a first conductive material, and part of the structure of the metal layer is electrically connected to the first conductive material in the cathode contact hole and the quenching resistor contact hole; a light incident window is formed above the avalanche photodiode cathode region for allowing external light to be incident on the avalanche photodiode cathode region through the light incident window.

[0026] In one of the embodiments, the cathode contact hole comprises a first contact hole on one side of the light incident window and a second contact hole on the other side.

[0027] In one of the embodiments, the avalanche photodiode cell further comprises: a second conductivity type well region on both sides of the avalanche photodiode cathode region; a second conductivity type buried layer in the epitaxial layer below the avalanche photodiode cathode region; wherein the doping concentration of the epitaxial layer is less than the doping concentration of the substrate and the second conductivity type buried layer.

[0028] In one of the embodiments, the avalanche photodiode cell further comprises a ring-shaped doped region in the epitaxial layer, the ring-shaped doped region is inside the second conductivity type well regions on both sides of the avalanche photodiode cathode region, and the ring-shaped doped region has the first conductivity type. BRIEF DESCRIPTION OF DRAWINGS

[0029] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without any creative effort.

[0030] Figure 1 FIG. 1 is a flow chart of a method of manufacturing a SPAD integrated with a quenching resistor according to an embodiment;

[0031] Figures 2a to 2n FIG. 2 is a schematic diagram of a structure of a SPAD integrated with a quenching resistor according to an embodiment; Figure 1

[0032] Figure 3 FIG. 3 is a schematic diagram of a structure of a SPAD integrated with a quenching resistor according to another embodiment;

[0033] Figure 4 FIG. 4 is a schematic diagram of a circuit of a SPAD and a quenching resistor according to an embodiment;

[0034] Figure 5 FIG. 5 is a flow chart of a method of manufacturing a SPAD integrated with a quenching resistor according to another embodiment. DETAILED DESCRIPTION

[0035] For the purposes of this disclosure, the term "coupled" (or "coupling" or "connected" or "connecting") means the joining of two components together such that the components together such that the components will not normally be apart except as expected in normal use of the device or process. Further, for the purposes of this disclosure, the term "coupled" or "connected" or "connecting" is used to indicate that two components co-operate or interact with each other to also allow a flow of current between them. The components will normally be apart except as expected in normal use of the device or process. The term "directly coupled" or "directly connected" or "directly connecting" is used in the same sense as "coupled" or "connected" or "connecting" except that the flow of current will be only between the two components.

[0036] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description of the application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this description, the terms "may" and "could" include any one or all of possible combinations of the inherent property of the device, software and / or system described herein, and / or the use of the devices under

[0037] ​It will be understood that when an element or layer is referred to as being "on" or "connected to" another element or layer, it can be directly on or connected to the other element or layer or intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element or layer, there are no intervening elements or layers present. It will also be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application.

[0038] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if a device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" or "over" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0039] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising", when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0040] Embodiments of the application are described herein with reference to cross-sectional illustrations that are schematic illustrations of ideal embodiments (and intermediate structures) of the application. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, embodiments of the application should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region illustrated as a rectangle will, typically, have rounded or curved features and / or a gradient of implant concentration at its edges rather than a binary change between implanted and non-implanted regions. Similarly, a buried region formed by implantation will typically result in some implant in a region between the buried region and a surface through which the implant was performed. Thus, the regions illustrated in the figures are schematic and their shapes are not intended to illustrate the precise shape of a region of a device and are not intended to limit the scope of the application.

[0041] As used herein, semiconductor terminology is used in accordance with its common usage in the semiconductor industry, e.g., for P-type and N-type impurities, P+ is used to denote a heavily doped P-type, P is used to denote a medium doped P-type, P- is used to denote a lightly doped P-type, N+ is used to denote a heavily doped N-type, N is used to denote a medium doped N-type, and N- is used to denote a lightly doped N-type.

[0042] The exemplary SPAD process needs to introduce a tungsten plug DTI process to isolate the APD sub-cell. If polysilicon quenching resistor is prepared first, the polysilicon will fill into the DTI first, causing the tungsten to be unable to fill into the DTI in the subsequent step. Therefore, the exemplary SPAD adopts a process technology of metal tungsten first and polysilicon second. In the production line of CMOS process and the like of a semiconductor fab, polysilicon deposition belongs to the front-end process, and the metal process such as tungsten plug belongs to the back-end process. After the tungsten plug process is performed, the wafer will be difficult to return to the polysilicon deposition process section of the front-end process for operation. Therefore, the exemplary SPAD process is contrary to the management rules of the conventional CMOS process, that is, incompatible with the CMOS process.

[0043] Figure 3 is a structural schematic diagram of an exemplary SPAD device. The entire APD cell is isolated from other cells by using a DTI to isolate the tungsten plug. A polysilicon strip resistor (quenching resistor) floating on the medium oxide layer is prepared at the cathode of the device, and the quenching resistor is connected through a metal layer. The cathode lead of the device is connected through a metal layer at the other end of the quenching resistor. The device structure is immediately subjected to the preparation of the inner sidewall oxide layer of the trench after the DTI trench is formed, and at the same time, the preparation of the isolation medium on the surface where the quenching resistor is located is completed. Then, the preparation of the tungsten plug in the DTI must be completed first. This is because if the quenching resistor polysilicon is prepared first, the polysilicon will fill into the DTI first, causing the tungsten to be unable to fill in the subsequent step. Therefore, the SPAD device adopts a process technology of metal first and polysilicon second, which is incompatible with the CMOS process.

[0044] The application is mainly directed to the production line operation mode of general semiconductor factory, and the structure and manufacturing method of the traditional integrated quenching resistor SPAD device are optimized to adapt to the production line of general semiconductor factory.

[0045] Figure 1 is a flowchart of a manufacturing method of a single-photon avalanche diode integrated with a quenching resistor in an embodiment, including the following steps:

[0046] S110, obtaining a wafer.

[0047] The wafer includes a substrate 210 and an avalanche photodiode cell formed in the substrate 210, that is, the basic structure of the APD can be prepared before step S120. In Figure 2a In the embodiment shown, the avalanche photodiode cell includes a second-conductivity-type buried layer 222, a second-conductivity-type well region 224, an avalanche photodiode cathode region 232, and a ring-shaped doped region 234. In an embodiment of the application, the substrate 210 includes a substrate and an epitaxial layer on the substrate; the substrate is a silicon substrate, and the epitaxial layer is a silicon epitaxial layer. The second-conductivity-type buried layer 222, the second-conductivity-type well region 224, the avalanche photodiode cathode region 232, and the ring-shaped doped region 234 are arranged in the epitaxial layer, the second-conductivity-type well region 224 is located on both sides of the avalanche photodiode cathode region 232, the second-conductivity-type buried layer 222 is located below the avalanche photodiode cathode region 232, and the ring-shaped doped region 234 is located inside the second-conductivity-type well region 224 on both sides of the avalanche photodiode cathode region 232. The substrate and the epitaxial layer have a second conductivity type, and the avalanche photodiode cathode region 232 and the ring-shaped doped region 234 have a first conductivity type. In an embodiment of the application, the first conductivity type is N-type, and the second conductivity type is P-type. In other embodiments of the application, the first conductivity type can be P-type, and the second conductivity type can be N-type.

[0048] S120, patterning and etching the front surface of the substrate to form a quenching resistor trench and an isolation trench.

[0049] The width of the isolation trench 213 is greater than the width of the quenching resistor trench 211. In an embodiment of the application, before step S120, the method further includes the steps of forming a light-transmitting silicon nitride layer 240 on the front surface of the substrate 210 (i.e., forming the light-transmitting silicon nitride layer 240 on the epitaxial layer) and forming a hard mask 252 on the light-transmitting silicon nitride layer 240.

[0050] Referring to Figure 2b and Figure 2cIn one embodiment of the present application, a first photo mask is used to form a quenching resistance trench etching window 291 and an isolation trench etching window 293 in a photoresist 292 on the hard mask 252. The width of the isolation trench etching window 293 is greater than the width of the quenching resistance trench etching window 291. Then, the hard mask 252, the transparent silicon nitride layer 240 and the substrate 210 are etched through the quenching resistance trench etching window 291 and the isolation trench etching window 293 to form the quenching resistance trench 211 and the isolation trench 213. The quenching resistance trench 211 and the isolation trench 213 are formed in the same step. Due to the loading effect of etching, the etching speed of the isolation trench 213 is greater than the etching speed of the quenching resistance trench 211, so the depth of the isolation trench 213 is greater than the depth of the quenching resistance trench 211. The resistance of the quenching resistance trench 211 can be adjusted by controlling the width and the depth of the quenching resistance trench 211, but the depth of the isolation trench 213 must be controlled to achieve the desired isolation effect. In one embodiment of the present application, the depth of the isolation trench 213 is not less than the thickness of the epitaxial layer, i.e. the bottom of the isolation trench 213 extends to the substrate. The hard mask 252 is made of a material different from the substrate, the epitaxial layer and the transparent silicon nitride layer 240. In one embodiment of the present application, the hard mask 252 is made of silicon oxide, such as silicon dioxide. After step S120, the photoresist 292 is removed.

[0051] S130, forming an insulating layer on the inner surface of the quenching resistance trench.

[0052] In one embodiment of the present application, before step S130, the inner surface of the quenching resistance trench 211 and the inner surface of the isolation trench 213 are subjected to an oxidation treatment. The oxidation treatment forms a sacrificial oxide layer. Then, the sacrificial oxide layer is removed by wet etching, and the hard mask 252 is removed to obtain the structure shown in FIG. 2C. Figure 2d Figure 2e

[0053] S140, depositing polycrystalline silicon on the front surface of the substrate, and the polycrystalline silicon fills the quenching resistance trench and the isolation trench.

[0054] ​​Polysilicon is filled into the quenching resistor trench 211 and seals the quenching resistor trench 211, while the polysilicon is filled into the isolation trench 213 without sealing the isolation trench 213. Since the subsequent step needs to fill the light-shielding conductive material into the isolation trench 213, the width of the isolation trench 213 is significantly larger than the width of the quenching resistor trench 211, so as to ensure that the isolation trench 213 is not sealed by the polysilicon on the premise that the polysilicon seals (or fills) the quenching resistor trench 211. See Figure 2f Polysilicon is deposited on the epitaxial layer and filled into the quenching resistor trench 211 (not shown in Figure 2f ) and the isolation trench 213 (not shown in Figure 2f ), fills the quenching resistor trench 211, and the polysilicon is formed on the inner surface of the isolation trench 213 without sealing the isolation trench 213. The polysilicon 260 in the quenching resistor trench 211 is used as a polysilicon quenching resistor in the subsequent step. The depth of the isolation trench 213 is designed to be much deeper than the depth of the quenching resistor trench 211, so as to shield the influence of the quenching resistor trench on the electric field of the avalanche region.

[0055] In an embodiment of the present application, the polysilicon quenching resistor can be adjusted by doping the polysilicon 260. The main adjustment method of the resistance value of the polysilicon quenching resistor is to adjust the resistance by ion implantation and to plan the width and total length of the quenching resistor trench 211.

[0056] S150, oxidizing the exposed structure in the isolation trench.

[0057] See Figure 2g , since the exposed structure of the isolation trench 213 is polysilicon 260, the polysilicon 260 is oxidized. The polysilicon in the isolation trench 213 (not shown in Figure 2g ) is oxidized at the same time, and the polysilicon on the epitaxial layer (i.e. the polysilicon on the front surface of the substrate) is also oxidized to obtain an insulating layer 256. Since the quenching resistor trench 211 is filled with polysilicon, only the surface of the polysilicon 260 in the quenching resistor trench 211 is oxidized, and the rest can remain as a polysilicon quenching resistor. If the inner surface of the isolation trench 213 exposes the material of the substrate 210, the silicon of the substrate 210 will be oxidized to an insulating material in step S150.

[0058] S160, filling the light-shielding conductive material into the isolation trench.

[0059] The light-shielding conductive material needs to isolate photons, so its light transmittance should be lower than that of the substrate, the epitaxial layer and the insulating layer 256. In an embodiment of the present application, the light transmittance of the light-shielding conductive material is lower than that of silicon and silicon dioxide. In Figure 2hIn the illustrated embodiment, the light-shielding conductive material is tungsten plug 270. In one embodiment of the present application, tungsten plug 270 can be formed by depositing tungsten on the front side of the substrate and then etching back the tungsten.

[0060] In one embodiment of the present application, insulating layer 254, insulating layer 256 and tungsten plug 270 collectively form a DTI structure, in which tungsten plug 270 can introduce a desired potential (e.g. a low potential) to the DTI and better prevent crosstalk between the cells (e.g. avalanche photodiode cells).

[0061] In the above method of manufacturing a single photon avalanche diode integrated with a quenching resistor, the polysilicon quenching resistor is formed in the quenching resistor trench 211. Since the width of the isolation trench 213 is greater than the width of the quenching resistor trench 211, in the case that the polysilicon 260 fills up the quenching resistor trench 211, there is still room in the isolation trench 213 for the subsequent filling of the light-shielding conductive material. The polysilicon in the isolation trench 213 will be oxidized as insulating layer 256 in step S150, and since the quenching resistor trench 211 is filled with polysilicon 260, only the surface of the polysilicon 260 in the quenching resistor trench 211 will be oxidized when the polysilicon in the isolation trench 213 is oxidized, and the polysilicon 260 in the quenching resistor trench 211 can be preserved as a polysilicon quenching resistor. In summary, the above method of manufacturing a single photon avalanche diode integrated with a quenching resistor can achieve the deposition of the polysilicon quenching resistor before the deposition of the light-shielding conductive material, and is compatible with CMOS processes and suitable for most semiconductor factory processes. On the other hand, since the quenching resistor trench 211 and the isolation trench 213 share one photomask, the manufacturing of the quenching resistor does not require a separate photomask, thereby reducing production costs.

[0062] Referring to Figure 5 In one embodiment of the present application, after step S160, the method further comprises the following steps:

[0063] S170, forming a dielectric layer covering the light-shielding conductive material on the front side of the substrate.

[0064] Referring to Figure 2i The dielectric layer 258 can be a silicon oxide layer, such as a doped or undoped silicon oxide material layer formed by a thermal CVD manufacturing process or a HDPCVD manufacturing process, such as undoped silicon glass (USG), phosphorus silicon glass (PSG) or boron phosphorus silicon glass (BPSG).

[0065] S180, forming a cathode contact hole and a quenching resistor contact hole.

[0066] The cathode contact holes (including the first contact hole 264 and the second contact hole 266) and the quenching resistance contact hole 262 are formed by photolithography and etching, see Figure 2j Specifically, photoresist can be coated on the dielectric layer 258, and then the photoresist is exposed by using a contact hole photomask, and then developed to obtain etching windows of the first contact hole 264, the second contact hole 266 and the quenching resistance contact hole 262, and then the dielectric layer 258, the insulating layer 256 and the light-transmitting silicon nitride layer 240 are etched through the etching windows to obtain the first contact hole 264, the second contact hole 266 and the quenching resistance contact hole 262. The bottom of the cathode contact hole extends to the avalanche photodiode cathode region 232, and the bottom of the quenching resistance contact hole 262 extends to the polysilicon 260. Then, the first contact hole 264, the second contact hole 266 and the quenching resistance contact hole 262 are filled with conductive materials, see Figure 2k The conductive material can be any suitable conductive material known to those skilled in the art, including but not limited to metal materials; wherein the metal material can include one or more of Ag, Au, Cu, Pd, Pt, Cr, Mo, Ti, Ta, W and Al. In an embodiment of the present application, the conductive material includes metallic tungsten. The excess conductive material on the dielectric layer 258 can be removed by a chemical mechanical polishing (CMP) process.

[0067] S190, forming a metal layer on the dielectric layer.

[0068] The metal layer 280 is formed by a surface metal interconnection process (i.e. depositing metal on the dielectric layer 258, then photolithography and etching). See Figure 2l Part of the structure of the metal layer 280 is electrically connected to the conductive material in the cathode contact hole (the first contact hole 264) and the conductive material in the quenching resistance contact hole 262.

[0069] In an embodiment of the present application, after step S190, it further includes the step of depositing a passivation layer 282 on the dielectric layer 258 and the metal layer 280, see Figure 2m Then, the passivation layer is etched and opened, and the insulating layer 256 and the dielectric layer 258 above part of the avalanche photodiode cathode region 232 are removed, and a light incident window 201 is formed on the light-transmitting silicon nitride layer 240, so that the external light can be incident on the avalanche photodiode cathode region 232 through the light incident window 201. The first contact hole 264 and the second contact hole 266 are located on both sides of the incident window 201.

[0070] In an embodiment of the present application, it further includes the step of forming a metal electrode layer on the back of the substrate. The metal electrode layer serves as a metal contact of the P+ substrate.

[0071] This application correspondingly provides a single-photon avalanche diode with an integrated quenching resistor, which can be manufactured using the manufacturing method for a single-photon avalanche diode with an integrated quenching resistor described in any of the foregoing embodiments. See also Figure 2n In one embodiment of this application, the single-photon avalanche diode integrated with a quenching resistor includes a substrate 210 and avalanche photodiode cells within the substrate 210. A quenching resistor trench and an isolation trench located outside the avalanche photodiode cells and the quenching resistor trench are also formed in the substrate 210, the width of the isolation trench being greater than the width of the quenching resistor trench. An insulating layer 254 is formed on the inner surface of the quenching resistor trench and the inner surface of the isolation trench. The single-photon avalanche diode integrated with a quenching resistor also includes a polysilicon quenching resistor (i.e., polysilicon 260) located within the quenching resistor trench, and a light-shielding conductive material (in the isolation trench) located within the isolation trench. Figure 2n In the illustrated embodiment, the light-shielding conductive material is a tungsten plug 270. Figure 2n In the illustrated embodiment, an insulating layer 256 is further formed between the tungsten plug 270 and the insulating layer 254 in the isolation trench. The insulating layer 254, the insulating layer 256, and the tungsten plug 270 together form a deep trench isolation (DTI) structure to isolate the avalanche photodiode cells and the quenching resistor. The tungsten plug 270 can introduce the desired potential (e.g., a low potential) into the DTI to better prevent crosstalk between cells (e.g., avalanche photodiode cells).

[0072] In the aforementioned single-photon avalanche diode with integrated quenching resistors, the polysilicon quenching resistors are formed within quenching resistor trenches, and the width of the quenching resistor trenches is smaller than the width of the isolation trenches. Therefore, the fabrication of the quenching resistors does not require a separate photomask (the quenching resistor trenches and isolation trenches share a single photomask), reducing production costs. Furthermore, the fabrication of this single-photon avalanche diode with integrated quenching resistors is compatible with CMOS processes.

[0073] In one embodiment of the present application, the substrate 210 comprises a substrate of the second conductivity type and an epitaxial layer of the second conductivity type on the substrate. The avalanche photodiode cell comprises an avalanche photodiode cathode region 232 in the epitaxial layer, the avalanche photodiode cathode region 232 having the first conductivity type. In one embodiment of the present application, the first conductivity type is N-type and the second conductivity type is P-type. In one embodiment of the present application, the single photon avalanche diode integrated with quenching resistance further comprises a dielectric layer 258 on the epitaxial layer and covering the light-shielding conductive material (i.e. tungsten plug 270), and a metal layer 280 on the dielectric layer 258. A cathode contact hole (including the first contact hole 264 and the second contact hole 266) is formed between the metal layer 280 and the avalanche photodiode cathode region 232, and a quenching resistance contact hole 262 is formed between the metal layer 280 and the polysilicon quenching resistance (i.e. polysilicon 260). The cathode contact hole and the quenching resistance contact hole 262 are filled with conductive material, and part of the structure of the metal layer 280 is electrically connected to the conductive material in the cathode contact hole and the quenching resistance contact hole 262. A light incident window 201 is formed above the avalanche photodiode cathode region 232, and external light can enter the avalanche photodiode cathode region 232 through the light incident window 201. The first contact hole 264 and the second contact hole 266 are formed on both sides of the light incident window 201.

[0074] In one embodiment of the present application, the single photon avalanche diode integrated with quenching resistance further comprises a second conductivity type well region 224 and a second conductivity type buried layer 222. The second conductivity type well region 224 is located on both sides of the avalanche photodiode cathode region 232, and the second conductivity type buried layer 222 is located below the avalanche photodiode cathode region 232 in the epitaxial layer. In one embodiment of the present application, the doping concentration of the epitaxial layer is less than the doping concentration of the substrate and the second conductivity type buried layer 222.

[0075] In one embodiment of the present application, the avalanche photodiode cell further comprises a ring-shaped doped region 234 in the epitaxial layer. The ring-shaped doped region is located inside the second conductivity type well region 224 on both sides of the avalanche photodiode cathode region 232, and the ring-shaped doped region 234 has the first conductivity type.

[0076] In one embodiment of the present application, a light-transmitting silicon nitride layer 240 is further provided between the epitaxial layer and the insulating layer 256.

[0077] In one embodiment of the present application, the depth of the isolation trench is greater than the depth of the quenching resistance trench.

[0078] In one embodiment of the present application, a metal electrode layer is further formed on the back of the substrate as a metal contact of the P+ substrate.

[0079] It should be understood that, although the steps in the flowcharts of the present application are shown in a sequence as indicated by arrows, the steps are not necessarily executed in the order as indicated by the arrows. Unless otherwise specified herein, the execution of the steps is not necessarily limited to the order as indicated by the arrows, and the steps can be executed in other orders. Moreover, at least some of the steps in the flowcharts of the present application can include multiple steps or multiple stages, which are not necessarily executed at the same time, but can be executed at different times, and the execution of the steps or stages is not necessarily sequential, but can be performed in rotation or alternation with at least some of the other steps or the steps or stages in the other steps.

[0080] In the description of the present specification, the description referring to the terms "some embodiments", "other embodiments", "ideal embodiments", and the like means that the specific features, structures, materials, or characteristics described in connection with the embodiments or examples are included in at least one embodiment or example of the present application. In the present specification, the illustrative description of the above terms does not necessarily refer to the same embodiment or example.

[0081] The technical features of the above-described embodiments can be combined in any manner. In order to make the description concise, not all possible combinations of the technical features of the above-described embodiments are described, however, as long as the combinations of the technical features do not contradict each other, they should be considered within the scope of the present specification.

[0082] The above-described embodiments only express several implementation manners of the present application, and the description is relatively specific and detailed, but it should not be understood as a limitation on the patent scope of the application. It should be noted that, for ordinary skilled persons in the art, several modifications and improvements can be made without departing from the concept of the present application, and these are within the protection scope of the present application. Therefore, the patent protection scope of the present application should be subject to the appended claims.

Claims

1. A method for manufacturing a single photon avalanche diode integrated with quenching resistor, comprising: obtaining a wafer; the wafer comprising a substrate and an avalanche photodiode cell formed in the substrate; patterning and etching a first surface of the substrate to form a quenching resistor trench and an isolation trench; the isolation trench has a width greater than that of the quenching resistor trench; forming an insulating layer on an inner surface of the quenching resistor trench; depositing polysilicon on the first surface of the substrate, the polysilicon filling the quenching resistor trench and sealing the quenching resistor trench, and the polysilicon filling the isolation trench without sealing the isolation trench; performing oxidation treatment on exposed structures in the isolation trench; filling the isolation trench with light-shielding conductive material; wherein the isolation trench is located outside the avalanche photodiode cell and the quenching resistor trench, and is used to isolate the avalanche photodiode cell and the quenching resistor.

2. The method of manufacturing a single photon avalanche diode integrated with quenching resistance according to claim 1, wherein In the step of obtaining a wafer, the avalanche photodiode cell of the obtained wafer comprises an avalanche photodiode cathode region, and the method further comprises: forming a dielectric layer covering the light-shielding conductive material on the first surface of the substrate; forming a cathode contact hole and a quenching resistor contact hole, the bottom of the cathode contact hole extending to the avalanche photodiode cathode region, and the bottom of the quenching resistor contact hole extending to the polysilicon in the quenching resistor trench, the cathode contact hole and the quenching resistor contact hole being filled with a first conductive material; forming a metal layer on the dielectric layer, part of the metal layer being electrically connected to the first conductive material in the cathode contact hole and the quenching resistor contact hole; forming a light incident window on the first surface of the substrate by removing the dielectric layer above part of the avalanche photodiode cathode region, so that external light can be incident on the avalanche photodiode cathode region through the light incident window.

3. The method of manufacturing a single photon avalanche diode integrated with quenching resistance according to claim 1, wherein The step of patterning and etching the first surface of the substrate to form the quenching resistor trench and the isolation trench comprises: forming a quenching resistor trench etching window and an isolation trench etching window in photoresist on the first surface of the substrate by first photolithography, the isolation trench etching window having a width greater than that of the quenching resistor trench etching window; etching the substrate through the quenching resistor trench etching window and the isolation trench etching window to form the quenching resistor trench and the isolation trench; wherein the depth of the isolation trench is greater than that of the quenching resistor trench.

4. The method of manufacturing a single photon avalanche diode integrated with quenching resistance according to claim 1, wherein The light transmittance of the light-shielding conductive material is lower than that of silicon and silicon dioxide.

5. The method of manufacturing a single photon avalanche diode integrated with quenching resistance according to claim 2, wherein In the step of obtaining a wafer, the substrate of the obtained wafer comprises a substrate of a second conductive type and an epitaxial layer on the substrate, the epitaxial layer having the second conductive type, and the avalanche photodiode cathode region being located in the epitaxial layer and having a first conductive type;The first conductive type and the second conductive type are opposite conductive types.

6. The method of manufacturing a single photon avalanche diode integrated with quenching resistance according to claim 5, wherein In the step of obtaining a wafer, the avalanche photodiode cell of the obtained wafer further comprises: a second conductive type well region located on both sides of the avalanche photodiode cathode region. a second-conductivity-type buried layer in the epitaxial layer below the avalanche photodiode cathode region; wherein the epitaxial layer has a doping concentration less than the doping concentration of the substrate and the second-conductivity-type buried layer.

7. The method of manufacturing a single photon avalanche diode integrated with quenching resistance according to claim 1, wherein The step of patterning and etching the first surface of the substrate further comprises the steps of forming a light-transmissive silicon nitride layer on the first surface of the substrate, and forming a hard mask on the light-transmissive silicon nitride layer. The step of patterning and etching the first surface of the substrate to form the quenching resistance trench and the isolation trench comprises the steps of: performing photolithography on the hard mask, and etching the hard mask, the light-transmissive silicon nitride layer, and the substrate to form the quenching resistance trench and the isolation trench.

8. The method of manufacturing a single photon avalanche diode integrated with quenching resistance according to claim 7, wherein, The material of the hard mask comprises silicon oxide. The step of forming the quenching resistance trench and the isolation trench is followed by the step of forming an insulating layer on the inner surface of the quenching resistance trench, and is preceded by the steps of: performing oxidation treatment on the inner surface of the quenching resistance trench and the inner surface of the isolation trench; and wet-removing the oxide layer on the inner surface of the quenching resistance trench and the inner surface of the isolation trench, while removing the hard mask.

9. An integrated quenching resistance single photon avalanche diode, comprising: a substrate; an avalanche photodiode cell in the substrate; characterized in that a quenching resistance trench and an isolation trench outside the avalanche photodiode cell and the quenching resistance trench are further formed in the substrate, the isolation trench has a width greater than that of the quenching resistance trench, and the isolation trench has a depth greater than that of the quenching resistance trench, so as to shield the influence of the quenching resistance trench on the electric field of the avalanche region; the inner surface of the quenching resistance trench and the inner surface of the isolation trench are formed with an insulating layer; the integrated quenching resistance single photon avalanche diode further comprises a polysilicon quenching resistance in the quenching resistance trench, and a light-shielding conductive material in the isolation trench; and the isolation trench is used to isolate the avalanche photodiode cell and the quenching resistance.

10. The single photon avalanche diode integrated with quenching resistance according to claim 9, characterized in that, The substrate comprises a substrate of a second conductivity type and an epitaxial layer of the second conductivity type on the substrate, the avalanche photodiode cell comprises an avalanche photodiode cathode region in the epitaxial layer, and the avalanche photodiode cathode region has a first conductivity type; the first conductivity type and the second conductivity type are opposite conductivity types; The integrated quenching resistance single photon avalanche diode further comprises: a dielectric layer on the epitaxial layer and covering the light-shielding conductive material; a metal layer on the dielectric layer; wherein a cathode contact hole is formed between the metal layer and the avalanche photodiode cathode region, a quenching resistance contact hole is formed between the metal layer and the polysilicon quenching resistance, the cathode contact hole and the quenching resistance contact hole are filled with a first conductive material, and part of the structure of the metal layer is electrically connected to the first conductive material in the cathode contact hole and the quenching resistance contact hole; a light incident window is formed above the avalanche photodiode cathode region, so that external light can be incident on the avalanche photodiode cathode region through the light incident window.

11. The single photon avalanche diode integrated with quenching resistance according to claim 10, characterized in that, The avalanche photodiode cell further comprises: a second conductivity type well region on both sides of the avalanche photodiode cathode region; a second conductivity type buried layer in the epitaxial layer below the avalanche photodiode cathode region; wherein a doping concentration of the epitaxial layer is less than a doping concentration of the substrate and the second conductivity type buried layer.

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