Successive approximation analog-to-digital converter and electronic device

Abstract

Disclosed are a successive approximation analog-to-digital converter and an electronic device. The successive approximation analog-to-digital converter comprises a dynamic comparator comprising first and second output terminals, the dynamic comparator generating first and second comparison results at the first and second output terminals, respectively, based on a comparator operating clock; and a read clock generation circuit connected to the first and second output terminals and generating a read clock signal for reading the comparison results based on the received first and second comparison results. The present application reads the comparison results by capturing the read clock signal generated from the output of the comparator, which can improve the overall analog-to-digital conversion speed of the SARADC. Further, the present application can detect the occurrence of metastability of the comparator when the output of the comparator has no pulse, and read the comparison results based on a backup clock generated based on the comparator operating clock, so that the comparator does not need to be reset when metastability occurs, thereby ensuring efficient operation of the SARADC.

Description

Technical Field

[0001] This disclosure relates to the field of circuits, and more particularly to a successive approximation analog-to-digital converter and electronic device. Background Technology

[0002] Successive approximation analog-to-digital converters (SARADCs) are common analog-to-digital conversion devices, typically used for medium to high resolution sampling rates, and are widely used due to their low power consumption and small size.

[0003] In existing SARADCs, a separate read clock is used to read the comparator's output. Figure 1 The diagram illustrates the timing of reading the comparator comparison result in the prior art. As shown, clkc is the comparator's operating clock, Q is the comparison result, and clk is the clock for reading Q. In the prior art, clk is a read clock independent of clkc. Assume the comparator starts operating when clkc is high, and after time d1, the comparator generates the comparison result Q. To prevent metastability when clk captures Q, there must be a delay d2 between Q and clk. Therefore, the delay d3 between clkc and clk must be designed to be no less than d1 + d2 to ensure clk can correctly capture Q. Since d1 is a value related to the input and PVT (process, voltage, temperature), to ensure clk can read Q under any circumstances, d3 must be designed as a large value that covers the sum of d2 and the maximum d1, but this will slow down the conversion speed of the SARADC.

[0004] Therefore, an improved successive approximation analog-to-digital converter is needed. Summary of the Invention

[0005] One technical problem this disclosure aims to solve is to provide an improved successive approximation analog-to-digital converter (ADC). This invention uses the comparator output as a clock to read the comparator's comparison result, enabling immediate result reading after the comparison result is generated. This avoids the requirement in existing technologies that the clock must satisfy the maximum comparison result generation time for reading, thereby improving the analog-to-digital conversion speed.

[0006] According to a first aspect of this disclosure, a successive approximation analog-to-digital converter is provided, comprising: a dynamic comparator including a first output terminal and a second output terminal, the dynamic comparator generating a first comparison result and a second comparison result at the first output terminal and the second output terminal respectively based on a comparator operating clock; and a readout clock generation circuit connected to the first output terminal and the second output terminal, and generating a readout clock signal for reading the comparison result based on the first comparison result and the second comparison result received from the dynamic comparator.

[0007] Optionally, the read clock generation circuit includes: a first logic gate circuit, used to generate a read pulse signal when the first comparison result and the second comparison result correspond to different levels, wherein the read pulse signal is delayed to obtain the read clock signal.

[0008] Optionally, the first logic gate circuit includes: a metastable signal extraction logic gate, used to connect the first output terminal and the second output terminal and to extract the same level signal when metastability occurs, wherein the signal extraction threshold of the metastable signal extraction logic gate is set between the inverted level of the reset level of the dynamic comparator and the metastable level.

[0009] Optionally, the metastable signal extraction logic gate includes: a first NOT gate connected to the first output terminal and a second NOT gate connected to the second output terminal, wherein: when the reset level of the dynamic comparator is high, the toggling threshold of the first NOT gate and the second NOT gate is set between a low level and a metastable level; when the reset level of the dynamic comparator is low, the toggling threshold of the first NOT gate and the second NOT gate is set between a high level and a metastable level.

[0010] Optionally, the same level signal extracted by the metastable signal extraction logic gate when metastability occurs enables the read clock generation circuit to generate the read clock signal based on the operating clock of the dynamic comparator.

[0011] Optionally, the read clock generation circuit further includes a signal selection circuit, configured to select a read pulse signal generated based on the first and second comparison results to generate the read clock signal when the first comparison result and the second comparison result correspond to different levels, and to select a clock pulse signal generated based on the working clock of the dynamic comparator to generate the read clock signal when the first comparison result and the second comparison result correspond to the same level.

[0012] Optionally, the successive approximation analog-to-digital converter further includes a data register that reads the first comparison result using the read clock signal generated by the signal selection circuit.

[0013] Optionally, the read clock generation circuit further includes: a first logic gate circuit, used to generate the read pulse signal based on the first comparison result and the second comparison result when the first comparison result and the second comparison result correspond to different levels; and a clock pulse generation circuit, used to generate the clock pulse signal based on the comparator operating clock, wherein the read pulse signal is generated before the clock pulse signal.

[0014] Optionally, the signal selection circuit includes: a first transmission gate, whose two control terminals are respectively coupled to the read pulse signal and the inverted signal of the read pulse signal, and whose input terminal is coupled to the read pulse signal; when the read pulse signal is high, the first transmission gate is turned on to output the read pulse signal; a second transmission gate, whose two control terminals are respectively coupled to the inverted signal of the read pulse signal and the read pulse signal, and whose input terminal is coupled to the clock pulse signal; when the read pulse signal is low, the second transmission gate is turned on to output the clock pulse signal; and a delay circuit that delays the outputs of the first transmission gate and the second transmission gate to generate the read clock signal.

[0015] Optionally, the signal selection circuit includes: a logic circuit that generates a selection pulse signal based on the read pulse signal and the clock pulse signal, wherein the selection pulse signal varies according to the clock pulse signal when the read pulse signal has a level indicating that the first comparison result and the second comparison result correspond to the same level; a transmission gate, whose two control terminals are respectively coupled to the selection pulse signal and the inverted signal of the selection pulse signal, and whose input terminal is coupled to the read pulse signal, wherein the transmission gate is turned on when the read pulse signal has a pulse indicating that the first comparison result and the second comparison result correspond to different levels, so as to output the read pulse signal; a switching transistor, whose control terminal is coupled to the selection pulse signal, and whose output terminal is coupled to the output terminal of the transmission gate, wherein the switching transistor is turned off when the selection pulse signal does not vary according to the clock pulse signal, and when the selection pulse signal varies according to the clock pulse signal, the switching transistor, in conjunction with the transmission gate, outputs the clock pulse signal; and a delay circuit that is coupled to the outputs of the transmission gate and the switching transistor, and delays the outputs to generate the read clock signal.

[0016] According to a second aspect of this disclosure, a successive approximation analog-to-digital converter is provided, comprising: a first readout clock generation circuit connected to a first output and a second output of a dynamic comparator, and generating a first signal based on receiving a first comparison result from the first output and a second comparison result from the second output; a clock pulse generation circuit connected to the comparator operating clock of the dynamic comparator, and generating a second signal based on the operating clock; and a metastability detection circuit configured to, when detecting that the first signal includes a readout pulse signal, select the first signal to generate a readout clock signal to read the first comparison result of the dynamic comparator, and when not detecting that the first signal includes the readout pulse signal, select the second signal to generate the readout clock signal to read the first comparison result of the dynamic comparator.

[0017] According to a third aspect of this disclosure, an electronic device is provided, comprising a successive approximation analog-to-digital converter as described in the first and second aspects.

[0018] Therefore, this invention improves the overall analog-to-digital conversion speed of the SARADC by reading the comparison result through a read clock signal generated from the comparator's output. Furthermore, this invention can detect metastability in the comparator by determining when there is no pulse at the comparator's output and read the comparison result based on a backup clock generated from the comparator's operating clock. This eliminates the need to reset the comparator when metastability occurs, thus ensuring the efficient operation of the SARADC. Attached Figure Description

[0019] The above and other objects, features and advantages of this disclosure will become more apparent from the more detailed description of exemplary embodiments thereof taken in conjunction with the accompanying drawings, wherein like reference numerals generally denote like parts.

[0020] Figure 1 The timing diagram for reading the comparator comparison result in the prior art is shown.

[0021] Figure 2 An example of a successive approximation analog-to-digital converter is shown.

[0022] Figure 3 A timing diagram for reading the comparator comparison result according to an embodiment of the present invention is shown.

[0023] Figure 4 A timing diagram for reading the comparator comparison result according to an embodiment of the present invention is shown.

[0024] Figure 5 A schematic diagram of the composition of a successive approximation analog-to-digital converter according to an embodiment of the present invention is shown.

[0025] Figure 6 A schematic diagram of the composition of a dynamic comparator used in one embodiment of the present invention is shown.

[0026] Figure 7 The diagram shows the level changes at the two output terminals after the dynamic comparator starts working.

[0027] Figure 8 The diagram shows the level changes at the two outputs of the dynamic comparator when metastability occurs.

[0028] Figure 9 A schematic diagram of a clock generation and signal selection circuit according to an embodiment of the present invention is shown.

[0029] Figure 10A -B shows Figure 9The timing diagrams of the circuit shown are for the circuits in the absence of metastability and the presence of metastability.

[0030] Figure 11 A schematic diagram of the composition of a read clock generation circuit according to an embodiment of the present invention is shown.

[0031] Figure 12A -B shows Figure 11 The timing diagrams of the circuit shown are for the circuits in the absence of metastability and the presence of metastability. Detailed Implementation

[0032] Preferred embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While preferred embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that the present disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0033] It should be understood that the terms “first” and “second” used in this disclosure are used only to distinguish different objects of the same kind and are not intended to imply the order or importance of these objects.

[0034] A successive approximation analog-to-digital converter (SARADC) is a common type of analog-to-digital conversion device. As the name suggests, a SARADC essentially implements a binary search algorithm. Although there are many different ways to implement a SAR ADC, its basic structure is very simple. Figure 2 An example of the components of a SARADC is shown. As shown, the SARADC 200 may include a dynamic comparator 210, a data register 220, a digital-to-analog converter (DAC) 230, and a shift register 240.

[0035] To implement the binary search algorithm, the N-bit data register 220 is initially set to the middle scale (i.e., 100...00, MSB set to 1). Thus, initially, the digital-to-analog converter 230 outputs V... DAC Set to V REF / 2, here, V REF This is the reference voltage provided to the SAR ADC 200. Figure 2 In the example, the digital-to-analog converter 230 is implemented as a capacitive digital-to-analog converter (CDAC), and the input V to be converted from analog to digital by the SARADC 200 is... IN The V output of the digital-to-analog converter 230 DAC These are represented as vinn and vinp. Then, comparator 210 determines the input voltage V. IN Is it less than or greater than V? DAC If V INGreater than V DAC If the comparator 210 outputs a comparison result Q that is logic high or 1 (of course, depending on the logic implementation, it could also be low or 0), the MSB of the N-bit data register 220 remains 1. Conversely, if V IN Less than V DAC If the comparison result Q output by comparator 210 is low, the MSB of the N-bit data register 220 is cleared to 0. Here, the data register 220 uses clk as its clock signal to read the comparison result Q as its input. The output of the data register 220 determines the connection of the capacitors in the digital-to-analog converter 230. The digital-to-analog converter 230 then outputs analog voltages vinn and vimp based on the adjusted capacitors for comparator 210 to compare. The shift register 240 (which, together with the data register 220, can be considered as SAR control logic, i.e., SARlogic) is shifted to the next bit and set to high for the next comparison. This process continues until the LSB. After the above operations are completed, the analog-to-digital conversion is finished, and the N-bit conversion result is stored in the data register 220.

[0036] In existing SAR ADCs, the data register 220 uses a read clock clk to read the output of comparator 210, i.e. Figure 1 As shown, clock clk can be considered as the comparator's operating clock clkc after a fixed, relatively large delay. In other words, data register 220 uses a clock clk independent of Q to read the logic low or logic high level output of comparator 210. Although delay d2 can be relatively fixed, delay d1 will vary due to changes in the operating environment and input. Therefore, the delay d3 of clk compared to clkc needs to satisfy the maximum sum of d1 and d2 (i.e., d3 = d1). max Only by adding d2) can we ensure that Q is correctly read into data register 220. The aforementioned fixed delay d3 reduces the reading speed, thereby reducing the overall efficiency of the SARADC.

[0037] To address this, the present invention proposes an improved successive approximation analog-to-digital converter (ADC). This invention uses the output of a dynamic comparator as a clock to read the comparison result of the dynamic comparator, enabling immediate result reading after the comparison result is generated. This avoids the requirement in existing technologies that the clock must satisfy the maximum comparison result generation time for reading, thereby improving the analog-to-digital conversion speed.

[0038] Figure 3A timing diagram for reading the comparison result of a dynamic comparator according to an embodiment of the present invention is shown. As shown, clkc is the operating clock of the dynamic comparator (hereinafter referred to as the "comparator operating clock"), Q' is the comparison result (described in detail below; the comparison result at this time is the comparison result at both output terminals), and clk is the read clock generated based on the comparison result Q' (hereinafter referred to as the "read clock signal"). Assume that the dynamic comparator starts working when clkc is high, and after time d1, the dynamic comparator generates the comparison result Q'. d4 is a fixed delay after the generation of the comparison result Q'. In other words, the delay of clk relative to clkc is no longer a fixed value, but a value that dynamically changes with d1. Even when the value of d4 is the same as d2, since d5 = d1... now +d4, therefore, the latency d5 of clk in this invention is less than d3 in the prior art compared to clkc, thus improving the readout rate of SARADC.

[0039] In addition, in a preferred embodiment, the present invention also includes a corresponding metastability handling mechanism. Specifically, for comparator 210, if metastability occurs, and the two input voltages vimp and vinn of the comparator have not yet separated when the input voltage is sampled (i.e., vimp and vinn are very close, making vimp-vinn approximately equal to 0), then comparator 210 will need a long time to achieve the standard level of the output logic. In other words, the time the circuit spends in the intermediate state becomes longer, making the circuit "respond" sluggish. The working time left for the dynamic comparator is limited. If the dynamic comparator cannot compare a clear result (either high or low) within this limited time, this is "metastability".

[0040] Figure 4 A timing diagram illustrating the reading of the comparator comparison result according to an embodiment of the present invention is shown. Figure 3 The difference is that, at this time, due to metastability in comparator 210, the comparison result Q' actually has no signal. Since the read clock clk cannot be obtained from the comparison result Q' of comparator 210, this invention obtains the read clock clk by processing the comparator's operating clock clkc when metastability occurs. Figure 4 In the example, the read clock clk is obtained by performing an AND operation between the inverted signal clkcb of the comparator clock clkc and the delayed signal clkc1 of the comparator clock. However, it should be understood that other operations can also be used to obtain the read clock clk based on the comparator clock clkc, for example, by simply adding a sufficient delay to clkc.

[0041] Therefore, in order to achieve Figure 3The present invention dynamically generates the read clock clk based on the comparison result Q', requiring an additional read clock generation circuit for the SARADC. In a preferred embodiment, to enable reading of the comparison result Q' even in metastable conditions and thus avoid comparator reset, the read clock generation circuit can also generate the read clock signal clk based on the comparator operating clock clkc. The read clock generation circuit further includes a signal selection circuit: selecting the read clock signal clk generated based on the comparison result Q' in non-metastable conditions; and selecting the read clock signal clk generated based on the comparator operating clock clkc when metastable conditions occur. Thus, Figure 5 A schematic diagram of the composition of a successive approximation analog-to-digital converter according to an embodiment of the present invention is shown.

[0042] like Figure 5 As shown, compared to Figure 2 The comparator used in the SARADC of this invention is a comparator that performs comparisons when the comparator's operating clock (clkc in the diagram) is valid and resets when the comparator's operating clock is invalid; that is, the dynamic comparator 510 shown in the diagram. It should be understood that the SARADC applicable to this invention can also have other data register, DAC, and comparator connections than those shown in the diagram, as long as successive approximation comparisons can be achieved.

[0043] Furthermore, Figure 5 The SARADC 500 shown also includes a read clock generation circuit 550. The two inputs of the circuit 550 are connected to the two outputs of the dynamic comparator 510, and it has two outputs, which output the comparison result Q of the dynamic comparator 510 and the read clock signal clk for reading the comparison result Q to the data register 520, respectively.

[0044] Therefore, in one embodiment, the read clock generation circuit 550 is connected to the first output and the second output of the dynamic comparator 510, and generates a read clock signal clk for reading the first comparison result (e.g., op) generated by the dynamic comparator 510 based on the first comparison result (e.g., op) received from the first output and the second comparison result (e.g., on) received from the second output.

[0045] It should be understood that, since the dynamic comparator 510 in the SARADC is used to compare the input voltage vinn and the digital-to-analog converter voltage vimp output from the data register 520 and then through the CDAC 530, under normal comparison conditions, one of the two outputs op and on of the dynamic comparator 510 will necessarily output a high level and the other a low level. For example, when using the output of op, or von as the comparison signal Q, op or von will output a high level when vinn > vimp and a low level when vinn < vimp.

[0046] In other words, in Figure 2 In the connection shown, the level value Q read by data register 220 will sometimes be high and sometimes low depending on the relationship between the magnitudes of vinn and vinp. Figure 1 The Q shown is an example of reading when the output level of comparator 210 is high, and it should be understood that when the Q value is low, the Q value can also be read using clk at time d5 after the rising edge of clkc.

[0047] In the embodiments of the present invention shown Figure 5 In the process, the level value Q read by data register 520 will sometimes be high and sometimes low depending on the relationship between vinn and vinp. However, the difference lies in the fact that circuit 550, used to generate the read clock signal clk, needs to simultaneously acquire signals from both outputs of the dynamic comparator 510, thereby generating a read clock for reading the output from one of the outputs. That is, in Figure 3 and Figure 4 In this context, Q' can refer to the signals op and on from the two outputs of the dynamic comparator 510. Since the dynamic comparator 510 will always have one high and one low output during normal comparison within one operating cycle, the clock generation circuit 550 of this invention can extract a pulse from op and on and use it as the comparator output Q'. Figure 3 The generation of the read clock signal clk shown, or in, as Figure 4 When a pulse with no change in Q' is detected, a spare clock generated by the comparator's operating clock clkc is used as the clock for reading the Q value.

[0048] Specifically, the read clock generation circuit 550 of the present invention may include a first logic gate circuit for generating a read pulse signal when the first comparison result and the second comparison result correspond to different levels (e.g., Figure 3 (Q' in the original text). The read pulse signal can be delayed to obtain the read clock signal.

[0049] Figure 6 A schematic diagram of the composition of a dynamic comparator used in one embodiment of the present invention is shown. Figure 7 The diagram illustrates the level changes of the two outputs after a dynamic comparator starts operating. The dynamic comparator shown outputs a high-level reset level (e.g., Vdd in the diagram) when the operating clock clkc is low. Comparison begins on the rising edge of clkc, and based on the relative magnitudes of vinn and vimp, one of the two outputs must be pulled low (shown as 'on' in the diagram), and then forcibly pulled high again after the falling edge of clkc. In a preferred embodiment, an inverter can be connected after each of the two outputs, op and on. By appropriately setting the toggle threshold of the inverters, it can be ensured that the output that is not pulled low to 0 (shown as op) will always output a low (L) output (vop) when inverted, while the output that is pulled low before the falling edge of clkc (shown as on) will output a high pulse when inverted as a high pulse output (von).

[0050] Although the figure shows a dynamic comparator with a high reset level and comparisons performed after the operating clock jumps high, those skilled in the art should understand that a dynamic comparator with a low reset level or comparisons performed after the operating clock jumps low can also be used. However, regardless of the comparator used, during normal comparison, the two outputs (either on or op) of the dynamic comparator will inevitably exhibit different levels. Therefore, the read clock generation circuit 550 of this invention may include a first logic gate circuit for generating (extracting) a read pulse signal when the first comparison result op and the second comparison result on correspond to different levels. This read pulse signal can be delayed and used to obtain the read clock signal clk for reading the comparison result Q. Figure 6 and Figure 7 In one example, the first logic gate can be an OR gate and two NOT gates. The two NOT gates invert the first and second comparison results op and on to generate vop and von, which are then passed through the OR gate to extract a read pulse from the OR operation of von and vop during normal comparison by the dynamic comparator 510. In an embodiment where the reset level of the dynamic comparator is low, when metastability occurs, both the first and second comparison results op and on are low. In this case, the first logic gate can be implemented with only one OR gate, which extracts the read pulse from the OR operation of on and op during normal comparison by the dynamic comparator 510 (when on and op are one high and one low). In other examples, the first logic gate can also be a NOR gate (if a low-level pulse is required by subsequent circuitry); if von and vop are high during reset, the first logic gate can also be an AND gate (if a low-level pulse is required by subsequent circuitry) or a NAND gate (if a high-level pulse is required by subsequent circuitry). In other words, the present invention imposes a limitation on the specific implementation of the first logic gate, as long as it can extract the read pulse that can be used to generate clk from the two outputs of the dynamic comparator.

[0051] Furthermore, in order to address the "metastable state" that may occur during comparison by the dynamic comparator as described above, the circuit 550 added to the SARADC by the present invention may also include additional circuitry.

[0052] First, the occurrence and detection of metastability will be explained by combining the output state of the dynamic comparator when metastability occurs. Figure 8 This diagram illustrates the level changes at the two outputs of a dynamic comparator when metastability occurs. Compared to Figure 7 The result is compared within the high-level pulse width of clkc, assuming one of the two inputs is successfully pulled low (i.e., no metastability occurs). Figure 8 The diagram shows that no result was obtained within the high-level pulse width of clkc, indicating a metastable state. For example... Figure 8 As shown, the two outputs op and on of the dynamic comparator were not completely separated within the high-level pulse width of clkc. Neither output was pulled to ground. After they both decreased, they were pulled high again when the falling edge of clkc arrived.

[0053] At this point, it is necessary to identify the metastable conditions described above within the dynamic comparator. Figure 8 In the example above, the inverters connected after on and op can be used to extract metastable signals. Specifically, the toggle threshold Vth1 of the two inverters can be set relatively low, for example, below the metastable level that will be pulled down during metastability (as shown by the dotted line in the figure). This ensures that von and vop are always low when metastability occurs. Therefore, for the dynamic comparator 510, since the inverters with low toggle threshold Vth1 are connected after op and on, one of von and von will necessarily generate a high-level pulse when no metastability occurs, and both von and von will remain low when metastability occurs. Thus, by detecting this high-level pulse (i.e., reading the pulse signal), it can be determined whether the comparator has experienced metastability. In addition to using two inverters connected to the first and second outputs of the dynamic comparator as metastable signal extraction logic gates, other forms of logic gates can also be used, as long as these logic gates take the first and second outputs as inputs and the logic operation determination voltage is between the reverse level of the reset level (0V in this example) and the metastable level.

[0054] thus, Figure 5The circuit 550 may further include a signal selection circuit, capable of determining that the dynamic comparator 510 is non-metastable when the first comparison result op and the second comparison result on correspond to different levels, thereby selecting a read pulse signal generated based on the first and second comparison results to generate the read clock signal clk; and determining that the dynamic comparator 510 is metastable and no read clock pulse is generated when the first comparison result op and the second comparison result on correspond to the same level, thereby selecting a clock pulse signal generated based on the operating clock clkc of the dynamic comparator to generate the read clock signal clk. For example, in Figure 4 When Q' is always low, clk, generated by clkcb and clkc1, is used to read the comparison result Q. This signal selection circuit, because it can select a different clock when metastability occurs, can also be considered a metastability detection circuit.

[0055] Furthermore, circuit 550 may include a clock pulse generation circuit for generating the aforementioned clock pulse signal based on the comparator operating clock clkc. Later embodiments will detail how the clock pulse signal is delayed when selected by the signal selection circuit to generate the read clock signal clk. For example, in generating... Figure 4 When the clock is as shown, the clock pulse generation circuit may include an inverting path for obtaining the inverted clock clkcb of the working clock clkc; a delay path for obtaining the delayed clock clkc1 of clkc; and an AND gate for obtaining... Figure 4 The clk is shown. In other embodiments, clkc can also be obtained by directly delaying it for a sufficient period of time. This invention does not limit the method of generating clock pulse signals based on the working clock.

[0056] Therefore, the signal selection circuit can select the signal upon receiving a read pulse signal (e.g.) Figure 3 When Q' is read, the read pulse signal is used to generate a read clock signal clk for the data register 520 to read the first comparison result generated by the dynamic comparator 510 (i.e., Q'). Figure 5 The data is fed into the Q register of data register 520, which can be used even when no read pulse signal is received (e.g., ...). Figure 4 When Q' is reached, a clock pulse signal is used to generate a read clock signal clk for the data register 520 to read the first comparison result generated by the dynamic comparator 510 (i.e., Q'). Figure 5 The data is sent to data register 520 (Q). Therefore, if there is a read pulse signal (such as...) Figure 3 The Q' signal shown is generated, and this read pulse signal must arrive before the clock pulse signal. If there is no read pulse signal (such as...), Figure 4 Once Q' is generated as shown, the signal selection circuit then uses the clock pulse signal to generate the read clock signal.

[0057] Therefore, in one embodiment, a clock pulse signal (e.g., p1 in Figure 10) can be generated based on each valid pulse of the operating clock, for example, a high-level clkc. Whether this clock pulse signal is used to generate the read clock for the comparison result depends on whether a read pulse signal is generated. If a read pulse signal (e.g., vo in Figure 10) is generated, the signal selection circuit directly uses the read pulse signal to generate the read clock signal clk; otherwise, the signal selection circuit uses the clock pulse signal to generate the read clock signal clk.

[0058] Figure 9 A schematic diagram of the composition of a read clock generation circuit according to an embodiment of the present invention is shown. Figure 10A -B shows Figure 9 The timing diagrams of the circuit shown are for the circuits in the absence of metastability and the presence of metastability.

[0059] like Figure 9 As shown, the read clock generation circuit 950 is connected to the two outputs op and on of the dynamic comparator. op and on are each inverted via inverters to obtain inverted signals vop and von. Here, the two inverters can be the inverters with the lower threshold Vth1 as described above, which can be used as the metastable signal extraction logic gate 951 to ensure that a read pulse signal is output only when the comparator is performing a normal comparison (i.e., no metastability occurs).

[0060] One of the two outputs of the dynamic comparator, such as op in the diagram, is used as the comparison result Q fed into data register 520. Before being fed into data register 520, op can pass through two inverters, thereby increasing the driving capability of subsequent stages.

[0061] Since a high-level pulse is always included in VOP and VONP during normal comparison by the comparator, it is possible to extract the pulse after passing through OR gate 952. Figure 10A The read pulse signal vo is shown in the diagram. The first logic gate circuit 957 may include a metastable signal extraction logic gate 951 and an OR gate 952 to generate the read pulse signal vo when the first comparison result op and the second comparison result on correspond to different levels. However, the invention is not limited to this. For example, if the reset level of the dynamic comparator is low, then when metastability occurs, both op and on are low, and the first logic gate circuit 957 may only include an OR gate 952. The selection and delay of the read pulse signal vo to obtain the read clock signal clk will be described in detail later.

[0062] Accordingly, the clock clkc can be as follows Figure 9As shown, clkca is obtained after being delayed by four inverters. In one embodiment, clkca can be used as the comparator's operating clock and fed into, for example... Figure 6 In the dynamic comparator shown, clkca and the inverted clkcb1 can generate a clock pulse signal p1 via AND gate 953. In summary, the clock pulse generation circuit 958 generates a clock pulse signal p1 based on the comparator's operating clock clkc. Figure 9 In one embodiment, the clock pulse generation circuit 958 includes four inverters and an AND gate 953. However, the invention is not limited thereto; the number and configuration of the inverters can be varied according to timing and drive capability requirements.

[0063] In such Figure 10A When no metastability occurs, the high-level pulse generated by vo can pass through transmission gate 1 (954), and after being delayed by transmission gate 1 and two inverters, it is sent to data register 520 as the read clock clk, which is used to read the comparison result Q.

[0064] In such Figure 10B When metastability occurs, vo is always low. At this time, the clock pulse signal pl can be sent to the data register 520 as the read clock clk after being delayed by the transmission gate 2 (955) and the two inverters, so as to read the comparison result Q.

[0065] In detail, the signal selection circuit 959 may include a first transmission gate 954, a second transmission gate 955, and a delay circuit 956: the two control terminals of the first transmission gate 954 are respectively coupled to the read pulse signal vo and the inverted signal of the read pulse signal vo, and its input terminal is coupled to the read pulse signal vo. When the read pulse signal vo is high, the first transmission gate 954 is turned on to output the read pulse signal vo; the two control terminals of the second transmission gate 955 are respectively coupled to the inverted signal of the read pulse signal vo and the read pulse signal vo, and its input terminal is coupled to the clock pulse signal vo. When the read pulse signal vo is low, the second transmission gate 955 is turned on to output the clock pulse signal pl; the delay circuit 956 delays the outputs of the first transmission gate 954 and the second transmission gate 955 to generate the read clock signal clk.

[0066] It should be understood that it can also be used Figure 9 Other circuits shown (e.g., latches) implement the clock generation and signal selection circuits described in this invention. Figure 11 A schematic diagram of the composition of a read clock generation circuit according to an embodiment of the present invention is shown. Figure 12A -B shows Figure 11 The timing diagrams of the circuit shown are for the circuits in the absence of metastability and the presence of metastability.

[0067] Specifically, the two outputs op and on of the dynamic comparator can be as follows: Figure 6 As shown, each signal is inverted via an inverter to obtain inverted signals vop and von, which are then used as inputs to the read clock generation circuit 1150. In other embodiments, the read clock circuit 1150 is also as follows... Figure 9 Similar to the read clock generation circuit 950, it includes two inverters that invert the two outputs op and on of the dynamic comparator to obtain vop and von. At this point, one of the two outputs of the dynamic comparator, such as vop as shown in the diagram, is used as the comparison result Q fed into the data register 520. Before being fed into the data register 520, vop can pass through two inverters, thereby increasing the driving capability of subsequent stages.

[0068] Since a high-level pulse is necessarily included in both VOP and VONP during normal comparison by the comparator, it is possible to extract the pulse after passing through OR gate 1151. Figure 12A The read pulse signal vo is shown in the signal vo. At this time, the first logic gate circuit may only include OR gate 1151 (in other embodiments, it may further include two inverters that implement the metastable signal extraction logic gate to obtain vop and von from op and on), and generate the read pulse signal vo when the first comparison result op and the second comparison result on correspond to different levels.

[0069] Accordingly, the clock clkc can be as follows Figure 11 As shown, clkca is obtained after being delayed by 6 inverters. clkca can be used as the comparator's operating clock and fed into the circuit as shown. Figure 6 In the dynamic comparator shown, the clock clkc is passed through eight inverters to obtain clkc1. clkc1 and its inverted counterpart clkcb1 can then be used with NAND gate 1152 to generate a clock pulse signal p1. In summary, the clock pulse generation circuit 1157 generates the clock pulse signal p1 based on the comparator's operating clock clkc. Figure 11 In one embodiment, the clock pulse generation circuit 1157 includes 10 inverters and NAND gates 1152 (the last three inverters used to generate clkca are not included). However, the present invention is not limited thereto, and the number and connection of inverters can be varied according to timing and drive capability requirements.

[0070] This example and Figure 9 The differences are especially evident in Figure 11 The clock readout circuit 1150 shown uses a latch 1153 and a transmission gate 1155 controlled by a MOSFET 1156 to select the readout pulse signal vo and the clock pulse signal p1.

[0071] Specifically, Figure 11The signal selection circuit 1158 shown may further include logic circuitry for generating a selection pulse signal s1 based on the read pulse signal vo and the clock pulse signal pl. Specifically, this is implemented in the figure as a latch 1153 and an OR gate 1154. Under the control of the latch 1153, if no metastability occurs, the pulse of p1 (shown as a low-level pulse) cannot pass through the OR gate 1154. However, if metastability occurs, the pulse of p1 can pass through the OR gate 1154, causing the selection pulse signal s1 to change according to the clock pulse signal pl.

[0072] The signal selection circuit 1158 may further include a transmission gate 1155 and a corresponding switch 1156. The two control terminals of the transmission gate 1155 are respectively coupled to the selection pulse signal sl and the inverted signal s1b of the selection pulse signal, and its input terminal is coupled to the read pulse signal vo. The switch 1156 is implemented as a PMOS transistor, its control terminal is coupled to the selection pulse signal sl, and its output terminal is coupled to the output terminal of the transmission gate.

[0073] When no metastability occurs, the selection pulse signal s1 is always high, the switch 1156 is turned off, and the transmission gate 1155 is turned on, so that the read pulse signal vo can be output.

[0074] When metastability occurs, since the selection pulse signal s1 changes according to the clock pulse signal pl, the switch 1156 is turned on based on the pulse in the selection pulse signal s1, causing the transmission gate 1155 to output the selection pulse signal (which will be combined with the following). Figure 12B (Details omitted). The signal output from the 1155 gate can then be used by a delay circuit consisting of two NOT gates to generate a delayed read clock signal clk.

[0075] As shown in the figure, in such Figure 12A When no metastability occurs, the high-level pulse generated by VO can pass through latch 1153. Specifically, before the comparator starts comparison, the comparator clock clkc is low and pl is high. When clkc goes high, rb goes low, resetting dff1153, at which point ctrl is low. When the dynamic comparator does not experience metastability, one of the comparison results, VOP and von, must generate a high-level pulse. Therefore, the OR result VO must generate a high-level pulse. When the rising edge of clkcb arrives, the high-level pulse of VO is read, and ctrl goes high. The NAND of clkcb1 and clkc1 generates pl. If ctrl is high, the low-level pulse of pl cannot pass through the OR gate connected to it. The selection pulse signal S1 remains high and does not change with the change of pl. PMOS transistor 1156 is affected by V GS =0 and remains off, transmission gate 1155 conducts, outputting vo to clk. Conversely, if Figure 12BAs shown, if metastability occurs, vo will always be low, ctrl will also be low, and the low-level pulse of the clock pulse signal pl can pass through the OR gate connected to it, and the selection pulse signal s1 will generate a low-level pulse. When the selection pulse signal s1 is low, vo1 is pulled high. When the selection pulse signal s1 is high, the transmission gate 1155 is turned on, and vo1 is pulled low. Therefore, vo1 generates a high-level pulse, that is, the clock pulse signal pl can pass through the transmission gate 1155, and clk generates a high-level pulse.

[0076] Therefore, the clock generation circuit of the present invention can generate the clock clk normally regardless of whether the comparator is in a metastable state, thereby avoiding the error caused by the absence of a clock in the metastable state, which prevents the data register dff from reading the comparison result (i.e., the previous information will be retained).

[0077] Therefore, in one embodiment, the successive approximation analog-to-digital converter of the present invention includes: a first readout clock generation circuit connected to a first output and a second output of a dynamic comparator, and generating a first signal based on receiving a first comparison result from the first output and a second comparison result from the second output; a clock pulse generation circuit connected to the operating clock of the dynamic comparator, and generating a second signal based on the operating clock; and a metastability detection circuit, configured to, when detecting that the first signal includes a readout pulse signal, select the first signal to generate a readout clock signal to read the first comparison result of the first output of the dynamic comparator, and when not detecting that the first signal includes a readout pulse signal, select the second signal to generate the readout clock signal to read the first comparison result of the first output of the dynamic comparator.

[0078] Since a clock signal can be used to read the comparison result when metastability occurs, there is no need to reset the comparator. In the signal selection circuit of this invention, when metastability occurs, the read clock signal generated based on the operating clock of the dynamic comparator is selected to read the first comparison result generated by the dynamic comparator, and the shift register controlled by clkc can still shift normally. Because the logic of the SAR ADC has the function of automatically repairing the effects of metastability, metastability in this invention has no impact on the continuous operation of the SAR ADC, and its impact on the output result is also minimal.

[0079] In one embodiment, the invention can also be implemented as an electronic device comprising a successive approximation analog-to-digital converter as described above. The electronic device can be any device requiring a successive approximation analog-to-digital converter to convert analog voltage into digital, such as a sensor device.

[0080] The successive approximation analog-to-digital converter according to the present invention has been described in detail above with reference to the accompanying drawings. In the SARADC of the present invention, the read clock clk of the data register comes from the output of the comparator, thereby enabling the result to be read immediately after the comparison result is generated, thus improving the read speed. Furthermore, the signal selection circuit of the present invention can automatically select the spare clock generated by the comparator operating clock as the read clock when metastability occurs, thereby enabling the comparison result to be read even when metastability occurs, thus avoiding resetting the comparator.

[0081] The various embodiments of the present invention have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or improvement of the technology in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A successive approximation analog-to-digital converter, comprising: a dynamic comparator including a first output and a second output, the dynamic comparator generating a first comparison result and a second comparison result at the first output and the second output, respectively, based on a comparator operating clock; and a read clock generation circuit connected to the first output and the second output and generating a read clock signal for reading the comparison results based on the first comparison result and the second comparison result received from the dynamic comparator, wherein the read clock generation circuit includes: a first logic gate circuit for generating a read pulse signal when the first comparison result and the second comparison result correspond to different levels, the read pulse signal being delayed to obtain the read clock signal, wherein the first logic gate circuit includes: a metastable signal extraction logic gate connected to the first output and the second output and capable of extracting a same level signal when a metastable state occurs.

2. The successive approximation analog-to-digital converter of claim 1, wherein, A signal extraction threshold of the metastable signal extraction logic gate is set between an inverse level of a reset level of the dynamic comparator and a metastable level.

3. The successive approximation analog-to-digital converter of claim 2, wherein, The metastable signal extraction logic gate includes: a first NOT gate connected to the first output and a second NOT gate connected to the second output, wherein: when the reset level of the dynamic comparator is high, a flip threshold of the first NOT gate and the second NOT gate is set between a low level and the metastable level; when the reset level of the dynamic comparator is low, the flip threshold of the first NOT gate and the second NOT gate is set between a high level and the metastable level.

4. The successive approximation analog-to-digital converter of claim 2, wherein, The same level signal extracted by the metastable signal extraction logic gate when a metastable state occurs causes the read clock generation circuit to generate the read clock signal based on the dynamic comparator operating clock.

5. The successive approximation analog-to-digital converter of claim 1, the read clock generation circuit further comprising: a signal selection circuit for selecting the read clock signal generated based on the read pulse signal generated based on the first and second comparison results when the first comparison result and the second comparison result correspond to different levels, and selecting the read clock signal generated based on a clock pulse signal generated based on the dynamic comparator operating clock when the first comparison result and the second comparison result correspond to the same level.

6. The successive approximation analog-to-digital converter of claim 5, further comprising: a data register reading the first comparison result using the read clock signal generated by the signal selection circuit.

7. The successive approximation analog-to-digital converter of claim 5, wherein, The first logic gate circuit is for generating the read pulse signal based on the first comparison result and the second comparison result when the first comparison result and the second comparison result correspond to different levels, and the read clock generation circuit further comprises: a clock pulse generation circuit for generating the clock pulse signal based on the comparator operating clock, wherein the read pulse signal is generated prior to the clock pulse signal.

8. The successive approximation analog-to-digital converter of claim 5, wherein the signal selection circuit includes: a first transmission gate, having two control terminals coupled to the read pulse signal and an inverted read pulse signal respectively, and an input terminal coupled to the read pulse signal, when the read pulse signal is high, the first transmission gate is turned on to output the read pulse signal; and a second transmission gate, having two control terminals coupled to the inverted read pulse signal and the read pulse signal respectively, and an input terminal coupled to the clock pulse signal, when the read pulse signal is low, the second transmission gate is turned on to output the clock pulse signal; and a delay circuit, generating the read clock signal by delaying the outputs of the first and second transmission gates.

9. The successive approximation analog-to-digital converter of claim 5, wherein the signal selection circuit comprises: a logic circuit, generating a selection pulse signal according to the read pulse signal and the clock pulse signal, the selection pulse signal varying with the clock pulse signal when the read pulse signal has a level indicating that the first comparison result and the second comparison result correspond to different levels; a transmission gate, having two control terminals coupled to the selection pulse signal and an inverted selection pulse signal respectively, and an input terminal coupled to the read pulse signal, when the read pulse signal has a pulse indicating that the first comparison result and the second comparison result correspond to different levels, the transmission gate is turned on to output the read pulse signal; and a switch, having a control terminal coupled to the selection pulse signal, and an output terminal coupled to the output terminal of the transmission gate, when the selection pulse signal does not vary with the clock pulse signal, the switch is turned off, when the selection pulse signal varies with the clock pulse signal, the switch outputs the clock pulse signal in combination with the transmission gate; a delay circuit, generating the read clock signal by delaying the outputs of the transmission gate and switch.

10. A successive approximation analog-to-digital converter, comprising: a first read clock generation circuit, connected to a first output terminal and a second output terminal of a dynamic comparator, and generating a first signal based on receiving a first comparison result from the first output terminal and a second comparison result from the second output terminal; a clock pulse generation circuit, connected to a comparator operating clock of the dynamic comparator, and generating a second signal based on the operating clock, a metastable state detection circuit, for selecting the first signal to generate a read clock signal to read the first comparison result of the dynamic comparator when detecting that the first signal includes a read pulse signal, and selecting the second signal to generate the read clock signal to read the first comparison result of the dynamic comparator when detecting that the first signal does not include the read pulse signal.

11. An electronic device, comprising the successive approximation analog-to-digital converter of claims 1-10.

Images