Display device and method of manufacturing a display device

Abstract

Provided are a display device and a method of manufacturing a display device, in which a hole is provided in an inorganic insulating layer in a region overlapping with an outer peripheral line of a flexible film or a region adjacent to the outer peripheral line of the flexible film, which makes it possible to suppress propagation of a crack caused by an air gap in a pad region and improve reliability of the display device, in accordance with embodiments of the present disclosure.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2021-0179516, filed on December 15, 2021, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference. Technical Field

[0003] This disclosure relates to display devices, and more specifically, to display devices that do not use plastic substrates, thereby improving moisture transport characteristics, reducing parasitic capacitance, and minimizing the occurrence and propagation of cracks in the pad areas. Background Technology

[0004] Display devices used in monitors for computers, televisions, mobile phones, etc., include organic light-emitting display (OLED) devices configured to emit light autonomously, and liquid crystal display (LCD) devices that require a separate light source.

[0005] The applications of display devices are diverse, ranging from monitors for computers and televisions to monitors for personal mobile devices, and research is underway on display devices with wide display areas and reduced size and weight.

[0006] In addition, flexible display devices have recently attracted attention as the next generation of display devices. These flexible display devices are made by forming display elements, circuits, etc. on a substrate made of flexible plastic material, and therefore can even display images when folded or rolled up. Summary of the Invention

[0007] One technical benefit provided by this disclosure is the ability to provide a display device that uses a substrate with a transparent conductive oxide layer and an oxide semiconductor layer instead of a plastic substrate.

[0008] One objective of this disclosure is to provide a display device that reduces, and in some cases eliminates, the infiltration of moisture and oxygen, or minimizes the infiltration of moisture and oxygen.

[0009] Another objective of this disclosure is to provide a display device that simplifies processing and reduces manufacturing costs by eliminating the use of a plastic substrate.

[0010] Another objective of this disclosure is to provide a display device that can reduce the occurrence and propagation of cracks in the peripheral region of a flexible film.

[0011] Another objective of this disclosure is to provide a display device in which the connecting wires are made of the same material as the anode, thereby ensuring leeway for the holes disposed in the inorganic insulating layer.

[0012] The purpose of this disclosure is not limited to the purposes mentioned above, but rather other purposes not mentioned above will be clearly understood by those skilled in the art based on the following description.

[0013] According to one aspect of this disclosure, a display device includes: a substrate configured as one of a transparent conductive oxide layer and an oxide semiconductor layer, and including a display area and a non-display area. The display area includes a plurality of sub-pixels; an insulating layer disposed on the substrate; an active layer disposed on the insulating layer and having a channel region; a plurality of thin-film transistors including a gate electrode, a source electrode, and a drain electrode; and a plurality of light-emitting elements disposed on the insulating layer and disposed in the plurality of sub-pixels, wherein the substrate includes a plurality of holes overlapping at least a portion of the active layer. Therefore, the substrate can be made of a transparent conductive oxide layer or an oxide semiconductor layer, and the plurality of holes can be disposed in the substrate. Thus, a display device with improved flexibility and reduced parasitic capacitance can be provided.

[0014] Further details of the exemplary implementation are included in the detailed implementation and the accompanying drawings.

[0015] According to this disclosure, moisture penetration can be easily controlled by using a transparent conductive oxide layer or an oxide semiconductor layer as the substrate of the display device.

[0016] According to this disclosure, the flexibility of a display device can be improved by using a thin-film transparent conductive oxide layer or a thin-film oxide semiconductor layer as the substrate of the display device.

[0017] According to this disclosure, a thin-film transparent conductive oxide layer or a thin-film oxide semiconductor layer is used as the substrate of the display device. Therefore, stress occurring when the display device is bent or rolled up can be reduced, thereby reducing cracks in the display device.

[0018] According to this disclosure, the structure of a display device can be simplified and manufacturing costs reduced by using a transparent conductive oxide layer or an oxide semiconductor layer as the substrate of the display device.

[0019] According to this disclosure, static electricity generated on the substrate and display quality can be improved by using a transparent conductive oxide layer or an oxide semiconductor layer as the substrate of the display device.

[0020] According to this disclosure, the substrate for a display device can be manufactured by deposition in a vacuum environment. Therefore, substrate manufacturing time can be shortened and the occurrence of particles on the substrate and defects caused by these particles can be reduced.

[0021] According to this disclosure, the holes are located in the inorganic insulating layer in a region overlapping with or adjacent to the outer perimeter of the flexible film. Therefore, the propagation of cracks caused by air gaps in the pad region can be suppressed, and the reliability of the display device can be improved.

[0022] According to this disclosure, the link lines can be formed as pixel link lines, and the holes can be disposed in the inorganic insulating layer in a region adjacent to the outer periphery of the flexible film, without limitation in size. Therefore, the occurrence of cracks in the inorganic insulating layer can be suppressed more effectively.

[0023] The effects of this disclosure are not limited to those exemplified above, and include a variety of other effects. Attached Figure Description

[0024] The above and other aspects, features and advantages of this disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0025] Figure 1 This is a top plan view of a display device according to an embodiment of the present disclosure;

[0026] Figure 2 This is a schematic cross-sectional view of a display device according to an embodiment of the present disclosure;

[0027] Figure 3 This is a circuit diagram of a sub-pixel of a display device according to an embodiment of the present disclosure;

[0028] Figure 4 yes Figure 1 Enlarged view of region A in the middle;

[0029] Figures 5A to 5C It is along Figure 4 Schematic cross-sectional views taken from the midline Va-Va', Vb-Vb', and Vc-Vc';

[0030] Figure 6 This is a cross-sectional view of a display device according to another embodiment of the present disclosure;

[0031] Figure 7 This is an enlarged top plan view of a display device according to yet another embodiment of the present disclosure;

[0032] Figure 8 This is an enlarged top plan view of a display device according to yet another embodiment of the present disclosure;

[0033] Figure 9 It is along Figure 8 A schematic cross-sectional view taken from lines VIIII-VIIII' in the diagram; and

[0034] Figure 10 This is a cross-sectional view of a display device according to yet another embodiment of the present disclosure. Detailed Implementation

[0035] Please refer to the following and appendix. Figure 1 The advantages and features of this disclosure, as well as methods for achieving these advantages and features, will become clear from the exemplary embodiments described in detail herein. However, this disclosure is not limited to the exemplary embodiments disclosed herein, but will be implemented in various forms. Exemplary embodiments are provided by way of example only so that those skilled in the art can fully understand the disclosure and scope of this disclosure. The shapes, dimensions, ratios, angles, numbers, etc., shown in the accompanying drawings for the purpose of describing exemplary embodiments of this disclosure are merely examples, and this disclosure is not limited thereto. Throughout this specification, the same reference numerals generally denote the same elements. Furthermore, in the following description of this disclosure, detailed descriptions of known related technologies may be omitted to avoid unnecessarily obscuring the subject matter of this disclosure. Terms such as “comprising,” “having,” and “consisting of” as used herein are generally intended to allow for the addition of additional components, unless these terms are used in conjunction with the term “only.” Unless otherwise expressly stated, any reference to the singular may include the plural.

[0036] The term "component" is interpreted to include both normal error range and manufacturing tolerance, even if not explicitly stated otherwise.

[0037] When using terms such as “above,” “over,” “below,” and “adjacent” to describe the positional relationship between two parts, one or more parts may be positioned between the two parts, unless these terms are used in conjunction with the terms “adjacent” or “direct.”

[0038] When one element or layer is placed on another element or layer, other layers or other elements can be directly inserted on the other element or between one element or layer and another element or layer.

[0039] Although the terms "first," "second," etc., are used to describe various components, these components are not limited by these terms. These terms are merely used to distinguish one component from other components. Therefore, in the technical concept of this disclosure, the first component referred to below can be the second component.

[0040] The dimensions and thicknesses of each component shown in the accompanying drawings are for ease of description, and this disclosure is not limited to the dimensions and thicknesses of the components shown.

[0041] Features of various embodiments of this disclosure may be partially or wholly dependent on or combined with each other, and may be technically interlocked and operated in various ways, and these embodiments may be performed independently or in conjunction with each other.

[0042] In the following, various exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0043] Figure 1 This is a top plan view of a display device according to an embodiment of the present disclosure. Figure 2 This is a schematic cross-sectional view of a display device according to an embodiment of the present disclosure. For ease of description, Figure 1 Only the substrate 110, multiple flexible films 160 and multiple printed circuit boards 170 among the various components of the display device 100 are shown.

[0044] Reference Figure 1 and Figure 2 The substrate 110 is a support member for supporting other components of the display device 100. The substrate 110 can be made of any of transparent conductive oxides and oxide semiconductors. For example, the substrate 110 can be made of transparent conductive oxides (TCOs) such as indium tin oxide (ITO), indium zinc oxide (IZO), and indium tin zinc oxide (ITZO).

[0045] Alternatively, substrate 110 can be made of oxide semiconductor materials containing indium (In) and gallium (Ga), such as transparent oxide semiconductors like indium gallium zinc oxide (IGZO), indium gallium oxide (IGO), and indium tin zinc oxide (ITZO). However, the types of transparent conductive oxide and oxide semiconductor materials provided are exemplary. Substrate 110 can be made of other transparent conductive oxide and oxide semiconductor materials not disclosed in this specification. However, this disclosure is not limited thereto.

[0046] Meanwhile, the substrate 110 can be formed by depositing a transparent conductive oxide or oxide semiconductor with a very small thickness. Therefore, since the substrate 110 has a very small thickness, it can be flexible. Furthermore, the display device 100 including the flexible substrate 110 can be implemented as a flexible display device 100, which can display images even when folded or rolled up. For example, in the case where the display device 100 is a foldable display device, the substrate 110 can be folded or unfolded about a folding axis. As another example, in the case where the display device 100 is a rollable display device, the display device can be rolled up and stored. Therefore, the display device 100 according to the embodiments of this disclosure can be implemented as a flexible display device 100, such as a foldable display device or a rollable display device, by using the flexible substrate 110.

[0047] Furthermore, the display device 100 according to embodiments of this disclosure can perform a laser lift-off (LLO) process using a substrate 110 made of a transparent conductive oxide or oxide semiconductor. LLO process refers to a process during the manufacturing of the display device 100 where a temporary substrate disposed beneath the substrate 110 is separated from the substrate 110 using a laser. Therefore, the substrate 110 is a layer used to further facilitate the LLO process, and thus the substrate 110 can be referred to as a functional thin film, a functional thin film layer, or a functional substrate. The LLO process will be described in more detail below.

[0048] The substrate 110 includes a display area AA and a non-display area NA.

[0049] The display area AA is an area that includes multiple sub-pixels SP to display an image. To display an image, pixel units 120 comprising multiple sub-pixels SP can be provided in the display area AA. For example, pixel unit 120 may include multiple sub-pixels SP, each sub-pixel SP including a light-emitting element and a driving circuit, thereby displaying the image.

[0050] The non-display area NA is a region located outside the display area AA and does not display any image. The non-display area NA can be set to surround the display area AA.

[0051] The non-display area NA includes the pad area PA, the link area LA located between the display area AA and the pad area PA, and the peripheral area EA of the display area AA.

[0052] The link area LA extends from one side of the display area AA. The link area LA is the region where multiple link lines are configured to connect multiple pad electrodes to multiple sub-pixels SP and send signals to the display area AA. Various link lines can be arranged in the link area LA. For example, data link lines, gate link lines, and high-potential voltage supply line connections can be arranged in the link area LA.

[0053] The pad area PA is the area where no image is displayed. Multiple pad electrodes are disposed in the pad area PA. The pad area PA extends from one side of the link area LA. The pad area PA is the area where multiple pad electrodes and external modules such as the flexible film 160 are bonded and electrically connected.

[0054] The peripheral region EA extends from the lateral portion of another display region AA that does not have a link region LA. The peripheral region EA can extend from three lateral portions of the display region AA. For example, the gate drive circuit can be located in the peripheral region EA.

[0055] Multiple flexible films 160 are disposed at one end of the substrate 110. The multiple flexible films 160 are electrically connected to one end of the substrate 110. The multiple flexible films 160 are films having various types of components disposed on a stretchable base film to provide signals to multiple sub-pixels in the display area AA. One end of the multiple flexible films 160 can be disposed in the non-display area NA of the substrate 110, and provide data voltages, etc., to multiple sub-pixels SP in the display area AA. Meanwhile, Figure 1 Four flexible membranes 160 are shown. However, the number of flexible membranes 160 can be varied depending on the design. However, this disclosure is not limited thereto.

[0056] Printed circuit board 170 is connected to multiple flexible films 160. Printed circuit board 170 is a component for providing signals to a driver IC. Various types of components for providing various signals such as drive signals and data voltages to the driver IC can be disposed on printed circuit board 170. Meanwhile, Figure 1 Two printed circuit boards 170 are shown. However, the number of printed circuit boards 170 can vary depending on the design. This disclosure is not limited thereto.

[0057] Reference Figure 2 An insulating layer IN is provided on the substrate 110. The insulating layer IN can suppress the diffusion of moisture and / or oxygen that permeates from the outside of the substrate 110. The moisture transport characteristics of the display device 100 can be controlled by controlling the thickness or layering structure of the insulating layer IN. In addition, the insulating layer IN prevents the substrate 110, which is made of transparent conductive oxide or oxide semiconductor, from being short-circuited when in contact with other components such as pixel units 120. The insulating layer IN can be made of a single layer or multiple layers of inorganic material, for example, configured as silicon oxide (SiOx) or silicon nitride (SiNx). However, the present disclosure is not limited thereto.

[0058] Pixel unit 120 is disposed on insulating layer IN. Pixel unit 120 can be configured to correspond to display area AA. Pixel unit 120 includes a plurality of sub-pixels SP and is configured to display an image. Pixel unit 120 consists of a plurality of elements and various layers, including transistors, conductors, semiconductors, insulators, light-emitting materials, and other materials and layers having circuitry constituting the pixel and circuitry for driving and controlling the pixel. For ease of reference, details of the pixel unit are not shown because its structure can be any structure known in the art. The plurality of sub-pixels SP of pixel unit 120 are the smallest units constituting display area AA. Light-emitting elements and driving circuitry can be disposed in each of the plurality of sub-pixels SP. For example, the light-emitting element of each of the plurality of sub-pixels SP may include an organic light-emitting element having an anode, an organic light-emitting layer, and a cathode, or may include an LED having N-type and P-type semiconductor layers and a light-emitting layer. However, this disclosure is not limited thereto. Furthermore, the driving circuitry for operating the plurality of sub-pixels may include driving elements such as thin-film transistors and storage capacitors. However, this disclosure is not limited thereto. In the following text, for ease of description, it is assumed that the light-emitting element of each of the plurality of sub-pixels SP is an organic light-emitting element. However, this disclosure is not limited thereto.

[0059] Meanwhile, the display device 100 can be a top-emitting display device or a bottom-emitting display device, depending on the direction in which light is emitted from the light-emitting element.

[0060] The top-emitting display device allows light emitted from the light-emitting element to propagate towards the upper side of the substrate 110 on which the light-emitting element is disposed. The top-emitting display device may form a reflective layer below the anode so that light emitted from the light-emitting element can propagate towards the upper side of the substrate 110, that is, towards the cathode.

[0061] Bottom-emitting display devices allow light emitted from the light-emitting element to propagate toward the underside of the substrate 110 on which the light-emitting element is disposed. In the case of a bottom-emitting display device, the anode may be made of only a transparent conductive material, and the cathode may be made of a metal material with high reflectivity, so that light emitted from the light-emitting element can propagate toward the underside of the substrate 110.

[0062] In the following description, for ease of description, the display device 100 according to the embodiments of this disclosure will be described as a bottom-emitting display device. However, this disclosure is not limited thereto.

[0063] A sealing layer 130 is configured to cover pixel unit 120. The sealing layer 130 seals the pixel unit 120 and protects the light-emitting element of the pixel unit 120 from external moisture, oxygen, impact, etc. The sealing layer 130 can be formed by alternately stacking multiple inorganic material layers and multiple organic material layers. For example, the inorganic material layers can be made of inorganic materials such as silicon nitride (SiNx), silicon oxide (SiOx), or aluminum oxide (AlOx). The organic material layers can be made of epoxy polymers or acrylic polymers. However, this disclosure is not limited thereto. Additionally, the sealing layer 130 can be configured as a surface-sealing type sealing layer. For example, the sealing layer 130 can be formed by applying a UV-curable or thermosetting sealant to the entire surface of the pixel unit 120. However, the sealing layer 130 can have various structures and be made of various materials. However, this disclosure is not limited thereto.

[0064] Simultaneously, a sealing substrate can also be disposed on the sealing layer 130. This sealing substrate can be made of a metallic material with high modulus and high corrosion resistance. For example, the sealing substrate can be made of a material with a modulus of up to approximately 200 MPa to 900 MPa. The sealing substrate can be made of metallic materials that are easily processed into foil or film form and have high corrosion resistance, such as aluminum (Al), nickel (Ni), chromium (Cr), iron (Fe), and nickel alloys. Therefore, since the sealing substrate is made of a metallic material, it can be implemented in the form of an ultra-thin film and has strong protective properties against external impacts and scratches.

[0065] A sealing member 140 is configured to surround the side surfaces of the pixel unit 120 and the sealing layer 130. The sealing member 140 may be disposed in the non-display area NA and configured to surround the pixel unit 120 disposed in the display area AA. The sealing member 140 may be configured to surround the side surfaces of the pixel unit 120 and the sealing layer 130, thereby reducing and, in some cases, completely eliminating moisture penetration into the pixel unit 120. For example, the sealing member 140 may be configured to cover a portion of the top surface of the insulating layer IN that overlaps with the non-display area NA protruding outside the pixel unit 120. The sealing member 140 may be configured to cover a portion of the side surface of the sealing layer 130 and be configured to surround the pixel unit 120. The sealing member 140 may be configured to cover a portion of the top surface of the sealing layer 130.

[0066] The sealing member 140 may be made of a flexible, non-conductive material to seal the side surface of the pixel unit 120 and increase the rigidity of the side surface of the display device 100. Additionally, the sealing member 140 may be made of an adhesive material. Furthermore, the sealing member 140 may include a desiccant to absorb moisture and oxygen from the outside and minimize the penetration of moisture through the lateral portion of the display device 100. For example, the sealing member 140 may be made of polyimide (PI), polyurethane, epoxy resin, or acrylic-based materials. However, this disclosure is not limited thereto.

[0067] A polarizing plate 150 is disposed below the substrate 110. The polarizing plate 150 selectively transmits light and reduces the reflection of external light incident on the substrate 110. Specifically, the display device 100 has various metallic materials formed on the substrate 110 and applied to semiconductor elements, circuits, and light-emitting elements. Therefore, external light incident on the substrate 110 may be reflected by the metallic materials. The reflection of external light may reduce the visibility of the display device 100. In this case, a polarizing plate 150 for suppressing the reflection of external light can be disposed below the substrate 110, thereby improving the outdoor visibility of the display device 100. Depending on the design of the display device, a polarizing plate may also be disposed above the sealing layer 130 in addition to or as a replacement for the polarizing plate 150. However, depending on the implementation of the display device 100, the polarizing plate 150 may be omitted.

[0068] Meanwhile, although not shown in the accompanying drawings, the barrier film can be disposed below the substrate 110 together with the polarizer 150. The barrier film can reduce the permeation of moisture and oxygen present outside the substrate 110 into the substrate 110, thereby protecting the pixel unit 120 including the light-emitting element. However, depending on the implementation of the display device 100, the barrier film can be omitted. However, this disclosure is not limited thereto.

[0069] In the following text, reference will be made to Figures 3 to 5C The non-display area NA is described in more detail, in which multiple flexible films 160 and pixel units 120 are arranged in multiple sub-pixels SP.

[0070] Figure 3 This is a circuit diagram of a sub-pixel of a display device according to an embodiment of the present disclosure.

[0071] Reference Figure 3 The driving circuit for operating the light-emitting element OLED of each of the multiple sub-pixels SP includes a first transistor TR1, a second transistor TR2, a third transistor TR3, and a storage capacitor SC. Furthermore, for operating the driving circuit, multiple lines are provided on the substrate 110, and these multiple lines include a gate line GL, a data line DL, a high-potential power line VDD, a sensing line SL, and a reference line RL.

[0072] The first transistor TR1, the second transistor TR2, and the third transistor TR3 included in the driving circuit of a single sub-pixel SP each include a gate electrode, a source electrode, and a drain electrode.

[0073] Furthermore, the first transistor TR1, the second transistor TR2, and the third transistor TR3 can each be a P-type thin-film transistor or an N-type thin-film transistor. For example, in a P-type thin-film transistor, positive holes flow from the source electrode to the drain electrode, allowing current to flow from the source electrode to the drain electrode. In an N-type thin-film transistor, electrons flow from the source electrode to the drain electrode, allowing current to flow from the drain electrode to the source electrode. In the following description, it is assumed that the first transistor TR1, the second transistor TR2, and the third transistor TR3 can each be an N-type thin-film transistor in which current flows from the drain electrode to the source electrode. However, this disclosure is not limited thereto.

[0074] The first transistor TR1 includes a first active layer, a first gate electrode, a first source electrode, and a first drain electrode. The first gate electrode is connected to a first node N1. The first source electrode is connected to the anode of the light-emitting element OLED. The first drain electrode is connected to the high-potential power line VDD. The first transistor TR1 can be turned on when the voltage of the first node N1 is higher than a threshold voltage. The first transistor TR1 can be turned off when the voltage of the first node N1 is lower than the threshold voltage. Furthermore, when the first transistor TR1 is turned on, drive current can be transmitted to the light-emitting element OLED through the first transistor TR1. Therefore, the first transistor TR1, configured to control the drive current to be supplied to the light-emitting element OLED, can be referred to as a drive transistor.

[0075] The second transistor TR2 includes a second active layer, a second gate electrode, a second source electrode, and a second drain electrode. The second gate electrode is connected to the gate line GL. The second source electrode is connected to the first node N1. The second drain electrode is connected to the data line DL. The second transistor TR2 can be turned on or off based on the gate voltage from the gate line GL. When the second transistor TR2 is turned on, the first node N1 can be charged using the data voltage from the data line DL. Therefore, the second transistor TR2, configured to be turned on or off by the gate line GL, can be referred to as a switching transistor.

[0076] The third transistor TR3 includes a third active layer, a third gate electrode, a third source electrode, and a third drain electrode. The third gate electrode is connected to the sensing line SL. The third source electrode is connected to the second node N2. The third drain electrode is connected to the reference line RL. The third transistor TR3 can be turned on or off based on the sensed voltage from the sensing line SL. Furthermore, when the third transistor TR3 is turned on, the reference voltage can be transferred from the reference line RL to the second node N2 and the storage capacitor SC. Therefore, the third transistor TR3 can be referred to as a sensing transistor.

[0077] at the same time, Figure 3 The diagram shows that the gate line GL and the sensing line SL are separate lines. However, the gate line GL and the sensing line SL can be implemented as a single line. However, this disclosure is not limited thereto.

[0078] The storage capacitor SC is connected between the first gate electrode and the first source electrode of the first transistor TR1. That is, the storage capacitor SC can be connected between the first node N1 and the second node N2. When the OLED emits light, the storage capacitor SC can supply a predetermined driving current to the OLED by maintaining the potential difference between the first gate electrode and the first source electrode of the first transistor TR1. The storage capacitor SC includes multiple capacitor electrodes. For example, one capacitor electrode can be connected to the first node N1, and another capacitor electrode can be connected to the second node N2.

[0079] The light-emitting element (OLED) includes an anode, an emissive layer, and a cathode. The anode of the OLED is connected to a second node N2, and the cathode is connected to a low-potential power line VSS. The OLED can emit light by receiving a drive current from a first transistor TR1.

[0080] at the same time, Figure 3 The driving circuit for the sub-pixel SP of the display device 100 according to an embodiment of the present disclosure is shown to have a 3T1C structure including three transistors and a single storage capacitor SC. However, the number of transistors, the number of storage capacitors SC, and the connection relationship between the transistors and the storage capacitors can be varied according to the design. The present disclosure is not limited thereto.

[0081] Figure 4 yes Figure 1 A magnified view of region A in the middle. Figures 5A to 5C This is a schematic cross-sectional view taken along lines Va-Va', Vb-Vb', and Vc-Vc'. For ease of explanation, Figure 4 Printed circuit board 170 is not shown. In the component in pad area PA, a flexible film 160 and a portion of the pad electrode P are shown. In the component in link area LA, multiple link lines LL are shown. Additionally, a portion of display area AA is shown. Figure 5A This is a cross-sectional view showing a subpixel SP, specifically a cross-sectional view showing a red subpixel. However, this disclosure is not limited thereto. Figure 5B This is a cross-sectional view showing the area where the connecting line LL is provided. Figure 5C This is a cross-sectional view showing the area where the linking line LL is not provided, that is, a cross-sectional view showing a portion of the edge region and linking region LA of the flexible membrane 160.

[0082] Refer to together Figures 3 to 5A The display device 100 according to the embodiments of the present disclosure includes a substrate 110, an insulating layer IN, a light blocking layer LS, an auxiliary high-potential power line VDDa, a storage capacitor SC, a first transistor TR1, a light-emitting element OLED, a color filter CF, a first inorganic insulating layer 111, a gate insulating layer 112, a second inorganic insulating layer 113, an organic insulating layer 114, and a dam 115.

[0083] Although not shown in the accompanying drawings, multiple high-potential power lines VDD, multiple data lines DL, multiple reference lines RL, and a light-blocking layer LS can be disposed on the same layer on the substrate 110 and made of the same conductive material. For example, the multiple high-potential power lines VDD, multiple data lines DL, multiple reference lines RL, and the light-blocking layer LS can be made of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or alloys thereof. However, this disclosure is not limited thereto.

[0084] Multiple high-potential power lines (VDDs) are lines used to transmit high-power voltages to each of multiple sub-pixels (SPs). Multiple high-potential power lines (VDDs) can extend along the column direction between the multiple sub-pixels (SPs). Two sub-pixels (SPs) adjacent to each other in the row direction can share a single high-potential power line (VDD).

[0085] Multiple data lines (DL) are lines that extend along the column direction between multiple sub-pixels (SP) and transmit data voltage to each of the multiple sub-pixels (SP).

[0086] Multiple reference lines RL are lines extending along the column direction between multiple sub-pixels SP, and transmit a reference voltage to each of the multiple sub-pixels SP. Multiple sub-pixels SP that make up a single pixel can share a single reference line RL.

[0087] Reference Figure 5AA light-blocking layer LS is disposed on the insulating layer IN. The light-blocking layer LS can be configured to overlap with the first active layer ACT1 of at least the first transistor TR1 among the plurality of transistors TR1, TR2, and TR3, and suppress light from entering the first active layer ACT1. If light shines on the first active layer ACT1, leakage current occurs, which may reduce the reliability of the first transistor TR1 as a driving transistor. In this case, when the light-blocking layer LS, made of an opaque conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or alloys thereof, is configured to overlap with the first active layer ACT1, the light-blocking layer LS can suppress light from entering the first active layer ACT1 from the underside of the substrate 110, thereby improving the reliability of the first transistor TR1. However, this disclosure is not limited thereto. The light-blocking layer LS can be configured to overlap with the second active layer of the second transistor TR2 and the third active layer of the third transistor TR3.

[0088] Meanwhile, the accompanying drawings show that the light-blocking layer LS is a single layer. However, the light-blocking layer LS can be configured as multiple layers. For example, the light-blocking layer LS can be configured as multiple layers, which are configured to overlap with at least one of the insulating layer IN, the first inorganic insulating layer 111, the gate insulating layer 112, and the second inorganic insulating layer 113 inserted therebetween.

[0089] A first inorganic insulating layer 111 is disposed on a plurality of high-potential power lines VDD, a plurality of data lines DL, a plurality of reference lines RL, and a light-blocking layer LS. The first inorganic insulating layer 111 can reduce the penetration of moisture or impurities through the substrate 110. Therefore, the first inorganic insulating layer 111 can be referred to as a buffer layer. For example, the first inorganic insulating layer 111 can be configured as a single layer or multiple layers made of silicon oxide (SiOx) or silicon nitride (SiNx), but this specification is not limited thereto. Furthermore, the first inorganic insulating layer 111 can be omitted depending on the type of substrate 110 or the type of transistor, but this specification is not limited thereto.

[0090] The first transistor TR1, the second transistor TR2, the third transistor TR3, and the storage capacitor SC are disposed on the first inorganic insulating layer 111 of each of the plurality of sub-pixels SP.

[0091] at the same time, Figure 5A A cross-section of the first transistor TR1, a second transistor TR2, and a third transistor TR3 is shown. The first transistor TR1 includes a first active layer ACT1, a first gate electrode GE1, a first source electrode SE1, and a first drain electrode DE1.

[0092] A first active layer ACT1 is disposed on a first inorganic insulating layer 111. The first active layer ACT1 may be made of a semiconductor material such as oxide semiconductor, amorphous silicon, or polycrystalline silicon, but this disclosure is not limited thereto. For example, if the first active layer ACT1 is made of oxide semiconductor, the first active layer ACT1 may include a channel region, a source region, and a drain region. The source region and drain region may be conductive regions. However, this disclosure is not limited thereto.

[0093] A gate insulating layer 112 is disposed on the first active layer ACT1. The gate insulating layer 112 may be a layer for insulating the first gate electrode GE1 from the first active layer ACT1, and may be made of an insulating material. For example, the gate insulating layer 112 may be configured as a single layer or multiple layers made of silicon oxide (SiOx) or silicon nitride (SiNx), but this disclosure is not limited thereto.

[0094] The first gate electrode GE1 is disposed on the gate insulating layer 112 so as to overlap with the first active layer ACT1. The first gate electrode GE1 may be made of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or alloys thereof. However, this disclosure is not limited thereto.

[0095] The first source electrode SE1 and the first drain electrode DE1 are disposed on the gate insulating layer 112 and spaced apart from each other. The first source electrode SE1 and the first drain electrode DE1 can be electrically connected to the first active layer ACT1 through contact holes formed in the gate insulating layer 112. The first source electrode SE1 and the first drain electrode DE1 can be disposed on the same layer and made of the same conductive material as the first gate electrode GE1. However, this disclosure is not limited thereto. For example, the first source electrode SE1 and the first drain electrode DE1 can be made of copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or alloys thereof. However, this disclosure is not limited thereto.

[0096] The first drain electrode DE1 is electrically connected to the high-potential power line VDD. In this case, an auxiliary high-potential power line VDDa can also be provided to electrically connect the first drain electrode DE1 to the high-potential power line VDD. One end of the auxiliary high-potential power line VDDa is electrically connected to the high-potential power line VDD, while the other end is electrically connected to the first drain electrode DE1 of each of the plurality of sub-pixels SP. For example, if the auxiliary high-potential power line VDDa is disposed on the same layer as the first drain electrode DE1 and is made of the same material as the first drain electrode DE1, one end of the auxiliary high-potential power line VDDa can be electrically connected to the high-potential power line VDD through a contact hole formed in the gate insulating layer 112 and the first inorganic insulating layer 111, while the other end of the auxiliary high-potential power line VDDa can extend to the first drain electrode DE1 and form an integral part of the first drain electrode DE1.

[0097] The first source electrode SE1 can be electrically connected to the light-blocking layer LS through contact holes formed in the gate insulating layer 112 and the first inorganic insulating layer 111. Additionally, a portion of the first active layer ACT1 connected to the first source electrode SE1 can be electrically connected to the light-blocking layer LS through contact holes formed in the first inorganic insulating layer 111. If the light-blocking layer LS is floating, the threshold voltage of the first transistor TR1 changes, which may affect the operation of the display device 100. Therefore, the light-blocking layer LS can be electrically connected to the first source electrode SE1, allowing voltage to be applied to the light-blocking layer LS without affecting the operation of the first transistor TR1. In this specification, a configuration in which both the first active layer ACT1 and the first source electrode SE1 are in contact with the light-blocking layer LS has been described. However, only either the first source electrode SE1 or the first active layer ACT1 can be in direct contact with the light-blocking layer LS. This disclosure is not limited thereto.

[0098] at the same time, Figure 5A The diagram shows a gate insulating layer 112 formed on the entire surface of the substrate 110. However, the gate insulating layer 112 may be patterned to overlap only with the first gate electrode GE1, the first source electrode SE1, and the first drain electrode DE1. However, this disclosure is not limited thereto.

[0099] A storage capacitor SC is disposed in the circuit area of ​​multiple sub-pixels SP. The storage capacitor SC can store the voltage between the first gate electrode GE1 and the first source electrode SE1 of the first transistor TR1, so that the light-emitting element OLED can continuously maintain the same state during a single frame. The storage capacitor SC may include a first capacitor electrode SC1 and a second capacitor electrode SC2.

[0100] A first capacitor electrode SC1 is disposed between the insulating layer IN and the first inorganic insulating layer 111 in each of the multiple sub-pixels SP. Among the conductive components disposed on the substrate 110, the first capacitor electrode SC1 can be positioned closest to the substrate 110. The first capacitor electrode SC1 can be integrally formed with the light-blocking layer LS. The first capacitor electrode SC1 can be electrically connected to the first source electrode SE1 through the light-blocking layer LS.

[0101] A second inorganic insulating layer 113 is provided on the first transistor TR1, the second transistor TR2, the third transistor TR3, and the storage capacitor SC. The second inorganic insulating layer 113 is an insulating layer used to protect components disposed beneath it. Therefore, the second inorganic insulating layer 113 can be referred to as a passivation layer. For example, the second inorganic insulating layer 113 can be configured as a single layer or multiple layers made of silicon oxide (SiOx) or silicon nitride (SiNx), but this specification is not limited thereto. Furthermore, according to this embodiment, the second inorganic insulating layer 113 can be omitted.

[0102] The multiple color filters (CFs) include a red filter, a blue filter, and a green filter. The red filter can be placed in the light-emitting area of ​​the red sub-pixel within the multiple sub-pixels (SPs). The blue filter can be placed in the light-emitting area of ​​the blue sub-pixel. The green filter can be placed in the light-emitting area of ​​the green sub-pixel.

[0103] An organic insulating layer 114 is disposed on the second inorganic insulating layer 113 and a plurality of color filters CF. The organic insulating layer 114 is an insulating layer used to planarize the upper portion of a substrate 110 on which a first transistor TR1, a second transistor TR2, a third transistor TR3, a storage capacitor SC, a plurality of high-potential power lines VDD, a plurality of data lines DL, a plurality of reference lines RL, a plurality of gate lines GL, and a plurality of sensing lines SL are disposed. The organic insulating layer 114 can be configured as a single layer or multiple layers made of organic materials such as polyimide or photoacrylic acid. However, this disclosure is not limited thereto. The organic insulating layer 114 is more flexible than the first inorganic insulating layer 111 and the inorganic insulating layer 113. Specifically, compared to either layer 111 or 113, layer 114 has a greater degree of compressibility and stretchability, and will not break or fracture. Therefore, the elastic modulus of the organic insulating layer 114 is lower than that of the inorganic insulating layers 111 and 113.

[0104] The light-emitting element (OLED) is disposed in the light-emitting region of each sub-pixel in the plurality of sub-pixels SP. The light-emitting element OLED is disposed on the organic insulating layer 114 of each sub-pixel in the plurality of sub-pixels SP. The light-emitting element OLED includes an anode AN, a light-emitting layer EL, and a cathode CA.

[0105] An anode AN is disposed on the organic insulating layer 114 in the light-emitting region. Since the anode AN supplies holes to the light-emitting layer EL, the anode AN can be made of a conductive material with a high work function and can also be referred to as the anode AN. For example, the anode AN can be made of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), but this disclosure is not limited thereto.

[0106] Simultaneously, the anode AN can extend toward the circuit region. A portion of the anode AN can extend from the light-emitting region toward the first source electrode SE1 of the circuit region and be electrically connected to the first source electrode SE1 through contact holes formed in the organic insulating layer 114 and the second inorganic insulating layer 113. Therefore, the anode AN of the light-emitting element OLED can extend to the circuit region and be electrically connected to the first source electrode SE1 of the first transistor TR1 or the second capacitor electrode SC2 of the storage capacitor SC.

[0107] An emitting layer (EL) is disposed on the anode (AN) in the light-emitting region and the circuit region. The EL can be configured as a single layer above multiple sub-pixels (SP). That is, the EL of each sub-pixel in the multiple sub-pixels (SP) can be connected to each other and formed as a single unit. The EL can be configured as a single emitting layer. The EL can have a structure in which multiple emitting layers configured to emit light beams of different colors are stacked. The EL can also include organic layers, such as hole injection layers, hole transport layers, electron transport layers, and electron injection layers.

[0108] The cathode CA is disposed on the light-emitting layer EL in the light-emitting region and the circuit region. Since the cathode CA supplies electrons to the light-emitting layer EL, the cathode CA can be made of a conductive material with a low work function. The cathode CA can be configured as a single layer above multiple sub-pixels SP. That is, the cathode CA of each sub-pixel in the multiple sub-pixels SP can be connected to each other and formed as a single unit. For example, the cathode CA can be made of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO) or an alloy of ytterbium (Yb). The cathode CA may also include a metal doped layer, but this specification is not limited thereto. Meanwhile, although not explicitly stated... Figure 4 and Figures 5A to 5C As shown, however, the cathode CA of the OLED light-emitting element can be electrically connected to the low-potential power line VSS and receive a low-potential power supply voltage.

[0109] A dam 115 is disposed between the anode AN and the light-emitting layer EL. The dam 115 is configured to overlap with the display area AA and cover the edge of the anode AN. The dam 115 may be disposed at the boundary between adjacent sub-pixels SP and reduce the mixing of colors of the light beams emitted from the light-emitting elements OLED of each of the multiple sub-pixels SP. The dam 115 may be made of an insulating material. For example, the dam 115 may be made of a polyimide-based resin, an acrylic-based resin, or a benzocyclobutene (BCB)-based resin. However, this disclosure is not limited thereto.

[0110] Refer to together Figure 4 , Figure 5B and Figure 5C The display device 100 according to the embodiments of the present disclosure includes a substrate 110, an insulating layer IN, a first inorganic insulating layer 111, a gate insulating layer 112, a second inorganic insulating layer 113, an organic insulating layer 114, a light blocking layer LS, a pad electrode P, a polarizing plate 150, and a flexible film 160.

[0111] Multiple pad electrodes P are disposed in pad regions PA on substrate 110. The pad electrodes P can be connected to printed circuit board 170 via flexible film 160. Simultaneously, the pad electrodes P can be connected to multiple sub-pixels SP via gate interconnect lines GLL.

[0112] A conductive layer ML1 disposed on the insulating layer IN is connected to the pad electrode P. Multiple gate link lines GLL can be electrically connected to the pad electrode P via the conductive layer ML1 disposed in the pad region PA. In this case, the conductive layer ML1 can be disposed below the pad electrode P and the gate link lines GLL, and on the same layer as the photoblocking layer LS, and made of the same material as the photoblocking layer LS. For example, the conductive layer ML1 can be made of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or alloys thereof. However, this disclosure is not limited thereto.

[0113] Multiple flexible films 160 are disposed on and electrically connected to multiple pad electrodes P. In this case, the multiple flexible films 160 are attached to the multiple pad electrodes P by means of an anisotropic conductive film ACF. The flexible films 160 are pressed such that the pad electrodes P in the pad region PA of the substrate 110 are electrically connected to the flexible films 160 by means of conductive balls in the anisotropic conductive film ACF.

[0114] The flexible film 160 includes a pad portion 161, a driver IC 162, a base film 163, and a coating layer 164.

[0115] The base film 163 is a layer used to support the flexible film 160. The base film 163 can be made of an insulating material, such as a flexible insulating material.

[0116] The coating layer 164 can be used to guide the anisotropic conductive film ACF to the flexible film 160. For example, the coating layer 164 can be made of resin, but this disclosure is not limited thereto.

[0117] The pad portion 161 supplies electrical voltage, data voltage, etc., to multiple sub-pixels SP in the display area AA via pad electrodes P disposed in the pad area PA. The pad portion 161 may be made of a conductive material such as copper (Cu). However, this disclosure is not limited thereto.

[0118] Driver IC 162 is a component configured to process data for displaying images and to process drive signals for processing that data. Driver IC 162 may be a gate driver IC, a data driver IC, etc. However, this disclosure is not limited thereto. Driver IC 162 can be configured in ways such as chip-on-glass (COG), chip-on-film (COF), and tape carrier packaging (TCP), depending on how the driver IC is mounted. In this specification, for ease of description, a configuration in which driver IC 162 is mounted on multiple flexible films 160 via a chip-on-film method has been described. However, this disclosure is not limited thereto.

[0119] Multiple link lines LL are set in the link area LA and the pad area PA, and connect the data line DL, gate line GL and gate inner panel in the display area AA to the pad electrode P in the pad area PA. Figure 5B The plurality of link lines LL shown in the embodiment of the present disclosure of the display device 100 are gate link lines GLL. However, the present disclosure is not limited thereto.

[0120] A gate link line GLL is disposed on the first inorganic insulating layer 111 and the gate insulating layer 112. The gate link line GLL can extend from the gate line GL. That is, the gate link line GLL can be integrally formed with the gate line GL. The gate link line GLL and the gate line GL can be made of the same conductive material. For example, the gate line GL can be made of copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or alloys thereof. However, this disclosure is not limited thereto.

[0121] The second inorganic insulating layer 113 is disposed on the gate link line GLL. In addition, the organic insulating layer 114 is disposed on the first inorganic insulating layer 111, the plurality of gate link lines GLL and the second inorganic insulating layer 113.

[0122] A hole H1 is provided in the insulating layer IN, the first inorganic insulating layer 111, the gate insulating layer 112, and the second inorganic insulating layer 113 to overlap with a portion of the outer periphery line of the flexible film 160 disposed on the substrate 110. The hole H1 can be formed by dry etching the insulating layer IN, the first inorganic insulating layer 111, the gate insulating layer 112, and the second inorganic insulating layer 113 disposed in the outer periphery line region of the flexible film 160. In other words, the hole H1 can be formed by etching the first inorganic insulating layer 111, the gate insulating layer 112, the second inorganic insulating layer 113, and the insulating layer IN using an etching gas, thereby exposing the substrate 110 through the hole H1. In one embodiment, the substrate 110 can be used as an etching baffle. In this case, refer to... Figure 5B During the etching process of the insulating layer IN, the first inorganic insulating layer 111, the gate insulating layer 112, and the second inorganic insulating layer 113, the gate link line GLL disposed in the via H1 may not be etched. That is, regardless of whether it is gas etching, wet etching, dry etching, laser removal, or other types of etching used to etch the insulating layer IN, the first inorganic insulating layer 111, the gate insulating layer 112, and the second inorganic insulating layer 113, the etching process selectively does not etch the gate link line GLL made of metallic material. Therefore, the gate link line GLL can remain in the via H1 without change. Thus, the gate link line GLL can be suspended in the air within the via after etching but before the organic insulating layer 114 is disposed. Thereafter, refer to... Figure 5B and Figure 5C When the organic insulating layer 114 is provided, the hole H1 is filled with the organic insulating layer 114. Therefore, the organic insulating layer 114 can be configured to surround the gate link line GLL in the region where the gate link line GLL is provided. At these locations, the layer 114 fills those portions of the hole H1 that are not filled by the link line LL (the gate link line GLL in this example) or other material that may be present in the hole. Thus, the layer 114 completes the filling of the hole. This structure is within the meaning of the phrase "layer 114 fills" or "fills the hole." Alternatively, the hole H1 can be completely filled by the organic insulating layer 114 in regions where there is no link line LL, for example, where the gate link line GLL is not provided.

[0123] As used herein, the term "filling" refers to a hole in a broad sense, encompassing both complete filling with only the material and filling any remaining portion of the hole that has not been filled by other materials. Therefore, other materials can be present in the hole, and the material that completes the filling of the hole can be understood as having filled the hole.

[0124] Reference Figure 4The aperture H1 is configured to overlap with the outer perimeter of the flexible film 160 adjacent to the link region LA. Additionally, the aperture H1 is configured to overlap with the edge of the outer perimeter of the flexible film 160. In this case, the width W1 of the aperture H1 adjacent to the link region LA can be smaller than the width W2 of the aperture H1 formed in the edge region of the flexible film 160. Near the edge of the flexible film 160 where the gate link line GLL is not located, the aperture H1 can have a larger size to increase the amount of the organic insulating layer 114, which can absorb more stress such as impact, torsion, compression, bending, etc., to prevent potential cracks and damage. Since the organic insulating layer 114 is more flexible than the inorganic layers 111 and 113, it can act as a buffer to absorb mechanical stress in the structure and reduce or avoid damage to other layers. However, if the size of the aperture H1 is too large at the location where one of the gate link lines LL or GLL is positioned within the aperture H1, there is a chance that the gate link line GLL may undergo significant shift, sag, or collapse during etching or after etching but before the organic insulating layer 114 is applied. The width W1 of any link line LL location is chosen to ensure that the integrity and functionality of the electrical connection via the link line LL are not compromised. Therefore, the width W1 of the aperture H1 overlapping with the link line LL can be smaller than the width W2 of the aperture H1 formed at locations where the link line LL does not overlap with the aperture. In one embodiment, the width of the aperture H1 located in a region adjacent to the link region LA can be smaller over its entire length than the width W2 of the aperture H1 formed in the edge region of the flexible film 160.

[0125] In the display device 100 according to an embodiment of the present disclosure, the substrate 110 may be made of a transparent conductive oxide and may undergo laser lift-off (LLO) processing. During the manufacturing process of the display device 100, after a temporary substrate having a sacrificial layer is attached to the lower portion of the substrate 110, pixel units 120 may be formed on the substrate 110. The sacrificial layer may be made of, for example, hydrogenated amorphous silicon or hydrogenated and impurity-doped amorphous silicon. Furthermore, after the display device 100 is fully manufactured, when a laser beam is emitted to the lower portion of the temporary substrate, the sacrificial layer may be dehydrogenated, and the sacrificial layer and the temporary substrate may be separated from the substrate 110. In this case, the transparent conductive oxide is a material that can undergo LLO processing together with the sacrificial layer and the temporary substrate. Therefore, even if the substrate 110 is made of a transparent conductive oxide, the substrate 110 and the temporary substrate can be easily separated. Therefore, in the display device 100 according to an embodiment of the present disclosure, the substrate 110 is configured as a transparent conductive oxide layer that can undergo LLO processing. Therefore, the display device 100 can be easily manufactured even by using processing and equipment in related technologies.

[0126] Depending on the magnitude or degree of pressure applied to the anisotropic conductive film electrically connecting the flexible film to the pad electrodes, the anisotropic conductive film can overflow between the flexible film and the organic insulating layer. An air gap can form between the flexible film and the organic insulating layer. Even when a seal is used to cover the area where the flexible film and the organic insulating layer overlap, the air gap can remain unfilled. In this case, when the substrate is made of plastic material, as with related technologies, sufficient substrate thickness can be ensured to suppress the occurrence of cracks caused by the air gap. However, when the substrate is configured as a transparent conductive oxide layer or an oxide semiconductor layer, the substrate has a very small thickness and therefore cannot absorb the impact caused by the air gap. For this reason, cracks may form in the inorganic insulating layer or the interconnects, and these cracks propagate through the inorganic insulating layer or the interconnects, which can lead to operational defects, such as dark lines formed for each block.

[0127] In the display device 100 according to an embodiment of the present disclosure, a hole H1 can be disposed in a region overlapping with the outer periphery line of the flexible film 160 disposed on the substrate 110, thereby reducing the chance of operational defects and disconnection between the inorganic insulating layer and the link line LL. Specifically, an air gap can be formed adjacent to the outer periphery line of the flexible film 160 and exist for a short period of time, and can be formed between the flexible film 160 and the organic insulating layer 114. Therefore, the hole H1 can be disposed in the region overlapping with the outer periphery line of the flexible film 160 in the insulating layer IN, the first inorganic insulating layer 111, the gate insulating layer 112, and the second inorganic insulating layer 113. Furthermore, the hole H1 can be filled with the organic insulating layer 114. Therefore, the occurrence of cracks in the inorganic insulating layer or the link line LL can be suppressed because the stress is absorbed by the layer 114.

[0128] Specifically, in the display device 100 according to the embodiments of the present disclosure, the edge region of the flexible film 160 is a region where stress is concentrated compared to other regions, and there is a possibility that cracks will form in the edge region of the flexible film 160. Therefore, a hole H1 with a sufficient width can be configured to overlap with the edge region of the flexible film 160, and the hole H1 can be filled with an organic insulating layer 114. Therefore, the occurrence of cracks that may form in the inorganic insulating layer and the link lines LL can be suppressed. In addition, the propagation of cracks into the display device can be suppressed. Furthermore, operational defects, such as dark lines formed for each block due to cracks formed in the link lines LL, can be suppressed. Therefore, in the display device 100 according to the embodiments of the present disclosure, the substrate 110 is made of a transparent conductive oxide. Therefore, the thickness of the display device 100 can be reduced, and the propagation of cracks caused by air gaps in the pad regions PA can still be suppressed, thereby improving the reliability of the display device 100.

[0129] Figure 6This is a cross-sectional view of a display device according to another embodiment of the present disclosure. Except for the gate insulating layer 612 and the hole H6, Figure 6 The display device 600 shown is configured similarly to Figures 1 to 5C The display device 100 shown is very similar. Therefore, repeated descriptions of similar or identical components will be omitted.

[0130] Reference Figure 6 A hole H6 is provided in the insulating layer IN, the first inorganic insulating layer 111, the gate insulating layer 612, and the second inorganic insulating layer 113. The hole H6 can be formed by dry etching of the insulating layer IN, the first inorganic insulating layer 111, the gate insulating layer 612, and the second inorganic insulating layer 113 disposed in the outer peripheral region of the flexible film 160. In this case, refer to... Figure 6 During the etching process of insulating layer IN, first inorganic insulating layer 111, gate insulating layer 612, and second inorganic insulating layer 113, the gate link line GLL disposed in the hole H6 may not be etched. That is, regardless of whether it is gas etching, wet etching, or other etching used to etch insulating layer IN, first inorganic insulating layer 111, gate insulating layer 612, and second inorganic insulating layer 113, the etching process selectively does not etch the gate link line GLL made of metallic material. Therefore, the gate link line GLL can remain in the hole H6 without alteration. In other words, the gate link line GLL can be suspended in the air within the hole H6 after etching but before the organic insulating layer 114 is disposed in the hole.

[0131] In one implementation, such as Figure 6As shown, the gate insulating layer 612 adjacent to the bottom surface of the gate link line GLL can remain in the via H6. In other words, the GLL may act as an etch shield for the layers directly beneath it. When etching occurs, some or all of the layers 612 directly beneath the link line LL may not be etched and remain to assist in supporting the GLL. Alternatively, an etching process can be used that selectively does not etch the link line LL or GLL and does not etch the gate insulating layer 612, but etches all other materials above the substrate layer 110. Thus, the top and side surfaces of the gate link line GLL disposed in the via H6 can be adjacent to the organic insulating layer 114 when the organic insulating layer 114 is deposited, while the bottom surface of the gate link line GLL overlapping the via H6 can be non-adjacent to the organic insulating layer 114. The via H6 can be formed during a dry etching process when the etching gas sequentially etches the second inorganic insulating layer 113, the gate insulating layer 612, and the first inorganic insulating layer 111. However, when the etching gas becomes plasma, the ion energy and linearity are high, and the gate insulating layer 612 covered by the gate link line GLL may not be fully etched. Therefore, at the bottom of the gate link line GLL overlapping with the hole H6, some or all of the gate insulating layer 612 may remain unetched. That is, the thickness of the gate insulating layer 612 disposed in the hole H6 can be less than the thickness of the gate insulating layer H6 disposed outside the hole H6.

[0132] In another embodiment of the display device 600 according to the present disclosure, a hole H6 can be disposed in a region overlapping with the outer periphery of the flexible film 160 disposed on the substrate 110, thereby minimizing operational defects and disconnections between the inorganic insulating layer and the link line LL. Specifically, an air gap can be formed adjacent to the outer periphery of the flexible film 160 and can be formed between the flexible film 160 and the organic insulating layer 114. Therefore, the hole H6 can be disposed in the region overlapping with the outer periphery of the flexible film 160 in the insulating layer IN, the first inorganic insulating layer 111, the gate insulating layer 612, and the second inorganic insulating layer 113. Furthermore, the hole H6 can be filled with the organic insulating layer 114. Therefore, the occurrence of cracks in the inorganic insulating layer or the link line LL can be suppressed. In addition, in another embodiment of the display device 600 according to the present disclosure, the substrate 110 is made of a transparent conductive oxide. Therefore, the thickness of the display device 600 can be reduced and the propagation of cracks caused by air gaps in the pad region PA can be suppressed, thereby improving the reliability of the display device 600.

[0133] Figure 7 This is an enlarged top plan view of a display device according to another embodiment of the present disclosure. Except for hole H7, Figure 7 The display device 700 shown is configured similarly to Figures 1 to 5CThe display device 100 shown is substantially the same. Therefore, repeated descriptions of the same components will be omitted.

[0134] Reference Figure 7 A hole H7 is disposed adjacent to the outer periphery line of the flexible film 160 adjacent to the link region LA. In other words, the hole H7 does not overlap with the outer periphery line of the flexible film 160 adjacent to the link region LA. However, the hole H7 can be disposed in the pad region PA or the link region LA. In this case, the width of the hole H7 adjacent to the link region LA can be smaller than the width of the hole H7 formed in the edge region of the flexible film 160. Near the edge of the flexible film 160 where no gate link line GLL is disposed, the hole H7 can have a larger size to increase the amount of organic insulating layer 114 that can absorb stress, potential cracks, impacts, or other crack sources. However, if the size of the hole H7 is too large when multiple gate link lines GLL are disposed in the hole H7, there is a certain chance that the gate link line GLL will collapse before the organic insulating layer 114 is disposed. Therefore, the width of the hole H7 adjacent to the link region LA or where there is a link line can be smaller than the width of the hole H7 formed in the edge region of the flexible film 160. Figure 7 The diagram shows that hole H7 is only located in pad area PA, but this disclosure is not limited thereto.

[0135] In another embodiment of the display device 700 according to the present disclosure, a hole H7 is provided in a region adjacent to the outer periphery of the flexible film 160 provided on the substrate 110 and in the edge region of the flexible film 160. Therefore, operational defects and breaks between the inorganic insulating layer and the link line LL can be reduced. Specifically, an air gap can be formed adjacent to the outer periphery of the flexible film 160 and can be formed between the flexible film 160 and the organic insulating layer 114. Therefore, the hole H7 can be provided in the insulating layer IN, the first inorganic insulating layer 111, the gate insulating layer 112, and the second inorganic insulating layer 113 in the pad region PA or the link region LA, which are regions adjacent to the outer periphery of the flexible film 160. Furthermore, the hole H7 can be filled with the organic insulating layer 114. Therefore, the occurrence of cracks in the inorganic insulating layer or the link line LL can be suppressed. Additionally, in another embodiment of the display device 700 according to the present disclosure, the substrate 110 is made of a transparent conductive oxide. Therefore, the thickness of the display device 700 can be reduced and the propagation of cracks caused by air gaps in the pad area PA can be suppressed, thereby improving the reliability of the display device 700.

[0136] Figure 8 This is an enlarged top view of a display device according to yet another embodiment of the present disclosure. Figure 9 It is along Figure 8 A schematic cross-sectional view taken along centerline VIIII-VIIII'. Except for hole H8, Figure 8 and Figure 9 The display device 800 shown is configured similarly to Figures 1 to 5C The display device 100 shown is basically similar. Therefore, repeated descriptions of similar components will be omitted.

[0137] Refer to together Figure 8 and Figure 9 A hole H8 may be provided adjacent to the outer periphery line of the flexible film 160 that is adjacent to the link region LA. Furthermore, a hole H8 may be provided adjacent to the outer periphery line of the substrate 110 provided in the pad region PA.

[0138] Hole H8 can be formed by dry etching of insulating layer IN, first inorganic insulating layer 111, gate insulating layer 112 and second inorganic insulating layer 113 in the area adjacent to the outer periphery line of flexible film 160 and the area adjacent to the outer periphery line of substrate 110 in pad area PA.

[0139] Reference Figure 9 A hole H8, which is disposed adjacent to the outer periphery of the substrate 110, is located in the region between the outer periphery of the substrate 110 and the hole in which an anisotropic conductive film ACF is disposed. Figure 8 and Figure 9 A hole H8 adjacent to the link region LA is shown disposed in the pad region PA. However, this disclosure is not limited thereto. Additionally, the hole H8 is configured to overlap with the edge of the outer periphery of the flexible film 160. In this case, the width of the hole H8 adjacent to the link region LA can be smaller than the width of the hole H8 formed in the edge region of the flexible film 160. Near the edge of the flexible film 160 where no gate link lines GLL are disposed, the hole H8 can have a larger size to increase the amount of organic insulating layer 114 that can absorb shocks. However, if the size of the hole H8 is too large when multiple gate link lines GLL are disposed in the hole H8, there is a certain chance that the gate link lines GLL will collapse before the organic insulating layer 114 is disposed. Therefore, the width of the hole H8 adjacent to the link region LA can be smaller than the width of the hole H8 formed in the edge region of the flexible film 160.

[0140] In a display device 800 according to another embodiment of the present disclosure, a hole H8 is provided in a region adjacent to the outer periphery of a flexible film 160 provided on a substrate 110, a region adjacent to the outer periphery of a substrate 110 provided in a pad region PA, and an edge region of the flexible film 160. Therefore, operational defects and breaks between the inorganic insulating layer and the link line LL can be reduced. Specifically, an air gap can be formed adjacent to the outer periphery of the flexible film 160 and can be formed between the flexible film 160 and the organic insulating layer 114. Therefore, the hole H8 can be provided in the insulating layer IN, the first inorganic insulating layer 111, the gate insulating layer 112, and the second inorganic insulating layer 113 in the pad region PA or the link region LA, which are regions adjacent to the outer periphery of the flexible film 160. Furthermore, the hole H8 can be filled with the organic insulating layer 114. Therefore, the occurrence of cracks in the inorganic insulating layer or the link line LL can be suppressed. Additionally, cracks can occur and propagate even in regions adjacent to the outer periphery of a substrate 110 provided in the pad region PA. Therefore, the hole H8 can be provided in the inorganic insulating layer of the pad region PA, which is a region adjacent to the outer periphery of the substrate 110. Furthermore, the hole H8 can be filled with an organic insulating layer 114. Therefore, the occurrence of cracks in the inorganic insulating layer between the outer periphery of the substrate 110 provided in the pad region PA and the hole in which the anisotropic conductive film ACF is provided can be suppressed. Furthermore, the propagation of any formed cracks can be suppressed. In addition, according to another embodiment of the display device 800 of this disclosure, the substrate 110 is made of a transparent conductive oxide. Therefore, the thickness of the display device 800 can be reduced and the propagation of cracks caused by air gaps in the pad region PA can be suppressed, thereby improving the reliability of the display device 800.

[0141] Figure 10 This is a cross-sectional view of a display device according to another embodiment of the present disclosure. Except for the gate interconnect GLL, conductive layer ML2, first inorganic insulating layer 1011, gate insulating layer 1012, second inorganic insulating layer 1013, organic insulating layer 1014, dam layer 1015, and via H10, the display device according to another embodiment of the present disclosure is configured similarly to... Figures 1 to 5C The display device 100 shown is substantially the same. Therefore, repeated descriptions of the same components will be omitted.

[0142] A conductive layer ML2 is disposed on the first inorganic insulating layer 1011. The conductive layer ML2 can electrically connect the gate link line GLL to the pad electrode P. In this case, the conductive layer ML2 can be formed on the same layer as the first source electrode SE1 or the first drain electrode DE1 and made of the same material as the first source electrode SE1 or the first drain electrode DE1. For example, the conductive layer ML2 can be made of copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or alloys thereof. However, this disclosure is not limited thereto.

[0143] Multiple link lines LL are set in the link area LA and the pad area PA, and the data line DL, gate line GL and gate inner panel in the display area AA are connected to the pad electrode P in the pad area PA. Figure 10 The plurality of link lines LL shown in another embodiment of the display device 1000 according to the present disclosure are gate link lines GLL. However, the present disclosure is not limited thereto.

[0144] The gate link line GLL is disposed on the organic insulating layer 1014. Additionally, a dam portion 1015 is disposed on the gate link line GLL. Meanwhile, the first inorganic insulating layer 1011, the gate insulating layer 1012, the second inorganic insulating layer 1013, and the organic insulating layer 1014 may be disposed below the gate link line GLL.

[0145] The gate link line (GLL) can be made of the same material as the anode (AN). That is, the gate link line (GLL) can be formed using the same process as the anode (AN). However, this disclosure is not limited thereto. For example, the gate link line (GLL) can be made of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO). However, this specification is not limited thereto.

[0146] The dam 1015 is disposed on the gate link line GLL and insulates the anisotropic conductive film ACF from the gate link line GLL. (Refer to...) Figure 5A In the display area AA, the embankment 115 covers the edge of the anode AN and defines the area of ​​the adjacent sub-pixel SP. Meanwhile, referring to... Figure 10 In the non-display area NA, the embankment 115 extending from the display area AA can even be provided in the link area LA and the pad area PA so as to insulate the gate link line GLL, which is provided on the same layer as the anode AN and made of the same material as the anode AN, from the anisotropic conductive film ACF.

[0147] Hole H10 is disposed below the gate interconnect line GLL so as to overlap with a portion of the outer peripheral line of the flexible film 160 disposed on the substrate 110. Hole H10 may be disposed in the insulating layer IN, the first inorganic insulating layer 1011, the gate insulating layer 1012, and the second inorganic insulating layer 1013. Hole H10 can be formed by dry etching the insulating layer IN, the first inorganic insulating layer 1011, the gate insulating layer 1012, and the second inorganic insulating layer 1013 disposed in the outer peripheral line region of the flexible film 160. Thereafter, hole H10 can be filled with organic insulating layer 1014. In this case, since no line is disposed in hole H10, hole H10 can be completely filled with organic insulating layer 1014.

[0148] The hole H10 can be configured to overlap with the outer periphery line of the flexible film 160 adjacent to the linking region LA. Alternatively, the hole H10 can be configured to overlap with the edge of the outer periphery line of the flexible film 160. In this case, since no wiring is provided in the hole H10 adjacent to the linking region LA, no wiring collapse problem occurs. Therefore, in the display device 1000 according to another embodiment of this disclosure, the width of the hole H10 can be freely selected without any limitations on the wiring.

[0149] Figure 10 The diagram shows that the aperture H10 is configured to overlap with the outer perimeter of the flexible membrane 160 adjacent to the link region LA. However, this disclosure is not limited thereto. For example, the aperture H10 may not overlap with the outer perimeter of the flexible membrane 160 adjacent to the link region LA. However, the aperture H10 may be located in the pad region PA or the link region LA.

[0150] In a display device 1000 according to another embodiment of the present disclosure, a hole H10 is provided in a region adjacent to the outer periphery of a flexible film 160 disposed on a substrate 110 and in an edge region of the flexible film 160. Therefore, operational defects and breaks between the inorganic insulating layer and the link line LL can be reduced. Specifically, an air gap can be formed adjacent to the outer periphery of the flexible film 160 and can be formed between the flexible film 160 and the organic insulating layer 1014. Therefore, the hole H10 can be provided in the insulating layer IN, the first inorganic insulating layer 1011, the gate insulating layer 1012, and the second inorganic insulating layer 1013 in the pad region PA or the link region LA, which are regions adjacent to the outer periphery of the flexible film 160. Furthermore, the hole H10 can be filled with the organic insulating layer 1014. Therefore, the occurrence of cracks in the inorganic insulating layer or the link line LL can be suppressed. Furthermore, since the gate link line GLL is disposed on the organic insulating layer 1014 in the display device 1000 according to another embodiment of the present disclosure, the gate link line GLL may not be disposed in the hole H10. Therefore, the hole H10 can be disposed in the region adjacent to the outer peripheral line of the flexible film 160, and its size is not limited. Therefore, the hole H10 having the desired size can be disposed in the inorganic insulating layer in the region adjacent to the outer peripheral line of the flexible film 160 disposed on the substrate 110 and in the edge region of the flexible film 160. Therefore, the occurrence of cracks in the inorganic insulating layer can be suppressed more effectively. Meanwhile, in the display device 1000 according to another embodiment of the present disclosure, the substrate 110 is made of transparent conductive oxide. Therefore, the thickness of the display device 1000 can be reduced and the propagation of cracks caused by air gaps in the pad region PA can be suppressed, thereby improving the reliability of the display device 1000.

[0151] In an alternative embodiment, the link layer LL can be positioned as the first layer on top of the insulating layer IN. The link layer LL can act as an etch baffle for etching the hole H1, and therefore the link layer LL is the bottommost layer in the hole H1. In this embodiment, when the organic layer 114 is deposited, the organic layer 114 is on top of the link layer LL and fills the remainder of the hole. In another alternative embodiment, the link layer LL can be positioned at the top above the hole, i.e., when layer 113 is absent and the link layer LL is on top of layer 112, and the link layer LL is the topmost layer when the hole is etched. After the hole is etched, the link layer LL will act as a bridge across the top of the hole. In this embodiment, when the organic layer 114 is deposited, the organic layer 114 is on top of the link layer LL and fills the hole below the link layer LL, and also covers the link layer LL.

[0152] Exemplary embodiments of this disclosure may also be described below.

[0153] According to one aspect of this disclosure, a display device includes: a substrate configured as one of a conductive oxide layer and an oxide semiconductor layer, and including a display area and a non-display area disposed at the periphery of the display area, the display area including a plurality of sub-pixels, the non-display area including a pad area and a link area disposed between the display area and the pad area; a first inorganic insulating layer disposed on the substrate; a plurality of pad electrodes disposed in the pad area; a plurality of link lines disposed in the link area, the plurality of link lines being configured to connect the plurality of pad electrodes to the plurality of sub-pixels; a flexible film disposed on and electrically connected to the plurality of pad electrodes; and an organic insulating layer disposed on the first inorganic insulating layer and the plurality of link lines, wherein a hole is formed in the first inorganic insulating layer to overlap with a portion of the periphery line of the flexible film disposed on the substrate, and the hole is filled with the organic insulating layer.

[0154] The hole can overlap with the edge of the outer perimeter of the flexible membrane.

[0155] The hole can overlap with the outer perimeter of the flexible membrane that is adjacent to the linking region.

[0156] The hole can be positioned between the display area and the outer perimeter of the flexible film adjacent to the linking area.

[0157] The hole can also be configured to be adjacent to the outer perimeter of the substrate located in the pad area.

[0158] The multiple link lines are gate link lines or data link lines, and the multiple link lines can be electrically connected to the pad electrodes through a conductive layer disposed in the pad area.

[0159] The display device also includes a second inorganic insulating layer disposed on a plurality of link lines, the plurality of link lines being gate link lines disposed in holes, and the holes may be disposed in the second inorganic insulating layer.

[0160] The conductive layer is configured to electrically connect the gate link line to the pad electrode, and the conductive layer may be disposed below the first inorganic insulating layer.

[0161] The entire surface of the gate link line disposed in the hole can be adjacent to the organic insulating layer.

[0162] The gate insulating layer disposed above the first inorganic insulating layer and below the gate link line, the top surface and side surface of the gate link line disposed in the hole are adjacent to the organic insulating layer, and the bottom surface of the gate link line disposed in the hole may be adjacent to the gate insulating layer.

[0163] Multiple connecting lines are disposed on the organic insulating layer, and holes can be disposed below the multiple connecting lines.

[0164] The conductive layer is configured to electrically connect multiple link lines to pad electrodes, and the conductive layer may be disposed above the first inorganic insulating layer.

[0165] Although exemplary embodiments of this disclosure have been described in detail with reference to the accompanying drawings, this disclosure is not limited thereto and can be implemented in many different forms without departing from the technical concept of this disclosure. Therefore, the exemplary embodiments of this disclosure are for illustrative purposes only and are not intended to limit the technical concept of this disclosure. The scope of the technical concept of this disclosure is not limited thereto. Therefore, it should be understood that the exemplary embodiments described above are illustrative in all respects and do not limit this disclosure. The scope of protection of this disclosure should be interpreted based on the appended claims, and all technical concepts within the equivalent scope thereof should be interpreted as falling within the scope of this disclosure.

[0166] The various embodiments described above can be combined to provide other embodiments. All U.S. patents, U.S. patent application publications, U.S. patent applications, foreign patents, foreign patent applications, and non-patent publications mentioned in this specification and / or listed in the application data sheets are incorporated herein by reference in their entirety. Modifications may be made to various aspects of the embodiments as necessary to incorporate the concepts of various patents, applications, and publications to provide other embodiments.

[0167] Based on the detailed description above, these and other modifications can be made to the embodiments. Generally, the terminology used in the appended claims should not be construed as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be interpreted to include all possible embodiments and the full scope of their equivalents. Therefore, the claims are not limited by this disclosure.

Claims

1. A display device, comprising: A substrate having a display area and a non-display area disposed adjacent to the display area, the display area including a plurality of sub-pixels; The pad area in the non-display area; A link area is provided between the display area and the pad area; A first inorganic insulating layer disposed in the link region on the substrate; Multiple pad electrodes are disposed in the pad area; A plurality of link lines are disposed in the link area and cover the first inorganic insulating layer, the plurality of link lines being configured to electrically connect the plurality of pad electrodes to the plurality of sub-pixels respectively; An organic insulating layer disposed on the plurality of link lines and on the first inorganic insulating layer; A hole is provided in the first inorganic insulating layer, the hole being positioned to partially overlap with at least one of the plurality of link lines provided on the substrate; as well as A flexible film disposed on and electrically connected to the plurality of pad electrodes, The organic insulating layer is positioned in the pore and fills the pore. The hole overlaps with the edge of the outer perimeter of the flexible membrane.

2. The display device according to claim 1, wherein, The connecting line is positioned in the hole and assists in filling the hole.

3. The display device according to claim 2, wherein, The hole overlaps with the outer perimeter of the flexible membrane adjacent to the linking region.

4. The display device according to claim 2, wherein, The hole is disposed between the outer perimeter of the display area and the outer perimeter of the flexible film, and between the outer perimeter of the linking area.

5. The display device according to claim 1, wherein, A second hole is provided adjacent to the outer periphery of the substrate located in the pad area.

6. The display device according to claim 1, wherein, The plurality of link lines includes at least one gate link line or at least one data link line; and Each of the plurality of link lines is electrically connected to the pad electrode via a conductive layer disposed in the pad region.

7. The display device according to claim 5, further comprising: A second inorganic insulating layer is disposed on the plurality of connecting lines. The plurality of link lines include gate link lines disposed in the second hole, and The second hole is disposed in the second inorganic insulating layer.

8. The display device according to claim 6, comprising: A conductive layer configured to electrically connect the gate link to the pad electrode, wherein the conductive layer is disposed beneath the first inorganic insulating layer.

9. The display device according to claim 6, comprising: A gate insulating layer disposed above the first inorganic insulating layer and below the gate connection line. The top and side surfaces of the gate link line disposed in the hole are adjacent to the organic insulating layer, and The bottom surface of the gate link line disposed in the hole is adjacent to the gate insulating layer.

10. The display device according to claim 1, wherein, The plurality of connecting lines are disposed on the organic insulating layer, and the hole is disposed below the plurality of connecting lines.

11. The display device according to claim 1, comprising: A conductive layer configured to electrically connect the plurality of interconnect lines to the pad electrodes. The conductive layer is disposed above the first inorganic insulating layer.

12. A display device, comprising: A substrate having a display area and a non-display area disposed adjacent to the display area; Multiple sub-pixels in the display area; The first insulating layer on the substrate; The pad area in the non-display area; Multiple pad electrodes are disposed in the pad area; The link area located between the display area and the pad area; Multiple insulating layers positioned on the first insulating layer in the link region; Multiple conductive lines disposed in the link region and positioned on the multiple insulating layers are configured to electrically connect the multiple pad electrodes to the multiple sub-pixels, respectively. A second insulating layer covering the plurality of conductive lines in the link area; Holes disposed in the plurality of insulating layers and the second insulating layer, the holes being positioned to overlap with at least one of the conductive wires; and An organic insulating layer that fills the hole and surrounds the at least one conductive wire.

13. The display device according to claim 12, wherein, The organic insulating layer filling the hole is in direct physical contact with the top and two sides of the at least one conductive wire.

14. The display device according to claim 13, wherein, The organic insulating layer filling the hole is in direct physical contact with the bottom of the at least one conductive wire.

15. The display device according to claim 12, further comprising: A flexible film disposed on and electrically connected to the plurality of pad electrodes, the flexible film being positioned to overlap with the holes in the plurality of insulating layers and the second insulating layer and the organic insulating layer filling the holes.

16. A method of manufacturing a display device, comprising: A display area is formed on a substrate, the display area including a pixel layer having a plurality of light-emitting pixels; A non-display area adjacent to the display area is formed on the substrate, the non-display area including a link area and a pad area; A first insulating layer is deposited on the substrate, the first insulating layer being disposed in the display area and the non-display area; A plurality of insulating layers are deposited on the first insulating layer, the plurality of insulating layers being disposed in the link region; Conductive pads are formed in the pad area; Conductive interconnects are deposited on the plurality of insulating layers, the conductive interconnects extending from the pad area, through the interconnect area and into the display area; A second insulating layer is deposited in the pad area and the link area to cover the conductive link lines; A hole is formed extending through the second insulating layer and the plurality of insulating layers in the link region, and the conductive link wire is not removed and is exposed in the hole after the hole is formed; as well as The hole is filled with an organic insulating layer that surrounds at least three sides of the conductive link within the hole.

17. The method according to claim 16, wherein, The step of forming a hole in the link region includes: The second insulating layer and the plurality of insulating layers are removed by an etching process, wherein the etching process does not remove the conductive link wire or the first insulating layer.

18. The method according to claim 17, wherein, The conductive link is suspended in the hole after the hole is formed and before the organic insulating layer fills the hole.

19. The method of claim 16, wherein, When the conductive link is surrounded by the organic insulating layer, the organic insulating layer is in direct contact with at least three surfaces of the conductive link, and at least one of the plurality of insulating layers is in contact with the conductive link.

20. The method of claim 16, wherein, The substrate is configured as a transparent conductive oxide layer or an oxide semiconductor layer.

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