An online monitoring and intelligent early warning method for intermittent faults of integrated circuits

Abstract

The present invention discloses an online monitoring and intelligent early warning method for intermittent faults in integrated circuits. The method utilizes the monitoring capacitor formed by the FPGA chip itself to simultaneously monitor the health of any two solder joints to be detected, eliminating the need to solder external monitoring capacitors on the PCB board and improving the cost-effectiveness of monitoring. The proposed monitoring module outputs the current time value and the time of the most recent failure, which can be used for more complete solder joint health status monitoring and life assessment. The fault threshold can be set through the port Fault_N signal, thereby improving the flexibility of solder joint health status monitoring.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuit health monitoring, and in particular relates to an online monitoring and intelligent early warning method for intermittent faults of integrated circuits. Background Art

[0002] Field-programmable gate arrays (FPGAs), with their unique fine-grained parallelism, are widely used in electronic systems. During operation, electronic systems are subject to thermal and mechanical stresses imposed by the external environment, which can cause solder joint failures in electronic components. As a core and critical component of electronic systems, solder joint failures in FPGAs can potentially lead to catastrophic failures of the entire system. Therefore, health monitoring of FPGA solder joints is of great significance.

[0003] Research has shown that when electronic component solder joints degrade under thermal and mechanical stress, their impedance increases. Therefore, monitoring the health of electronic component solder joints can be translated into monitoring their impedance. The results provide data support for component health monitoring and lifespan prediction. The industry generally considers the following criteria for BGA packaged FPGA solder joint failure: ① Peak resistance greater than 300Ω persists for more than 200µs; ② 10 or more failures occur within 10% of the time after the first failure.

[0004] The document "Ball Grid Array (BGA) Solder Joint Intermittency Detection: SJBIST" introduces the SJ-BIST (Solder Joint Built-In Selftest) method proposed by the American company Retopo Group. This method monitors FPGA solder joint faults and only requires a single capacitor to detect two solder joints simultaneously. The SJ-BIST method can detect changes in FPGA solder joint resistance within a few nanoseconds. However, this method cannot obtain the resistance value of the detected solder joint and can only diagnose whether the detected solder joint is faulty. This makes it difficult to use this method's fault data for related research on life prediction. Patent No. 2019102486286, "A High-Precision FPGA Solder Joint Fault Real-Time Diagnosis Method and Diagnostic Device," proposes a method that uses a single capacitor to monitor the health of two FPGA solder joints and obtain the solder joint resistance value. Regardless of whether or not existing online solder joint monitoring methods can accurately obtain solder joint resistance values, they all require an external monitoring capacitor. The addition of a monitoring capacitor has the following impacts: ① The accuracy of the capacitor is affected by the production process and the working environment, which affects the accuracy of solder joint health monitoring; ② Failure of the monitoring capacitor can lead to erroneous monitoring results; and ③ The cost of the monitoring capacitor increases the cost of the electronic system. Therefore, proposing a new FPGA solder joint health monitoring method that does not require a monitoring capacitor is of great engineering significance. Summary of the Invention

[0005] The purpose of the present invention is to overcome the above-mentioned problems existing in the prior art and provide an online monitoring and intelligent early warning method for intermittent faults in integrated circuits. The method utilizes the monitoring capacitor formed by the FPGA chip itself to simultaneously monitor the health of any two solder joints to be tested, providing a more cost-effective and accurate monitoring method for FPGA solder joint health monitoring.

[0006] In order to achieve the above technical objectives and the above technical effects, the present invention is implemented through the following technical solutions:

[0007] An online monitoring and intelligent early warning method for intermittent faults of integrated circuits is characterized by comprising the following steps:

[0008] Step 1: Set a monitoring capacitor on the FPGA chip to be tested. Use any two adjacent layers of copper foil on the FPGA chip PCB as capacitor plates and use the substrate between the two layers of copper foil as the dielectric material to form a monitoring capacitor.

[0009] Step 2: Select any two solder joints to be tested on the FPGA chip, solder joint A and solder joint B, and short-circuit their pins to the monitoring capacitor;

[0010] Step 3: Set up a monitoring module, which includes port A, port B, port Fault_N, port Clk-S, port Clk-C, port CntA, port CntB, port FaultA_T, port FaultB_T, and port Current_T;

[0011] Wherein, the port A and port B are used to connect two solder joints A and B to be tested on the FPGA chip respectively;

[0012] The port Fault_N is used to manually preset the number of high-frequency sampling cycles of the fault threshold;

[0013] The port Clk-C is used to connect the low-frequency clock control signal to control the state of port A and port B, and respectively control port A and port B to output a high level or a low level state;

[0014] The port Clk-S is used to connect a high-frequency clock sampling signal, sample the signal of port A or port B, obtain the state of port A or port B, and record the corresponding number of sampling signal cycles;

[0015] The port CntA is used to output the number of sampling signal cycles when sampling port B, and the port CntB is used to output the number of sampling signal cycles when sampling port A;

[0016] The port Current_T is used to connect the timer signal and record the current time value in real time;

[0017] The port FaultA_T is used to output the time when the most recent A solder point fault occurred, and the port FaultB_T is used to output the time when the most recent B solder point fault occurred;

[0018] Step 4: Run the monitoring module. After the monitoring module is powered on and initialized, it enters the following states in sequence:

[0019] State 1: Port A and port B output low level at the same time to discharge the monitoring capacitor;

[0020] When the low-frequency clock control signal of port Clk-C falls, it enters state 2: port A outputs a high level, charging the monitoring capacitor through pad A. At the same time, the signal of port B is sampled through the high-frequency clock sampling signal of port Clk-S. The number of sampling signal cycles from the start of port A outputting a high level to the end of port B inputting a high level is recorded and outputted through port CntA.

[0021] When the low-frequency clock control signal of port Clk-C rises, it enters state 3: port A and port B output low level at the same time, discharging the monitoring capacitor again;

[0022] When the low-frequency clock control signal of port Clk-C falls again, it enters state 4: port B outputs a high level, charging the monitoring capacitor through pad B. At the same time, the signal of port A is sampled through the high-frequency clock sampling signal of port Clk-S. The number of sampling signal cycles from the start of port B outputting a high level to the end of port A inputting a high level is recorded and outputted through port CntB.

[0023] Step 5: During the operation of the monitoring module, the current time value is recorded in real time through port Current_T; when the output value of port CntA is greater than the fault threshold preset in port Fault_N, the current time value recorded by port Current_T is output to port FaultA_T; when the output value of port CntB is greater than the fault threshold preset in port Fault_N, the current time value recorded by port Current_T is output to port FaultB_T.

[0024] Furthermore, the pins of the soldering point A and the soldering point B are both short-circuited and connected to one of the plates of the monitoring capacitor, and the other plate of the monitoring capacitor is grounded.

[0025] Furthermore, the monitoring module is further provided with a port RST, and the port RST is used to input a reset signal of the monitoring module, and reset the timer to time 0 when the monitoring module is powered on and initialized.

[0026] Furthermore, the resistance value R of the solder joint to be detected of the FPGA chip is expressed as:

[0027]

[0028] Where ε is the relative dielectric constant, S is the area of ​​the two electrodes of the monitoring capacitor, d is the vertical distance between the two electrodes of the monitoring capacitor, V1 is the voltage value to which the monitoring capacitor can be charged, f is the frequency of the high-frequency clock sampling signal, V t is the critical voltage value of the sampling point from the low level state to the high level state, and n is the number of sampling signal cycles;

[0029] When the monitoring module is running, in state 2, the number of sampling signal cycles obtained by the high-frequency clock sampling signal from the start of the high-level output of port A to the end of the high-level input of port B is taken as n, that is, the output value of port CntA, which is substituted into the above formula to obtain the resistance value of solder joint A at the current moment; in state 4, the number of sampling signal cycles obtained by the high-frequency clock sampling signal from the start of the high-level output of port B to the end of the high-level input of port A is taken as n, that is, the output value of port CntB, which is substituted into the above formula to obtain the resistance value of solder joint B at the current moment.

[0030] The beneficial effects of the present invention are:

[0031] The online monitoring and intelligent early warning method for intermittent faults in integrated circuits provided by the present invention utilizes the monitoring capacitor formed by the FPGA chip itself to simultaneously monitor the health of any two solder joints to be detected, eliminating the need to solder external monitoring capacitors on the PCB board and improving the cost-effectiveness of monitoring. The proposed monitoring module outputs the current time value and the time of the most recent failure, which can be used for more complete solder joint health status monitoring and life assessment. The fault threshold can be set through the port Fault_N signal, improving the flexibility of solder joint health status monitoring. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of this application. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0033] Figure 1 It is a schematic diagram of the principle connection of the present invention;

[0034] Figure 2 It is a schematic diagram of various states of the monitoring module in the present invention. DETAILED DESCRIPTION

[0035] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making any creative efforts shall fall within the scope of protection of the present invention.

[0036] like Figure 1 The method for online monitoring and intelligent early warning of intermittent faults in integrated circuits uses the monitoring capacitor formed by the FPGA chip itself to simultaneously monitor the health of any two solder joints to be tested, including the following steps:

[0037] Step 1: Set a monitoring capacitor on the FPGA chip to be tested. Specifically, use any two adjacent layers of copper foil 10 on the FPGA chip PCB board as capacitor plates, and use the substrate 20 between the two layers of copper foil 10 as the dielectric material to form a monitoring capacitor.

[0038] From the knowledge of physics, we know that capacitance can be generated between two parallel electrode plates, such as Figure 1 As shown, a capacitor can be formed by using two adjacent layers of copper foil on a PCB as capacitor plates and the substrate between the two layers of copper foil as a dielectric material. The capacitance value is shown in formula (1):

[0039]

[0040] Among them, CF is the capacitance between the two parallel electrode plates, in F, ε is the relative dielectric constant, S is the area of ​​the two parallel electrode plates, d is the vertical distance between the two parallel electrode plates, π is the pi constant, which is approximately equal to 3.14159, and k is the electrostatic force constant, which is: 8.987551×10 9 N·m 2 / C 2 .

[0041] Substituting the known constants into formula (1) and transforming them, we can get formula (2):

[0042]

[0043] The capacitance value obtained in formula (2) is in F. Formula (2) is further transformed to obtain formula (3):

[0044]

[0045] The capacitance value obtained in formula (3) is in pF.

[0046] Step 2: Randomly select two solder joints to be detected on the FPGA chip, solder joint A and solder joint B, and short-circuit their pins to one of the plates of the monitoring capacitor, and ground the other plate of the monitoring capacitor.

[0047] Step 3: Set up a monitoring module. Specifically, the monitoring module is provided with port A, port B, port Fault_N, port Clk-S, port Clk-C, port CntA, port CntB, port FaultA_T, port FaultB_T, port Current_T and port RST.

[0048] Among them, port A and port B are respectively used to connect two solder joints A and B to be tested on the FPGA chip.

[0049] Port Fault_N is used to manually preset the number of high-frequency sampling cycles of the fault threshold.

[0050] Port Clk-C is used to connect a 500KHz low-frequency clock control signal to control the status of port A and port B, controlling port A and port B to output a high or low level state respectively. The charging and discharging time of the external capacitor can be accurate to 1μs.

[0051] Port Clk-S is used to connect a 100 MHz high-frequency clock sampling signal to sample the signal at port A or port B, obtain the status of port A or port B, and record the corresponding number of sampling signal cycles.

[0052] Port CntA is used to output the number of sampling signal cycles when sampling port B, and port CntB is used to output the number of sampling signal cycles when sampling port A.

[0053] Port Current_T is used to connect the timer signal and record the current time value in real time.

[0054] The port FaultA_T is used to output the time when the most recent A solder point fault occurred, and the port FaultB_T is used to output the time when the most recent B solder point fault occurred.

[0055] Port RST is used to input the reset signal of the monitoring module.

[0056] Step 4: Run the monitoring module, such as Figure 2 As shown in the figure, after the monitoring module is powered on and initialized, it enters the following states in sequence:

[0057] State 1: Port A and port B output low level at the same time to discharge the monitoring capacitor, and port RST resets the timer to time 0;

[0058] When the low-frequency clock control signal of port Clk-C falls, it enters state 2: port A outputs a high level, charging the monitoring capacitor through solder joint A. At the same time, the signal of port B is sampled through the high-frequency clock sampling signal of port Clk-S. The number of sampling signal cycles from the start of port A outputting a high level to the end of port B inputting a high level is recorded and outputted through port CntA to calculate the resistance value of solder joint A at the current moment.

[0059] When the low-frequency clock control signal of port Clk-C rises, it enters state 3: port A and port B output low level at the same time, discharging the monitoring capacitor again;

[0060] When the low-frequency clock control signal of port Clk-C falls again, it enters state 4: port B outputs a high level, charging the monitoring capacitor through solder joint B. At the same time, the signal of port A is sampled through the high-frequency clock sampling signal of port Clk-S, and the number of sampling signal cycles from the start of port B outputting a high level to the end of port A inputting a high level is recorded and outputted from port CntB to calculate the resistance value of solder joint B at the current moment.

[0061] According to the charging characteristics of the capacitor, the capacitor charging time is related to the capacitance value of the capacitor and the solder joint resistance, and the capacitance value of the capacitor is fixed.

[0062] As we all know, the charge and discharge of a capacitor can be expressed as:

[0063]

[0064] Among them, V0 is the initial voltage value of the capacitor, V1 is the voltage value that the capacitor can eventually be charged to, t is the charging time, V t is the voltage value at charging time t.

[0065] After transforming the above formula, the resistance value of the FPGA solder joint is expressed as:

[0066]

[0067] In the present invention, by first discharging the monitoring capacitor, the initial voltage V0 of the charging process is 0V; sampling is performed by a high-frequency clock sampling signal with a frequency of f, and the critical voltage value of the sampling point from the low level state to the high level state is obtained, which is the voltage value V at the charging time t. t , the number of sampling signal cycles recorded is n; the capacitance value C of the monitoring capacitor can be calculated by formula (3) pF , and substitute it into the capacitance value C in formula (5), and then the resistance value R of the FPGA solder joint is expressed as:

[0068]

[0069] For 3.3V FPGA pins, the time from charging from low level to detecting high level is t, then V0 is 0V, V1 is 3.3V, V t is 2V. Then, by transforming formula (6), we can know:

[0070]

[0071] When the monitoring module is running, in state 2, the high-frequency clock sampling signal CLK_S is used to obtain the number of sampling signal cycles from the start of the high-level output of port A to the end of the high-level input of port B as n, which is the monitoring module output signal CntA. Substituting it into formula (6) can obtain the resistance value of solder joint A at the current moment; in state 4, the high-frequency clock sampling signal CLK_S is used to obtain the number of sampling signal cycles from the start of the high-level output of port B to the end of the high-level input of port A as n, which is the monitoring module output signal CntB. Substituting it into formula (6) can obtain the resistance value of solder joint B at the current moment.

[0072] Step 5: During the operation of the monitoring module, the current value is recorded in real time through port Current_T; when the output value of port CntA is greater than the fault threshold preset in port Fault_N, the current value recorded by port Current_T is output to port FaultA_T; when the output value of port CntB is greater than the fault threshold preset in port Fault_N, the current value recorded by port Current_T is output to port FaultB_T;

[0073] Among them, FaultA_T is the time when the most recent welding point A fails, and FaultB_T is the time when the most recent welding point B fails.

[0074] The online monitoring and intelligent early warning method for intermittent faults in integrated circuits provided by the present invention utilizes the monitoring capacitor formed by the FPGA chip itself to simultaneously monitor the health of any two solder joints to be detected, eliminating the need to solder external monitoring capacitors on the PCB board and improving the cost-effectiveness of monitoring. The proposed monitoring module outputs the current time value and the time of the most recent failure, which can be used for more complete solder joint health status monitoring and life assessment. The fault threshold can be set through the port Fault_N signal, improving the flexibility of solder joint health status monitoring.

[0075] Throughout this specification, references to terms such as "one embodiment," "example," or "specific example" indicate that the specific features, structures, materials, or characteristics described in conjunction with that embodiment or example are included in at least one embodiment or example of the present invention. In this specification, schematic representations of these terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

[0076] The basic principles, main features, and advantages of the present invention are shown and described above. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The above embodiments and descriptions are merely illustrative of the principles of the present invention. Various changes and modifications may be made to the present invention without departing from the spirit and scope of the present invention, and such changes and modifications fall within the scope of the invention as claimed.

Claims

1. A method for online monitoring and intelligent early warning of intermittent faults of integrated circuits, characterized in that: The following steps are involved: Step 1: Setting a monitoring capacitor on the FPGA chip to be detected, using any two adjacent layers of copper foil (10) on the FPGA chip PCB as capacitor plates, and using the base material (20) between the two layers of copper foil (10) as a dielectric material to form a monitoring capacitor; Step 2: Select any two solder joints to be tested on the FPGA chip, solder joint A and solder joint B, and short-circuit their pins to the monitoring capacitor; Step 3: Set up a monitoring module, which includes port A, port B, port Fault_N, port Clk-S, port Clk-C, port CntA, port CntB, port FaultA_T, port FaultB_T, and port Current_T; Wherein, the port A and port B are used to connect two solder joints A and B to be tested on the FPGA chip respectively; The port Fault_N is used to manually preset the number of high-frequency sampling cycles of the fault threshold; The port Clk-C is used to connect the low-frequency clock control signal to control the state of port A and port B, and respectively control port A and port B to output a high level or a low level state; The port Clk-S is used to connect a high-frequency clock sampling signal, sample the signal of port A or port B, obtain the state of port A or port B, and record the corresponding number of sampling signal cycles; The port CntA is used to output the number of sampling signal cycles when sampling port B, and the port CntB is used to output the number of sampling signal cycles when sampling port A; The port Current_T is used to connect the timer signal and record the current time value in real time; The port FaultA_T is used to output the time when the most recent A solder point fault occurred, and the port FaultB_T is used to output the time when the most recent B solder point fault occurred; Step 4: Run the monitoring module. After the monitoring module is powered on and initialized, it enters the following states in sequence: State 1: Port A and port B output low level at the same time to discharge the monitoring capacitor; When the low-frequency clock control signal of port Clk-C falls, it enters state 2: port A outputs a high level, charging the monitoring capacitor through pad A. At the same time, the signal of port B is sampled through the high-frequency clock sampling signal of port Clk-S. The number of sampling signal cycles from the start of port A outputting a high level to the end of port B inputting a high level is recorded and outputted through port CntA. When the low-frequency clock control signal of port Clk-C rises, it enters state 3: port A and port B output low level at the same time, discharging the monitoring capacitor again; When the low-frequency clock control signal of port Clk-C falls again, it enters state 4: port B outputs a high level, charging the monitoring capacitor through pad B. At the same time, the signal of port A is sampled through the high-frequency clock sampling signal of port Clk-S. The number of sampling signal cycles from the start of port B outputting a high level to the end of port A inputting a high level is recorded and outputted through port CntB. Step 5: During the operation of the monitoring module, the current time value is recorded in real time through port Current_T; when the output value of port CntA is greater than the fault threshold preset in port Fault_N, the current time value recorded by port Current_T is output to port FaultA_T; when the output value of port CntB is greater than the fault threshold preset in port Fault_N, the current time value recorded by port Current_T is output to port FaultB_T.

2. The method for online monitoring and intelligent early warning of intermittent faults of integrated circuits according to claim 1, characterized in that: The pins of the soldering point A and the soldering point B are both short-circuited and connected to one of the plates of the monitoring capacitor, and the other plate of the monitoring capacitor is grounded.

3. The method for online monitoring and intelligent early warning of intermittent faults of integrated circuits according to claim 1, characterized in that: The monitoring module is further provided with a port RST, and the port RST is used to input a reset signal of the monitoring module, and reset the timer to time 0 when the monitoring module is powered on and initialized.

4. The method for online monitoring and intelligent early warning of intermittent faults of integrated circuits according to claim 1, characterized in that: The resistance value R of the solder joint to be detected on the FPGA chip is expressed as: Where ε is the relative dielectric constant, S is the area of ​​the two electrodes of the monitoring capacitor, d is the vertical distance between the two electrodes of the monitoring capacitor, V1 is the voltage value to which the monitoring capacitor can be charged, f is the frequency of the high-frequency clock sampling signal, V t is the critical voltage value of the sampling point from the low level state to the high level state, and n is the number of sampling signal cycles; When the monitoring module is running, in state 2, the number of sampling signal cycles obtained by the high-frequency clock sampling signal from the start of the high-level output of port A to the end of the high-level input of port B is taken as n, that is, the output value of port CntA, which is substituted into the above formula to obtain the resistance value of solder joint A at the current moment; in state 4, the number of sampling signal cycles obtained by the high-frequency clock sampling signal from the start of the high-level output of port B to the end of the high-level input of port A is taken as n, that is, the output value of port CntB, which is substituted into the above formula to obtain the resistance value of solder joint B at the current moment.

Images