Multi-channel acoustic emission signal acquisition system based on AD conversion IP core

Abstract

This invention discloses a multi-channel acoustic emission signal acquisition system based on an AD analog-to-digital converter (AD) IP core. The system comprises: an AD IP core that drives multiple channel AD chips to perform analog-to-digital conversion to obtain acoustic emission data, and integrates the acoustic emission data from multiple channels before sending it to a FIFO buffer module; a FIFO buffer module that buffers the integrated acoustic emission data; a DMA module that transmits the integrated acoustic emission data buffered in the FIFO buffer module to the DDR3 memory of a host computer; a timing control module that receives a clock signal generated by the host computer and transmits it to other modules; and a host computer that provides the clock signal required by the multi-channel data acquisition system, retrieves the integrated acoustic emission data from the DDR3 memory, and extracts the acoustic emission data of each channel through bitwise operations. This invention achieves channel partitioning functionality in a multi-channel data acquisition system through multi-channel data integration and bitwise operations, reducing the workload and complexity of system development and design, and increasing the proportion of effective data bits in the transmitted data.

Description

Technical Field

[0001] This invention relates to the field of high-speed signal data acquisition, and in particular to a multi-channel acoustic emission signal acquisition system based on an AD analog-to-digital converter IP core. Background Technology

[0002] Acoustic emission (AE) is a common physical phenomenon. When materials (such as rocks and metals) fracture or deform under external and internal forces, stress concentration occurs in localized areas, rapidly releasing energy and generating transient elastic waves. This phenomenon is called acoustic emission (AE). Due to changes in the material's internal structure, the stress within the material suddenly redistributes, converting mechanical energy into acoustic energy and generating elastic waves. The frequency of acoustic emission is generally between 1 kHz and 1 MHz. Acoustic emission detection, by collecting and analyzing the acoustic emission signals generated in materials, enables non-destructive testing of materials and has been successfully applied in materials science, petrochemicals, aerospace, metal processing, geotechnical engineering, and other fields. Because of the relatively high frequency of acoustic emission, a high sampling frequency is required to sample the analog signal and a high-speed analog-to-digital converter (ADC) is used to obtain the desired digital signal in order to satisfy the Nyquist sampling law and achieve complete sampling of the acoustic emission signal.

[0003] An FPGA (Field Programmable Gate Array) employs an array of logic cells, internally comprising three parts: Configurable Logic Blocks (CLBs), Input / Output Blocks (IOBs), and interconnects. Users can reconfigure the internal logic and I / O modules of the FPGA to achieve their desired logic functions; therefore, an FPGA can implement the functionality of any digital device. Because an FPGA integrates numerous hardware resources onto a single chip, it can integrate multiple controllers and various peripheral interface circuits. It boasts advantages such as high clock frequency, low internal latency, flexible programming configuration, pure hardware parallel control, and high processing speed, making it highly suitable for real-time, high-speed data acquisition.

[0004] Although FPGA-based data acquisition systems can drive different analog-to-digital converter (AD) modules by configuring the FPGA's logic and I / O modules, thereby converting the analog signals acquired by the sensors into digital signals that can be recognized by digital circuits, different AD conversion IP cores need to be designed for AD conversion modules with different specific requirements.

[0005] Furthermore, multi-channel data acquisition systems require distinguishing the channels from which the acquired data is processed. For FPGA-based multi-channel data acquisition systems, there are currently three methods for channel partitioning:

[0006] 1. Channel selection IP core: When designing FPGA soft cores, in addition to designing an IP core for driving the AD analog-to-digital conversion module, users also design an IP core for channel selection as an analog switch for multiple channels, used for channel selection during multi-channel data acquisition.

[0007] 2. Use multiple FIFO IP cores to store data from different channels: When designing FPGA soft cores, users can design multiple FIFO modules to store the data collected by the AD analog-to-digital conversion modules of different channels.

[0008] 3. Channel Information Encoding: In the IP core driving the AD analog-to-digital converter module, channel information is encoded using additional data bits. The channel information and data information are then concatenated, and the concatenated data is transmitted to the host computer. The host computer receives the concatenated data, decodes the channel information, and obtains the corresponding channel number.

[0009] Currently, most FPGA-based multi-channel data acquisition systems employ the first channel partitioning method mentioned above. Both the first and second channel partitioning methods require users to design additional IP cores, increasing their workload and complicating the data acquisition system design. The third channel partitioning method requires additional data bits for channel marking. However, this method results in a significant amount of useless information (channel bits) in the transmitted data, reducing the proportion of effective data bits. Furthermore, due to the limited data bit width of both the AD converter and the FIFO buffer module, the available number of additional data bits for channel information marking may be insufficient to represent all channels through encoding. Summary of the Invention

[0010] This invention provides an AD analog-to-digital converter IP core for multi-channel acoustic emission signal acquisition, which solves the problems of complex system design and low proportion of effective data bits in the transmitted data caused by channel division of the acquired data in existing multi-channel data acquisition systems.

[0011] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0012] An analog-to-digital converter (AD) IP core for multi-channel acoustic emission signal acquisition includes the following:

[0013] The AD analog-to-digital conversion IP core is connected to the host computer and the FIFO buffer module. It receives data conversion instructions from the host computer, drives the AD chip with multiple channels to perform analog-to-digital conversion on the acoustic emission signals collected by the acoustic emission sensor to obtain acoustic emission data of multiple channels, and then integrates the acoustic emission data of multiple channels and sends it to the FIFO buffer module for buffering.

[0014] The FIFO buffer module is connected to the AD analog-to-digital converter IP core and the DMA module. It provides data buffering function for the AD analog-to-digital converter IP core and stores the multi-channel acoustic emission integrated data transmitted by the AD analog-to-digital converter IP core. When the size of the buffered multi-channel acoustic emission integrated data reaches the maximum storage capacity of the FIFO, the FIFO buffer module sends the buffered multi-channel acoustic emission integrated data to the DMA module.

[0015] The DMA module, connected to the FIFO cache module and the host computer, receives the multi-channel acoustic emission integrated data sent by the FIFO cache module and further transmits it to the DDR3 memory of the host computer.

[0016] The timing control module connects to the AD analog-to-digital converter IP core, FIFO buffer module, DMA module, and host computer. It receives the clock signal generated by the host computer and provides the clock signal required for the operation of the AD analog-to-digital converter IP core, FIFO buffer module, and DMA module.

[0017] The host computer provides the clock signal required for the multi-channel data acquisition system to operate, reads the integrated acoustic emission data of the multi-channel from DDR3 memory, and extracts the acoustic emission data of each channel through bitwise operations.

[0018] Furthermore, the AD analog-to-digital conversion IP core includes a state machine unit, which controls the process of the AD analog-to-digital conversion of acoustic emission signals and the transmission of acoustic emission data by the AD analog-to-digital conversion IP core, including three states: "init", "process", and "transmit". In the "init" state, the AD analog-to-digital converter IP core waits for the host computer to send a command to start data conversion. Upon receiving the command, the AD analog-to-digital converter IP core enters the "process" state, driving multiple channels of AD chips to perform high-speed AD conversion on the acoustic emission signals collected by the acoustic emission sensors to obtain acoustic emission data that can be recognized and processed by digital chips. Then, the acoustic emission data from multiple channels is padded with zeros and integrated according to the channel order, so that the data bit width of the integrated multi-channel acoustic emission data is the same as the data storage bit width of the FIFO buffer module. After the multi-channel data integration is completed, the AD analog-to-digital converter IP core enters the "transmit" state and sends the multi-channel acoustic emission integrated data to the FIFO buffer module for caching. If the number of multi-channel acoustic emission integrated data sent reaches the storage depth of the FIFO buffer module, the AD analog-to-digital converter IP core completes the acoustic emission data acquisition task for a single analog-to-digital conversion command and enters the "init" state; otherwise, the AD analog-to-digital converter IP core returns to the "process" state and continues to integrate the next multi-channel acoustic emission integrated data.

[0019] Furthermore, the process of integrating acoustic emission data from multiple channels by the AD analog-to-digital conversion IP core includes the following steps:

[0020] Step 1.1: Perform AD analog-to-digital conversion on the acoustic emission signal of each channel to obtain the acoustic emission data of all channels;

[0021] Step 1.2: By padding the high address bits of the data with 0, the data bit width of the acoustic emission data of each channel is filled to an integer multiple of 8, so as to meet the storage requirements of the FIFO buffer module for the data bit width;

[0022] Step 1.3 involves splicing the acoustic emission data from all channels after data filling according to the channel order, integrating them into multi-channel acoustic emission integrated data with the same data bit width as the data storage bit width of the FIFO buffer module, thereby completing the integration of acoustic emission data from multiple channels.

[0023] Furthermore, the process by which the host computer reads the multi-channel acoustic emission integrated data from the DDR3 memory and extracts the acoustic emission data of each channel through bitwise operations includes the following steps:

[0024] Step 2.1: Read the multi-channel acoustic emission integrated data from the DDR3 memory;

[0025] Step 2.2: Set a channel mask with the same data bit width as the integrated data of the multi-channel acoustic emission. According to the channel data to be selected, set the corresponding channel bits of the channel mask to 1 and the remaining bits to 0.

[0026] Step 2.3: Perform a bitwise AND operation on the channel mask corresponding to each channel and the integrated acoustic emission data of the multi-channel, and then right-shift the bitwise AND result by the corresponding number of channel bits to obtain the acoustic emission data of each channel.

[0027] The present invention, by adopting the above technical solution, has the following beneficial effects:

[0028] (1) This invention integrates acoustic emission data from multiple channels within an AD analog-to-digital converter IP core, and then performs bitwise operations between the integrated multi-channel acoustic emission data and the channel mask on the host computer to divide the acoustic emission data from multiple channels. In this way, users do not need to design an additional IP core for channel selection, thereby reducing the complexity of system design and the workload of system development.

[0029] (2) The present invention transmits the integrated data of multi-channel acoustic emission to the host computer, and then performs bit operations on the integrated multi-channel acoustic emission data and channel mask on the host computer to extract the data of each channel. This method can realize the channel division of acoustic emission data of multiple channels without using additional data bits for channel marking, and improves the effective data bit ratio in the data transmission process.

[0030] (3) The AD analog-to-digital conversion IP core proposed in this invention has a channel division method that is well applicable to data acquisition systems with different numbers of channels and different data transmission bit widths. Attached Figure Description

[0031] Figure 1 This is a logic framework diagram of an AD analog-to-digital converter IP core for acoustic emission signal acquisition of four channels provided in an embodiment of the present invention;

[0032] Figure 2 This is the state transition diagram of the state machine unit in this embodiment of the invention;

[0033] Figure 3 This is a schematic diagram illustrating the integration of acoustic emission data from four channels in an embodiment of the present invention.

[0034] Figure 4 This is a schematic diagram of the principle of extracting the acoustic emission data CH3 of channel 3 by performing bit operations on the four-channel acoustic emission integrated data and the channel mask of channel 3 in this embodiment of the invention.

[0035] Figure 5This is a circuit design diagram of an AD analog-to-digital converter IP core for acoustic emission signal acquisition of four channels, based on an FPGA+ARM system in this embodiment of the invention. Detailed Implementation

[0036] To make the objectives, technical solutions, and advantages of this invention clearer, the embodiments of this invention are further described in detail below with reference to the accompanying drawings. However, it is obvious that the described embodiments are merely some embodiments of this invention, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0037] The following uses a four-channel acoustic emission signal acquisition system as an example to specifically describe the AD analog-to-digital converter IP core used for four-channel acoustic emission signal acquisition in this embodiment of the invention. The data bit width of the AD chip used in this embodiment is 10 bits.

[0038] like Figure 1 As shown, this embodiment of the invention provides an AD analog-to-digital converter IP core for four-channel acoustic emission signal acquisition based on an FPGA+ARM system, including an AD analog-to-digital converter IP core, a FIFO buffer module, a DMA module, a timing control module, and a host computer, wherein:

[0039] The AD analog-to-digital converter IP core, acting as a slave device in the AXI4 protocol, receives the start data conversion command from the host computer. It drives the four-channel AD chip to perform analog-to-digital conversion on the acoustic emission signals collected by the acoustic emission sensor to obtain four channels of acoustic emission data. Then, it integrates the four channels of acoustic emission data to obtain four-channel integrated acoustic emission data. After obtaining the four-channel integrated acoustic emission data, the AD analog-to-digital converter IP core, acting as a master device in the AXI-Stream protocol, sends the four-channel integrated acoustic emission data to the FIFO buffer module.

[0040] The FIFO buffer module, acting as a slave of the AXI-Stream protocol, receives and buffers the four-channel acoustic emission integrated data sent by the AD analog-to-digital conversion IP core. When the size of the buffered four-channel acoustic emission integrated data reaches the maximum storage capacity of the FIFO buffer module, the FIFO buffer module, acting as the master of the AXI-Stream protocol, sends the buffered four-channel acoustic emission integrated data to the DMA module.

[0041] The DMA module, acting as a slave in the AXI-Stream protocol, receives the four-channel acoustic emission integrated data sent by the FIFO buffer module; acting as a master in the AXI4 protocol, it further transmits the received four-channel acoustic emission integrated data to the DDR3 memory of the host computer.

[0042] The timing control module receives the clock signal generated by the host computer and provides the clock required for the operation of the AD analog-to-digital conversion IP core, FIFO buffer module, and DMA module.

[0043] The host computer provides the clock signal required for the four-channel acoustic emission signal acquisition system to operate, reads the integrated acoustic emission data of the four channels from DDR3 memory, and then extracts the acoustic emission data of each channel through bitwise operations.

[0044] like Figure 2 As shown, the state machine unit used to control the AD analog-to-digital converter IP core for acoustic emission signal data conversion and acoustic emission data transmission includes three states: "init", "process", and "transmit". In the "init" state, the AD analog-to-digital converter IP core waits for the host computer to send a command to start data conversion. After receiving the command to start data conversion, the AD analog-to-digital converter IP core enters the "process" state, drives the four-channel AD chip to perform high-speed AD acquisition of the acoustic emission signal to obtain acoustic emission data, then pads the acoustic emission data of the four channels with zeros and integrates them according to the channel order, so that the integrated four-channel acoustic emission data... The data width is 64 bits (8 bytes), the same as the data width of the FIFO buffer module. After the acoustic emission data of the four channels is integrated, the AD analog-to-digital converter IP core enters the "transmit" state and sends the integrated four-channel acoustic emission data to the FIFO buffer module through the AXI-Stream protocol. If the number of multi-channel acoustic emission integrated data sent reaches the storage depth of the FIFO buffer module, the AD analog-to-digital converter IP core completes the acoustic emission data acquisition task of a single instruction and enters the "init" state. Otherwise, the AD analog-to-digital converter IP core returns to the "process" state and continues to integrate the next multi-channel acoustic emission integrated data.

[0045] like Figure 3 As shown, the integration process of acoustic emission data from the four channels in the AD analog-to-digital converter IP core includes the following steps:

[0046] A1: Acoustic emission data CH1, CH2, CH3, and CH4 of the four channels are acquired by AD acquisition of the acoustic emission signals of the four channels. The acoustic emission data of each channel has a bit width of 10 bits.

[0047] A2: Add 6 "0"s to the high address bits of acoustic emission data CH1, CH2, CH3, and CH4 to make the data bit width of each acoustic emission data 16 bits;

[0048] A3: The acoustic emission data CH1, CH2, CH3, and CH4 after data filling are concatenated in the channel order of CH4, CH3, CH2, and CH1 to obtain a 64-bit (8-byte) four-channel acoustic emission integrated data packet, thus completing the integration of the acoustic emission data of the four channels.

[0049] like Figure 4 As shown, the process by which the host computer reads the four-channel acoustic emission integrated data packet from the DDR3 memory and extracts the acoustic emission data CH3 of channel 3 through bitwise operations includes the following steps:

[0050] B1: Reads the quad-channel acoustic emission integrated data packet from DDR3 memory;

[0051] B2: Set the channel mask of channel 3 to Ch_Mask3, with a value of 0x0000FFFF00000000;

[0052] B3: Perform a bitwise AND operation on the four-channel acoustic emission data packet and Ch_Mask3, and then shift the result 16 bits to the right to obtain the acoustic emission data CH3 of channel 3.

[0053] like Figure 5 As shown in the figure, this embodiment of the invention provides a circuit design diagram of an AD analog-to-digital converter IP core for four-channel acoustic emission signal acquisition based on an FPGA+ARM system, including the following:

[0054] The `data_source_generator` IP core serves as the AD (Analog-to-Digital) converter IP core. To drive four 10-bit data-width AD converter modules, the `data_source_generator` IP core defines corresponding pins for each of the four AD channels, including data pins `ad0_data[9:0]`, `ad1_data[9:0]`, `ad2_data[9:0]`, and `ad3_data[9:0]`, overflow pins `ad0_otr`, `ad1_otr`, `ad2_otr`, and `ad3_otr`, clock pins `ad0_clk`, `ad1_clk`, `ad2_clk`, and `ad3_clk`, and enable pins `ad0_oe`, `ad1_oe`, `ad2_oe`, and `ad3_oe`. Besides the pins related to the AD chips, the `data_source_generator`... The main pins defined by the IP core also include the clock pin sys_clk, the reset pin sys_aresetn, the host pins related to the AXI-Stream protocol M00_AXIS, the clock pin m00_axis_aclk, the reset pin m00_axis_aresetn, and the slave pins related to the AXI4 protocol S00_AXI, the clock pin s00_axi_aclk, and the reset pin s00_axi_aresetn.

[0055] The FIFO IP core, as a FIFO buffer module, has a data storage width of 8 bytes, which is the same as the data bit width of the four-channel acoustic emission integrated data. Its main pins include the clock pin s_axis_aclk, the reset pin s_axis_aresetn, the slave pin S_AXIS of the AXI-Stream protocol for receiving the four-channel acoustic emission integrated data sent by the AD analog-to-digital converter IP core, and the master pin S_AXIS of the AXI-Stream protocol for sending the four-channel acoustic emission integrated data to the DMA module.

[0056] The DMA IP core, as a DMA module, transmits data from the FPGA to the DDR3 memory of the host computer. Its main pins include the slave pin S_AXIS-S2MM of the AXI-Stream protocol for receiving four-channel acoustic emission integrated data sent by the FIFO buffer module, and the master pin M_AXI_S2MM of the AXI4 protocol for further transmitting data to the DDR3 memory of the host computer.

[0057] The Processing System IP core, an ARM processing system provided by Vivado software, serves as a timing control module and host computer. Its main pins include the FCLK_CLK0 pin, which provides the clock signal required for the entire system to operate; the M_AXI_GP0 pin, which is used to pass data conversion instructions to the AD analog-to-digital converter IP core; and the DDR pin, which is used to store the integrated data of the four-channel acoustic emission.

[0058] The above description is only one embodiment of the present invention. It should be noted that those skilled in the art can make several improvements and refinements without departing from the principle of the invention, and these improvements and refinements should also be considered within the scope of protection of the present invention.

Claims

1. A multi-channel acoustic emission signal acquisition system based on an AD analog-to-digital converter IP core, characterized in that, The system includes: The AD analog-to-digital conversion IP core is connected to the host computer and the FIFO buffer module. It receives data conversion instructions sent by the host computer, drives the AD chip with multiple channels to perform analog-to-digital conversion on the acoustic emission signals collected by the acoustic emission sensor to obtain acoustic emission data of multiple channels, and then integrates the acoustic emission data of multiple channels and sends it to the FIFO buffer module for buffering, so that the data bit width of the integrated multi-channel acoustic emission data is the same as the data storage bit width of the FIFO buffer module. The FIFO buffer module is connected to the AD analog-to-digital converter IP core and the DMA module. It provides data buffering function for the AD analog-to-digital converter IP core and stores the multi-channel acoustic emission integrated data transmitted by the AD analog-to-digital converter IP core. When the size of the buffered multi-channel acoustic emission integrated data reaches the maximum storage capacity of the FIFO, the FIFO buffer module sends the buffered multi-channel acoustic emission integrated data to the DMA module. The DMA module, connected to the FIFO cache module and the host computer, receives the multi-channel acoustic emission integrated data sent by the FIFO cache module and further transmits it to the DDR3 memory of the host computer. The timing control module connects to the AD analog-to-digital converter IP core, FIFO buffer module, DMA module, and host computer. It receives the clock signal generated by the host computer and provides the clock signal required for the operation of the AD analog-to-digital converter IP core, FIFO buffer module, and DMA module. The host computer provides the clock signal required for the multi-channel data acquisition system to operate, reads the integrated acoustic emission data of the multi-channel from DDR3 memory, and extracts the acoustic emission data of each channel through bitwise operations.

2. The multi-channel acoustic emission signal acquisition system based on an AD analog-to-digital converter IP core according to claim 1, characterized in that, The aforementioned AD analog-to-digital converter IP core includes a state machine unit, which is used to control the process of the AD analog-to-digital converter IP core performing acoustic emission signal analog-to-digital conversion and acoustic emission data transmission.

3. The multi-channel acoustic emission signal acquisition system based on an AD analog-to-digital converter IP core according to claim 2, characterized in that, The state machine unit includes three states: "init", "process", and "transmit". In the "init" state, the AD analog-to-digital converter IP core waits for the host computer to send a command to start data conversion. After receiving the command, the AD analog-to-digital converter IP core enters the "process" state, coordinating the AD chips of each channel to perform high-speed AD analog-to-digital conversion on the acoustic emission signals collected by the acoustic emission sensors, thereby obtaining acoustic emission data that can be recognized and processed by the digital chip. Then, the acoustic emission data of multiple channels is padded with zeros and integrated in channel order, so that the data bit width of the integrated multi-channel acoustic emission data is the same as the data storage bit width of the FIFO buffer module. After the acoustic emission data of multiple channels is integrated, the AD analog-to-digital converter IP core enters the "transmit" state and sends the multi-channel acoustic emission integrated data to the FIFO buffer module for buffering. If the number of multi-channel acoustic emission integrated data sent reaches the storage depth of the FIFO buffer module, the AD analog-to-digital converter IP core completes the acoustic emission data acquisition task of a single data conversion command and enters the "init" state; otherwise, the AD analog-to-digital converter IP core returns to the "process" state and continues to integrate the next multi-channel acoustic emission integrated data.

4. The multi-channel acoustic emission signal acquisition system based on an AD analog-to-digital converter IP core according to claim 1, characterized in that, The steps for integrating acoustic emission data from multiple channels using the AD analog-to-digital conversion IP core are as follows: Step 1.1: Perform AD analog-to-digital conversion on the acoustic emission signal of each channel to obtain the acoustic emission data of all channels; Step 1.2: By padding the high address bits of the data with 0, the data bit width of the acoustic emission data of each channel is filled to an integer multiple of 8, so as to meet the storage requirements of the FIFO buffer module for the data bit width; Step 1.3 involves splicing the acoustic emission data from all channels after data filling according to the channel order, integrating them into multi-channel acoustic emission integrated data with the same data bit width as the data storage bit width of the FIFO buffer module, thereby completing the integration of acoustic emission data from multiple channels.

5. A multi-channel acoustic emission signal acquisition system based on an AD analog-to-digital converter IP core according to claim 1, characterized in that, The steps for the host computer to obtain multi-channel acoustic emission integrated data from DDR3 memory and extract the acoustic emission data of each channel through bitwise operations are as follows: Step 2.1: Read the multi-channel acoustic emission integrated data from DDR3 memory; Step 2.2: Set a channel mask with the same data bit width as the integrated data of the multi-channel acoustic emission. According to the channel data to be selected, set the corresponding channel bits of the channel mask to 1 and the remaining bits to 0. Step 2.3: Perform a bitwise AND operation on the channel mask corresponding to each channel and the integrated acoustic emission data of the multi-channel, and then right-shift the bitwise AND result by the corresponding number of channel bits to obtain the acoustic emission data of each channel.

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