Data processing method, core, system, electronic device and computer readable medium
By setting up a cache in the core and using mapping relationships to store axon events, parallel data processing was achieved, solving the problem of slow data processing speed in many-core systems and improving data processing efficiency.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2021-12-28
- Publication Date
- 2026-03-27
AI Technical Summary
In many-core systems, the slow data processing speed is caused by multiple cores performing operations based on synchronous cycles.
At least two caches are set up in the core. Axon events are stored in the corresponding caches through a pre-defined mapping relationship between cache identifiers and axon identifiers. Axon events are stored and processed separately and synchronously through multiple caches to achieve parallel data processing.
It improves data processing speed, reduces computation time through parallel processing, and enhances data processing efficiency.
Smart Images
Figure CN116362302B_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present disclosure relates to the technical field of computer, and particularly relates to a data processing method, a core, a system, an electronic device and a computer readable medium. BACKGROUND
[0002] The neural network chip has a plurality of computing units, and the smallest computing unit that can be independently scheduled and has complete computing capability in each chip is referred to as a core. In some related technologies, a plurality of cores of a many-core system perform operations based on a synchronization period, and the data processing speed is slow. SUMMARY
[0003] The present disclosure provides a data processing method, a core, a system, an electronic device and a computer readable medium.
[0004] In a first aspect, an embodiment of the present disclosure provides a data processing method applied to a core, the core comprising at least two caches, and the method comprises:
[0005] In response to receiving a data packet, an axon event in the data packet is obtained, and the axon event comprises at least an axon identifier;
[0006] According to a first mapping relationship between a preset cache identifier and an axon identifier, the axon event is stored in a cache corresponding to the axon identifier.
[0007] In some embodiments, the method further comprises determining a neuron identifier and a weight corresponding to the axon event;
[0008] After storing the axon event in the cache corresponding to the axon identifier, the method further comprises:
[0009] For each neuron, in response to receiving an axon event and a weight, an operation is performed according to the weight.
[0010] In some embodiments, the data packet further comprises a second mapping relationship between the axon identifier, the neuron identifier and the weight, and the determination of the neuron identifier and the weight corresponding to the axon event comprises:
[0011] The second mapping relationship in the data packet is obtained, and the neuron identifier and the weight corresponding to the axon event are determined according to the second mapping relationship.
[0012] In some embodiments, the determination of the neuron identifier and the weight corresponding to the axon event comprises:
[0013] According to a second mapping relationship between a preset axon identifier, a neuron identifier and a weight, the neuron identifier and the weight corresponding to the axon event are determined.
[0014] In some embodiments, the step of performing calculations based on the weights in response to receiving an axonal event for each neuron includes:
[0015] For each neuron, in response to receiving multiple axon events, the first operation result corresponding to each axon event is calculated according to the weight corresponding to each axon event.
[0016] The first calculation results corresponding to each axon event are accumulated to obtain the calculation result of the neuron's input current.
[0017] In some embodiments, the summation of the first calculation results corresponding to each of the axon events to obtain the calculation result of the neuron input current includes:
[0018] For each cache, the first operation result corresponding to the axon event stored in the cache is accumulated to obtain the second operation result corresponding to each cache;
[0019] The results of each of the second operations are summed to obtain the result of the neuron's input current.
[0020] In some embodiments, the step of performing calculations based on the weights in response to receiving an axonal event for each neuron includes:
[0021] For each neuron, in response to receiving an axonal event and weights and firing a pulse, calculations are performed based on the weights to obtain the calculation result of the neuron's input current. The calculation result of the neuron's input current is used to determine the current membrane potential.
[0022] In response to the current membrane potential being greater than a preset membrane potential threshold, an emission pulse and a data packet are sent, the data packet including at least the axon event.
[0023] In some embodiments, in the first mapping relationship, at least one cache identifier corresponds to at least two axon identifiers.
[0024] In some embodiments, in the first mapping relationship, the number of axon identifiers corresponding to each cache identifier is the same.
[0025] In some embodiments, the number of caches is 2-20.
[0026] Secondly, this disclosure provides a core, the core comprising:
[0027] One or more processing units;
[0028] a storage unit having one or more programs stored thereon, which, when executed by the one or more processing units, cause the one or more processing units to implement any of the data processing methods described above.
[0029] In a third aspect, the embodiments of the present disclosure provide a many-core system, which includes at least two cores as described above, and the data packets received by the cores are sent by other cores in the many-core system.
[0030] In a fourth aspect, the embodiments of the present disclosure provide an electronic device, which includes:
[0031] a plurality of cores; and
[0032] a network-on-chip configured to interact data among the plurality of cores and external data;
[0033] one or more instructions stored in one or more of the cores, which are executed by the one or more cores to enable the one or more cores to implement any of the data processing methods described above.
[0034] In a fifth aspect, the embodiments of the present disclosure provide a computer readable medium having a computer program stored thereon, which, when executed by a processor, implements any of the data processing methods described above.
[0035] In the embodiments of the present disclosure, at least two caches are set in the core, after receiving the data packet, the axon event including the axon identifier in the data packet is obtained, and the axon event is stored in the cache corresponding to the axon identifier according to a preset first mapping relationship between the cache identifier and the axon identifier. By setting multiple caches in the core, each cache can store axon events respectively and synchronously, data parallel processing is achieved, and the data processing speed is improved.
[0036] It should be understood that the content described in this section is not intended to identify key or important features of the embodiments of the present disclosure, nor is it used to limit the scope of the present disclosure. Other features of the present disclosure will become apparent through the following description. BRIEF DESCRIPTION OF DRAWINGS
[0037] The accompanying drawings are included to provide a further understanding of the present disclosure and constitute a part of the specification, which together with the embodiments of the present disclosure are used to explain the present disclosure and do not constitute a limitation of the present disclosure. The above and other features and advantages will become more apparent to those skilled in the art from the detailed description of the exemplary embodiments with reference to the accompanying drawings, in which:
[0038] Figure 1 is a flowchart of a data processing method provided by the embodiments of the present disclosure;
[0039] Figure 2 is a flowchart of the neuron performing operation provided by an embodiment of the present disclosure Figure 1 ;
[0040] Figure 3 is a flowchart of the neuron performing operation provided by an embodiment of the present disclosure Figure 2 ;
[0041] Figure 4 is a schematic diagram of a specific example implementing data processing provided by an embodiment of the present disclosure
[0042] Figure 5 is a schematic diagram of a many-core system implementing data processing provided by an embodiment of the present disclosure
[0043] Figure 6 is a block diagram of a core provided by an embodiment of the present disclosure
[0044] Figure 7 is a block diagram of an electronic device provided by an embodiment of the present disclosure
[0045] Figure 8 is a block diagram of a computer readable medium provided by an embodiment of the present disclosure. DETAILED DESCRIPTION
[0046] In order to enable one skilled in the art to better understand the technical solutions of the present disclosure, the exemplary embodiments of the present disclosure are described below with reference to the accompanying drawings, including various details of the embodiments of the present disclosure to help understanding, which should be considered only as exemplary. Therefore, those of ordinary skill in the art should recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of the present disclosure. Also, for the sake of clarity and conciseness, the description below omits the description of well-known functions and structures.
[0047] In the case of no conflict, the embodiments of the present disclosure and the features in the embodiments can be combined with each other.
[0048] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.
[0049] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. "Coupled" or "connected" or similar terms are not restricted to physical or mechanical connections or associations, but can also include electrical connections, whether direct or indirect.
[0050] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted in an overly literal or overly formal sense unless expressly so defined herein.
[0051] In a first aspect, the embodiments of the present disclosure provide a data processing method, which can be applied to a core of a single-core system or a core of a many-core system. The core includes at least two caches, each of which is configured to store axon events in a data packet (i.e., a routing data packet), each data packet including at least an axon event, the axon event including an axon identifier, and by configuring the axon identifier managed by each cache, the axon events to be processed can be distributed to different caches.
[0052] With reference to Figure 1 The data processing method of the embodiments of the present disclosure includes the following steps:
[0053] Step 11, in response to receiving the data packet, obtaining the axon event in the data packet, the axon event including at least an axon identifier.
[0054] In this step, after the core receives the data packet, the core parses the data packet to obtain the axon event including the axon identifier.
[0055] Step 12, storing the axon event in the cache corresponding to the axon identifier according to a first mapping relationship between the cache identifier and the axon identifier.
[0056] The first mapping relationship between the cache identifier and the axon identifier is pre-stored in the core, wherein one cache identifier can correspond to multiple axon identifiers, and the axon identifiers corresponding to different cache identifiers are different. That is, different caches manage different multiple axons. For example, cache 1 manages axons 0-6, cache 2 manages axons 7-11, and cache 3 manages axons 12-16.
[0057] In this step, the axon identifier obtained in step 11 is used to query the first mapping relationship to obtain the cache identifier corresponding to the axon identifier, and the axon event obtained in step 11 is assigned to the cache corresponding to the cache identifier, and the axon event is stored by the cache.
[0058] The axon event is an event delivered by a core or a processor other than the current core to the current core, and the axon event corresponds to at least one neuron of the current core. The at least one neuron corresponding to the axon event is a neuron that needs to update the current membrane potential. It can be understood that the at least one neuron corresponding to the axon event of the current core has a non-zero weight between the neuron that emits the axon event.
[0059] In the embodiments of the present disclosure, at least two caches are set in the core. After receiving the data packet, the axon event including the axon identifier in the data packet is obtained, and the axon event is stored in the cache corresponding to the axon identifier according to the first mapping relationship between the preset cache identifier and the axon identifier. By setting multiple caches in the core, each cache can store and process the axon event corresponding to different axon identifiers, and each cache can store the axon event synchronously, so as to realize data parallel processing and improve data processing speed.
[0060] In some embodiments, the data processing method further includes the following steps: determining the neuron identifier and the weight corresponding to the axon event.
[0061] Correspondingly, after storing the axon event in the cache corresponding to the axon identifier (i.e., step 12), the data processing method further includes the following steps: for each neuron, in response to receiving the axon event and the weight, performing an operation according to the weight. In this step, after determining the neuron identifier and the weight corresponding to the axon event, each cache sends the axon event and the weight to the neuron corresponding to the neuron identifier, and the neuron performs an operation according to the weight.
[0062] It should be noted that for the neurons in the core, when receiving at least one axon event corresponding thereto, the corresponding weight can be determined, and an operation can be performed according to the weight to update the current membrane potential. When it does not receive the axon event corresponding thereto, it can not need to start the operation, thereby reducing the operation power consumption of the core.
[0063] In some embodiments, the data packet can further include a second mapping relationship between the axon identifier, the neuron identifier and the weight. The step of determining the neuron identifier and the weight corresponding to the axon event includes: obtaining the second mapping relationship between the axon identifier, the neuron identifier and the weight in the data packet, and determining the neuron identifier and the weight corresponding to the axon event according to the second mapping relationship.
[0064] In some embodiments, the step of determining the neuron identifier and the weight corresponding to the axon event comprises: determining the neuron identifier and the weight corresponding to the axon event according to a preset second mapping relationship between the axon identifier, the neuron identifier and the weight.
[0065] The second mapping relationship can be pre-stored in a memory of the core.
[0066] In the embodiments of the present disclosure, the neuron identifier and the weight corresponding to the axon event are determined according to a second mapping relationship between the axon identifier, the neuron identifier and the weight. There are two ways to obtain the second mapping relationship between the axon identifier, the neuron identifier and the weight: one is to carry the second mapping relationship between the axon identifier, the neuron identifier and the weight in the data packet, since the data packet also carries the axon event including the axon identifier, the axon event and the second mapping relationship can be obtained by analyzing the data packet, and the neuron identifier and the weight corresponding to the axon event are determined according to the second mapping relationship; the other is to store the second mapping relationship between the axon identifier, the neuron identifier and the weight in the core, and after the axon event including the axon identifier is obtained by analyzing the data packet, the neuron identifier and the weight corresponding to the axon event are determined according to the second mapping relationship stored in the core.
[0067] In some embodiments, as shown in Figure 2 For each neuron, in response to receiving the axon event and the weight, the operation according to the weight comprises the following steps:
[0068] Step 21, for each neuron, in response to receiving a plurality of axon events, a first operation result corresponding to each axon event is calculated according to a weight corresponding to the axon event.
[0069] For a neuron, an axon event corresponds to an axon identifier and a first operation result.
[0070] Step 22, the first operation results corresponding to the axon events are accumulated to obtain an operation result of the neuron input current.
[0071] In this step, the first operation results corresponding to different axon identifiers (i.e. axon events) in the same dendrite are accumulated to obtain the operation result of the corresponding neuron input current. In some embodiments, the first operation results corresponding to the axon events can be accumulated by using an adder. In some embodiments, the number of adders can be the same as the number of neurons, in which case one adder is connected to one neuron, that is, each neuron corresponds to one adder. In some embodiments, the number of adders can also be less than the number of neurons, in which case the adders can be multiplexed.
[0072] In some embodiments, as shown inFigure 3 As shown, the first operation results corresponding to each of the axon events are accumulated to obtain the operation result of the neuron input current (i.e., step 22), including the following steps:
[0073] Step 221, for each cache, the first operation results corresponding to the axon events stored in the cache are accumulated to obtain the second operation result corresponding to each cache.
[0074] One cache manages multiple axon identifiers, and correspondingly, one cache stores multiple axon events. In this step, each dendrite is divided into multiple parts corresponding to the caches (each part of the dendrite can correspond to one or more axon identifiers), and for each part of the dendrite, the neuron accumulates each first operation result corresponding to the respective cache to obtain the second operation result corresponding to each cache, which is the post-synaptic current corresponding to the cache.
[0075] For each neuron and each cache, the second operation result corresponding to each cache of the neuron is recorded, which is a set of the first operation results of the axon events corresponding to each cache of the neuron.
[0076] Step 222, each second operation result is accumulated to obtain the operation result of the neuron input current.
[0077] In this step, the neuron accumulates the second operation result corresponding to each cache to obtain the operation result of the neuron input current.
[0078] In this embodiment, for each neuron, the first operation results corresponding to each cache are respectively accumulated and calculated in the unit of cache to obtain the second operation results. The neuron then performs segmented accumulation, i.e., accumulates each second operation result to finally obtain the operation result of the neuron input current.
[0079] In this way, for each neuron, when multiple second operation results need to be calculated, the operation processes of the multiple second operation results can be parallel processing, which can improve the efficiency of determining the operation result of the neuron input current.
[0080] In some embodiments, the step of, for each neuron, performing operation according to the weight in response to receiving the axon event and the weight, includes: for each neuron, performing operation according to the weight in response to receiving the axon event and the weight and the firing pulse to obtain the operation result of the neuron input current, which is used to determine the current membrane potential of the neuron; and in response to the current membrane potential being greater than a preset membrane potential threshold, sending the firing pulse and a data packet, the data packet at least including the axon event.
[0081] It should be noted that when a neuron fires a spike, a current core in which the neuron is located can determine a target core, the target core being at least one core in the many-core system that needs to receive the fired spike. The current core can determine a data packet sent to each target core, the data packet including at least one axon event, each axon event including an axon identifier. The target core receiving the data packet can determine a cache for storing each axon event according to the axon identifier of each axon event in the data packet and a first mapping relationship between the cache identifier and the axon identifier.
[0082] For the spiking neural network, only when a neuron receives a spike signal, the weight is accumulated with the historical membrane potential to obtain a current membrane potential, and it is determined whether to fire a data packet to a corresponding core according to the current membrane potential and a membrane potential threshold. If the current membrane potential is greater than the membrane potential threshold, the spike signal and the data packet are transmitted to the corresponding core through routing. It should be noted that the data packet fired to the corresponding core at least includes an axon event (the axon event includes an axon identifier). In some embodiments, the data packet can further include a second mapping relationship between the axon identifier, the neuron identifier and the weight.
[0083] The core fires the determined weight and the axon event stored in the cache to the neuron in the order of the cache storage queue, so that the neuron performs operation when receiving the spike signal, that is, the neuron obtains the current membrane potential by integrating the membrane potential, and when the current membrane potential is greater than the membrane potential threshold, further processes such as sending the spike signal and the data packet, resetting the membrane potential, and leaking the membrane potential are performed.
[0084] In some embodiments, in the first mapping relationship, at least one cache identifier corresponds to at least two axon identifiers. That is, at least one cache manages multiple axons (that is, at least one cache is responsible for the axon event firing of multiple axons). Of course, those skilled in the art can know that each cache manages multiple axons is a more optimal solution. In this case, the sum of the number of axon identifiers corresponding to each cache is equal to the total number of axons, that is, each axon in the spiking neural network is divided into each cache for management, and each cache manages a part of axons and is responsible for the storage of the axon events corresponding to the axons.
[0085] In some embodiments, in the first mapping relationship, the number of axon identifiers corresponding to each cache identifier is the same, so that the data processing task can be evenly distributed to each cache, and the data processing efficiency can be further improved.
[0086] In some embodiments, generally, several caches can be set on a chip, for example, the number of caches can be 2-20.
[0087] In the embodiments of the present disclosure, each cache respectively and synchronously stores axon events and weights, and correspondingly, the same axon event can be operated synchronously between different neurons, and different axon events can be operated synchronously in the same neuron, so that the data processing speed is improved.
[0088] In order to clearly illustrate the technical solutions of the embodiments of the present disclosure, the following Figure 4 will be described in detail in conjunction with specific examples. As shown in Figure 4 , the core includes three caches (cache 1-3), and the core stores a first mapping relationship between cache identifiers and axon identifiers. For example, the first mapping relationship is shown in Table 1.
[0089] Table 1
[0090] Cache identification Axon identification i 1 0，1，…，49 2 50，51，…，99 3 100，101，…，149
[0091] In conjunction with Table 1 and Figure 3 , the core has 150 axons, cache 1 manages the 0th to 49th axons, that is, the axon identifiers managed by cache 1 are 0 to 49; cache 2 manages the 50th to 99th axons, that is, the axon identifiers managed by cache 2 are 50 to 99; and cache 3 manages the 100th to 149th axons, that is, the axon identifiers managed by cache 3 are 100 to 149.
[0092] After the core receives a data packet and obtains an axon event including an axon identifier in the data packet, the axon event is allocated to the corresponding cache for storage according to Table 1.
[0093] The core also stores a second mapping relationship between axon identifiers, neuron identifiers and weights. For example, the second mapping relationship is shown in Table 2.
[0094] Table 2
[0095]
[0096] In this example, each neuron operates in a segmented manner. For example, for neuron 3, an axon event with an axon identifier of 0 is received, and Table 2 is queried to obtain the weight of neuron 3 as W 0,3 = 10, an axon event with an axon identifier of 2 is received, and Table 2 is queried to obtain the weight of neuron 3 as W 2,3 = 1, an axon event with an axon identifier of 60 is received, and Table 2 is queried to obtain the weight of neuron 3 as W 60,3 = 5, an axon event with an axon identifier of 87 is received, and Table 2 is queried to obtain the weight of neuron 3 as W 87,3 = 32, and an axon event with an axon identifier of 115 is received, and Table 2 is queried to obtain the weight of neuron 3 as W 115,3=18, the axon event with the axon identifier 121 is received, and the weight of the neuron 3 is obtained from the table 2 as W 121,3 =7. In combination with the table 1, it can be known that the axon events with the axon identifiers 0 and 2 are stored in the buffer 1, the axon events with the axon identifiers 60 and 87 are stored in the buffer 2, and the axon events with the axon identifiers 115 and 121 are stored in the buffer 3.
[0097] For the neuron 3, the axon events with the axon identifiers 0, 2, 60, 87, 115 and 121 are received, and six first operation results corresponding to the six axon events are calculated according to the weights W 0,3 =10, W 2,3 =1, W 60,3 =5, W 87,3 =32, W 115,3 =18, W 121,3 =7. In combination with the table 1, it can be known that the axon events with the axon identifiers 0 and 2 are stored in the buffer 1, the axon events with the axon identifiers 60 and 87 are stored in the buffer 2, and the axon events with the axon identifiers 115 and 121 are stored in the buffer 3.
[0098] The operations of the neuron 3 on different axon events are independent of each other, and can be processed in parallel, and finally the operation results of the axon events are summarized and added, so that the operation time can be greatly reduced and the operation speed can be improved compared with the traditional sequential operation.
[0099] It should be noted that, for any neuron, the operation of the input current is performed according to the received axon event, and when no axon event related to the neuron is received, the operation of the input current is not required.
[0100] In the many-core system, multiple cores can work jointly, and each core can independently run program instructions, utilize the parallel computing capability to speed up the program running speed, and provide multi-task processing capability. The data processing method of the embodiment of the disclosure is described below by taking a many-core system including two cores, core A and core B, as an example. Figure 5 The data processing method of the embodiment of the disclosure is described below by taking a many-core system including two cores, core A and core B, as an example. Figure 5The core B receives the axon event and the weight from the core A, and the neuron of the core B performs operation according to the weight corresponding to each axon event to obtain a first operation result corresponding to each axon event, and accumulates each first operation result to obtain an operation result of the input current of the neuron.
[0101] By setting a plurality of buffers, each buffer respectively and synchronously sends the axon event and the weight, and correspondingly, different neurons can synchronously perform operation on the same axon event, and the same neuron can synchronously perform operation on different axon events, so that the data processing speed of the many-core system can be improved.
[0102] In some embodiments, each neuron of the current core can have a refractory period time greater than or equal to a routing transmission delay threshold of the many-core system globally, so that the time interval between two neuron sending can be long enough to effectively solve the problem caused by the routing delay of the many-core system. The routing transmission delay threshold refers to the longest routing delay in the global system of the many-core system, that is, the longest time for a routing packet to be transmitted from a source core to a destination core.
[0103] The refractory period refers to a period of time after a neuron is stimulated by a pulse and reacts (sending), during which the neuron will not react even if it receives a pulse again. This period is generally referred to as the refractory period of the neuron.
[0104] In a second aspect, the embodiments of the present disclosure provide a core, which refers to Figure 6 , and the core comprises:
[0105] one or more processing units 101;
[0106] a storage unit 102, which stores one or more programs, and when the one or more programs are executed by the one or more processing units, the one or more processing units implement the data processing method of the first aspect of the embodiments of the present disclosure.
[0107] The processing unit 101 is a device with data processing capability, including but not limited to an operator and the like; the storage unit 102 is a device with data storage capability, including but not limited to a random access memory (RAM), a read-only memory (ROM), an electrically erasable programmable read-only memory (EEPROM), and a flash memory (FLASH).
[0108] In a third aspect, the embodiments of the present disclosure provide a single-core system, which comprises the core as described above.
[0109] Fourthly, this disclosure provides a many-core system, which includes at least two cores, at least one of which is the core described above, and the data packets received by the core are sent by other cores in the many-core system.
[0110] Fifthly, embodiments of this disclosure provide an electronic device, referring to... Figure 7 The electronic device includes:
[0111] Multiple cores 201; and
[0112] The on-chip network 202 is configured to interact with data between the plurality of cores 201 and external data;
[0113] One or more cores 201 store one or more instructions, which are executed by one or more cores 201 to enable one or more cores 201 to perform the data processing method described in the first aspect of the present disclosure.
[0114] Sixthly, refer to Figure 8 This disclosure provides a computer-readable medium having a computer program stored thereon, which, when executed by a processor, implements the data processing method described in the first aspect of this disclosure.
[0115] Those of ordinary skill in the art will realize and understand that all or some of the steps in the methods disclosed above and the functional modules / units in the systems and devices can be implemented as software, firmware, hardware, and appropriate combinations thereof. In hardware implementation, the division between the functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component can have multiple functions, or one function or step can be performed by several physical components in cooperation. Some or all of the physical components can be implemented as software executed by a processor, such as a central processing unit, a digital signal processor, or a microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit. Such software can be distributed on computer-readable media, which can include computer storage media (or non-transitory media) and communication media (or transitory media). As is well known to those of ordinary skill in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can be accessed by a computer. Furthermore, it is common technical knowledge that communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media.
[0116] Example embodiments have been disclosed herein and, although the use of specific terms is expressly used herein, they are intended in a generic sense only and are not intended to limit the scope of the present disclosure. In some instances, it will be apparent to those skilled in the art that features, characteristics or / and elements described in connection with a particular embodiment can be used in conjunction with other embodiments unless otherwise explicitly stated. As such, those skilled in the art will appreciate that various changes can be made in form and detail without departing from the scope of the disclosure as set forth in the appended claims.
Claims
1. A data processing method applied to a core, the core including at least two caches, the method comprising: In response to receiving a data packet, an axon event in the data packet is obtained, the axon event including at least an axon identifier; According to the first mapping relationship between the preset cache identifier and the axon identifier, the axon event is stored in the cache corresponding to the axon identifier, wherein the first mapping relationship is stored in the core; The step of storing the axon event in the cache corresponding to the axon identifier according to the first mapping relationship between the preset cache identifier and the axon identifier includes: Based on the first mapping relationship, the cache identifier corresponding to the axon identifier of the axon event is determined, and the axon event is stored in the cache corresponding to the cache identifier.
2. The data processing method of claim 1, wherein, The method further includes: determining the neuron identifier and weight corresponding to the axon event; After storing the axon event in the cache corresponding to the axon identifier, the method further includes: For each neuron, in response to the received axonal event and weights, computation is performed based on the weights.
3. The data processing method of claim 2, wherein, The data packet also includes a second mapping relationship between axon identifiers, neuron identifiers, and weights. Determining the neuron identifier and weights corresponding to the axon event includes: Obtain the second mapping relationship in the data packet, and determine the neuron identifier and weight corresponding to the axon event based on the second mapping relationship.
4. The data processing method of claim 2, wherein, Determining the neuron identifier and weight corresponding to the axon event includes: Based on the preset second mapping relationship between axon identifiers, neuron identifiers, and weights, the neuron identifier and weight corresponding to the axon event are determined.
5. The data processing method of claim 2, wherein, For each neuron, in response to receiving an axonal event and a weight, the computation based on the weight includes: For each neuron, in response to receiving multiple axon events, the first operation result corresponding to each axon event is calculated according to the weight corresponding to each axon event. The first calculation results corresponding to each axon event are accumulated to obtain the calculation result of the neuron's input current.
6. The data processing method of claim 5, wherein, The summation of the first calculation results corresponding to each of the axon events to obtain the calculation result of the neuron input current includes: For each cache, the first operation result corresponding to the axon event stored in the cache is accumulated to obtain the second operation result corresponding to each cache; The results of each of the second operations are summed to obtain the result of the neuron's input current.
7. The data processing method according to claim 2, wherein, For each neuron, in response to receiving an axonal event and a weight, the computation based on the weight includes: For each neuron, in response to receiving an axonal event and weights and firing a pulse, calculations are performed based on the weights to obtain the calculation result of the neuron's input current. The calculation result of the neuron's input current is used to determine the current membrane potential. In response to the current membrane potential being greater than a preset membrane potential threshold, an emission pulse and a data packet are sent, the data packet including at least the axon event.
8. A core, said core comprising: One or more processing units; A storage unit storing one or more programs, which, when executed by the one or more processing units, cause the one or more processing units to implement the data processing method according to any one of claims 1 to 7.
9. A many-core system comprising at least two cores, at least one of the cores being the core as described in claim 8, wherein data packets received by the core are sent by other cores in the many-core system.
10. An electronic device, comprising: Multiple cores; as well as The on-chip network is configured to interact with data between the multiple cores and with external data; One or more of the cores store one or more instructions, which are executed by one or more of the cores to enable the one or more cores to perform the data processing method according to any one of claims 1 to 7.
11. A computer-readable medium having a computer program stored thereon, which, when executed by a processor, implements the data processing method according to any one of claims 1 to 7.