Display panel and array substrate

Abstract

The display panel and the array substrate are provided. The array substrate comprises: a pixel circuit; a data signal line arranged on one side of the substrate and connected with the pixel circuit; a display driving circuit arranged on one side of the substrate and located in the peripheral area, the display driving circuit being provided with m output channels, the output channels of the display driving circuit being connected with the data signal line; and a selection circuit arranged on one side of the substrate and located in the peripheral area, the selection circuit being provided with a control end, n first input ends and a first output end, n being greater than or equal to 2 and less than m; the n first input ends of the selection circuit are correspondingly connected with n output channels in the m output channels; and the selection circuit is used for connecting one first input end with the first output end under the control of the control end. The display panel and the array substrate can improve the detection effect.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a display panel and array substrate. Background Technology

[0002] With the advancement of technology, display panels have attracted increasing attention. However, existing display panels still need improvement. Summary of the Invention

[0003] The purpose of this disclosure is to provide a display panel and array substrate that can improve detection performance.

[0004] According to one aspect of this disclosure, an array substrate is provided, the array substrate including a display area and a peripheral area surrounding the display area, the array substrate comprising:

[0005] Substrate;

[0006] A pixel circuit is disposed on one side of the substrate and located in the display area;

[0007] A data signal line is located on one side of the substrate and connected to the pixel circuit.

[0008] The display driving circuit is disposed on one side of the substrate and located in the peripheral area. The display driving circuit has m output channels, and the output channels of the display driving circuit are connected to the data signal lines.

[0009] A selection circuit is disposed on one side of the substrate and located in the peripheral area. The selection circuit has a control terminal, n first input terminals and a first output terminal, where n is greater than or equal to 2 and less than m. The n first input terminals of the selection circuit are connected to n of the m output channels. The selection circuit is used to select one first input terminal from the n first input terminals and connect it to the first output terminal under the control of the control terminal.

[0010] Furthermore, the array substrate further includes:

[0011] The first switching unit is provided between the output channel and the first input terminal of the selection circuit;

[0012] A control circuit, connected to the first switching unit, is used to control the first switching unit to be turned on or off.

[0013] Furthermore, the m output channels constitute k channel groups, and each channel group includes n output channels. In the k channel groups, at least two of the n output channels are connected to the n first input terminals of the selection circuit.

[0014] The n first switch units connected between one of the channel groups and the selection circuit constitute a switch group, and the control circuit is used to control all the first switch units in one of the multiple switch groups to be turned on.

[0015] Furthermore, the control circuit includes a second input terminal and a plurality of second output terminals, one second output terminal corresponds to one of the switch groups, and different second output terminals correspond to different switch groups, and one second output terminal is connected to a plurality of first switch units in the corresponding switch group; the second output terminals are provided with digital numbers, and different second output terminals have different digital numbers;

[0016] The second input terminal is used to receive a pulse signal. The control circuit can respond to the pulse signal and select one of the second output terminals from a plurality of second output terminals as the target output terminal, and turn on a plurality of first switch units in the switch group corresponding to the target output terminal; wherein, the digital number of the target output terminal is mapped to the number of pulses of the pulse signal.

[0017] Furthermore, the digital number of the target output terminal is the same as the number of pulses.

[0018] Furthermore, the control circuit is a latch.

[0019] Furthermore, the first switching unit is a transistor, and the control circuit is connected to the gate of the transistor.

[0020] Furthermore, the selection circuit includes:

[0021] n second switch units are respectively located between n first input terminals and first output terminals;

[0022] The selection circuit is connected to n second switching units and is used to control one of the n second switching units to turn on.

[0023] Furthermore, the control terminal is located in the gating circuit, and the n second switch units are assigned numerical numbers, with different numerical numbers for different second switch units; the control terminal is used to receive binary numbers, and the gating circuit can convert the binary numbers into decimal numbers, and can select one of the n second switch units as the target switch based on the decimal number, and turn on the target switch; the numerical number of the target switch is mapped to the decimal number.

[0024] Furthermore, the numerical designation of the target switch is the same as the decimal number.

[0025] Furthermore, the second switching unit is a transistor.

[0026] Furthermore, there are two selection circuits. Among the k channel groups, n output channels in some channel groups are connected to n first input terminals of one selection circuit, and n output channels in the remaining channel groups in the k channel groups are connected to n first input terminals of the other selection circuit.

[0027] Furthermore, the display driving circuit, the selection circuit, and the control circuit are integrated on a single chip.

[0028] Furthermore, the array substrate further includes:

[0029] A circuit board is disposed on the substrate and located in the peripheral area. The circuit board is provided with a test pad, and the first output terminal of the selection circuit is connected to the test pad.

[0030] According to one aspect of this disclosure, a display panel is provided, including the array substrate.

[0031] In the display panel and array substrate disclosed herein, during the detection process, the n first input terminals of the selection circuit are correspondingly connected to the n output channels among the m output channels. The selection circuit is used to select one first input terminal from the n first input terminals and connect it to the first output terminal under the control of the control terminal. This allows any one of the n output channels to be connected to the first output terminal. By performing signal detection on the first output terminal, signal detection can be performed on any one of the n output channels, thereby improving the detection effect. Attached Figure Description

[0032] Figure 1 This is a schematic diagram of an array substrate according to an embodiment of the present disclosure.

[0033] Figure 2 This is a schematic diagram of pixel distribution according to an embodiment of the present disclosure.

[0034] Figure 3 This is a schematic diagram of the cross-sectional distribution of the array substrate according to an embodiment of the present disclosure.

[0035] Figure 4 This is a block diagram of an array substrate according to an embodiment of the present disclosure.

[0036] Figure 5 and Figure 6 Timing diagram of the shift latch in the embodiments of this disclosure.

[0037] Explanation of reference numerals in the attached figures: 1. Output channel; 2. First switching unit; 3. Control circuit; 301. Second input terminal; 302. Second output terminal; 4. Selection circuit; 41. Second switching unit; 42. Gating circuit; 43. First input terminal; 44. First output terminal; 5. Channel group; 6. Switch group; 7. Pixel; 701. Subpixel; 8. Data signal line; 9. Pixel row; 10. Pixel circuit; 11. Pixel column; 12. Chip; 13. Circuit board; 14. Substrate; 15. Active layer; 16. Gate insulating layer; 17. Gate; 18. First source / drain; 19. Second source / drain; 20. First insulating layer; 21. Pixel electrode; 22. Second insulating layer; 23. Common electrode; A0. Display area; A1. Peripheral area; T2. Switching transistor. Detailed Implementation

[0038] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this disclosure. Rather, they are merely examples of apparatuses consistent with some aspects of this disclosure as detailed in the appended claims.

[0039] The terminology used in this disclosure is for the purpose of describing particular embodiments only and is not intended to limit the disclosure. Unless otherwise defined, the technical or scientific terms used in this disclosure should be understood in their ordinary sense by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure and the claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “a” or “one,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. “A plurality” or “several” indicates two or more. Unless otherwise stated, the terms “front,” “rear,” “lower,” and / or “upper,” and similar terms are for ease of description only and are not limited to a location or spatial orientation. The terms “comprising,” “including,” and similar terms mean that the elements or objects preceding “comprising,” encompass the elements or objects listed following “comprising,” and their equivalents, and do not exclude other elements or objects. The terms “connected,” “linked,” and similar terms are not limited to physical or mechanical connections and can include electrical connections, whether direct or indirect. The singular forms “a,” “the,” and “the” used in this disclosure and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any or all possible combinations of one or more of the associated listed items.

[0040] This disclosure provides an array substrate. For example... Figure 1 and Figure 2 As shown, the array substrate may include a display area A0 and a peripheral area A1 surrounding the display area A0. The display area A0 may include a plurality of pixels 7 (see...). Figure 2 A pixel 7 may include multiple sub-pixels 701. Specifically, a pixel 7 may include three sub-pixels 701, such as a red sub-pixel, a green sub-pixel, and a blue sub-pixel. The three sub-pixels 701 in a pixel 7 may be distributed sequentially in a first direction (the X direction in the figure), or sequentially in a second direction (the Y direction in the figure), but this disclosure does not specifically limit this. The first direction may be perpendicular or substantially perpendicular to the second direction. Multiple pixels 7 may be arranged in an array. Among the arrayed multiple pixels 7, multiple pixels 7 distributed along the second direction may form a pixel column 11, and multiple pixels 7 distributed along the first direction may form a pixel row 9.

[0041] like Figure 2 , Figure 3 as well as Figure 4 As shown, the array substrate may include a substrate 14, a pixel circuit 10, a display driving circuit, a data signal line 8, and a selection circuit 4, wherein:

[0042] The pixel circuit 10 is disposed on one side of the substrate 14 and located in the display area A0. The data signal line 8 is disposed on one side of the substrate 14 and connected to the pixel circuit 10. The display driving circuit is disposed on one side of the substrate 14 and located in the peripheral area A1. The display driving circuit has m output channels 1 (see...). Figure 4 The output channel 1 of the display driving circuit is connected to the data signal line 8. The selection circuit 4 is located on one side of the substrate 14 and in the peripheral area A1. The selection circuit 4 has a control terminal and n first input terminals 43 (see...). Figure 4 ) and a first output terminal 44 (see Figure 4 ), where n is greater than or equal to 2 and less than m; the n first input terminals 43 of the selection circuit 4 are connected to the n output channels 1 of the m output channels 1 respectively. The selection circuit 4 is used to select one first input terminal 43 from the n first input terminals 43 and connect it to the first output terminal 44 under the control of the control terminal.

[0043] In the array substrate of this embodiment, during the detection process, the n first input terminals 43 of the selection circuit 4 are correspondingly connected to the n output channels 1 of the m output channels 1. The selection circuit 4 is used to select one first input terminal 43 from the n first input terminals 43 and connect it to the first output terminal 44 under the control of the control terminal. This allows any one of the n output channels 1 to be connected to the first output terminal 44. By performing signal detection on the first output terminal 44, signal detection can be performed on any one of the n output channels 1, thereby improving the detection effect.

[0044] The array substrate of the present disclosure will now be described in detail as follows:

[0045] like Figure 3 As shown, the substrate 14 can be a rigid substrate. This rigid substrate can be a glass substrate or a PMMA (Polymethyl methacrylate) substrate, etc. Of course, the substrate 14 can also be a flexible substrate.

[0046] like Figure 1 As shown, the pixel circuit 10 is disposed on one side of the substrate 14. The pixel circuit 10 may be located in the display area A0, but this disclosure does not limit this. There may be multiple pixel circuits 10, each corresponding one-to-one with the aforementioned multiple sub-pixels 701. The multiple pixel circuits 10 can be arranged in an array. Among the arrayed multiple pixel circuits 10, those distributed along the second direction can form a circuit column, and those distributed along the first direction can form a circuit row.

[0047] like Figure 1 As shown, the array substrate of this disclosure may further include data signal lines 8. These data signal lines 8 may be disposed on one side of the substrate 14 and electrically connected to the pixel circuits 10. Multiple pixel circuits 10 in a circuit array may be connected to the same data signal line 8. Furthermore, the number of data signal lines 8 may be multiple, and these multiple data signal lines 8 may correspond one-to-one with multiple circuit arrays. The data signal lines 8 and circuit arrays may be arranged alternately in a first direction, and the multiple pixel circuits 10 in each circuit array are electrically connected to the corresponding data signal lines 8.

[0048] Specifically, such as Figure 3As shown, the pixel circuit 10 may include a switching transistor T2. The switching transistor T2 may be a thin-film transistor. The switching transistor T2 may include a gate 17, a first source-drain 18, and a second source-drain 19. One of the first source-drain 18 and the second source-drain 19 is the source, and the other is the drain. The gate 17 of the switching transistor T2 may be disposed on one side of the substrate 14. The first source-drain 18 and the second source-drain 19 of the switching transistor T2 may be disposed in the same layer and located on the side of the gate 17 of the switching transistor T2 that faces away from the substrate 14. The switching transistor T2 may also include an active layer 15 and a gate insulating layer 16. Taking the switching transistor T2 as a bottom-gate thin-film transistor as an example, the active layer 15 of the switching transistor T2 can be disposed on the side of the gate 17 of the switching transistor T2 facing away from the substrate 14, the gate insulating layer 16 can be disposed on the side of the active layer 15 of the switching transistor T2 facing away from the substrate 14, and the first source drain 18 and the second source drain 19 of the switching transistor T2 can be disposed on the side of the active layer 15 facing away from the substrate 14.

[0049] like Figure 3 As shown, the array substrate of this disclosure may further include a first insulating layer 20, a pixel electrode 21, a second insulating layer 22, and a common electrode 23. The pixel electrode 21 may be located in the display area A0. The common electrode 23 may be located in the display area A0. The first insulating layer 20 may be disposed on the side of the second source / drain electrode 19 of the switching transistor T2 facing away from the substrate 14. The pixel electrode 21 and the common electrode 23 may be located on the side of the first insulating layer 20 facing away from the substrate 14. Specifically, the common electrode 23 may be disposed on the side of the pixel electrode 21 facing away from the substrate 14, and the second insulating layer 22 may be disposed between the common electrode 23 and the pixel electrode 21. The pixel electrode 21 is electrically connected to the second source / drain electrode 19 of the switching transistor T2. In other embodiments, the common electrode 23 may also be disposed on the side of the pixel electrode 21 facing the substrate 14. Furthermore, a horizontal electric field, i.e., an electric field in ADS (Advanced Super Dimension Switch) mode or an electric field in IPS (In-Plane Switching) mode, may be generated between the common electrode 23 and the pixel electrode 21.

[0050] The aforementioned display driving circuit is disposed on one side of the substrate 14 and located in the peripheral region A1. For example... Figure 4As shown, the display driving circuit has m output channels 1. These m output channels 1 are used to output data signals. Each output channel 1 is electrically connected to the aforementioned data signal line 8, and the data signal output by the output channel 1 can reach the pixel circuit 10 through the aforementioned data signal line 8. m can be an even number, such as 2568. In other embodiments of this disclosure, m can also be an odd number. The m output channels 1 constitute k channel groups 5, and one channel group 5 includes n output channels 1. For example, k can be 2^14, and n can be 12.

[0051] like Figure 4 As shown, the selection circuit 4 is disposed on one side of the substrate 14 and located in the peripheral region A1. The selection circuit 4 has a control terminal, n first input terminals 43, and a first output terminal 44, where n is greater than or equal to 2 and less than m. The n first input terminals 43 of the selection circuit 4 are connected to n output channels 1 in one of the m output channels 1. Furthermore, at least two of the k channel groups 5 have n output channels 1 connected to the n first input terminals 43 of the selection circuit 4, meaning that at least two of the channel groups 5 have n output channels 1 connected one-to-one to the n first input terminals 43 of the selection circuit 4. Taking two selection circuits 4 as an example, n output channels 1 in a portion of the k channel groups 5 are connected to the n first input terminals 43 of one selection circuit 4, and the remaining n output channels 1 in the k channel groups 5 are connected to the n first input terminals 43 of the other selection circuit 4. With this configuration, any one of the m output channels 1 can be selected for detection using the two selection circuits 4. Taking an even number of k as an example, n output channels 1 in half of the k channel groups 5 are connected to the n first input terminals 43 of one selection circuit 4, and n output channels 1 in the other half of the channel groups 5 are connected to the n first input terminals 43 of the other selection circuit 4. The first output terminal 44 of this selection circuit 4 can be a test terminal; signal detection is performed on the first output terminal 44 to detect the signal of the output channel 1.

[0052] The selection circuit 4 is used to select one of the n first input terminals 43 to connect to the first output terminal 44 under the control of the control terminal. In one embodiment, as shown... Figure 4As shown, the selection circuit 4 may include a gating circuit 42 and n second switching units 41. The n second switching units 41 are correspondingly located between the n first input terminals 43 and the first output terminal 44; that is, each first input terminal 43 is connected to the first output terminal 44 through a second switching unit 41. The gating circuit 42 is connected to the n second switching units 41 and is used to control one of the n second switching units 41 to be turned on, so that one of the n first input terminals 43 is connected to the first output terminal 44. The control terminal of the selection circuit 4 is located in the gating circuit 42. The n second switching units 41 are numbered, and different second switching units 41 have different numbered numbers. These numbered numbers can be natural numbers, but this disclosure does not limit this. The control terminal is used to receive binary numbers. The gating circuit 42 can convert the binary numbers into decimal numbers and can select one second switching unit 41 from the n second switching units 41 as the target switch based on the decimal number, and turn on the target switch. The numerical designation of the target switch is mapped to a decimal number. Furthermore, the numerical designation of the target switch is identical to the decimal number. The second switching unit can be a transistor, with one of its source and drain connected to the first input terminal 43, the other connected to the first output terminal 44, and its gate 17 connected to the gating circuit 42.

[0053] Specifically, taking n=12 as an example, the numbers of the n second switch units 41 are 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, and 11 respectively. This control terminal has four interfaces, D0, D1, D2, and D3, for receiving four-bit binary numbers. The correspondence between these four-bit binary numbers and their corresponding numbers is shown in Table 1 below.

[0054] Table 1

[0055] D3 D2 D1 D0 binary number Number 0 0 0 0 0000 0 0 0 0 1 0001 1 0 0 1 0 0010 2 0 0 1 1 0011 3 0 1 0 0 0100 4 0 1 0 1 0101 5 0 1 1 0 0110 6 0 1 1 1 0111 7 1 0 0 0 1000 8 1 0 0 1 1001 9 1 0 1 0 1010 10 1 0 1 1 1011 11

[0056] like Figure 4As shown, the array substrate of this disclosure may further include a first switching unit 2. A first switching unit 2 is provided between the output channel 1 of the correspondingly connected display driving circuit and the first input terminal 43 of the selection circuit 4. The control circuit 3 is connected to the first switching unit 2 and is used to control the first switching unit 2 to be turned on or off. The first switching unit 2 can be a transistor, with its first electrode connected to the output channel 1 of the display driving circuit, its second electrode connected to the first input terminal 43 of the selection circuit 4, and its gate 17 connected to the control circuit 3. The signal output from the output channel 1 of the display driving circuit can be transmitted to the first input terminal 43 of the selection circuit 4 through the first switching unit 2. Taking m output channels 1 forming k channel groups 5 as an example, n first switching units 2 connected between a channel group 5 and the selection circuit 4 form a switch group 6. Since m output channels 1 form k channel groups 5, the array substrate of this disclosure may also include k switch groups 6. The control circuit 3 is used to control all the first switching units 2 in one of the k switch groups 6 to be turned on. As can be seen from the above, this disclosure divides the output channel 1 into multiple channel groups 5. One channel group 5 can be selected through the first switching unit 2 and the control circuit 3. Any output channel 1 can be selected from the channel group 5 through the selection circuit 4 mentioned above, thereby realizing any number of output channels 1, which greatly improves the efficiency of testing and debugging.

[0057] For example, such as Figure 4 As shown, the control circuit 3 may include a second input terminal 301 and multiple second output terminals 302. One second output terminal 302 corresponds to one switch group 6, and different second output terminals 302 correspond to different switch groups 6. Furthermore, one second output terminal 302 is connected to multiple first switch units 2 in the corresponding switch group 6. The number of control circuits 3 can be one or two. Taking an array substrate comprising k (k is an even number) switch groups 6 and two control circuits 3 as an example, each control circuit 3 may include k / 2 second output terminals 302. The k / 2 second output terminals 302 of one control circuit 3 correspond one-to-one with k / 2 switch groups 6, and the k / 2 second output terminals 302 of the other control circuit 3 correspond one-to-one with the remaining k / 2 switch groups 6. In addition, the second output terminal 302 is connected to the gate 17 of all the first switch units 2 in the corresponding switch group 6.

[0058] The aforementioned second output terminal 302 is numbered, and different second output terminals 302 have different numbered numbers. The numbering of the second output terminal 302 can be a natural number, but this disclosure does not limit this. Taking a control circuit 3 with k / 2 second output terminals 302 corresponding one-to-one with k / 2 switch groups 6 as an example, the numbering of the k / 2 second output terminals 302 can be 1, 2, 3, 4, 5…(k / 2-1), k / 2. The second input terminal 301 of the control circuit 3 is used to receive pulse signals. The control circuit 3 can respond to the pulse signals and select one second output terminal 302 from the k / 2 second output terminals 302 as the target output terminal, and turn on multiple first switch units 2 in the switch group 6 corresponding to the target output terminal; wherein, the numbering of the target output terminal is mapped to the number of pulses in the pulse signal. Further, the numbering of the target output terminal is the same as the number of pulses.

[0059] like Figure 4 As shown, the control circuit 3 described above can be a latch. Further, this latch can be a shift latch. This shift latch can have a reset signal terminal TRST, an enable signal terminal TDI, and a second input terminal 301. The reset signal terminal TRST can receive a hardware reset signal, and the enable signal terminal TDI can receive an enable signal. During operation, the shift latch can respond to the enable signal and receive a pulse signal through the second input terminal 301. The shift register can calculate and latch the number of pulses in the pulse signal, and then pull up the second output terminal 302 with the corresponding numerical number according to the number of pulses (taking an N-type transistor as an example for the first switching unit 2). Wherein, in Figure 5 In the middle, the number of pulses of the pulse signal received by the second input terminal 301 is one; in Figure 6 In the second input terminal 301, the number of pulses of the pulse signal received is two.

[0060] like Figure 1 As shown, the aforementioned display driving circuit, selection circuit 4, and control circuit 3 can be integrated onto a single chip 12. Furthermore, the aforementioned display driving circuit, selection circuit 4, first switching unit 2, and control circuit 3 can be integrated onto a single chip 12. In addition, the array substrate of this disclosure also includes a circuit board 13. The circuit board 13 can be disposed on the substrate 14 and located in the peripheral area A1. The circuit board 13 can be disposed on the side of the chip 12 away from the display area A0. The circuit board 13 is provided with a test pad, and the first output terminal 44 of the selection circuit 4 is connected to the test pad. With this configuration, by detecting the signal from the test pad, any output channel 1 of the display driving circuit can be detected.

[0061] This disclosure also provides a display panel. The display panel may include the array substrate of any of the above embodiments. Alternatively, the display panel may further include a counter substrate and a liquid crystal layer. The counter substrate is disposed opposite to the array substrate, and the liquid crystal layer may be disposed between the array substrate and the counter substrate.

[0062] The display panel and array substrate provided in this disclosure belong to the same inventive concept. The descriptions of related details and beneficial effects can be found in each other and will not be repeated here.

[0063] The above are merely preferred embodiments of this disclosure and are not intended to limit this disclosure in any way. Although this disclosure has been disclosed above with reference to preferred embodiments, it is not intended to limit this disclosure. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the technical solution of this disclosure. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this disclosure without departing from the content of the technical solution of this disclosure shall still fall within the scope of the technical solution of this disclosure.

Claims

1. An array substrate, characterized in that, The array substrate includes a display area and a peripheral area surrounding the display area, and the array substrate includes: Substrate; A pixel circuit is disposed on one side of the substrate and located in the display area; A data signal line is located on one side of the substrate and connected to the pixel circuit. The display driving circuit is disposed on one side of the substrate and located in the peripheral area. The display driving circuit has m output channels, and the output channels of the display driving circuit are connected to the data signal lines. A selection circuit is disposed on one side of the substrate and located in the peripheral area. The selection circuit has a control terminal, n first input terminals and a first output terminal, where n is greater than or equal to 2 and less than m. The n first input terminals of the selection circuit are connected to n of the m output channels. The selection circuit is used to select one first input terminal from the n first input terminals and connect it to the first output terminal under the control of the control terminal. The array substrate further includes: The first switching unit is provided between the output channel and the first input terminal of the selection circuit; A control circuit, connected to the first switching unit, is used to control the first switching unit to be turned on or off; Among them, m output channels constitute k channel groups, and one channel group includes n output channels. At least two of the k channel groups have n output channels that are connected to the n first input terminals of the selection circuit. The n first switch units connected between one of the channel groups and the selection circuit constitute a switch group, and the control circuit is used to control all the first switch units in one of the multiple switch groups to be turned on. The control circuit includes a second input terminal and multiple second output terminals. One second output terminal corresponds to one of the switch groups, and different second output terminals correspond to different switch groups. One second output terminal is connected to multiple first switch units in the corresponding switch group. The second output terminals are provided with digital numbers, and different second output terminals have different digital numbers. The second input terminal is used to receive a pulse signal. The control circuit can respond to the pulse signal and select one of the second output terminals from a plurality of second output terminals as the target output terminal, and turn on a plurality of first switch units in the switch group corresponding to the target output terminal; wherein, the digital number of the target output terminal is mapped to the number of pulses of the pulse signal.

2. The array substrate according to claim 1, characterized in that, The numerical designation of the target output terminal is the same as the number of pulses.

3. The array substrate according to claim 1, characterized in that, The control circuit is a latch.

4. The array substrate according to claim 1, characterized in that, The first switching unit is a transistor, and the control circuit is connected to the gate of the transistor.

5. The array substrate according to claim 1, characterized in that, The selection circuit includes: n second switch units are respectively located between n first input terminals and first output terminals; The selection circuit is connected to n second switching units and is used to control one of the n second switching units to turn on.

6. The array substrate according to claim 5, characterized in that, The control terminal is located in the selection circuit. The n second switch units are numbered, and the numbering of different second switch units is different. The control terminal is used to receive binary numbers. The selection circuit can convert the binary numbers into decimal numbers and select one of the n second switch units as the target switch according to the decimal number, and turn on the target switch. The numbering of the target switch is mapped to the decimal number.

7. The array substrate according to claim 6, characterized in that, The numerical designation of the target switch is the same as the decimal number.

8. The array substrate according to claim 5, characterized in that, The second switching unit is a transistor.

9. The array substrate according to claim 1, characterized in that, The number of selection circuits is two. Among the k channel groups, n output channels in some channel groups are connected to n first input terminals of one selection circuit, and n output channels in the remaining channel groups in the k channel groups are connected to n first input terminals of the other selection circuit.

10. The array substrate according to claim 1, characterized in that, The display driver circuit, the selection circuit, and the control circuit are integrated on a single chip.

11. The array substrate according to claim 1, characterized in that, The array substrate further includes: A circuit board is disposed on the substrate and located in the peripheral area. The circuit board is provided with a test pad, and the first output terminal of the selection circuit is connected to the test pad.

12. A display panel, characterized in that, Includes the array substrate as described in any one of claims 1-11.

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