Pixel driving circuit, driving circuit and driving method

Abstract

The application discloses a pixel driving circuit, a driving circuit and a driving method of a display panel. In the data line direction, a plurality of pixels are divided into a plurality of pixel areas. In the scanning line direction, each pixel area is divided into a plurality of pixel sub-areas. Each pixel sub-area includes four pixels arranged in 2*2. Each pixel includes three sub-pixels of different colors. In the two rows of scanning lines between the two rows of pixels, the two sub-pixels on the same data line are of the same color. The application provides a novel pixel driving circuit. In the frequency doubling display mode, the two rows of scanning lines are opened at the same time, and the two rows of pixel data lines driven by the two rows of scanning lines control the same color pixels and display the same gray scale. In the frequency doubling mode, the two different color pixels cannot display the same gray scale, and a monochrome image cannot be displayed, so that the display panel cannot normally display colors. Meanwhile, the number of chip on film (COF) is saved, and the preparation cost of the display panel is reduced.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a pixel driving circuit, driving circuit and driving method. Background Technology

[0002] Liquid Crystal Displays (LCDs) have many advantages such as thinness, energy saving, and no radiation, and have been widely used. In the development of large-size and high-refresh-rate display panels, Dual Line Gate (DLG) technology has attracted attention. DLG technology is also known as frequency doubling refresh technology. Its principle is that the panel's GDL circuit simultaneously opens two rows of scan lines, and the two rows input the same scan signal. In this mode, it is equivalent to reducing the number of pixels in the vertical display by half. Without changing the original hardware and chip computing power, the refresh rate can be doubled.

[0003] In the LCD display industry, DRD (Double Row Driving) design is increasingly used because it can save on the number of chip-on-film (COF) films and reduce costs. However, in DRD display panels, adjacent rows are connected to different color pixels by the same data line. In DLG mode, two different color pixels display the same grayscale, which cannot display RGB monochrome images. As a result, the display panel cannot display colors normally. How to use DLG technology under the DRD pixel architecture has become an urgent problem to be solved. Summary of the Invention

[0004] The purpose of this application is to provide a pixel driving circuit, driving circuit, and driving method, which aims to solve the problem that RGB monochrome images cannot be displayed using DLG technology under the existing DRD pixel architecture.

[0005] This application discloses a pixel driving circuit, which includes multiple scan lines and multiple data lines, and multiple pixels driven by the multiple scan lines and multiple data lines respectively. Along the direction of the data lines, the multiple pixels are divided into multiple pixel regions. Along the direction of the scan lines, each pixel region is divided into multiple pixel sub-regions. Each pixel sub-region includes four pixels arranged in a 2*2 pattern. Each pixel includes three sub-pixels of different colors. The four pixels are respectively a first pixel, a second pixel, a third pixel, and a fourth pixel.

[0006] In the first pixel, one sub-pixel connects to the (n-1)th scan line, and the other two sub-pixels connect to the nth scan line; in the second pixel, one sub-pixel connects to the nth scan line, and the other two sub-pixels connect to the (n-1)th scan line; the three sub-pixels connected by the (n-1)th scan line are of different colors, and the three sub-pixels connected by the nth scan line are also of different colors.

[0007] One sub-pixel of the third pixel is connected to the (n+2)th scan line, and the other two sub-pixels are connected to the (n+1)th scan line; one sub-pixel of the fourth pixel is connected to the (n+1)th scan line, and the other two sub-pixels are connected to the (n+2)th scan line; the three sub-pixels connected by the (n+1)th scan line are of different colors, and the three sub-pixels connected by the (n+2)th scan line are also of different colors.

[0008] Where n is a natural number greater than or equal to 2, when the pixel area is displayed with double frequency, the nth scan line and the (n+1)th scan line receive the same scan signal, the sub-pixels of the same color in the first pixel and the third pixel receive the same data signal, and the sub-pixels of the same color in the second pixel and the fourth pixel receive the same data signal.

[0009] Optionally, two adjacent pixel regions are designated as a first pixel region and a second pixel region, and the first pixel region and the second pixel region are symmetrical about the center line between the first pixel region and the second pixel region. The scan lines corresponding to the first pixel region are the (n-1)th scan line, the nth scan line, the (n+1)th scan line and the (n+2)th scan line, and the scan lines corresponding to the second pixel region are the (n+3)th scan line, the (n+4)th scan line, the (n+5)th scan line and the (n+6)th scan line.

[0010] When the pixel area is displayed with frequency multiplication, the nth scan line and the (n+1)th scan line receive the same scan signal, the (n+2)th scan line and the (n+3)th scan line receive the same scan signal, the (n+4)th scan line and the (n+5)th scan line receive the same scan signal, and the sub-pixels that are charged corresponding to the nth scan line and the (n+1)th scan line have different colors than the sub-pixels that are charged corresponding to the (n+2)th scan line and the (n+3)th scan line.

[0011] Optionally, the first to fourth pixels each include three sub-pixels of different colors: a red sub-pixel, a green sub-pixel, and a blue sub-pixel.

[0012] The threshold of the thin-film transistor connected to each red sub-pixel is greater than the threshold of the thin-film transistor connected to each green sub-pixel and the threshold of the thin-film transistor connected to each blue sub-pixel.

[0013] Optionally, among the sub-pixels connected by the nth scan line and the (n+1)th scan line, the threshold values ​​of the thin-film transistors corresponding to the same color sub-pixels in the first pixel and the third pixel are different, and the threshold values ​​of the thin-film transistors corresponding to the same color sub-pixels in the second pixel and the fourth pixel are different.

[0014] This application also discloses a driving circuit for a display panel, the driving circuit including a frequency doubling control circuit, a gate driving circuit, and a pixel driving circuit as described above, the frequency doubling control circuit being connected to the pixel driving circuit through the gate driving circuit; the gate driving circuit including a plurality of gate driving units, the plurality of gate driving units being respectively connected to the scan lines in the pixel driving circuit one-to-one; wherein, when the display panel enters the frequency doubling mode, the frequency doubling control circuit controls the two gate driving units connected to the two scan lines between the corresponding two rows of pixels to generate the same scan signal to the corresponding two rows of scan lines.

[0015] Optionally, except for the first and last scan lines, all scan lines are connected to the gate driving unit by a pull-down circuit. In frequency multiplication mode, the pull-down circuit is turned on, and the pull-down voltages of the two pull-down circuits corresponding to the two scan lines of the same scan signal are different.

[0016] Optionally, a pull-up circuit is provided between all scan lines and the gate driving unit. In frequency multiplication mode, the pull-up circuit is turned on, and the pull-up voltages of the two pull-up circuits corresponding to the two scan lines of the same scan signal are different.

[0017] Optionally, the pull-up voltage of the pull-up circuit corresponding to the scan line closer to the data signal input terminal is less than the pull-up voltage of the pull-up circuit corresponding to the scan line farther from the data signal input terminal.

[0018] This application also discloses a driving method for driving the driving circuit of any of the display panels described above, the driving method comprising the steps of:

[0019] Detect the refresh rate of the next frame;

[0020] Based on the refresh rate of the next frame and the refresh rate of the current frame, determine whether the next frame will enter the frequency multiplication display mode. If so, control the two gate drive units connected to the two scan lines between the corresponding two rows of pixels to generate the same scan signal to the corresponding two rows of scan lines, and sequentially input the cascaded scan signal to each of the corresponding two rows of scan lines; if not, sequentially input the cascaded scan signal to each of the corresponding rows of scan lines.

[0021] Optionally, the step of determining whether the next frame enters the frequency multiplication display mode based on the refresh rate of the next frame and the refresh rate of the current frame, and if so, controlling the two gate driving units connected to the two scan lines between the corresponding two rows of pixels to generate the same scan signal to the corresponding two rows of scan lines, and sequentially inputting the cascaded scan signal to each of the corresponding two rows of scan lines; if not, the step of sequentially inputting the cascaded scan signal to each of the corresponding rows of scan lines includes:

[0022] When generating the same scan signal input to the corresponding two scan lines, the pull-down circuit is turned on to pull down the scan signal to different degrees to generate new and different scan signals to the corresponding two scan lines.

[0023] Compared to the original DRD pixel architecture, this application provides a novel DRD pixel architecture. The same data line design of adjacent rows (such as Gn and Gn+1 rows) connects and drives the same color pixels in adjacent rows above and below. When adopting this design scheme, when DLG high-frequency technology is activated, the scan lines of Gn and Gn+1 rows are turned on simultaneously. The two rows of pixel data lines controlled drive the same color pixels and display the same grayscale. This can realize DLG high-frequency display and avoid the situation where two different color pixels display the same grayscale in DLG mode, which would prevent the display of RGB monochrome images and cause the display panel to fail to display colors normally. At the same time, it saves the number of COFs and reduces the manufacturing cost of the display panel. Attached Figure Description

[0024] The accompanying drawings, which form part of the specification, are used to provide a further understanding of the embodiments of this application and illustrate the implementation methods of this application, together with the textual description, to explain the principles of this application. Obviously, the drawings described below are merely some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings without any creative effort. In the drawings:

[0025] Figure 1 This is a schematic diagram of the structure of a pixel driving circuit according to the first embodiment of this application;

[0026] Figure 2 This is a schematic diagram of the drive circuit of the second embodiment of this application;

[0027] Figure 3 This is a schematic diagram of the drive circuit according to the third embodiment of this application;

[0028] Figure 4 This is a schematic diagram of the drive circuit according to the fourth embodiment of this application;

[0029] Figure 5 This is a schematic flowchart of the driving method according to the fifth embodiment of this application.

[0030] Among them, 100 is a pixel driving circuit; 110 is a scan line; 120 is a data line; 130 is a pixel area; 131 is a first pixel area; 132 is a second pixel area; 140 is a pixel sub-area; 141 is a first pixel; 142 is a second pixel; 143 is a third pixel; 144 is a fourth pixel; 200 is a driving circuit; 210 is a gate driving circuit; 211 is a gate driving unit; 220 is a frequency multiplication control circuit; 230 is a pull-down circuit; and 240 is a pull-up circuit. Detailed Implementation

[0031] It should be understood that the terminology, specific structural and functional details used herein are merely for describing particular embodiments and are representative. However, this application may be implemented in many alternative forms and should not be construed as being limited to the embodiments set forth herein.

[0032] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating relative importance or implying the number of technical features indicated. Therefore, unless otherwise stated, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature; "multiple" means two or more. The term "comprising" and any variations thereof mean non-exclusive inclusion, where one or more other features, integers, steps, operations, units, components, and / or combinations thereof may be present or added.

[0033] In addition, terms such as “center,” “horizontal,” “up,” “down,” “left,” “right,” “vertical,” “horizontal,” “top,” “bottom,” “inner,” and “outer” that indicate orientation or positional relationship are based on the orientation or relative positional relationship shown in the accompanying drawings. They are only for the purpose of simplifying the description of this application and do not indicate that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0034] Furthermore, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium, or internal connections between two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0035] The present application will now be described in detail with reference to the accompanying drawings and optional embodiments.

[0036] like Figure 1As shown, as a first embodiment of this application, a pixel driving circuit 100 is disclosed. The pixel driving circuit 100 includes multiple scan lines 110 and multiple data lines 120, and multiple pixels driven by the multiple scan lines 110 and multiple data lines 120 respectively. Along the direction of the data lines 120, the multiple pixels are divided into multiple pixel regions 130. Along the upward direction of the scan lines 110, each pixel region 130 is divided into multiple pixel sub-regions 140. Each pixel sub-region 140 includes four pixels arranged in a 2*2 pattern. Each pixel includes three sub-pixels of different colors, namely red sub-pixel R, green sub-pixel G, and blue sub-pixel B. The four pixels are respectively a first pixel 141, a second pixel 142, a third pixel 143, and a fourth pixel 144.

[0037] In the first pixel 141, one sub-pixel is connected to the (n-1)th scan line Gn-1, and the other two sub-pixels are connected to the nth scan line Gn; in the second pixel 142, one sub-pixel is connected to the nth scan line Gn, and the other two sub-pixels are connected to the (n-1)th scan line Gn-1; the three sub-pixels connected to the (n-1)th scan line Gn-1 are of different colors, and the three sub-pixels connected to the nth scan line Gn are also of different colors; in the third pixel 143, one sub-pixel is connected to the (n+2)th scan line Gn+2, and the other two sub-pixels are connected to the (n+1)th scan line Gn+1; in the fourth pixel 144, one sub-pixel is connected to the (n+1)th scan line Gn+1, and the other two sub-pixels are connected to the (n+2)th scan line Gn+2; the three sub-pixels connected to the (n+1)th scan line Gn+1 are of different colors, and the three sub-pixels connected to the (n+2)th scan line Gn+2 are also of different colors.

[0038] Where n is a natural number greater than or equal to 2, when the pixel area 130 is displayed at double frequency, the nth scan line 110 and the (n+1)th scan line 110 receive the same scan signal, the sub-pixels of the same color in the first pixel 141 and the third pixel 143 receive the same data signal, and the sub-pixels of the same color in the second pixel 142 and the fourth pixel 144 receive the same data signal.

[0039] This application provides a novel DRD pixel architecture. Pixels connected on two scan lines 110 that receive the same scan signal are configured to have the same color if they receive the same data signal. During DLG (Digital Multiplexing) display, the nth scan line Gn and the (n+1)th scan line Gn+1 receive the same scan signal. Sub-pixels of the same color in the first pixel 141 and the third pixel 143 receive the same data signal, as do sub-pixels of the same color in the second pixel 142 and the fourth pixel 144. This avoids the situation where, in DLG mode, two different color pixels on adjacent rows connected by the same data line 120 display the same grayscale, preventing the display from showing a monochrome RGB image and thus hindering normal color display.

[0040] Furthermore, two adjacent pixel regions 130 are respectively the first pixel region 131 and the second pixel region 132. The first pixel region 131 and the second pixel region 132 are symmetrical about the center line between the first pixel region 131 and the second pixel region 132. The scan lines 110 corresponding to the first pixel region 131 are the (n-1)th scan line Gn-1, the nth scan line Gn, the (n+1)th scan line Gn+1 and the (n+2)th scan line Gn+2. The scan lines 110 corresponding to the second pixel region 132 are the (n+3)th scan line Gn+3, the (n+4)th scan line Gn+4, the (n+5)th scan line Gn+5 and the (n+6)th scan line Gn+6. Subsequently, there are also the (n+m-3)th scan line Gn+m-3, the (n+m-2)th scan line Gn+m-2, the (n+m-1)th scan line Gn+m-1 and the (n+m)th scan line Gn+m.

[0041] When the pixel area 130 performs frequency multiplication display, the nth scan line Gn and the (n+1)th scan line Gn+1 receive the same scan signal, the (n+2)th scan line Gn+2 and the (n+3)th scan line Gn+3 receive the same scan signal, the (n+4)th scan line Gn+4 and the (n+5)th scan line Gn+5 receive the same scan signal, and the sub-pixels that are charged corresponding to the nth scan line Gn and the (n+1)th scan line Gn+1 have different colors than the sub-pixels that are charged corresponding to the (n+2)th scan line Gn+2 and the (n+3)th scan line Gn+3. In this way, the entire display panel can achieve DLG mode display.

[0042] The first pixel 141 to the fourth pixel 144 each include three sub-pixels of different colors: red sub-pixel, green sub-pixel, and blue sub-pixel. Considering that in DLG mode, the scanning time of the scan line 110 is halved, resulting in a decrease in the amount of charge of the pixel, and since the transmittance of sub-pixels of different colors is different, if the amount of charge required remains unchanged, the difference in brightness between sub-pixels after charging will be large, and the light mixed by RGB will deviate from the ideal light. Therefore, the threshold of the thin film transistor connected to each red sub-pixel is greater than the threshold of the thin film transistor connected to each green sub-pixel and the threshold of the thin film transistor connected to each blue sub-pixel, and the threshold of the thin film transistor connected to the green sub-pixel is greater than the threshold of the thin film transistor connected to the blue sub-pixel.

[0043] Furthermore, the drawback of DLG mode is that after the vertical resolution is halved, the image clarity decreases when displaying patterns at the original resolution, and the jagged edges at the curves are more obvious, resulting in an unsatisfactory display effect. In the sub-pixels connected by the nth scan line 110 and the (n+1)th scan line 110, the threshold values ​​of the thin-film transistors corresponding to the same color sub-pixels in the first pixel 141 and the third pixel 143 are different, and the threshold values ​​of the thin-film transistors corresponding to the same color sub-pixels in the second pixel 142 and the fourth pixel 144 are different. This results in different gate opening degrees between adjacent rows, causing two rows of pixels that are simultaneously open to have different charging rates, thus producing different display effects. Compared to pixels with the same charging rate, this can optimize the jagged edges of the image and avoid obvious and strong jagged edges, thereby compensating for the display effect of DLG mode.

[0044] like Figure 2 As shown, a driving circuit 200 for a display panel is disclosed. The driving circuit 200 includes a frequency doubling control circuit 220, a gate driving circuit 210, and a pixel driving circuit 100 as described above. The frequency doubling control circuit 220 is connected to the pixel driving circuit 100 through the gate driving circuit 210. The gate driving circuit 210 includes a plurality of gate driving units 211, which are respectively connected to the scan lines 110 in the pixel driving circuit 100. When the display panel enters the frequency doubling mode, the frequency doubling control circuit 220 controls the two gate driving units 211 connected to the two scan lines 110 between the corresponding two rows of pixels to generate the same scan signal to the corresponding two rows of scan lines 110.

[0045] The driving circuit 200 can be used for driving in normal mode or driving in frequency multiplication mode. In normal mode, the frequency multiplication control circuit 220 controls the gate driving circuit 210 to generate different scanning signals for each row of scan lines 110 to be input to the scan lines 110 for driving. In frequency multiplication mode, the two rows of scan lines 110 between two rows of pixels receive the same scanning signal. This same scanning signal is also generated by the gate driving circuit 210 controlled by the frequency multiplication control module. The nth scan line Gn and the (n+1)th scan line Gn+1 receive the same scanning signal, the (n+2)th scan line Gn+2 and the (n+3)th scan line Gn+3 receive the same scanning signal, the (n+4)th scan line Gn+4 and the (n+5)th scan line Gn+5 receive the same scanning signal. The sub-pixels that are charged corresponding to the (n+1)th scan line Gn and the (n+2)th scan line Gn+1 have different colors than the sub-pixels that are charged corresponding to the (n+2)th scan line Gn+2 and the (n+3)th scan line Gn+3. The (n)th scan line Gn and the (n+1)th scan line Gn+1 receive the same scan signal, the (n+2)th scan line Gn+2 and the (n+3)th scan line Gn+3 receive the same scan signal, and the (n+4)th scan line Gn+4 and the (n+5)th scan line Gn+5 receive different scan signals. These are cascaded scan signals. Due to the improvement in the pixel arrangement connection method in the pixel driving circuit 100, two pixels of the same color can display the same grayscale in DLG mode, displaying an RGB monochrome image. At the same time, the number of COFs is saved, reducing the manufacturing cost of the display panel.

[0046] like Figure 3 As shown, the third embodiment of this application is a further improvement on the second embodiment described above. Currently, the drawback of the DLG mode is that after the vertical resolution is halved, the image clarity decreases when displaying patterns of the original resolution, and the jagged edges at the curve edges are more obvious, resulting in an unsatisfactory display effect. Except for the first and last scan lines 110, all scan lines 110 are connected to the gate driving unit 211 by a pull-down circuit 230. In the frequency multiplication mode, the pull-down circuit 230 is turned on. The two pull-down circuits 230 corresponding to the same scan signal have different pull-down voltages. By setting the pull-down circuit 230, different scan signal waveforms are generated and output to the scan lines 110. The two scan signal waveforms are different, and the turn-on voltage of the thin-film transistor of the sub-pixel is different, so that the gate opening degree of the thin-film transistor corresponding to the two adjacent rows of pixels is different. This results in different charging rates for the two rows of pixels that are turned on at the same time, thereby producing different display effects to optimize the jagged edges of the image and avoid obvious and strong jagged edges, thus compensating for the display effect of the DLG mode.

[0047] like Figure 4 As shown, this is the fourth embodiment of the present application, and also an improvement on the second embodiment. Considering that the charging time of each row of pixels is halved after frequency multiplication, insufficient charging of sub-pixels may occur when entering DLG mode. Therefore, a pull-up circuit 240 is added to pull up the voltage of the scanning signal to avoid insufficient charging. Specifically, a pull-up circuit 240 is provided between all scan lines 110 and the gate driving unit 211 to increase the opening degree of the thin-film transistor corresponding to each row of pixels, thereby increasing charging efficiency. In frequency multiplication mode, the pull-up circuit 240 is turned on, and the two pull-up circuits 240 corresponding to the two scan lines 110 of the same scanning signal are... The different pull-up voltages result in different gate opening degrees between adjacent rows, leading to different charging rates for the two simultaneously opened pixel rows and thus producing different display effects. This also avoids the situation in DLG mode where two scan lines 110 receiving the same scan signal have the same charging amount, resulting in decreased image clarity, more obvious jagged edges at curve edges, and unsatisfactory display effects. In addition, it should be noted that the pull-up circuit 240 can also be set to pull up the clock signal before the scan signal is generated, so that the voltage of the scan signal generated by the gate drive circuit 210 is greater than the voltage of the scan signal generated before the pull-up circuit 240 was not used.

[0048] Furthermore, considering that there may be some loss of data signal on data line 120, or that parasitic capacitance may be generated due to line resistance when charging the data line 120 with input voltage, the pull-up voltage VGH1 of the pull-up circuit 240 corresponding to the scan line 110 near the data signal input end is less than the pull-up voltage VGH2 of the pull-up circuit 240 corresponding to the scan line 110 far from the data signal input end, thereby reducing the influence of parasitic capacitance and improving the display effect.

[0049] As a fifth embodiment of this application, a driving method is disclosed. The driving method can be used in the driving circuit described in any of the above embodiments. The driving method includes the following steps:

[0050] S1: Detect the refresh rate of the next frame;

[0051] S2: Based on the refresh rate of the next frame and the refresh rate of the current frame, determine whether the next frame will enter the frequency multiplication display mode. If yes, control the two gate driving units connected to the two scan lines between the corresponding two rows of pixels to generate the same scan signal to the corresponding two rows of scan lines, and sequentially input the cascaded scan signal to each of the corresponding two rows of scan lines; if no, sequentially input the cascaded scan signal to each of the corresponding rows of scan lines.

[0052] Before enabling DLG mode, the refresh rate of the next frame is detected. When the refresh rate of the next frame changes or doubles, it is determined that the next frame will enter the frequency doubling mode. Then, the scanning signal is gradually input from each line to the two scan lines between the two rows of pixels, thereby achieving frequency doubling display. Under this pixel driving circuit, there is no need to worry about two different colored pixels displaying the same grayscale in DLG mode, which would prevent the display of RGB monochrome images and the panel from displaying colors normally. Therefore, the problem that DRD architecture display panels cannot use DLG technology currently does not occur.

[0053] Generally, step S2 further includes:

[0054] S21: When generating the same scan signal input to the corresponding two scan lines, enable the pull-down circuit to pull down the scan signal to different degrees to generate new and different scan signals to the corresponding two scan lines.

[0055] By activating the pull-down circuit, the waveform of the gate drive signal output to the scan line is controlled. When the pull-down circuit is activated, the waveforms and voltages of the scan signals of the two scan lines are different, resulting in different gate opening degrees for adjacent lines. This causes the two simultaneously activated pixels to have different charging rates, thus producing different display effects. Compared to pixels with the same charging rate, this can optimize the jagged edges of the image and avoid obvious and strong jagged edges, thereby compensating for the display effect of DLG mode. In addition, although two gate drive units that receive the same scan signal can each have a pull-down circuit, it is also possible for one pull-down circuit to be active while the other is inactive.

[0056] Considering that there are multiple possibilities for refresh rate switching, such as switching from 60Hz to 120Hz or from 120Hz to 240Hz, and considering that different refresh rate differences may result in different jagged edges, the greater the difference in refresh rates, the more obvious the jagged edges will be, and a stronger pull-down force is needed to improve the jagged edges of the screen and improve the display effect of the dual-gate mode. Therefore, the pull-down circuit can be set with two pull-down voltages, which can be used for switching between different refresh rates.

[0057] It should be noted that the limitations on each step involved in this solution are not considered as limiting the order of steps, provided that they do not affect the implementation of the specific solution. The steps listed first can be executed first, later, or even simultaneously. As long as this solution can be implemented, it should be considered to fall within the scope of protection of this application.

[0058] It should be noted that the inventive concept of this application can form many embodiments, but due to the limited space of the application documents, they cannot all be listed. Therefore, without conflict, the embodiments described above or the technical features can be arbitrarily combined to form new embodiments. After the embodiments or technical features are combined, the original technical effect will be enhanced.

[0059] The technical solution of this application can be widely used in driving circuits of various display panels, such as driving circuits of TN (Twisted Nematic) display panels, driving circuits of IPS (In-Plane Switching) display panels, driving circuits of VA (Vertical Alignment) display panels, and driving circuits of MVA (Multi-Domain Vertical Alignment) display panels. Of course, it can also be used for driving circuits of other types of display panels, such as driving circuits of OLED (Organic Light-Emitting Diode) display panels, and the above solution is applicable to all of them.

[0060] The above description, in conjunction with specific optional embodiments, provides a further detailed explanation of this application and should not be construed as limiting the specific implementation of this application to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of this application, and all such modifications or substitutions should be considered within the scope of protection of this application.

Claims

1. A pixel driving circuit comprising a plurality of scan lines and a plurality of data lines, and a plurality of pixels driven by the plurality of scan lines and the plurality of data lines, respectively, characterized in that, Along the data line direction, a plurality of pixels are divided into a plurality of pixel regions, and along the scanning line direction, each pixel region is divided into a plurality of pixel sub-regions, each pixel sub-region including four pixels arranged in 2*2, each pixel including three sub-pixels of different colors, and the four pixels being a first pixel, a second pixel, a third pixel and a fourth pixel respectively; One of the sub-pixels in the first pixel is connected to an n-1th scanning line, and the other two sub-pixels are connected to an nth scanning line; one of the sub-pixels in the second pixel is connected to the nth scanning line, and the other two sub-pixels are connected to the n-1th scanning line; the three sub-pixels connected to the n-1th scanning line are of different colors, and the three sub-pixels connected to the nth scanning line are also of different colors; One of the sub-pixels in the third pixel is connected to an n+2th scanning line, and the other two sub-pixels are connected to an n+1th scanning line; one of the sub-pixels in the fourth pixel is connected to the n+1th scanning line, and the other two sub-pixels are connected to the n+2th scanning line; the three sub-pixels connected to the n+1th scanning line are of different colors, and the three sub-pixels connected to the n+2th scanning line are also of different colors; Wherein, n is a natural number greater than or equal to 2, when the pixel region performs frequency doubling display, the nth scanning line and the n+1th scanning line receive the same scanning signal, the same color sub-pixels in the first pixel and the third pixel receive the same data signal, and the same color sub-pixels in the second pixel and the fourth pixel receive the same data signal; The first pixel region and the second pixel region are respectively a first pixel region and a second pixel region, the first pixel region and the second pixel region are symmetrical to each other with a center line between the first pixel region and the second pixel region, the scanning lines corresponding to the first pixel region are an n-1th scanning line, an nth scanning line, an n+1th scanning line and an n+2th scanning line, and the scanning lines corresponding to the second pixel region are an n+3th scanning line, an n+4th scanning line, an n+5th scanning line and an n+6th scanning line; wherein, when the pixel region performs frequency doubling display, the nth scanning line and the n+1th scanning line receive the same scanning signal, the n+2th scanning line and the n+3th scanning line receive the same scanning signal, the n+4th scanning line and the n+5th scanning line receive the same scanning signal, and the colors of the sub-pixels corresponding to the nth scanning line and the n+1th scanning line and the colors of the sub-pixels corresponding to the n+2th scanning line and the n+3th scanning line are different.

2. The pixel driving circuit according to claim 1, wherein The first pixel to the fourth pixel each include three sub-pixels of different colors, such as a red sub-pixel, a green sub-pixel and a blue sub-pixel; The threshold value of the thin film transistor connected to each red sub-pixel is greater than the threshold value of the thin film transistor connected to each green sub-pixel and the threshold value of the thin film transistor connected to each blue sub-pixel.

3. The pixel driving circuit of claim 1, wherein, The threshold values of the thin film transistors corresponding to the sub-pixels of the same color in the first pixel and the third pixel are different in the sub-pixels connected by the nth scan line and the (n+1)th scan line, and the threshold values of the thin film transistors corresponding to the sub-pixels of the same color in the second pixel and the fourth pixel are different.

4. A drive circuit of a display panel, characterized by comprising: The display panel comprises a frequency doubling control circuit, a gate driving circuit and a pixel driving circuit as claimed in any one of claims 1-3, the frequency doubling control circuit is connected with the pixel driving circuit through the gate driving circuit; the gate driving circuit comprises a plurality of gate driving units, and each of the plurality of gate driving units is connected with one of the scan lines in the pixel driving circuit one by one. When the display panel enters the frequency doubling mode, the frequency doubling control circuit controls two gate driving units connected by two scan lines between two rows of pixels to generate the same scan signal to the corresponding two rows of scan lines.

5. The driving circuit of a display panel according to claim 4, wherein A pull-down circuit is arranged between each of the scan lines and the gate driving unit, and the pull-down circuit is turned on in the frequency doubling mode, and the voltages pulled down by the two pull-down circuits corresponding to the two scan lines with the same scan signal are different.

6. The driving circuit of a display panel according to claim 4, wherein A pull-up circuit is arranged between each of the scan lines and the gate driving unit, and the pull-up circuit is turned on in the frequency doubling mode, and the voltages pulled up by the two pull-up circuits corresponding to the two scan lines with the same scan signal are different.

7. The driving circuit of a display panel according to claim 6, wherein The pull-up voltage of the pull-up circuit corresponding to the scan line close to the data signal input end is smaller than the pull-up voltage of the pull-up circuit corresponding to the scan line far from the data signal input end.

8. A driving method for driving the driving circuit of the display panel according to any one of claims 4 to 7, characterized by, The driving method comprises the steps of: detecting the refresh rate of the next frame; determining whether the next frame enters the frequency doubling display mode according to the refresh rate of the next frame and the refresh rate of the current frame, if yes, controlling two gate driving units connected by two scan lines between two rows of pixels to generate the same scan signal to the corresponding two rows of scan lines, and sequentially inputting the cascaded scan signals to each two rows of scan lines; if no, sequentially inputting the cascaded scan signals to each row of scan lines.

9. The driving method of claim 8, wherein, The step of determining whether the next frame enters the frequency doubling display mode according to the refresh rate of the next frame and the refresh rate of the current frame, if yes, controlling two gate driving units connected by two scan lines between two rows of pixels to generate the same scan signal to the corresponding two rows of scan lines, and sequentially inputting the cascaded scan signals to each two rows of scan lines; if no, sequentially inputting the cascaded scan signals to each row of scan lines comprises: when the same scan signal is generated and input to the corresponding two rows of scan lines, the pull-down circuit is turned on to pull down the scan signal to different degrees to generate new different scan signals to the corresponding two rows of scan lines.

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