Voltage detection for managed memory systems

Abstract

This application relates to voltage detection for managed memory systems. In some cases, a memory system can include circuitry to monitor one or more supply voltages to the memory system or voltages generated by the memory system to determine whether a voltage has risen above an operating range. In some cases, an overvoltage detector can include an undervoltage detector that has been tuned or manufactured to have a threshold value that is higher than an undervoltage detector used to determine whether a voltage has fallen below the operating range. Thus, the memory system can monitor voltages using an undervoltage detector having a threshold value corresponding to a lower limit or lower operating point of the operating range of the monitored voltage and an overvoltage detector having a threshold value corresponding to an upper limit or upper operating point of the operating range.

Description

[0001] CROSS-REFERENCE

[0002] This patent application claims priority to U.S. Patent Application No. 17 / 655,138 to Weinberg et al., titled “VOLTAGE DETECTION FOR MANAGED MEMORY SYSTEMS,” filed March 16, 2022, and U.S. Provisional Patent Application No. 63 / 266,151 to Weinberg et al., titled “VOLTAGE DETECTION FOR MANAGED MEMORY SYSTEMS,” filed December 29, 2021, each of which is assigned to the assignee hereof and each of which is expressly incorporated by reference herein in its entirety. TECHNICAL FIELD

[0003] The technical field relates to voltage detection for managed memory systems. BACKGROUND

[0004] Memory devices are widely used in various electronic devices to store information, such as computers, user devices, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming memory cells within a memory device into various states. For example, binary memory cells can be programmed into one of two support states, typically corresponding to a logic 1 or a logic 0. In some examples, individual memory cells can support more than two possible states, any of which can be stored by the memory cell. To access information stored by a memory device, a component can read or sense the state of one or more memory cells within the memory device. To store information, a component can write or program one or more memory cells within the memory device to a corresponding state.

[0005] There are various types of memory devices, including magnetic hard disks, random access memory (RAM), read only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), 3D cross point memory (3D cross point), or NOR and NAND memory devices, among others. Memory devices can be volatile or non-volatile. Volatile memory cells (e.g., DRAM cells) can lose their programmed state over time unless they are periodically refreshed by an external power source. Non-volatile memory cells (e.g., NAND memory cells) can maintain their programmed state for a long period of time, even in the absence of an external power source. SUMMARY

[0006] An apparatus is described. The apparatus can include a memory device; a controller coupled with the memory device, the controller configured to couple with a host device and perform a mapping between a logical address received from the host device and a physical address of the memory device; a first voltage detector having a first configuration and a second voltage detector having a second configuration, the first voltage detector and the second voltage detector coupled with the memory device and configured to monitor one or more supply voltages of the memory device and determine whether the one or more supply voltages satisfy respective ranges based at least in part on monitoring the one or more supply voltages; and a health engine coupled with the first voltage detector, the second voltage detector, and the controller, the health engine configured to initiate a safe mode of at least one of the controller or the memory device based at least in part on determining that a supply voltage of the one or more supply voltages exceeds an upper operating point of the respective range.

[0007] A non-transitory computer-readable medium is described. The non-transitory computer-readable medium can store code that includes instructions executable by a processor of an electronic device to monitor one or more supply voltages of a memory device; determine, using a first voltage detector having a first configuration and a second voltage detector having a second configuration, whether the one or more supply voltages satisfy respective ranges based at least in part on monitoring the one or more supply voltages; and initiate, at a health engine of the memory device, a safe mode of the memory device based at least in part on determining that a supply voltage of the one or more supply voltages exceeds an upper operating point of the respective range.

[0008] A method is described. The method can include monitoring one or more supply voltages of a memory device; determining, using a first voltage detector having a first configuration and a second voltage detector having a second configuration, whether the one or more supply voltages satisfy respective ranges based at least in part on monitoring the one or more supply voltages; and initiating, at a health engine of the memory device, a safe mode of the memory device based at least in part on determining that a supply voltage of the one or more supply voltages exceeds an upper operating point of the respective range. BRIEF DESCRIPTION OF DRAWINGS

[0009] FIG. 1 An example of a system that supports voltage detection for a managed memory system is shown in accordance with examples disclosed herein.

[0010] FIG. 2 An example of a system that supports voltage detection for a managed memory system is shown in accordance with examples disclosed herein.

[0011] FIG. 3 An example of a block diagram that supports voltage detection for a managed memory system is shown in accordance with examples disclosed herein.

[0012] FIG. 4 An example of a flow diagram that supports voltage detection for a managed memory system is shown in accordance with examples disclosed herein.

[0013] FIG. 5 An example of a block diagram that supports voltage detection for a managed memory system is shown in accordance with examples disclosed herein.

[0014] FIG. 6 A block diagram of a memory system that supports voltage detection for a managed memory system is shown in accordance with examples disclosed herein.

[0015] FIG. 7 A flow diagram showing one or more methods that support voltage detection for a managed memory system is shown in accordance with examples disclosed herein. DETAILED DESCRIPTION

[0016] Some memory systems, such as managed memory systems, can receive one or more supply voltages, for example, from a host system or other external power source. In some cases, a supply voltage can unexpectedly decrease or change value. For example, an electrical connection for a supply voltage can be weak or faulty, which can cause a drop in power supply. Additionally, a supply voltage can decrease if a memory system or other system drawing power from a host system or external power source activates multiple features, or if multiple devices drawing power from an external power source are simultaneously active. Alternatively, a supply voltage can unexpectedly increase or spike if multiple devices drawing power from an external power source are simultaneously disconnected, which can damage a memory system or cause unstable behavior in a memory system. In some cases, a memory system can include an undervoltage detector for monitoring a supply voltage of the memory system, and an undervoltage detector for monitoring a voltage generated by the memory system. If a supply voltage drops below a threshold of an undervoltage detector (e.g., if an undervoltage event is detected), the undervoltage detector can notify a health engine of the memory system. The health engine can accordingly initiate a safe state or safe mode of the memory system. However, a memory system, such as a managed memory system, can not include circuitry for determining if a supply voltage increases above an operating range. Accordingly, some memory systems can be susceptible to overvoltage events. Techniques for detecting overvoltage events are needed.

[0017] As described herein, a memory system can include circuitry, such as an overvoltage detector, for monitoring one or more supply voltages to the memory system or a voltage generated by the memory system to determine if the voltage increases above an operating range. In some cases, an overvoltage detector can include the same voltage detector circuit as an undervoltage detector that has been tuned or manufactured to have a threshold value that is higher than an undervoltage detector for determining if a voltage has dropped below an operating range. The threshold value of the voltage detector can be determined by a configuration of the voltage detector, such as trimming of one or more active resistors or resistors of the voltage detector. The configuration can be determined during manufacturing or testing of the memory system, such that the voltage detector can be “tuned” or set to have a desired threshold value. Accordingly, a memory system can monitor a voltage using an undervoltage detector having a threshold value that corresponds to a lower limit or lower operating point of an operating range of the monitored voltage, and an overvoltage detector having a threshold value that corresponds to an upper limit or upper operating point of the operating range. Accordingly, a memory system can determine if a monitored voltage increases above or below an operating range, which can allow a health engine of the memory system to initiate a safe mode or take other actions in the event of an overvoltage event or in the event of an undervoltage event.

[0018] Features of the present disclosure are first described in the context of systems, devices, and circuitry of FIGS. 1-2 . Features of the present disclosure are further described in the context of systems, devices, and circuitry of FIGS. 3-5in the context of block and flow diagrams. These and other features of the present disclosure are further described below with reference to the following description and attached drawings. FIGS. 6-7 devices and flow diagrams related to voltage detection for a managed memory system are shown and described in the context of the device diagrams and flow diagrams.

[0019] FIG. 1 An example of a system 100 that supports voltage detection for a managed memory system is shown in accordance with examples disclosed herein. The system 100 includes a host system 105 coupled with a memory system 110.

[0020] The memory system 110 can be or include any device or collection of devices that includes at least one memory array. For example, the memory system 110 can be or include a Universal Flash Storage (UFS) device, an Embedded Multimedia Controller (eMMC) device, a flash device, a Universal Serial Bus (USB) flash device, a Secure Digital (SD) card, a Solid State Drive (SSD), a Hard Disk Drive (HDD), a Dual In-line Memory Module (DIMM), a Small Outline DIMM (SO-DIMM), or a Non-Volatile DIMM (NVDIMM), among other possibilities.

[0021] The system 100 can be included in a computing device such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., an airplane, a drone, a train, a car, or other conveyance), an Internet of Things (IoT) enabled device, an embedded computer (e.g., included in a vehicle, industrial equipment, or a networked commercial device), or any other computing device that includes memory and a processing device.

[0022] The system 100 can include a host system 105 that can be coupled with the memory system 110. In some examples, this coupling can include interfacing with a host system controller 106, which can be an example of a controller or control component configured to cause the host system 105 to perform various operations in accordance with examples as described herein. The host system 105 can include one or more devices, and in some cases, can include a processor chipset and a software stack executed by the processor chipset. For example, the host system 105 can include an application configured to communicate with the memory system 110 or a device therein. The processor chipset can include one or more cores, one or more caches (e.g., memory local to or included in the host system 105), a memory controller (e.g., a NVDIMM controller), and a storage protocol controller (e.g., a Peripheral Component Interconnect Express (PCIe) controller, a Serial Advanced Technology Attachment (SATA) controller). The host system 105 can use the memory system 110, for example, to write data to and read data from the memory system 110. Although one memory system 110 is shown in FIG. 1

[0023] The host system 105 can be coupled with the memory system 110 via at least one physical host interface. In some cases, the host system 105 and the memory system 110 can be configured to communicate (e.g., exchange or otherwise transfer control, address, data, and other signals) via the physical host interface using an associated protocol. Examples of physical host interfaces can include, but are not limited to, a SATA interface, a UFS interface, an eMMC interface, a PCIe interface, a USB interface, a Fibre Channel interface, a Small Computer System Interface (SCSI), a Serial Attached SCSI (SAS), a Double Data Rate (DDR) interface, a DIMM interface (e.g., a DDR-enabled DIMM socket interface), an Open NAND Flash Interface (ONFI), and a Low Power Double Data Rate (LPDDR) interface. In some examples, one or more such interfaces can be included in or otherwise supported between the host system controller 106 of the host system 105 and the memory system controller 115 of the memory system 110. In some examples, the host system 105 can be coupled with the memory system 110 via a respective physical host interface for each memory device 130 included in the memory system 110 or via a respective physical host interface for each type of memory device 130 included in the memory system 110 (e.g., the host system controller 106 can be coupled with the memory system controller 115).

[0024] ​The memory system 110 can include a memory system controller 115 and one or more memory devices 130. The memory devices 130 can include one or more memory arrays of any type of memory cells (e.g., non-volatile memory cells, volatile memory cells, or any combination thereof). Although FIG. 1 Two memory devices 130-a and 130-b are shown in the example of FIG. 1, but the memory system 110 can include any number of memory devices 130. Moreover, if the memory system 110 includes more than one memory device 130, different memory devices 130 within the memory system 110 can include the same or different types of memory cells.

[0025] The memory system controller 115 can be coupled with and in communication with the host system 105 (e.g., via a physical host interface) and can be an example of a controller or control component configured to cause the memory system 110 to perform various operations in accordance with examples as described herein. The memory system controller 115 can also be coupled with and in communication with the memory devices 130 to perform operations such as reading data, writing data, erasing data, or refreshing data at the memory devices 130, among other such operations, which can be collectively referred to as access operations. In some cases, the memory system controller 115 can receive commands from the host system 105 and communicate with one or more memory devices 130 to execute such commands (e.g., at memory arrays within the one or more memory devices 130). For example, the memory system controller 115 can receive commands or operations from the host system 105 and can convert the commands or operations into instructions or appropriate commands to effectuate desired accesses of the memory devices 130. In some cases, the memory system controller 115 can exchange data with the host system 105 and the one or more memory devices 130 (e.g., in response to or otherwise in association with commands from the host system 105). For example, the memory system controller 115 can convert responses (e.g., data packets or other signals) associated with the memory devices 130 into corresponding signals for the host system 105.

[0026] The memory system controller 115 can be configured for other operations associated with the memory devices 130. For example, the memory system controller 115 can perform or manage operations such as wear leveling operations, garbage collection operations, error detection operations or error correction operations, encryption operations, cache operations, media management operations, background refresh, health monitoring, and address translations between logical addresses (e.g., logical block addresses (LBAs)) associated with commands from the host system 105 and physical addresses (e.g., physical block addresses) associated with memory cells within the memory devices 130.

[0027] The memory system controller 115 can include hardware such as one or more integrated circuits or discrete components, a buffer memory, or a combination thereof. The hardware can include circuitry with specialized (e.g., hard-coded) logic to perform the operations attributed herein to the memory system controller 115. The memory system controller 115 can be or include a microcontroller, special purpose logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a digital signal processor (DSP)), or any other suitable processor or processing circuitry.

[0028] The memory system controller 115 can also include a local memory 120. In some cases, the local memory 120 can include read-only memory (ROM) or other memory that can store operational code (e.g., executable instructions) that can be executed by the memory system controller 115 to perform the functions attributed herein to the memory system controller 115. In some cases, the local memory 120 can additionally or alternatively include static random access memory (SRAM) or other memory that can be used by the memory system controller 115 for internal storage or computation, e.g., in connection with the functions attributed herein to the memory system controller 115. Additionally or alternatively, the local memory 120 can be used as a cache for the memory system controller 115. For example, if data is read from or written to the memory devices 130, the data can be stored in the local memory 120, and the data can be used by the host system 105 (e.g., with reduced latency relative to the memory devices 130) for subsequent retrieval or manipulation (e.g., updating) in accordance with a cache policy, within the local memory 120.

[0029] Although FIG. 1 Although the example of the memory system 110 in FIG. 1 has been shown as including the memory system controller 115, in some cases the memory system 110 can not include the memory system controller 115. For example, the memory system 110 can additionally or alternatively rely on an external controller (e.g., implemented by the host system 105) or one or more local controllers 135, which can be respectively internal to the memory devices 130, to perform the functions attributed herein to the memory system controller 115. Generally speaking, one or more of the functions attributed herein to the memory system controller 115 can in some cases actually be performed by the host system 105, the local controller 135, or any combination thereof. In some cases, a memory device 130 that is at least partially managed by the memory system controller 115 can be referred to as a managed memory device. An example of a managed memory device is a managed NAND (MNAND) device.

[0030] Memory devices 130 can include one or more arrays of non-volatile memory cells. For example, memory devices 130 can include NAND (e.g., NAND flash) memory, ROM, phase change memory (PCM), resistive memory, ferroelectric random access memory (FeRAM), magnetic RAM (MRAM), NOR (e.g., NOR flash) memory, spin-transfer torque (STT)-MRAM, conductive-bridge RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), electrically erasable programable ROM (EEPROM), or any combination thereof. Additionally or alternatively, memory devices 130 can include one or more arrays of volatile memory cells. For example, memory devices 130 can include RAM memory cells, such as dynamic RAM (DRAM) memory cells and synchronous DRAM (SDRAM) memory cells.

[0031] In some examples, memory devices 130 can include (e.g., on the same die or within the same package) local controllers 135 that can perform operations on one or more memory cells of respective memory devices 130. Local controllers 135 can operate in conjunction with memory system controller 115, or can perform one or more functions attributed herein to memory system controller 115. For example, as shown in FIG. 1, memory device 130-a can include local controller 135-a, and memory device 130-b can include local controller 135-b. FIG. 1

[0032] In some cases, memory devices 130 can be or include NAND devices (e.g., NAND flash devices). Memory devices 130 can be or include memory dies 160. For example, in some cases, memory devices 130 can be a package that includes one or more dies 160. In some examples, a die 160 can be a piece of electronic-grade semiconductor (e.g., a silicon die cut from a silicon wafer) that is cut from a wafer. Each die 160 can include one or more planes 165, each plane 165 can include a respective set of blocks 170, where each block 170 can include a respective set of pages 175, each page 175 can include a set of memory cells.

[0033] ​In some cases, the NAND memory devices 130 can include memory cells configured to each store one bit of information, which can be referred to as single-level cells (SLCs). Additionally or alternatively, the NAND memory devices 130 can include memory cells configured to each store multiple bits of information, which can be referred to as multi-level cells (MLCs) if configured to each store two bits of information, triple-level cells (TLCs) if configured to each store three bits of information, quad-level cells (QLCs) if configured to each store four bits of information, or more generally as multi-level memory cells. Multi-level memory cells can provide greater storage density relative to SLC memory cells, but in some cases can involve narrower read or write margins or greater complexity of supporting circuitry.

[0034] In some cases, a plane 165 can refer to a group of blocks 170, and in some cases, parallel operations can be performed within different planes 165. For example, parallel operations can be performed on memory cells within different blocks 170, so long as the different blocks 170 are in different planes 165. In some cases, individual blocks 170 can be referred to as physical blocks, and a virtual block 180 can refer to a group of blocks 170 within which parallel operations can be performed. For example, parallel operations can be performed on blocks 170-a, 170-b, 170-c, and 170-d located in planes 165-a, 165-b, 165-c, and 165-d, respectively, and blocks 170-a, 170-b, 170-c, and 170-d can collectively be referred to as a virtual block 180. In some cases, a virtual block can include blocks 170 from different memory devices 130 (e.g., include blocks in one or more planes of memory device 130-a and memory device 130-b). In some cases, blocks 170 within a virtual block can have the same block address within their respective planes 165 (e.g., block 170-a can be “block 0” of plane 165-a, block 170-b can be “block 0” of plane 165-b, and so on). In some cases, performing parallel operations in different planes 165 can have one or more restrictions, such as that the parallel operations are performed on memory cells within different pages 175 that have the same page address within the respective planes 165 (e.g., related to command decoding, page address decoding circuitry, or other circuitry being shared across planes 165).

[0035] In some cases, a block 170 can include memory cells organized into rows (pages 175) and columns (e.g., strings, not shown). For example, memory cells in the same page 175 can share a common word line (e.g., be coupled with) and memory cells in the same string can share a common digit line (which can be alternatively referred to as a bit line) (e.g., be coupled with).

[0036] For some NAND architectures, memory cells can be read and programmed (e.g., written) at a first granularity level (e.g., at a page granularity level), but can be erased at a second granularity level (e.g., at a block granularity level). That is, a page 175 can be the smallest memory (e.g., set of memory cells) unit that can be programmed or read independently (e.g., in parallel as part of a single program or read operation), and a block 170 can be the smallest memory (e.g., set of memory cells) unit that can be erased independently (e.g., in parallel as part of a single erase operation). Further, in some cases, NAND memory cells can be erased before they can be overwritten with new data. Thus, for example, in some cases, a used page 175 can not be updated until the entire block 170 containing the page 175 is erased.

[0037] In some cases, the memory system controller 115 or local controller 135 can perform operations of the memory device 130 (e.g., as part of one or more media management algorithms), such as wear leveling, background refresh, garbage collection, cleaning, block scanning, health monitoring, or other operations, or any combination thereof. For example, within the memory device 130, a block 170 can have some pages 175 containing valid data and some pages 175 containing invalid data. To avoid waiting for all pages 175 in the block 170 to have invalid data in order to erase and reuse the block 170, an algorithm called “garbage collection” can be invoked such that the block 170 is erased and released as a free block for subsequent write operations. Garbage collection can refer to a set of media management operations including, for example, selecting a block 170 containing valid and invalid data, selecting pages 175 in the block containing valid data, copying the valid data from the selected pages 175 to a new location (e.g., a free page 175 in another block 170), marking the data in the previously selected pages 175 as invalid, and erasing the selected block 170. Thus, the number of blocks 170 that have been erased can increase such that more blocks 170 are available for storing subsequent data (e.g., data subsequently received from the host system 105).

[0038] The system 100 can include any number of non-transitory computer- readable media that support voltage detection for a managed memory system. For example, the host system 105, the memory system controller 115, or the memory device 130 (e.g., the local controller 135) can include or otherwise have access to one or more non-transitory computer-readable media that store instructions (e.g., firmware) for performing the functions attributed herein to the host system 105, the memory system controller 115, or the memory device 130. For example, such instructions, when executed by the host system 105 (e.g., the host system controller 106), the memory system controller 115, or the memory device 130 (e.g., the local controller 135), can cause the host system 105, the memory system controller 115, or the memory device 130 to perform one or more of the associated functions described herein.

[0039] In some cases, the memory system 110 can provide a managed memory system using the memory system controller 115, which can include, for example, one or more memory arrays and related circuitry in combination with a local (e.g., on-die or in-package) controller (e.g., the local controller 135). An example of a managed memory system is a managed NAND (MNAND) system.

[0040] In some cases, the memory system 110 can include circuitry, such as an overvoltage detector, for monitoring one or more supply voltages to the memory system 110 or voltages generated by the memory system 110 to determine whether the voltage has risen above an operating range. In some cases, the overvoltage detector can include the same voltage detector circuit as an undervoltage detector that has been tuned or manufactured to have a threshold value that is higher than an undervoltage detector used to determine whether a voltage has fallen below an operating range. Thus, the memory system 110 can monitor a voltage using an undervoltage detector having a threshold value that corresponds to a lower limit or lower operating point of an operating range for the monitored voltage and an overvoltage detector having a threshold value that corresponds to an upper limit or upper operating point of the operating range. Thus, the memory system 110 can determine whether a monitored voltage has risen above or fallen below an operating range, which can allow a health engine of the memory system 110 to initiate a safe mode or take other action in the event of an overvoltage event or in the event of an undervoltage event.

[0041] FIG. 2 An example of a system 200 that supports voltage detection for a managed memory system is shown in accordance with examples disclosed herein. The system 200 can be a host system 105, a memory system controller 115, or a memory device 130 (e.g., a local controller 135) as described with reference to FIG. 1. The system 200 can include a memory system 110, a memory system controller 115, and a health engine 120 as described with reference to FIG. 1. FIG. 1An example of the system 100 or aspects thereof is described. The system 200 can include a memory system 210 configured to store data received from a host system 205 and send data to the host system 205 upon request by the host system 205 using an access command (e.g., a read command or a write command). The system 200 can implement the memory system 110 and the host system 205 as described with reference to FIG. 1 Aspects of the system 100 are described. For example, the memory system 210 and the host system 205 can be examples of the memory system 110 and the host system 105, respectively.

[0042] The memory system 210 can include a memory device 240 for storing data transferred between the memory system 210 and the host system 205, for example, in response to receiving an access command from the host system 205, as described herein. The memory device 240 can include a NAND memory, a PCM, a self-selecting memory, a 3D cross-point, other chalcogenide-based memory, a FERAM, an MRAM, a NOR (e.g., NOR flash) memory, an STT-MRAM, a CBRAM, a RRAM, or an OxRAM, as described with reference to FIG. 1 The memory device 240 can include a NAND memory, a PCM, a self-selecting memory, a 3D cross-point, other chalcogenide-based memory, a FERAM, an MRAM, a NOR (e.g., NOR flash) memory, an STT-MRAM, a CBRAM, a RRAM, or an OxRAM, as described with reference to

[0043] The memory system 210 can include a memory controller 230 for controlling the direct transfer of data to and from the memory device 240, for example, storing data, retrieving data, and determining memory locations where data is to be stored and retrieved from. The memory controller 230 can communicate with the memory device 240 directly or via a bus (not shown) using a protocol specific to each type of memory device 240. In some cases, a single memory controller 230 can be used to control multiple memory devices 240 of the same or different types. In some cases, the memory system 210 can include multiple memory controllers 230, for example, a different memory controller 230 for each type of memory device 240. In some cases, the memory controller 230 can implement aspects of the local controller 135 as described with reference to FIG. 1 Aspects of the local controller 135 are described.

[0044] The memory system 210 can additionally include an interface 220 for communicating with the host system 205 and a buffer 225 for temporary storage of data transferred between the host system 205 and the memory device 240. The interface 220, the buffer 225, and the memory controller 230 can be used to convert data between the host system 205 and the memory device 240, for example, as illustrated by the data path 250, and can be referred to collectively as data path components.

[0045] The use of the buffer 225 to temporarily store data during transfer can allow the data to be buffered while the command is processed, thereby reducing latency between commands, and allowing for any data size associated with the command. This can also allow for processing of a burst of commands, and the buffered data can be stored or transmitted (or both) immediately after the burst stops. The buffer 225 can include relatively fast memory (e.g., some type of volatile memory such as SRAM or DRAM) or a hardware accelerator or both to allow for fast storage and retrieval of data to and from the buffer 225. The buffer 225 can include a data path switch component for bidirectional data transfer between the buffer 225 and other components.

[0046] The temporary storage of data within the buffer 225 can refer to the storage of data in the buffer 225 during execution of an access command. That is, the associated data can not be maintained in the buffer 225 after completion of the access command (e.g., can be overwritten with data for an additional access command). Additionally, the buffer 225 can be a non-cached buffer. That is, data can not be read from the buffer 225 directly by the host system 205. For example, a read command can be added to a queue without the operation of matching an address to an address already in the buffer 225 (e.g., without a cache address match or lookup operation).

[0047] The memory system 210 can additionally include a memory system controller 215 for executing commands received from the host system 205 and controlling the data path components when moving data. The memory system controller 215 can be a reference FIG. 1 The bus 235 can be used to transfer between system components.

[0048] In some cases, one or more queues (e.g., the command queue 260, the buffer queue 265, and the storage queue 270) can be used to control the processing of access commands and movement of corresponding data. This can be beneficial, for example, when more than one access command from the host system 205 is processed in parallel by the memory system 210. As an example of a possible implementation, the command queue 260, the buffer queue 265, and the storage queue 270 are depicted at the interface 220, the memory system controller 215, and the storage controller 230, respectively. However, if used, the queues can be located anywhere within the memory system 210.

[0049] Data transferred between the host system 205 and the memory device 240 can take a different path in the memory system 210 than non-data information (e.g., command status information). For example, system components in the memory system 210 can communicate with each other using the bus 235, while data can be transferred using a data path 250 through data path components instead of the bus 235. The memory system controller 215 can control how and whether data is transferred between the host system 205 and the memory device 240 through communication with data path components on the bus 235 (e.g., using a protocol specific to the memory system 210).

[0050] If the host system 205 transmits an access command to the memory system 210, the command can be received by the interface 220, e.g., according to a protocol (e.g., a UFS protocol or an eMMC protocol). Thus, the interface 220 can be considered a front end of the memory system 210. Upon receiving each access command, the interface 220 can transfer the command to the memory system controller 215, e.g., via the bus 235. In some cases, each command can be added to a command queue 260 by the interface 220 to transfer the command to the memory system controller 215.

[0051] The memory system controller 215 can determine that an access command has been received based on a transfer from the interface 220. In some cases, the memory system controller 215 can determine that an access command has been received by retrieving a command from the command queue 260. The command can be removed from the command queue 260 after it has been retrieved by, e.g., the memory system controller 215. In some cases, the memory system controller 215 can cause the interface 220 to remove a command from the command queue 260, e.g., via the bus 235.

[0052] Upon determining that an access command has been received, the memory system controller 215 can execute the access command. For a read command, this can refer to obtaining data from the memory device 240 and transmitting the data to the host system 205. For a write command, this can refer to receiving data from the host system 205 and moving the data to the memory device 240.

[0053] In either case, the memory system controller 215 can use the buffer 225 to temporarily store data received from or sent to the host system 205, among other uses. The buffer 225 can be considered a mid-end of the memory system 210. In some cases, buffer address management (e.g., pointers to address locations in the buffer 225) can be performed by hardware (e.g., dedicated circuitry) in the interface 220, the buffer 225, or the memory controller 230.

[0054] To handle a write command received from the host system 205, the memory system controller 215 can first determine whether the buffer 225 has sufficient available space to store data associated with the command. For example, the memory system controller 215 can determine, e.g., via firmware (e.g., controller firmware), an amount of space within the buffer 225 available to store data associated with a write command.

[0055] In some cases, the buffer queue 265 can be used to control a flow of commands associated with data stored in the buffer 225, including write commands. The buffer queue 265 can include access commands associated with data currently stored in the buffer 225. In some cases, a command in the command queue 260 can be moved by the memory system controller 215 to the buffer queue 265 and can remain in the buffer queue 265 while associated data is stored in the buffer 225. In some cases, each command in the buffer queue 265 can be associated with an address at the buffer 225. That is, a pointer indicating where data associated with each command is stored in the buffer 225 can be maintained. Using the buffer queue 265, multiple access commands can be received sequentially from the host system 205 and at least a portion of the access commands can be processed in parallel.

[0056] If the buffer 225 has sufficient space to store write data, the memory system controller 215 can cause the interface 220 to transmit an available indication (e.g., a “ready to transfer” indication) to the host system 205, e.g., according to a protocol (e.g., a UFS protocol or an eMMC protocol). When the interface 220 subsequently receives data associated with a write command from the host system 205, the interface 220 can transfer the data to the buffer 225 for temporary storage using the data path 250. In some cases, the interface 220 can obtain from the buffer 225 or the buffer queue 265 a location within the buffer 225 to store the data. The interface 220 can indicate to the memory system controller 215, e.g., via the bus 235, whether transfer of data to the buffer 225 has completed.

[0057] Once write data has been stored in the buffer 225 by the interface 220, the data can be transferred out of the buffer 225 and stored in the memory device 240. This can be done using the storage controller 230. For example, the memory system controller 215 can cause the storage controller 230 to retrieve data out of the buffer 225 using the data path 250 and transfer the data to the memory device 240. The storage controller 230 can be considered a back end of the memory system 210. The storage controller 230 can indicate to the memory system controller 215, e.g., via the bus 235, that transfer of data to the memory device 240 of the memory device has completed.

[0058] In some cases, a store queue 270 can be used to assist in the transfer of write data. For example, the memory system controller 215 can push a write command from the buffer queue 265 to the store queue 270 (e.g., via the bus 235) for processing. The store queue 270 can include an entry for each access command. In some examples, the store queue 270 can additionally include a buffer pointer (e.g., address) that can indicate where the data associated with the command is stored in the buffer 225 and a store pointer (e.g., address) that can indicate a location in the memory device 240 associated with the data. In some cases, the store controller 230 can obtain a location within the buffer 225 from which to obtain data from the buffer 225, the buffer queue 265, or the store queue 270. The store controller 230 can manage locations within the memory device 240 to store data (e.g., perform wear leveling, garbage collection, etc.). Entries can be added to the store queue 270, for example, by the memory system controller 215. For example, entries can be removed from the store queue 270 by the store controller 230 or the memory system controller 215 upon completion of the data transfer.

[0059] To process a read command received from the host system 205, the memory system controller 215 can likewise first determine whether the buffer 225 has sufficient available space to store data associated with the command. For example, the memory system controller 215 can determine an amount of space within the buffer 225 available to store data associated with a read command, for example, via firmware (e.g., controller firmware).

[0060] In some cases, the buffer queue 265 can be used to assist in buffering data associated with a read command in a manner similar to that discussed with respect to write commands. For example, if the buffer 225 has sufficient space to store read data, the memory system controller 215 can cause the store controller 230 to retrieve data associated with a read command from the memory device 240 and store the data in the buffer 225 for temporary storage using the data path 250. When the data transfer to the buffer 225 is complete, the store controller 230 can indicate to the memory system controller 215, for example, via the bus 235.

[0061] In some cases, the storage queue 270 can be used to assist in the transfer of read data. For example, the memory system controller 215 can push a read command to the storage queue 270 for processing. In some cases, the storage controller 230 can obtain, from the buffer 225 or the storage queue 270, a location within the memory device 240 from which to retrieve data. In some cases, the storage controller 230 can obtain, from the buffer queue 265, a location within the buffer 225 that stores data. In some cases, the storage controller 230 can obtain, from the storage queue 270, a location within the buffer 225 that stores data. In some cases, the memory system controller 215 can move a command processed by the storage queue 270 back to the command queue 260.

[0062] Once data has been stored in the buffer 225 by the storage controller 230, the data can be transferred out of the buffer 225 and sent to the host system 205. For example, the memory system controller 215 can cause the interface 220 to retrieve data out of the buffer 225 and transmit the data to the host system 205 using the data path 250, e.g., according to a protocol (e.g., a UFS protocol or an eMMC protocol). For example, the interface 220 can process a command from the command queue 260, and can indicate to the memory system controller 215, e.g., via the bus 235, that the transmission of data to the host system 205 has completed.

[0063] The memory system controller 215 can execute received commands according to some order (e.g., a first-in-first-out order, an order according to the command queue 260). For each command, the memory system controller 215 can cause data corresponding to the command to move into and out of the buffer 225, as discussed above. While data is moved into and stored within the buffer 225, the command can remain in the buffer queue 265. If processing of a command has completed (e.g., if data corresponding to an access command has been transferred out of the buffer 225), the command can be removed from the buffer queue 265, e.g., by the memory system controller 215. If a command is removed from the buffer queue 265, an address at which data associated with the command was previously stored can be available for storing data associated with a new command.

[0064] The memory system controller 215 can additionally be configured for operations associated with the memory devices 240. For example, the memory system controller 215 can perform or manage operations such as wear leveling operations, garbage collection operations, error control operations such as error detection operations or error correction operations, encryption operations, caching operations, media management operations, background refresh, health monitoring, and address translations between logical addresses (e.g., LBAs) associated with commands from the host system 205 and physical addresses (e.g., physical block addresses) associated with memory cells within the memory devices 240. That is, the host system 205 can issue a command indicating one or more LBAs, and the memory system controller 215 can identify one or more physical block addresses indicated by the LBAs. In some cases, one or more contiguous LBAs can correspond to non-contiguous physical block addresses. In some cases, the storage controller 230 can be configured to perform one or more of the above operations in conjunction with or in place of the memory system controller 215. In some cases, the memory system controller 215 can perform the functions of the storage controller 230, and the storage controller 230 can be omitted.

[0065] In some cases, the memory system 210 can include circuitry, such as an overvoltage detector, for monitoring one or more supply voltages to the memory system 210 or voltages generated by the memory system 210 to determine whether the voltage rises above an operating range. In some cases, the overvoltage detector can include the same voltage detector circuit as an undervoltage detector that has been tuned or manufactured to have a threshold value that is higher than an undervoltage detector used to determine whether a voltage has fallen below an operating range. Thus, the memory system 210 can monitor a voltage using an undervoltage detector having a threshold value corresponding to a lower limit or lower operating point of an operating range of the monitored voltage and an overvoltage detector having a threshold value corresponding to an upper limit or upper operating point of the operating range. Thus, the memory system 210 can determine whether a monitored voltage rises above or falls below an operating range, which can allow a health engine of the memory system 210 to initiate a safe mode or take other action in the event of an overvoltage event or in the event of an undervoltage event.

[0066] FIG. 3 An example of a block diagram 300 supporting voltage detection for a managed memory system is shown in accordance with the examples disclosed herein. The block diagram 300 can include a memory system 310, which can be in communication with a host system 305. The memory system 310 can be an example of the memory system 210. The host system 305 can be an example of the host system 205. The memory system 310 can execute commands received from the host system 305 using components such as a controller 315, a data path 350, and one or more memory devices 340, which can be examples of the components described with reference to the memory system 210. FIG. 2Examples of corresponding apparatus or circuitry are described. In some cases, the memory device can be an example of a non-volatile memory device, such as a NAND or 3D cross-point device. In other cases, the memory device 340 can be an example of a volatile memory device, such as a DRAM or FeRAM device.

[0067] In some examples, the memory system 310 can include a health engine 330. In some cases, the health engine 330 can be referred to as a safety island, or can be an example of a safety island. In some cases, the health engine 330 can be a separate component or logic of the memory system 310 (e.g., partitioned apart from other components of the memory system 310, such as the controller 315), or can be integrated into another component of the memory system 310, such as the controller 315.

[0068] The health engine 330 can perform aspects related to health monitoring of the memory system 310. For example, the health engine 330 can alert components of the memory system 310, such as the controller 315, the data path 350, or the memory device 340, of operating conditions, such as whether an operating voltage of the memory system 310 has fallen outside of a predetermined or acceptable operating range. The health engine 330 can issue an indication of the operating condition directly to the controller 315, the data path 350, or the memory device 340, or the health engine 330 can issue the indication to an intermediary component, such as the controller 315, which can notify other components of the memory system 310 accordingly or take action on behalf of the other components. In some cases, the health engine can transmit an indication of the operating condition to the host system 305.

[0069] The memory system 310 can include one or more voltage detectors 320. The voltage detectors 320 can monitor one or more operating or supply voltages of the memory system 310, such as the input voltage 325, to determine whether the supply voltage is outside of a predefined range, such as an operating range. In some cases, if the monitored supply voltage is outside of the operating range, the voltage detector 320 can issue a notification to the health engine 330. For example, the voltage detector 320 can include an under-voltage detector. The under-voltage detector can be a circuit with a voltage threshold, and can take as an input the supply voltage to be monitored. The under-voltage detector can be configured to output a first logic value (e.g., a logic “0”) when the monitored supply voltage is above the threshold, and can be configured to output a second logic value (e.g., a logic “1”) when the supply voltage is below the threshold. Thus, the under-voltage detector can be configured to notify the health engine when the monitored supply voltage falls below the threshold of the under-voltage detector.

[0070] In some cases, the voltage detector 320 can also include an overvoltage detector to determine whether the monitored supply voltage is above an operating range. The overvoltage detector can include the same voltage detector circuit as the undervoltage detector (e.g., the overvoltage detector can include a circuit configured to output a first logic value when the monitored supply voltage is above a threshold of the circuit and a second logic value when the monitored supply voltage is below the threshold). In some cases, the overvoltage detector can invert the output of the included voltage detector, e.g., by using an inverter coupled with the voltage detector. Thus, the output of the overvoltage detector can be the inverse of the output of the included voltage detector. Thus, the overvoltage detector can output a second logic value (e.g., a logic “1”) if the monitored supply voltage is above the threshold of the voltage detector, and a first logic value (e.g., a logic “0”) if the monitored supply voltage is below the threshold of the undervoltage detector.

[0071] In some cases, the undervoltage detector and the overvoltage detector can be used together to determine whether a supply voltage is outside of an operating range. For example, the operating range of a supply voltage can be a range of acceptable or safe values of voltage supplied to one or more components of the memory system 310. Thus, the operating range can have a lower threshold (e.g., corresponding to a lower value of the operating range) and an upper threshold (e.g., corresponding to an upper value of the operating range). The undervoltage detector having a threshold corresponding to the lower threshold can be used to determine whether a supply voltage is below the operating range, while the overvoltage detector having a threshold corresponding to the upper threshold can be used to determine whether a supply voltage is above the operating range.

[0072] In some cases, different components of the memory system 310 can use different supply voltages having different operating ranges. In such cases, the memory system 310 can include circuitry, e.g., a voltage generator 335, to generate one or more supply voltages for components of the memory system 310. The voltage generator 335 may, for example, receive one or more input voltages 325 from the host system 305 and generate one or more additional supply voltages for use by the memory system 310. Each of the additional supply voltages can have an associated operating range. Thus, the voltage detector 320 can include undervoltage detectors and overvoltage detectors for multiple supply voltages. That is, the voltage detector 320 can include a first set of voltage detectors including an undervoltage detector and an overvoltage detector having thresholds corresponding to a first operating range of a first supply voltage, and a second set of voltage detectors including an undervoltage detector and an overvoltage detector having thresholds corresponding to a second operating range of a second supply voltage (e.g., generated by the voltage generator 335).

[0073] In some examples, if the voltage detector 320 determines that the supply voltage is outside of the corresponding operating range, the voltage detector 320 can issue a notification to the health engine 330. For example, the notification can indicate that the supply voltage is above the operating range (e.g., the voltage detector 320 detected an overvoltage event). Accordingly, the health engine 330 can initiate a safe mode for the memory device. As part of initiating the safe mode, the health engine 330 can place the controller 315 in a safe state.

[0074] In some cases, while in the safe mode, the health engine 330 can delay the transfer of data or other information between components of the memory system 310. For example, the health engine 330 can issue an indication to the memory device 340 to delay or interrupt the execution of read or write commands or delay the execution of other data management operations (e.g., garbage collection). In some cases, the controller 315 can delay issuing commands or status checks to the memory device 340. In some cases, the health engine 330 can issue an indication or command to interrupt actions or commands that are being executed or using the data path 350. Additionally or alternatively, while in the safe mode, the health engine 330 can delay the transfer of data or other information between the memory system 310 and the host system 305. For example, the health engine 330 can transmit a notification to the host system 305 that the memory system 310 is in the safe mode. Accordingly, the host system 305 can delay transmitting commands, data, or both to the memory system 310. In some cases, if the memory system 310 initiates the safe mode after receiving a command for data (e.g., a read command) but before returning the data to the host system 305, the memory system 310 can delay or abort transmitting the data to the host system 305 (e.g., the command can not be completed).

[0075] FIG. 4 An example of a flow diagram 400 that supports voltage detection for a managed memory system is shown in accordance with examples as disclosed herein. The flow diagram 400 can be implemented by a memory system 410 and a host system 405, such as the memory system and host system described with reference to FIG. 1 , 2 or 3. The memory system 410 can include one or more voltage detectors 420, a health engine 430, a controller 415, a data path 450, and one or more memory devices 440, which can each be examples of the corresponding devices and circuits described with reference to FIG. 3 In some examples, the data path 450 can be an example of or can include the buffer 225 of FIG. 2 In the following description of the flow diagram 400, the operations can be performed in a different order than shown. For example, certain operations can also be omitted from the flow diagram 400, or other operations can be added to the flow diagram 400.

[0076] In some examples, the flowchart 400 can include monitoring one or more supply voltages. For example, at 425, the voltage detector 420 can monitor one or more supply voltages. The voltage detector 420 can include an overvoltage detector and an undervoltage detector. In non-limiting examples, each voltage detector can be configured to take as input a supply voltage to be monitored, and can output an indication of whether the monitored supply voltage is below or above a threshold value associated with the voltage detector. For example, the voltage detector 420 can include a first voltage detector that can be an example of an undervoltage detector and a second voltage detector that can be an example of an overvoltage detector.

[0077] The first voltage detector can have a first configuration, which can include a configuration of one or more resistors. The one or more resistors can be trimmed or otherwise manufactured to have a first set of resistance values. The first voltage detector can have a first threshold value, which can be generated or determined by the first set of resistance values (e.g., the first threshold value can be determined by the trimming of the first voltage detector). Additionally or alternatively, the second voltage detector can have a second configuration, which can include a configuration of one or more resistors having a second set of resistance values. In other words, both the first voltage detector and the second voltage detector can use the same or similar configuration of resistors, but the resistors of the first voltage detector and the resistors of the second voltage detector can have different trimming or can be trimmed by fuses, which can result in a different set of resistance values. Accordingly, the second voltage detector can have a second threshold value, which can be different than the first threshold value. The second voltage detector can include an inverter or other circuitry for inverting the output of the second voltage detector. That is, the second voltage detector can include an undervoltage detector having a second threshold value, and can invert the output of the undervoltage detector to determine whether the monitored supply voltage is above the second threshold value.

[0078] In some cases, the flowchart 400 can include determining whether one or more supply voltages satisfy a respective operating range. For example, at 435, the undervoltage detector and the overvoltage detector of the voltage detector 420 can monitor a supply voltage. The undervoltage detector can have a first threshold value corresponding to a lower limit or lower value of the operating range, while the overvoltage detector can have a second threshold value corresponding to an upper limit or upper value of the operating range. In some cases, the voltage detectors can determine that the supply voltage exceeds an upper operating point of the corresponding operating range. For example, the undervoltage detector can set a first flag indicating that the supply voltage exceeds the first threshold value, and the overvoltage detector can set a second flag indicating that the supply voltage exceeds the second threshold value. In some cases, the overvoltage detector can invert the second flag (e.g., using an inverter).

[0079] In some cases, if the voltage detector 420 determines that at least one supply voltage is outside of the operating range (e.g., if the supply voltage is above the operating range), the flowchart 400 can include issuing an indication that the supply voltage is outside of the operating range. For example, at 445, the voltage detector 420 can issue the indication to the health engine. In some examples, the indication transmitted to the health engine 430 can be an indication of an overvoltage event (e.g., if the voltage detector 420 determines that the supply voltage is above the operating range). In other examples, the indication transmitted to the health engine 430 can be an indication of an undervoltage event (e.g., if the voltage detector 420 determines that the supply voltage is below the operating range).

[0080] In some examples, the flowchart 400 can include initiating a safe mode of the memory system 410. For example, at 455, the health engine 430 can initiate the safe mode in response to receiving the indication of the overvoltage event at 445. In some cases, when in the safe mode, the health engine 430 can delay the transfer of data or other information between components of the memory system 410.

[0081] For example, the flowchart 400 can include issuing an indication of the safe mode to the controller 415. In some cases, at 460, the health engine 430 can issue the indication to the controller 415. In some cases, the indication can include an interrupt to the controller 415. The flowchart 400 can include delaying one or more commands. For example, at 465, the controller 415 can delay or interrupt the execution of access commands, such as read or write commands, received from the host system 405. For example, if the memory system 410 receives a command from the host system 405 while in the safe mode, the controller 415 can ignore the command or delay operations related to the command (e.g., the controller 415 can leave the command in a command queue). Additionally or alternatively, other data management operations, such as garbage collection, can be suspended or delayed by the controller 415 while in the safe mode.

[0082] Additionally or alternatively, the flowchart 400 can include issuing an indication of the safe mode to the data path 450. In some cases, at 470, the health engine 430 can issue the indication to the data path 450. For example, at 475, the indication can be issued or sent to the data path 450, which can delay or suspend any data transfer operations. For example, the data path 450 can suspend data transfer operations between the data path 450 and an interface (e.g., the interface 220) of the memory system 410 or the memory device 440. In some cases, the indication at 460 or 470 can include aborting commands that are in progress in the controller 315 or the data path 450.

[0083] In some cases, flowchart 400 can include issuing an indication of a safe mode to memory device 440. For example, at 480, health engine 430 can issue the indication to memory device 440. Thus, at 485, execution of access commands can be delayed. For example, memory device 440 can delay execution of read or write commands received from controller 415 or a memory controller (e.g., storage controller 230) shown. FIG. 2

[0084] In some cases, flowchart 400 can include issuing an indication of a safe mode to host system 405. For example, at 490, health engine 430 can issue the indication to host system 405. Thus, host system 405 can delay transmission of commands, data, or both to memory system 410. In some cases, if memory system 410 initiates a safe mode after receiving a command for data (e.g., a read command) but before returning the data to host system 405, memory system 410 can delay or abort transmission of data to host system 405 (e.g., the command can not be completed).

[0085] Aspects of flowchart 400 can be implemented by a controller and other components. Additionally or alternatively, aspects of flowchart 400 can be implemented as instructions stored in memory (e.g., firmware stored in memory coupled to memory system 410, host system 405, or both). For example, the instructions, when executed by a controller, can cause the controller to perform the operations of flowchart 400.

[0086] FIG. 5 An example of a block diagram 500 that supports voltage detection for a managed memory system is shown in accordance with examples disclosed herein. Block diagram 500 can be an example of an under-voltage detector 520-a and an over-voltage detector 520-b, which can be included in voltage detector 320 or voltage detector 420 described with reference to FIG. 3 and 4 .

[0087] In some cases, under-voltage detector 520-a can monitor a supply voltage of a memory system, for example, with reference to FIG. 3 and 4 ​The memory system 310 or the memory system 410 is described. The undervoltage detector 520-a can monitor the input 515-a (e.g., a supply voltage) to determine whether the supply voltage is below a first threshold of the undervoltage detector 520-a. The undervoltage detector 520-a can generate an output 525-a indicating whether the monitored supply voltage is below the first threshold. For example, the output 525-a can be a first logic value (e.g., a logic “0”) if the monitored supply voltage is above the first threshold, and a second logic value (e.g., a logic “1”) if the monitored supply voltage is below the first threshold. In some cases, the output 525-a can be provided or issued to a health engine of the memory system, e.g., with reference to FIG. 3 and 4 The health engine 330 or the health engine 430 is described.

[0088] The undervoltage detector 520-a can include a voltage detector circuit 535-a that can detect whether the input 515-a is below or above a voltage relative to a bias voltage 540-a. The voltage detector circuit 535 can include a comparator that compares an input voltage to a reference voltage (e.g., a threshold voltage) and outputs an indication, e.g., a signal, of whether the input voltage exceeds the reference voltage. In some cases, the voltage detector circuit can include a set of resistors configured to generate the reference voltage for input to the comparator.

[0089] In some cases, a threshold (e.g., the first threshold) of the undervoltage detector 520-a can be determined by or depend on a configuration of the undervoltage detector. For example, the undervoltage detector 520-a can include a set of resistors, e.g., the resistor 505-a and the resistor 510-a. The configuration of the undervoltage detector 520-a can indicate an arrangement or trimming of active or inactive resistors. For example, each of the resistors 505-a and 505-b can include a plurality of resistors, and the configuration of the undervoltage detector 520-a can indicate that a subset of resistors of the resistor 505-a or a subset of resistors of the resistor 510-a can be active. For example, each of the resistors 505-a and 505-b can include a plurality of resistors, and each resistor can be activated or deactivated (e.g., shorted) via a fuse or an anti-fuse. In some cases, a value of the first threshold can depend on which resistors are active and which resistors are inactive, which can set the bias voltage 540-a relative to the reference voltage 545. Thus, the first threshold can be determined by or depend on the configuration of the undervoltage detector 520-a.

[0090] Additionally or alternatively, the configuration of the undervoltage detector 520-a can include a trim setting or trimming of the resistor 505-a or the resistor 510-a. For example, during manufacturing, the resistance value of a resistor can be adjusted or tuned by trimming the resistor (e.g., using laser trimming), such as by removing or altering portions of material of the resistor. Thus, the resistance of the resistor 505-a and the resistor 510-a can be selected or tuned during manufacturing. In some cases, the value of the first threshold can depend on the resistance values of the resistor 505-a and the resistor 510-a. Thus, the first threshold can be determined by or depend on the configuration of the undervoltage detector 520-a.

[0091] The overvoltage detector 520-b can monitor a supply voltage of a memory system input to the overvoltage detector 520-b via the input 515-b to determine whether the supply voltage is above a second threshold of the overvoltage detector 520-b. The overvoltage detector 520-b can generate an output 525-b indicating whether the monitored supply voltage is above the second threshold. In some cases, the overvoltage detector 520-b can include an inverter 530 for inverting the output 525-b. For example, the overvoltage detector 520-b can be configured to output a first logic value (e.g., a logic “0”) when the monitored supply voltage is above the second threshold, and can output a second logic value (e.g., a logic “1”) when the monitored supply voltage is below the second threshold. Thus, the inverter 530 can invert the output of the overvoltage detector 520-b such that the output 525-b can be the second logic value (e.g., a logic “1”) when the monitored supply voltage is above the second threshold, and can be the first logic value (e.g., a logic “0”) when the monitored supply voltage is below the second threshold.

[0092] In some cases, the overvoltage detector 520-b can include the same or similar voltage detector circuit 535-b and the same or similar set of resistors, including resistor 505-b and resistor 510-b, as the undervoltage detector 520-a. For example, the voltage detector circuit 535-b can have the same size, structure, or transistor layout as the voltage detector circuit 535-a, can include a bias voltage 540-b, and can be a copy of the voltage detector circuit 535-a. Additionally, the resistors 505-b and 510-b can include the same number of resistors as the resistors 505-a and 510-a, respectively, and each resistor can have the same resistance value (e.g., before trimming or fuses are programmed). That is, the overvoltage detector 520-b and the undervoltage detector 520-a can include the same or similar circuitry. However, the overvoltage detector 520-b can have a higher threshold (e.g., a second threshold) relative to the undervoltage detector 520-a. For example, the overvoltage detector 520-b can have a second configuration, such as a different arrangement of active and passive resistors than the first configuration. Additionally or alternatively, the resistors 505-b and 510-b can have different trim (e.g., can have been trimmed or tuned to different resistance values during manufacturing) than the resistors 505-a and 510-a.

[0093] For example, during manufacturing, the voltage (e.g., the supply voltage input to the inputs 515-a and 515-b) can vary, and the outputs 525-a and 525-b can be monitored to determine the configuration of the resistors 505-a, 510-a, 505-b, and 510-b to provide the first threshold and the second threshold. In one example, one or more settings of a fuse or antifuse can be configured to test the first threshold or the second threshold, and the fuse or antifuse can be programmed according to the settings associated with the desired values of the first threshold and the second threshold.

[0094] FIG. 6 A block diagram 600 of a memory system 620 that supports voltage detection for a managed memory system is shown, in accordance with examples disclosed herein. The memory system 620 can be an example of aspects of the memory systems described with reference to FIGS. 1-5 The memory system 620, or various components thereof, can be an example of means for performing various aspects of voltage detection for a managed memory system described herein. For example, the memory system 620 can include a voltage monitoring component 625, a voltage determination component 630, a security component 635, a voltage management component 640, a signaling component 645, or any combination thereof. Each of these components can communicate, directly or indirectly, with one another (e.g., via one or more buses).

[0095] The voltage monitoring component 625 can be configured as or otherwise support means for monitoring one or more supply voltages of a memory device. The voltage determination component 630 can be configured as or otherwise support means for determining, using a first voltage detector having a first configuration and a second voltage detector having a second configuration, whether the one or more supply voltages satisfy respective ranges based at least in part on monitoring the one or more supply voltages. The safety component 635 can be configured as or otherwise support means for initiating, at a health engine of the memory device, a safety mode of the memory device based at least in part on determining that a supply voltage of the one or more supply voltages exceeds an upper operating point of a respective range.

[0096] In some examples, the voltage determination component 630 can be configured as or otherwise support means for setting a first flag indicating that a supply voltage exceeds a first threshold of the first voltage detector. In some examples, the voltage determination component 630 can be configured as or otherwise support means for setting a second flag indicating that a supply voltage exceeds a second threshold of the second voltage detector. In some examples, the voltage management component 640 can be configured as or otherwise support means for inverting the second flag, where determining that a supply voltage exceeds an upper operating point of a respective range is based at least in part on inverting the second flag.

[0097] In some examples, the signaling component 645 can be configured as or otherwise support means for signaling, to a health engine of the memory device, an indication of the one or more supply voltages.

[0098] In some examples, the signaling component 645 can be configured as or otherwise support means for transmitting, to a host device, an indication of a safety mode based at least in part on determining that a supply voltage exceeds an upper operating point of a respective range.

[0099] In some examples, the signaling component 645 can be configured as or otherwise support means for signaling, from a health engine to a controller of the memory device, an indication of a safety mode based at least in part on determining that a supply voltage exceeds an upper operating point of a respective range.

[0100] In some examples, the signaling component 645 can be configured as or otherwise support means for sending an interrupt to a processor based at least in part on determining that a supply voltage exceeds an upper operating point of a respective range.

[0101] In some examples, the safety component 635 can be configured as or otherwise support means for delaying a data transfer between the memory device and a host device based at least in part on determining that a supply voltage exceeds an upper operating point of a respective range.

[0102] In some instances, the first voltage detector and the second voltage detector comprise a corresponding plurality of resistors. In some instances, a first configuration comprises a first active resistor subset of the corresponding plurality of resistors, and a second configuration comprises a second active resistor subset of the corresponding plurality of resistors.

[0103] In some instances, the voltage management component 640 may be configured or otherwise support a component for receiving a first supply voltage of the one or more supply voltages. In some instances, the voltage management component 640 may be configured or otherwise support a component for receiving a second supply voltage of the one or more supply voltages. In some instances, the voltage management component 640 may be configured or otherwise support a component for generating one or more additional supply voltages of the one or more supply voltages using the second supply voltage, wherein each of the one or more additional supply voltages is less than the second supply voltage.

[0104] In some instances, voltage monitoring component 625 may be configured to, or otherwise support, components for monitoring the one or more additional supply voltages. In some instances, voltage determination component 630 may be configured to, or otherwise support, components for determining, at least in part, whether the one or more additional supply voltages meet a corresponding range based on monitoring the one or more additional supply voltages.

[0105] FIG. 7 A flowchart illustrating an example disclosed herein shows a method 700 for supporting voltage detection in a managed memory system. Operation of method 700 can be implemented by the memory system or its components described herein. For example, operation of method 700 can be described by reference to... FIGS. 1-6 The described memory system performs the function. In some instances, the memory system can execute a set of instructions. Functional elements of the control device perform the described function. Alternatively, the memory system may use dedicated hardware to perform aspects of the described function.

[0106] At 705, the method may include monitoring one or more supply voltages of the memory device. Operation 705 may be performed according to the examples disclosed herein. In some examples, aspects of operation 705 may be referenced... FIG. 6 The voltage monitoring component 625 described herein performs this function.

[0107] At 710, the method may include using a first voltage detector having a first configuration and a second voltage detector having a second configuration, at least in part based on monitoring the one or more supply voltages, to determine whether the one or more supply voltages meet a corresponding range. Operation 710 may be performed according to the examples disclosed herein. In some examples, aspects of operation 710 may be referenced from... FIG. 6 The voltage determination component 630 described is executed.

[0108] At 715, the method can include initiating, at a health engine of a memory device, a safe mode of the memory device based at least in part on determining that a supply voltage of the one or more supply voltages exceeds an upper operating point of a respective range. Operation 715 can be performed in accordance with examples as disclosed herein. In some examples, aspects of the operation 715 can be performed by the safe component 635 described with reference to FIG. 6 as described.

[0109] In some examples, an apparatus described herein can perform one or more methods, such as the method 700. The apparatus can include features, circuitry, logic, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for performing aspects of the disclosure, or any combination thereof:

[0110] Aspect 1 : An apparatus comprising features, circuitry, logic, means, or instructions for, or any combination thereof: monitoring one or more supply voltages of a memory device; determining, using a first voltage detector having a first configuration and a second voltage detector having a second configuration, whether the one or more supply voltages satisfy a respective range based at least in part on monitoring the one or more supply voltages; and initiating, at a health engine of the memory device, a safe mode of the memory device based at least in part on determining that a supply voltage of the one or more supply voltages exceeds an upper operating point of the respective range.

[0111] Aspect 2: The apparatus of aspect 1, further comprising operations, features, circuitry, logic, means, or instructions for, or any combination thereof: setting a first flag indicating that the supply voltage exceeds a first threshold of the first voltage detector; setting a second flag indicating that the supply voltage exceeds a second threshold of the second voltage detector; and inverting the second flag, wherein determining that the supply voltage exceeds the upper operating point of the respective range is based at least in part on inverting the second flag.

[0112] Aspect 3 : The apparatus of any of aspects 1 -2, further comprising operations, features, circuitry, logic, means, or instructions for, or any combination thereof: issuing an indication of the one or more supply voltages to the health engine of the memory device.

[0113] Aspect 4: The apparatus of any of aspects 1 -3, further comprising operations, features, circuitry, logic, means, or instructions for, or any combination thereof: transmitting an indication of the safe mode to a host device based at least in part on determining that the supply voltage exceeds the upper operating point of the respective range.

[0114] Aspect 5: The apparatus of any one of aspects 1 through 4, further comprising operations, features, circuitry, logic, means, or instructions for, or any combination of the same, issuing an indication of the safe mode from the health engine to a controller of the memory device based at least in part on determining that the supply voltage exceeds the upper operating point of the respective range.

[0115] Aspect 6: The apparatus of any one of aspects 1 through 5, further comprising operations, features, circuitry, logic, means, or instructions for, or any combination of the same, sending an interrupt to the processor based at least in part on determining that the supply voltage exceeds the upper operating point of the respective range.

[0116] Aspect 7: The apparatus of any one of aspects 1 through 6, further comprising operations, features, circuitry, logic, means, or instructions for, or any combination of the same, delaying a data transfer between the memory device and a host device based at least in part on determining that the supply voltage exceeds the upper operating point of the respective range.

[0117] Aspect 8: The apparatus of any one of aspects 1 through 7, further comprising operations, features, circuitry, logic, means, or instructions for, or any combination of the same, the first voltage detector and the second voltage detector comprising a respective plurality of resistors, the first configuration comprising a first active subset of resistors of the respective plurality of resistors, and the second configuration comprising a second active subset of resistors of the respective plurality of resistors.

[0118] Aspect 9: The apparatus of any one of aspects 1 through 8, further comprising operations, features, circuitry, logic, means, or instructions for, or any combination of the same, receiving a first supply voltage of the one or more supply voltages; receiving a second supply voltage of the one or more supply voltages; and generating one or more additional supply voltages of the one or more supply voltages using the second supply voltage, wherein each additional supply voltage of the one or more additional supply voltages is less than the second supply voltage.

[0119] Aspect 10: The apparatus of aspect 9, further comprising operations, features, circuitry, logic, means, or instructions for, or any combination of the same, monitoring the one or more additional supply voltages, and determining whether the one or more additional supply voltages satisfy a respective range based at least in part on monitoring the one or more additional supply voltages.

[0120] It should be noted that the methods described above describe possible implementations, and that the operations and the steps can be rearranged or otherwise modified and that other implementations are possible. Furthermore, portions from two or more of the methods can be combined.

[0121] Information and signals described herein can be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that can be referenced throughout the above description can be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some drawings can illustrate signals as single signals; however, such signals can represent a bus of signals, where buses can have a variety of bit widths.

[0122] The terms“in electronic communication,”“in conductive contact,”“connected,” and“coupled” can refer to a relationship between components in which a signal can flow from one component to another. Components are considered to be in electronic communication with each other (or in conductive contact with each other, or connected to each other, or coupled to each other) if there is any conductive path that can support the flow of a signal between the components at any time. The conductive path between components that are in electronic communication with each other (or in conductive contact with each other, or connected to each other, or coupled to each other) can be an open circuit or a closed circuit at any given time, based on the operation of the device that includes the connected components. The conductive path between connected components can be a direct conductive path between the components, or the conductive path between connected components can be an indirect conductive path that can include intermediate components such as switches, transistors, or other components. In some examples, the flow of signals between connected components can be interrupted for a period of time, for example, using one or more intermediate components such as switches or transistors.

[0123] The term“coupled” refers to the condition of components moving from an open circuit relationship between the components, in which a signal cannot currently pass between the components through a conductive path, to a closed circuit relationship between the components, in which a signal can pass between the components through a conductive path. If a component, such as a controller, couples other components together, the component causes a change that allows a signal to flow between the other components through a conductive path that previously did not allow signal flow.

[0124] The term“isolated” refers to a relationship between components in which a signal cannot currently flow between the components. Components are isolated from each other if there is a break in the circuit between the components. Components that are isolated from each other by a switch positioned between the two components are isolated from each other when the switch is open. If a controller isolates two components, the controller effects a change that prevents a signal from flowing between the components using a conductive path that previously permitted signal flow.

[0125] The terms“if,”“when,”“based on,” or“based at least in part on” can be used interchangeably. In some examples, the terms“if,”“when,”“based on,” or“based at least in part on” can be used interchangeably if the terms are used to describe a conditional relationship between two or more processes, actions, or process steps.

[0126] Devices including memory arrays discussed herein can be formed on a semiconductor substrate, such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some examples, the substrate is a semiconductor wafer. In some other examples, the substrate can be a silicon-on-insulator (SOI) substrate, such as a silicon-on-glass (SOG) or a silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate, or sub-regions of the substrate, can be controlled by doping using various chemicals including, but not limited to, phosphorus, boron, or arsenic. Doping can be performed during initial formation or growth of the substrate, by ion implantation, or by any other doping method.

[0127] Switching components or transistors discussed herein can represent field effect transistors (FETs) and include three-terminal devices including a source, a drain, and a gate. The terminals can be connected to other electronic elements by conductive materials, such as metals. The source and drain can be conductive and can include heavily doped (e.g., degenerate) semiconductor regions. The source and drain can be separated by a lightly doped semiconductor region or channel. If the channel is n-type (i.e., majority carriers are electrons), the FET can be referred to as an n-type FET. If the channel is p-type (i.e., majority carriers are holes), the FET can be referred to as a p-type FET. The channel can be capped by an insulating gate oxide. The channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type or p-type FET, respectively, can cause the channel to become conductive. A transistor can be "turned on" or "activated" if a voltage greater than or equal to the threshold voltage of the transistor is applied to the transistor gate. A transistor can be "turned off" or "deactivated" if a voltage less than the threshold voltage of the transistor is applied to the transistor gate.

[0128] The description set forth herein, in connection with the appended drawings, describes example configurations and does not represent all the examples that can be implemented or that are within the scope of the claims. The term "exemplary" used herein means "serving as an example, instance, or illustration," and not "preferred" over other examples. The detailed description includes specific details for the purpose of providing an understanding of the described techniques. These techniques, however, can be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form in order to avoid obscuring the concepts of the described examples.

[0129] In the appended figures, similar components or features can have similar reference labels. Further, various components of the same type can be distinguished by following the convention of using a first reference label and then distinguishing among the identical components with a second reference label utilizing a prime notation. For example, one exemplary device can use a reference label "100" and another device of the same type can use a reference label "100'". If only the first reference label is used in the specification, the detail can be applicable to any one among several similar components and the detail description omits the use of the prime. Constituent components that do not require a prime notation can simply use the primary reference label.

[0130] The functions described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions can be stored on or transferred over as one or more instructions or code on a computer-readable medium. Other examples and implementations are within the scope of the disclosure and appended claims. For example, due to the nature of software, functions described above can be implemented using software executed by a processor, hardware, firmware, hardwiring, or combinations of any of these. Features implementing functions can also be physically located at various positions, including being distributed such that portions of functions are implemented at different physical locations.

[0131] The various illustrative blocks and components described in connection with the disclosure herein can be implemented or performed with a general-purpose processor, a DSP, an ASIC, an FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein, for example. The general-purpose processor can be a microprocessor, but in the alternative, the processor can be any processor, controller or controller, microcontroller, or state machine. The processor can be implemented as a combination of a

[0132] As used herein, including in the claims, “or” as used in a list of items (for example, a list of items prefaced by a phrase such as “at least one of’ or “one or more of’) indicates an inclusive list such that, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Also, as used herein, the phrase “based on” shall not be construed as a reference to a closed set of conditions. For example, an exemplary step that is described as “based on condition A” can be based on both a condition A and a condition B without departing from the scope of the present disclosure. In other words, as used herein, the phrase “based on” shall be construed in the same manner as the phrase “based at least in part on.”

[0133] Computer-readable media includes both non-transitory computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A non-transitory storage medium can be any available medium that can be accessed by a general purpose or special purpose computer. By way of example, and not limitation, non-transitory computer-readable media can comprise RAM, ROM, electrically erasable programmable read only memory (EEPROM), compact disk (CD) ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other non-transitory medium that can be used to carry or store desired program elements in the form of instructions or data structures and that can be accessed by a general-purpose or special-purpose computer, or a general-purpose or special-purpose processor. Also, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. Disk and disc, as used herein, include CD, laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above are also included within the scope of computer-readable media.

[0134] The description herein is presented to enable any person skilled in the art to make or use the disclosure. Modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein can be applied to other variations without departing from the scope of the disclosure. Thus, the present disclosure is not intended to be limited to the examples described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A memory device, comprising: a memory device; a controller coupled with the memory device, the controller configured to couple with a host device and perform a mapping between a logical address received from the host device and a physical address of the memory device; a first voltage detector having a first configuration and a second voltage detector having a second configuration, the first and second voltage detectors coupled with the memory device and configured to monitor one or more supply voltages of the memory device and, based at least in part on monitoring the one or more supply voltages, determine whether the one or more supply voltages satisfy respective ranges, wherein: the first voltage detector is configured to set a first flag indicating that a supply voltage of the one or more supply voltages exceeds a first threshold of the first voltage detector; the second voltage detector is configured to set a second flag indicating that the supply voltage exceeds a second threshold of the second voltage detector; and the second voltage detector is configured to invert the second flag; and a health engine coupled with the first voltage detector, the second voltage detector, and the controller, the health engine configured to initiate a safe mode of at least one of the controller or the memory device based at least in part on determining that the supply voltage exceeds an upper operating point of the respective range, wherein determining that the supply voltage exceeds the upper operating point of the respective range is based at least in part on the second voltage detector inverting the second flag.

2. The memory device of claim 1, wherein the first voltage detector and the second voltage detector are configured to issue an indication of the one or more supply voltages to the health engine.

3. The memory device of claim 1, wherein to initiate the safe mode, the health engine is configured to transmit an indication of the safe mode to the host device based at least in part on determining that the supply voltage exceeds the upper operating point of the respective range.

4. The memory device of claim 1, wherein the controller comprises a processor and code executable by the processor.

5. The memory device of claim 4, wherein to initiate the safe mode, the health engine is further configured to send an interrupt to the processor based at least in part on determining that the supply voltage exceeds the upper operating point of the respective range.

6. The memory device of claim 4, wherein to initiate the safe mode, the health engine is further configured to set a flag accessible by the code based at least in part on determining that the supply voltage exceeds the upper operating point of the respective range.

7. The memory device of claim 1, wherein to initiate the safe mode, the health engine is further configured to delay data transfers between the memory device and the host device based at least in part on determining that the supply voltage exceeds the upper operating point of the respective range.

8. The memory device of claim 1, wherein the first voltage detector and the second voltage detector comprise a respective plurality of resistors, wherein the first configuration comprises a first active subset of resistors of the respective plurality of resistors and the second configuration comprises a second active subset of resistors of the respective plurality of resistors.

9. The memory device of claim 1, wherein the controller is configured to: receive the one or more supply voltages; and generate one or more additional supply voltages using the one or more supply voltages.

10. The memory device of claim 9, wherein a third voltage detector and a fourth voltage detector are further configured to monitor the one or more additional supply voltages and, based at least in part on monitoring the one or more additional supply voltages, determine whether the one or more additional supply voltages satisfy respective ranges.

11. The memory device of claim 1, wherein a circuit block of the first voltage detector matches a circuit block of the second voltage detector.

12. A non-transitory computer-readable medium storing code comprising instructions that, when executed by a processor of an electronic device, cause the electronic device to: monitor one or more supply voltages of a memory device; using a first voltage detector having a first configuration and a second voltage detector having a second configuration, determine, based at least in part on monitoring the one or more supply voltages, whether the one or more supply voltages satisfy respective ranges; set a first flag indicating that a supply voltage of the one or more supply voltages exceeds a first threshold of the first voltage detector; set a second flag indicating that the supply voltage exceeds a second threshold of the second voltage detector; invert the second flag; and at a health engine of the memory device, initiate a safe mode of the memory device based at least in part on determining that the supply voltage exceeds an upper operating point of the respective range, wherein determining that the supply voltage exceeds the upper operating point of the respective range is based at least in part on inverting the second flag.

13. The non-transitory computer-readable medium of claim 12, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: issue an indication of the one or more supply voltages to the health engine of the memory device.

14. The non-transitory computer-readable medium of claim 12, wherein to initiate the safe mode, the instructions, when executed by the processor of the electronic device, further cause the electronic device to: transmit an indication of the safe mode to a host device based at least in part on determining that the supply voltage exceeds the upper operating point of the respective range.

15. The non-transitory computer-readable medium of claim 12, wherein to initiate the safe mode, the instructions, when executed by the processor of the electronic device, further cause the electronic device to: ​ based at least in part on determining that the supply voltage exceeds the upper operating point of the respective range, issuing an indication of the safe mode from the health engine to a controller of the memory device.

16. The non-transitory computer-readable medium of claim 12, wherein to initiate the safe mode, the instructions, when executed by the processor of the electronic device, further cause the electronic device to: based at least in part on determining that the supply voltage exceeds the upper operating point of the respective range, send an interrupt to the processor.

17. The non-transitory computer-readable medium of claim 12, wherein to initiate the safe mode, the instructions, when executed by the processor of the electronic device, further cause the electronic device to: based at least in part on determining that the supply voltage exceeds the upper operating point of the respective range, delay data transfers between the memory device and a host device.

18. The non-transitory computer-readable medium of claim 12, wherein the first voltage detector and the second voltage detector comprise a respective plurality of resistors, wherein the first configuration comprises a first active subset of resistors of the respective plurality of resistors and the second configuration comprises a second active subset of resistors of the respective plurality of resistors.

19. The non-transitory computer-readable medium of claim 12, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: receive the one or more supply voltages; and generate one or more additional supply voltages using the one or more supply voltages.

20. The non-transitory computer-readable medium of claim 19, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: monitor the one or more additional supply voltages; and based at least in part on monitoring the one or more additional supply voltages, determine whether the one or more additional supply voltages satisfy a respective range.

21. A method for memory operations, comprising: monitoring one or more supply voltages of a memory device; using a first voltage detector having a first configuration and a second voltage detector having a second configuration, determining whether the one or more supply voltages satisfy a respective range based at least in part on monitoring the one or more supply voltages; setting a first flag indicating that a supply voltage of the one or more supply voltages exceeds a first threshold of the first voltage detector; setting a second flag indicating that the supply voltage exceeds a second threshold of the second voltage detector; inverting the second flag; and at a health engine of the memory device, initiating a safe mode of the memory device based at least in part on determining that a supply voltage of the one or more supply voltages exceeds an upper operating point of the respective range, wherein determining that the supply voltage exceeds the upper operating point of the respective range is based at least in part on inverting the second flag.

22. The method of claim 21, further comprising: ​ issue an indication of the one or more supply voltages to the health engine of the memory device.

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