Method for manufacturing super junction trench gate mosfet
By etching away the tungsten metal in the source contact hole during the manufacturing process of superjunction trench gate MOSFETs, the number of mask layers is reduced, which solves the problems of increased manufacturing costs and exposed tungsten metal, and improves the reliability of the process.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- HUA HONG SEMICON WUXI LTD
- Filing Date
- 2023-03-29
- Publication Date
- 2026-06-02
AI Technical Summary
In existing superjunction trench gate MOSFET manufacturing methods, the introduction of an additional mask layer increases manufacturing costs, and there is a risk that the exposed tungsten metal in the source contact hole in the source region may cause a short circuit to other conductors.
By not removing the second mask layer after etching the top metal layer, continuing to etch and remove the tungsten metal in the source contact hole of the source region, and removing the second mask layer before forming the second dielectric layer, the number of mask layers is reduced, and the tungsten metal is avoided from being exposed.
This reduces manufacturing costs and avoids the risk of tungsten metal short-circuiting to other conductors, thus improving process reliability.
Smart Images
Figure CN116364552B_ABST
Abstract
Description
Technical Field
[0001] This invention pertains to integrated circuit design and manufacturing technology, and specifically relates to a method for manufacturing a superjunction trench gate MOSFET. Background Technology
[0002] Trench gate MOSFETs are widely used in power conversion circuits, often as power switching devices. The on-resistance Rsp and breakdown voltage BV of the trench gate are among its important parameters; achieving a higher breakdown voltage BV and a lower on-resistance Rsp can improve product competitiveness. To improve the on-resistance of medium- to high-voltage (50–200V) trench gates, the concept of superjunction trench gates achieved through injection has been proposed, such as… Figure 1 As shown, a source doped pillar (P-pillar / PPL) 1032 is formed in the epitaxial layer below the body region between the trench gates to assist the depletion of the N-type drift region. The bottom of the source doped pillar (P-pillar / PPL) 1032 is as close as possible to the highly doped N-type substrate 101 to make the depletable N-type drift region longer.
[0003] To simplify the design, an additional mask layer is introduced during the implantation of the source doped pillar (P-pillar / PPL) 1032, as shown on the left. Figure 2 As shown, however, the introduction of an additional mask layer increases the manufacturing cost of the process, thus reducing the advantages of superjunctions.
[0004] Figure 2 The cross section at point B of the cutting line is as follows Figure 1 As shown, the cross-section at cutting line A is as follows Figure 3 As shown, at dicing line A, the gate terminal is led out to the gate metal layer GATE M1 through contact hole (CT) 109, and at dicing line B, the source-body terminal is led out to the source-body metal layer SOURCE-BULK M1 through contact hole (CT) 109. This design allows the process to achieve separate gate and source-body terminal leads with only one metal layer, that is, the top metal layer M1 is divided into the gate metal layer GATE M1 (GATE M1, GATE PAD M1) and the source-body metal layer (SOURCE-BULK M1, SOURCE M1). To reduce the chip area, due to the simultaneous presence of contact hole (CT) and doped pillar mask layer (PPL layer), the area can be reduced. Figure 2 The gate metal layer (GATE M1) on the left side and part of the gate pin metal layer (GATE PAD M1) in the middle are placed at the middle position of the annular source doped pillar (P-pillar / PPL) 1032 and the annular trench gate 105 in the front-back direction.
[0005] To further reduce the manufacturing cost of superjunction trench gate MOSFETs, reducing the number of mask layers is the most direct and effective method.
[0006] An existing method for manufacturing an N-type superjunction trench gate MOSFET includes the following steps:
[0007] (i) A trench gate 105 is formed on the N-type epitaxial layer 102 on the upper side of the N-type substrate 101, a P-type body region 106 is formed on the surface of the N-type epitaxial layer 102, and an N-type heavy doping implantation is performed on the surface of the P-type body region 106 to form a source-end N-implantation region 108.
[0008] (ii) A first dielectric layer 110 is formed on the upper surface of the wafer;
[0009] (iii) A first mask layer 501 is covered on the upper surface of the wafer and etched to form a gate contact hole (Contact / CT) 1091 connecting the trench gate and the first dielectric layer 110 at the trench gate 105 of the gate region. At the same time, a gate source contact hole 1092 connecting the source end N-type injection region 108 and P-type body region 106 is formed between the left and right adjacent trench gates of the gate region. A source source contact hole 1093 connecting the source end N-type injection region 108 and P-type body region 106 is formed between the left and right adjacent trench gates of the source region.
[0010] (iv) Perform P-type ion implantation to form source P-type doped pillars (P-pillars / PPLs) 1032 in the N-type epitaxial layer 102 below the source contact holes 1092 and source contact holes 1093 in each gate region, such as... Figure 4 As shown, the source P-type doped pillar 1032 is used to assist in the depletion of the drift region;
[0011] (v) Remove the first mask layer 501 and perform a contact hole metal forming process, filling each contact hole with tungsten metal, such as... Figure 5 As shown;
[0012] (vi) Deposit a metal layer to form a top metal layer 111 on the upper surface of the wafer;
[0013] (vii) Cover the top metal layer 111 with the second mask layer 502, etch to remove the source contact hole 1093 in the source region and the second mask layer 502 and top metal layer 111 above the trench gate in the source region, retain the second mask layer 502 and top metal layer 111 above the trench gate in the gate region, and retain the second mask layer 502 and top metal layer 111 above the source contact hole 1092 in the gate region, as shown. Figure 6 As shown;
[0014] (viii) Remove the second mask layer 502, as above. Figure 7 As shown;
[0015] (ix) Deposit a second dielectric layer 113 on the upper surface of the wafer, as above. Figure 8 As shown.
[0016] In the existing manufacturing method of N-type superjunction trench gate MOSFETs, in order to reduce the number of photomask layers, the two mask layers of contact vias (CT) and doped pillars (PPL) are combined into a single mask layer in the layout design, such as... Figure 9 As shown.
[0017] In existing methods for manufacturing N-type superjunction trench gate MOSFETs, all gate contact holes (CTs) and doped pillars (PPLs) are covered by the gate metal layer GATE M1. The gate dielectric (first dielectric layer 110) effectively separates the gate contact holes (CTs) and doped pillars (PPLs) from their adjacent counterparts. Figure 8 The leftmost gate trench contains the gate contact hole 1091 and the gate P-pillar / PPL 1031 below the gate trench, while the rightmost gate source contact hole 1092 and the source P-pillar / PPL 1032 below it. However, this manufacturing method results in the tungsten metal in the source contact hole 1093 of the source region being uncovered by the top metal layer M1, and the tungsten metal in the source contact hole 1093 in the region where the source-bulk metal layer M1 is located being exposed, such as... Figure 8 As shown, the source contact hole 1093 in the middle of the source area is exposed, and the tungsten metal in the contact hole poses a risk of short-circuiting to other conductors. Summary of the Invention
[0018] The technical problem to be solved by the present invention is to provide a method for manufacturing a superjunction trench gate MOSFET, which can not only reduce the number of mask layers and reduce manufacturing costs, but also avoid the exposure of tungsten metal in the source contact hole in the source region, which could lead to short circuits to other conductors and reduce process risks.
[0019] To solve the above-mentioned technical problems, the present invention provides a method for manufacturing a superjunction trench gate MOSFET, which includes the following steps:
[0020] S1. A trench gate 105 is formed on the first type epitaxial layer 102 on the upper side of the first type substrate 101. A second type body region 106 is formed on the surface of the first type epitaxial layer 102. A first type heavy doping implantation is performed on the surface of the second type body region 106 to form a source end first type implantation region 108. The first type is N and the second type is P, or the first type is P and the second type is N.
[0021] S2. A first dielectric layer 110 is formed on the upper surface of the wafer;
[0022] S3. Cover the upper surface of the wafer with a first mask layer 501, and etch to form a gate contact hole 1091 at the trench gate 105 of the gate region, which connects the trench gate and the first dielectric layer 110. At the same time, a gate source contact hole 1092 connecting the first type injection region 108 and the second type body region 106 of the source end is formed between the left and right adjacent trench gates of the gate region. A source contact hole 1093 connecting the first type injection region 108 and the second type body region 106 of the source end is formed between the left and right adjacent trench gates of the source region.
[0023] S4. Perform second-type ion implantation to form source second-type doped pillars 1032 in the first-type epitaxial layer 102 below each gate region source contact hole 1092 and source region source contact hole 1093, and simultaneously form gate second-type doped pillars 1031 in the first-type epitaxial layer 102 below the gate region gate contact hole 1091.
[0024] S5. Remove the first mask layer 501, perform contact hole metallization process, and fill each contact hole with tungsten metal;
[0025] S6. Perform metal layer deposition to form a top metal layer 111 on the upper surface of the wafer;
[0026] S7. Cover the top metal layer 111 with the second mask layer 502, etch away the source contact hole 1093 in the source region and the second mask layer 502 and the top metal layer 111 above the trench gate in the source region, retain the second mask layer 502 and the top metal layer 111 above the trench gate in the gate region, and retain the second mask layer 502 and the top metal layer 111 above the source contact hole 1092 in the gate region.
[0027] S8. Etching removes the tungsten metal from the source contact hole 1093 in the source region;
[0028] S9. Remove the second mask layer 502, and then deposit the second dielectric layer 113 on the upper surface of the wafer.
[0029] Preferably, in step S8, a wet etching process is used to etch and remove the tungsten metal in the source contact hole 1093 in the source region.
[0030] Preferably, in step S6, a metal layer deposition is performed to form a top metal layer 111 on the upper surface of the wafer and a bottom metal layer 112 as a drain metal layer on the lower surface of the wafer.
[0031] Preferably, the lower end of the source type II doped pillar 1032 is lower than the lower end of the gate trench.
[0032] Preferably, in step S5, the contact hole metal process includes:
[0033] S51. Deposit a Ti / TiN layer;
[0034] S52. Annealing alloys the Ti / TiN layer with silicon.
[0035] S53. Deposited metallic tungsten;
[0036] S54. Reverse etching or CMP removes the tungsten and Ti / TiN layers from the wafer surface, leaving tungsten plugs to fill the contact holes.
[0037] Preferably, in step S8, a wet etching process is used to etch and remove the Ti / TiN / tungsten metal stack in the source contact hole 1093 in the source region.
[0038] Preferably, step S1 includes the following steps:
[0039] S11. An N-type epitaxial layer 102 is formed on an N-type substrate 101;
[0040] S12. P-type ion implantation is performed on the surface of the N-type epitaxial layer 102 to form a P-type body region 106;
[0041] S13. Photolithography etching to form gate trenches in the N-type epitaxial layer 102 and source trenches in the source region;
[0042] S14. A trench gate dielectric layer 104 and a trench gate polysilicon layer are sequentially formed in both the gate trench in the gate region and the gate trench in the source region to form a trench gate 105.
[0043] S15. N-type heavy doping is performed on the surface of the P-type body region 106 to form a source-end N-implantation region 108.
[0044] Preferably, the doping concentration of the N-type substrate 101 is 2.5e13 to 1e14 cm⁻¹. -3 .
[0045] Preferably, the doping concentration of the N-type epitaxial layer 102 is 5e15 to 1e17 cm⁻¹. -3 .
[0046] Preferably, the second mask layer 502 is a hard mask material;
[0047] The first mask layer 502 is photoresist.
[0048] The manufacturing method of the superjunction trench gate MOSFET of the present invention utilizes a photomask for etching the top metal layer 111 and a second mask layer 502. After the top metal layer 111 is cleanly etched, the second mask layer 502 is not removed. Instead, the exposed tungsten metal in the source contact hole 1093 is etched and removed completely. Then, the second mask layer 502 is removed, and then the second dielectric layer 113 is formed. This method not only reduces the number of mask layers and lowers manufacturing costs, but also avoids the exposure of tungsten metal in the source contact hole 1093, which could lead to short circuits to other conductors. This method can avoid the exposure of tungsten metal while saving one mask layer, thus reducing process risks. Attached Figure Description
[0049] To more clearly illustrate the technical solution of the present invention, the accompanying drawings used in the present invention will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0050] Figure 1 This is a schematic diagram of a longitudinal cross-section of an existing superjunction trench gate MOSFET;
[0051] Figure 2 It is a layout structure of an existing superjunction trench gate MOSFET with an additional mask layer introduced;
[0052] Figure 3 yes Figure 2 A schematic diagram of the longitudinal cross-section at cut line A of a superjunction trench gate MOSFET;
[0053] Figure 4 This is a schematic diagram of a longitudinal section showing the formation of a source type II doped pillar in the fabrication method of a superjunction trench gate MOSFET.
[0054] Figure 5 This is a schematic diagram of a longitudinal section showing the manufacturing process of a superjunction trench gate MOSFET, in which tungsten metal is filled into the contact hole.
[0055] Figure 6 This is a longitudinal cross-sectional schematic diagram of the manufacturing method of a superjunction trench gate MOSFET, which involves removing the source contact hole and the mask layer and metal layer above the trench gate in the source region.
[0056] Figure 7 This is a schematic diagram of a longitudinal cross-section of an existing superjunction trench gate MOSFET manufacturing method that directly removes the second mask layer;
[0057] Figure 8This is a schematic diagram of a longitudinal cross-section of the existing superjunction trench gate MOSFET fabrication method, showing the deposition of a second dielectric layer on the upper surface of a wafer.
[0058] Figure 9 It is a new layout structure for a superjunction trench gate MOSFET with an additional mask layer.
[0059] Figure 10 This is a longitudinal cross-sectional schematic diagram of the etching process for removing tungsten metal from the source contact hole in the source region using the manufacturing method of the superjunction trench gate MOSFET of the present invention.
[0060] Figure 11 This is a longitudinal cross-sectional schematic diagram of the deposition of a second dielectric layer on the upper surface of a wafer in the manufacturing method of the superjunction trench gate MOSFET of the present invention. Detailed Implementation
[0061] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0062] The terms "first," "second," and similar words used in this application do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Words such as "including" or "comprising" mean that the element or object preceding the word encompasses the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are used only to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.
[0063] It should be noted that, unless otherwise specified, the embodiments and features described in the present invention can be combined with each other.
[0064] Example 1
[0065] A method for manufacturing a superjunction trench gate MOSFET includes the following steps:
[0066] Includes the following steps:
[0067] S1. A trench gate 105 is formed on the first type epitaxial layer 102 on the upper side of the first type substrate 101. A second type body region 106 is formed on the surface of the first type epitaxial layer 102. A first type heavy doping implantation is performed on the surface of the second type body region 106 to form a source end first type implantation region 108. The first type is N and the second type is P, or the first type is P and the second type is N.
[0068] S2. A first dielectric layer 110 is formed on the upper surface of the wafer;
[0069] S3. Cover the upper surface of the wafer with a first mask layer 501, and etch to form a gate contact hole (Contact / CT) 1091 at the trench gate 105 of the gate region, which connects the trench gate and the first dielectric layer 110. At the same time, a gate source contact hole 1092 connecting the first type injection region 108 and the second type body region 106 of the source end is formed between the left and right adjacent trench gates of the gate region. A source source contact hole 1093 connecting the first type injection region 108 and the second type body region 106 of the source end is formed between the left and right adjacent trench gates of the source region.
[0070] S4. Perform second-type ion implantation, forming source second-type doped pillars 1032 in the first-type epitaxial layer 102 below each gate region source contact hole 1092 and source region source contact hole 1093, and simultaneously forming gate second-type doped pillars 1031 in the first-type epitaxial layer 102 below the gate region gate contact hole 1091, as follows. Figure 4 As shown, the source type II doped pillar 1032 is used to assist in the depletion of the drift region;
[0071] S5. Remove the first mask layer 501, perform contact hole metallization, and fill each contact hole with tungsten metal, such as... Figure 5 As shown;
[0072] S6. Perform metal layer deposition to form a top metal layer 111 on the upper surface of the wafer;
[0073] S7. Cover the top metal layer 111 with the second mask layer 502, etch away the source contact hole 1093 in the source region and the second mask layer 502 and top metal layer 111 above the trench gate in the source region, retain the second mask layer 502 and top metal layer 111 above the trench gate in the gate region, and retain the second mask layer 502 and top metal layer 111 above the source contact hole 1092 in the gate region, as shown. Figure 6 As shown;
[0074] S8. Etching removes the tungsten metal from the source contact hole 1093 in the source region, such as Figure 10 As shown;
[0075] S9. Remove the second mask layer 502, and then deposit the second dielectric layer 113 on the upper surface of the wafer, as shown. Figure 11 As shown.
[0076] The manufacturing method of the superjunction trench gate MOSFET in Embodiment 1 involves forming a first dielectric layer 110, coating a first mask layer 501 and developing it, etching the first dielectric layer 110, and then simultaneously etching polysilicon / silicon. Ion implantation is performed using the same photomask and the first mask layer 501 to form source second-type doped pillars 1032 in the first-type epitaxial layer 102 below the gate region source contact holes 1092 and the source region source contact holes 1093. All gate region contact holes (CTs) and doped pillars are covered by the gate region metal layer GATE M1. The gate dielectric (first dielectric layer 110) isolates the gate region contact holes (CTs) and doped pillars from their neighboring contact holes (CTs) and doped pillars. Furthermore, the source region source contact holes 1093 do not contain tungsten metal and are filled by the second dielectric layer 113. Figure 11 As shown. The manufacturing method of this superjunction trench gate MOSFET utilizes a photomask for etching the top metal layer 111 and a second mask layer 502. After the top metal layer 111 is cleanly etched, the second mask layer 502 is not removed. The exposed tungsten metal in the source contact hole 1093 is then etched away completely. The exposed tungsten metal (or metal stack) in the source contact hole 1093 is then removed. The second mask layer 502 is then removed, and the second dielectric layer 113 is then formed. This method not only reduces the number of mask layers, thus lowering manufacturing costs, but also prevents the source contact hole 1093 from being exposed and short-circuited to other conductors. This method can avoid the exposure of tungsten metal while saving one mask layer, thus reducing process risks.
[0077] Example 2
[0078] In the manufacturing method of the superjunction trench gate MOSFET based on Embodiment 1, in step S8, a wet etching process is used to etch and remove the tungsten metal in the source contact hole 1093 of the source region that is not covered by the second mask layer 502, so as to prevent the tungsten metal from being exposed.
[0079] Preferably, in step S6, a metal layer deposition is performed to form a top metal layer 111 on the upper surface of the wafer and a bottom metal layer 112 as a drain metal layer on the lower surface of the wafer.
[0080] Preferably, the lower end of the source type II doped pillar 1032 is lower than the lower end of the gate trench.
[0081] Example 3
[0082] In the manufacturing method of the superjunction trench gate MOSFET based on Embodiment 1, step S5 includes the following contact hole metallization process:
[0083] S51. Deposit a Ti / TiN layer;
[0084] S52. Annealing alloys the Ti / TiN layer with silicon.
[0085] S53. Deposited metallic tungsten;
[0086] S54. Etching or CMP (chemical mechanical polishing) removes the tungsten and Ti / TiN layers from the wafer surface, leaving tungsten plugs to fill the contact holes.
[0087] Preferably, in step S8, a wet etching process is used to etch and remove the Ti / TiN / tungsten metal stack in the source contact hole 1093 in the source region.
[0088] Example 5
[0089] The manufacturing method of the superjunction trench gate MOSFET based on Embodiment 1 includes the following steps in step S1:
[0090] S11. An N-type epitaxial layer 102 is formed on an N-type substrate 101;
[0091] S12. P-type ion implantation is performed on the surface of the N-type epitaxial layer 102 to form a P-type body region 106;
[0092] S13. Photolithography etching to form gate trenches and source trenches in the N-type epitaxial layer 102;
[0093] S14. Using a P-type ion implantation process, a vertically extending P-type doped gate pillar (P-pillar / PPL) 1031 is formed in the N-type epitaxial layer below the gate trench in the gate region.
[0094] S15. A trench gate dielectric layer 104 and a trench gate polysilicon layer are sequentially formed in both the gate trench and the source trench to form a trench gate 105.
[0095] S16. N-type heavy doping is performed on the surface of the P-type body region 106 to form a source-end N-implantation region 108.
[0096] Preferably, the doping concentration of the N-type substrate 101 is 2.5e13 to 1e14 cm⁻¹. -3 .
[0097] Preferably, the doping concentration of the N-type epitaxial layer 102 is 5e15 to 1e17 cm⁻¹. -3 .
[0098] Preferably, the second mask layer 502 is a hard mask material or photoresist.
[0099] Preferably, the first mask layer 501 is a photoresist or a hard mask material.
[0100] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.
Claims
1. A method for manufacturing a superjunction trench gate MOSFET, characterized in that, Includes the following steps: S1. A trench gate (105) is formed on the first type epitaxial layer (102) on the upper side of the first type substrate (101), a second type body region (106) is formed on the surface of the first type epitaxial layer (102), and a first type heavy doping implantation is performed on the surface of the second type body region (106) to form a source end first type implantation region (108), wherein the first type is N and the second type is P, or the first type is P and the second type is N; S2. A first dielectric layer (110) is formed on the upper surface of the wafer. S3. Cover the upper surface of the wafer with a first mask layer (501), and etch to form a gate contact hole (1091) connecting the trench gate and the first dielectric layer (110) at the trench gate (105) of the gate region. At the same time, a gate source contact hole (1092) connecting the first type injection region (108) and the second type body region (106) of the source end is formed between the left and right adjacent trench gates of the gate region. A source contact hole (1093) connecting the first type injection region (108) and the second type body region (106) of the source end is formed between the left and right adjacent trench gates of the source region. S4. Perform second-type ion implantation to form source second-type doped pillars (1032) in the first-type epitaxial layer (102) below each gate region source contact hole (1092) and source region source contact hole (1093), and simultaneously form gate second-type doped pillars (1031) in the first-type epitaxial layer 102 below the gate region gate contact hole (1091). S5. Remove the first mask layer (501), perform contact hole metal processing, and fill each contact hole with tungsten metal; S6. Perform metal layer deposition to form a top metal layer (111) on the upper surface of the wafer. S7. Cover the top metal layer (111) with a second mask layer (502), etch away the source contact hole (1093) of the source region and the second mask layer (502) and top metal layer (111) above the trench gate of the source region, retain the second mask layer (502) and top metal layer (111) above the trench gate of the gate region, and retain the second mask layer (502) and top metal layer (111) above the source contact hole (1092) of the gate region. S8. Etching removes tungsten metal from the source contact hole (1093) in the source region; S9. Remove the second mask layer (502) and then deposit a second dielectric layer (113) on the upper surface of the wafer.
2. The method for manufacturing a superjunction trench gate MOSFET according to claim 1, characterized in that, In step S8, a wet etching process is used to etch and remove the tungsten metal in the source contact hole (1093) in the source region.
3. The method for manufacturing a superjunction trench gate MOSFET according to claim 1, characterized in that, In step S6, metal layer deposition is performed to form a top metal layer (111) on the upper surface of the wafer and a bottom metal layer (112) as a drain metal layer on the lower surface of the wafer.
4. The method for manufacturing a superjunction trench gate MOSFET according to claim 1, characterized in that, The lower end of the source type II doped pillar (1032) is lower than the lower end of the gate trench.
5. The method for manufacturing a superjunction trench gate MOSFET according to claim 1, characterized in that, In step S5, the contact hole metal process includes: S51. Deposit a Ti / TiN layer; S52. Annealing alloys the Ti / TiN layer with silicon. S53. Deposited metallic tungsten; S54. Reverse etching or CMP removes the tungsten and Ti / TiN layers from the wafer surface, leaving tungsten plugs to fill the contact holes.
6. The method for manufacturing a superjunction trench gate MOSFET according to claim 5, characterized in that, In step S8, a wet etching process is used to etch and remove the Ti / TiN / tungsten metal stack in the source contact hole (1093) of the source region.
7. The method for manufacturing a superjunction trench gate MOSFET according to claim 4, characterized in that, Step S1 includes the following steps: S11. An N-type epitaxial layer (102) is formed on an N-type substrate (101). S12. P-type ion implantation is performed on the surface of the N-type epitaxial layer (102) to form a P-type body region (106). S13. Photolithography etching to form gate trenches in the N-type epitaxial layer (102) and source trenches in the source region; S14. A trench gate dielectric layer (104) and a trench gate polysilicon layer are sequentially formed in both the gate trench in the gate region and the gate trench in the source region to form a trench gate (105). S15. N-type heavy doping is performed on the surface of the P-type body region (106) to form a source-end N-implantation region (108).
8. The method for manufacturing a superjunction trench gate MOSFET according to claim 7, characterized in that, The N-type substrate (101) has a doping concentration of 2.5e13~1e14cm -3 .
9. The method for manufacturing a superjunction trench gate MOSFET according to claim 7, characterized in that, The doping concentration of the N-type epitaxial layer (102) is 5e15~1e17cm. -3 .
10. The method for manufacturing a superjunction trench gate MOSFET according to claim 1, characterized in that, The second mask layer (502) is a hard mask material; The first mask layer (501) is photoresist.