Semiconductor device

Abstract

The application relates to a semiconductor device. The semiconductor device comprises a substrate, a first chip and a second chip which are arranged in parallel and spaced apart above the substrate, a power supply integration module which is arranged above the first chip and the second chip and is electrically connected to the first chip and the second chip, and a power supply line which is arranged below the power supply integration module and extends from an upper surface of the substrate to a lower surface of the power supply integration module. The semiconductor device provided by the application can at least shorten the wiring path of the power supply line.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically, to a semiconductor device. Background Technology

[0002] With the rapid development of integrated circuits and the Internet, 3C products, including computers, communication devices, and consumer electronics, have experienced rapid growth and widespread application. However, due to the complexity of 3C products, the integration of power supplies for internal components presents a challenge. Figure 1 In the prior art shown, chips 10 and 20 are disposed on substrate 30. To accommodate the power lines 50 of chips 10 and 20 extending to their back surfaces, a power integrator 40 is directly connected across the back surfaces of chips 10 and 20 to synchronously regulate the voltage supply to chips 10 and 20. However, the power lines 50 between the power integrator 40 and substrate 30 are routed in the peripheral area of ​​chips 10 and 20, resulting in excessively long power supply paths. Summary of the Invention

[0003] To address the aforementioned problems in related technologies, this invention proposes a semiconductor device that can shorten the routing path of power supply lines.

[0004] An embodiment of the present invention provides a semiconductor device, comprising: a substrate; a first chip and a second chip, disposed laterally side-by-side at intervals above the substrate; a power integrator, bridging the first chip and the second chip and electrically connected to the first chip and the second chip; and a power supply line located below the power integrator, wherein the power supply line extends from the upper surface of the substrate to the lower surface of the power integrator.

[0005] In some embodiments, the power supply line includes an upper portion connected to a power integrator and a lower portion connected below the upper portion, wherein the width of the lower portion of the power supply line is greater than the width of the upper portion.

[0006] In some embodiments, the top of the lower portion of the power supply line is below the upper surface of the first chip and the second chip.

[0007] In some embodiments, the power supply line is located between the first chip and the second chip.

[0008] In some embodiments, the power supply line is the same distance from the first chip and from the second chip.

[0009] In some embodiments, a plurality of voltage transmission elements are also provided on the lower surface of the power integrator, and the plurality of voltage transmission elements are located on the same side of the first chip, the second chip and the power supply line.

[0010] In some embodiments, the power supply line is positioned adjacent to the edge of the power integrator, and multiple voltage transmission elements are located on the same side of the power supply line.

[0011] In some embodiments, the semiconductor device further includes a first tuning circuit and a second tuning circuit, the first tuning circuit and the second tuning circuit being respectively disposed at the overlap of the first chip and the power integrator and the second chip and the power integrator.

[0012] In some embodiments, the first tuning circuit or the second tuning circuit includes a first capacitor and a first inductor stacked together.

[0013] In some embodiments, the first tuning circuit or the second tuning circuit further includes a second capacitor and a second inductor stacked together, wherein a third capacitor and a fourth inductor are stacked on top of the first capacitor and the first inductor.

[0014] In some embodiments, the semiconductor device further includes a signal transmission element, one end of which is connected to a first chip or a second chip, and the other end of which is connected to a power integrator. Attached Figure Description

[0015] The various aspects of the invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, according to standard industrial practice, the components are not drawn to scale. In fact, the dimensions of the components may be arbitrarily increased or decreased for clarity of discussion.

[0016] Figure 1 This is a schematic diagram of a conventional semiconductor device.

[0017] Figure 2 This is a side view of a semiconductor device according to an embodiment of the present invention.

[0018] Figure 3 This is a top view of a semiconductor device according to an embodiment of the present invention.

[0019] Figure 4 This is a top view of a semiconductor device according to another embodiment of the present invention. Specific Implementation

[0020] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of elements and arrangements will be described below to simplify the invention. These are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, or embodiments where an additional component is formed between the first and second components such that the first and second components are not in direct contact. Furthermore, reference numerals and / or letters may be repeated throughout the various instances. Such repetition is for brevity and clarity only and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0021] An embodiment of the present invention provides a semiconductor device. Figure 2 This is a side view of a semiconductor device according to an embodiment of the present invention. Figure 2 As shown, the semiconductor device 1000 has a substrate 300, and a first chip 100 and a second chip 200 are disposed laterally side by side on the substrate 300. The first chip 100 and the second chip 200 are disposed at intervals on the substrate 300. The active surface (lower surface) of the first chip 100 and the active surface (lower surface) of the second chip 200 are connected to the upper surface of the substrate 300 via a connector 350.

[0022] A power integrator 400 is disposed above the first chip 100 and the second chip 200, bridging the first chip 100 and the second chip 200 to synchronously regulate and supply power to the first chip 100 and the second chip 200. The power integrator 400 may be, for example, an integrated voltage regulator (IVR) or other devices that can be used for voltage regulation. The power integrator 400 is electrically connected to the first chip 100 and the second chip 200. A power supply line 500 is disposed below the power integrator 400, extending from the lower surface of the power integrator 400 to the upper surface of the substrate 300.

[0023] The above-described technical solution of the present invention arranges the power supply line 500 between the power integrator 400 and the substrate, and extends from the upper surface of the substrate 300 to the lower surface of the power integrator 400, thereby shortening the routing path of the power supply line and improving the electrical conduction efficiency.

[0024] Continue to refer to Figure 2As shown, in some embodiments, the distance between the power supply line 500 and the first chip 100 and the second chip 200 may be the same. The power supply line 500 extends continuously and vertically between the substrate 300 and the power integrator 400. The power supply line 500 may include an upper portion 510 connected to the power integrator 400 and a lower portion 520 connected below the upper portion 510. The upper portion 510 and the lower portion 520 are in direct contact. Both the upper portion 510 and the lower portion 520 may be vertically extending conductive pillars. In some embodiments, the width of the lower portion 520 is greater than the width of the upper portion 510. The top of the lower portion 520, i.e., the junction of the lower portion 520 and the upper portion 510, is below the upper surface of the first chip 100 and / or the second chip 200. In some embodiments, the power supply line 500 may be formed using a two-stage electroplating process. Alternatively, a "pick and place" process can be used, where a lower portion 520 is first formed on the surface of the substrate 300 using metal, and then electroplating is performed on the lower portion 520 to form the power supply line 500. In some embodiments, the power supply line 500 can be made of metal. The upper portion 510 and the lower portion 520 of the power supply line 500 can be made of the same material. Alternatively, the upper portion 510 and the lower portion 520 of the power supply line 500 can be made of different materials.

[0025] To match the overall resonant frequency of the semiconductor device 1000, a first tuning circuit 600 may be disposed between the first chip 100 and the substrate 300, and a second tuning circuit 700 may be disposed between the second chip 200 and the substrate 300. The first tuning circuit 600 is disposed at the overlap between the first chip 100 and the power integrator 400, and the second tuning circuit 700 is disposed at the overlap between the second chip 200 and the power integrator 400. The first tuning circuit 600 and / or the second tuning circuit 700 may include at least one capacitor and at least one inductor to form an LC circuit for fine-tuning the capacitance and inductance values ​​of the power integrator 400.

[0026] exist Figure 2 In the illustrated embodiment, the first tuning circuit 600 includes a first capacitor 610, a first inductor 620, a second capacitor 630, and a second inductor 640 stacked sequentially from bottom to top. In some embodiments, the first capacitor 610 and / or the second capacitor 630 may be film capacitors, and the first inductor 620 and / or the second inductor 640 may be film inductors.

[0027] The first capacitor 610, the first inductor 620, the second capacitor 630, and the second inductor 640 can be connected via connector 950. The lowermost first capacitor 610 is connected to the first chip 100 via connector 950, and the uppermost second inductor 640 is connected to the power integrator 400 via connector 950. By configuring connector 950 to interconnect the first capacitor 610, the first inductor 620, the second capacitor 630, and the second inductor 640, they can be configured in parallel or in series. Furthermore, the first inductor 620 and the second inductor 640 can be interconnected using the vertical space between the first chip 100 and the power integrator 400. This increases the flexibility in LC circuit design.

[0028] The second tuning circuit 700 may include a first capacitor 710, a first inductor 720, a second capacitor 730, and a second inductor 740 stacked sequentially from bottom to top. In some embodiments, the first capacitor 710 and / or the second capacitor 730 may be film capacitors, and the first inductor 720 and / or the second inductor 740 may be film inductors. The first capacitor 710, the first inductor 720, the second capacitor 730, and the second inductor 740 may be connected via connectors 950. The bottommost first capacitor 710 is connected to the second chip 200 via connectors 950, and the topmost second inductor 740 is connected to the power integrator 400 via connectors 950.

[0029] In some embodiments, the structures of the first tuning circuit 600 and the second tuning circuit 700 differ depending on the first chip 100 and the second chip 200. For example... Figure 2 In the embodiments shown, the capacitors and inductors in the first tuning circuit 600 and the second tuning circuit 700 are arranged differently.

[0030] A through-silicon via (TSV) 900 is provided in both the first chip 100 and the second chip 200. The TSV 900 is located below the first tuning circuit 600 and the second tuning circuit 700, and is used to connect the first tuning circuit 600 and the second tuning circuit 700 respectively. The first tuning circuit 600 and the first chip 100 are connected through the TSV 900, and the second tuning circuit 700 and the second chip 200 are connected through the TSV 900.

[0031] A signal transmission device may also be provided between the first chip 100 and / or the second chip 200 and the power integrator 400 to connect the first chip 100 and / or the second chip 200 and the power integrator 400. Figure 2In the illustrated embodiment, a signal transmission device 800 is provided between the second chip 200 and the power integrator 400. One end (lower end) of the signal transmission device 800 is connected to the second chip 200, and the other end (upper end) is connected to the power integrator 400. To meet the different needs of the first chip 100 and the second chip 200, the power integrator 400 can receive control signals from the first chip 100 and / or the second chip 200 through the signal transmission device 800, thereby controlling the power integrator 400.

[0032] Figure 3 This is a top view of a semiconductor device according to an embodiment of the present invention. Figure 3 In the illustrated embodiment, a plurality of voltage transmission elements 850 are also disposed on the lower surface of the power integrator 400. A power supply line 500 is disposed adjacent to the edge of the power integrator 400, and the plurality of voltage transmission elements 850 are located on one side of the power supply line 500. The power supply line 500 on the lower surface of the power integrator 400 is located within the gap between the first chip 100 and the second chip 200. Furthermore, it can be located between the first tuning circuit 600 and the second tuning circuit 700. The distance between the power supply line 500 and the first chip 100 and the second chip 200 can be the same. The plurality of voltage transmission elements 850 are located on the same side of the first chip 100, the second chip 200, and the power supply line 500. In some embodiments, Figure 3 The layout of the power supply line 500 and voltage transmission element 850 in the illustrated embodiment is applicable to situations where the spacing between the first chip 100 and the second chip 200 is small.

[0033] Figure 4 This is a top view of another embodiment of a semiconductor device according to an embodiment of the present invention. Figure 4 In the illustrated embodiment, the power supply line 500 is disposed adjacent to the edge of the power integrator 400, and a plurality of voltage transmission elements 850 are located on one side of the power supply line 500. At least a portion of the plurality of voltage transmission elements 850 are located within the gap between the first chip 100 and the second chip 200. The power supply line 500 is located outside the same-side edge of the first chip 100 and the second chip 200, for example, the power supply line 500 is disposed outside the side edge adjacent to the first tuning circuit 600 and the second tuning circuit 700. The power supply line 500 is opposite to the gap between the first chip 100 and the second chip 200. The distance between the power supply line 500 and the first chip 100 and the second chip 200 may be the same. In some embodiments, Figure 4 The layout of the power supply line 500 and voltage transmission device 850 in the illustrated embodiment is applicable to situations where the interval between the first chip 100 and the second chip 200 is large.

[0034] The foregoing summary outlines features of several embodiments that enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that other processes and structures can be readily designed or modified based on this invention to achieve the same objectives and / or benefits as the embodiments described herein. Those skilled in the art should also recognize that these equivalent structures do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of the invention.

Claims

1. A semiconductor device, characterized in that, include: substrate; The first chip and the second chip are arranged horizontally side by side with intervals above the substrate; A power integrator is connected across and electrically to the first chip and the second chip. A power supply line is located below the power integrator, wherein the power supply line extends from the upper surface of the substrate to the lower surface of the power integrator, and the power supply line is between the first chip and the second chip.

2. The semiconductor device according to claim 1, characterized in that, The power supply line includes an upper portion connected to the power integrator and a lower portion connected below the upper portion, wherein the width of the lower portion of the power supply line is greater than the width of the upper portion.

3. The semiconductor device according to claim 2, characterized in that, The top of the lower portion of the power supply line is below the upper surfaces of the first chip and the second chip.

4. The semiconductor device according to claim 1, characterized in that, The power supply line is equidistant from the first chip and from the second chip.

5. The semiconductor device according to claim 1, characterized in that, The lower surface of the power integrator is also provided with a plurality of voltage transmission components, which are located on the same side of the first chip, the second chip and the power supply line.

6. The semiconductor device according to claim 1, characterized in that, The power supply line is positioned adjacent to the edge of the power integrator, and a plurality of voltage transmission elements on the lower surface of the power integrator are located on the same side of the power supply line.

7. The semiconductor device according to claim 5, characterized in that, Also includes: The first tuning circuit and the second tuning circuit are respectively located at the overlap between the first chip and the power integrator and the second chip and the power integrator.

8. The semiconductor device according to claim 7, characterized in that, The first tuning circuit or the second tuning circuit includes a first capacitor and a first inductor stacked together.

9. The semiconductor device according to claim 8, characterized in that, The first tuning circuit or the second tuning circuit further includes a second capacitor and a second inductor stacked on top of the first capacitor and the first inductor.

10. The semiconductor device according to claim 6, characterized in that, Also includes: A signal transmission device, one end of which is connected to the first chip or the second chip, and the other end of which is connected to the power integrator.

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