High performance oxide thin film transistor by atomic layer deposition and method of manufacturing the same

Abstract

The application discloses a high-performance atomic layer deposition oxide thin film transistor and a preparation method thereof. The method optimizes a thin film structure and improves thin film transistor performance by adding a new two-dimensional metal sulfide material as an interface modification layer between two metal oxide layers in each cycle of an atomic layer deposition active layer thin film. The new film layer added by the method is a two-dimensional conductive material with excellent optical and electrical properties, which can well assist the generation of reaction sites, improve interface defects and lattice mismatch due to the alternation of interfaces when a multicomponent oxide thin film is prepared by an atomic layer deposition method, effectively improve the deposition efficiency and quality of the thin film, and improve the interface state, thereby improving the electrical performance of the thin film transistor device.

Description

Technical Field

[0001] This invention belongs to the field of thin-film transistor devices, specifically relating to a high-performance atomic layer deposition oxide thin-film transistor and its fabrication method. Background Technology

[0002] Oxide thin-film transistors (TFTs) have become a viable alternative to silicon-based TFTs due to their advantages such as high mobility, low fabrication cost, and adaptability to flexible fabrication. The optical and electrical properties of oxide thin films are closely related to the performance of transistor devices; therefore, improving the quality of oxide thin films is crucial. Currently, the main methods for preparing oxide thin films include sputtering, chemical vapor deposition, solution deposition, and atomic layer deposition (ALD). Among these, ALD is particularly well-suited for oxide thin film preparation due to its self-limiting reaction mechanism, precise thickness control, low-temperature deposition, large-area deposition, and excellent three-dimensional deposition uniformity.

[0003] Currently, indium oxide-based multi-component oxides are the highest-performing active layer materials, with indium zinc oxide (IZO) being widely studied due to its high mobility. However, there is limited flexibility in the selection of indium precursors for deposited indium oxide-based oxide materials. Precursors such as indium chloride and trimethylindium, which are used for thermal oxidation deposition of indium oxide, suffer from slow deposition rates and narrow temperature ranges. Indium cyclopentadienyl (InCp) offers a wider reaction temperature range and faster deposition rates, making it a promising indium precursor. However, its relatively low reactivity requires strong oxidizing conditions for indium oxide deposition, and excessively high temperatures can lead to precursor decomposition and carbon contamination. Furthermore, its active temperature range is incompatible with other precursors. Therefore, there are currently no reports of using InCp to fabricate high-mobility thin-film transistors.

[0004] As active layer materials for TFT devices, single-component binary oxides generally struggle to achieve good performance. Therefore, most devices opt for ternary or higher-component oxides as the active layer material. Taking indium zinc oxide (InZnO) as an example, during ALD deposition, the InZnO precursor typically requires a relatively high deposition temperature to deposit a high-quality film. However, at this temperature, the ZincO layer experiences precursor decomposition and zinc desorption, resulting in poor film quality. The continuous alternation of these two materials leads to numerous atomic-level defect states at the interface, affecting the overall film quality. Therefore, balancing the deposition conditions of different components and addressing the film interface problems caused by alternating growth is crucial for obtaining high-performance films.

[0005] The alternating growth of multi-component oxides involves mutual influence. Due to the different lattice structures of the materials, lattice mismatches easily occur at the interfaces, leading to a greater likelihood of defect states. Minimizing the impact of interface temperatures on the thin film is crucial. Furthermore, when combining thermal oxidation and plasma oxidation methods, the influence of plasma on the precursor film is also critical and must be considered during deposition. Taking IZO thin films as an example, when diethylzinc is commonly used as a zinc oxide precursor, the growth temperature should not be too high, but many indium oxide precursors require higher temperatures to achieve reactivity. On the one hand, alternating growth causes different materials to influence each other, leading to a decrease in deposition rate and film quality when deposited on non-substrate surfaces. On the other hand, an increase in interfaces leads to an increase in defect states, which reduces the mobility and stability of TFT devices.

[0006] One paper describes the deposition of IZO thin films using the ALD method, preparing IZO films with different cycle ratios. It was found that alternating growth of the two different materials leads to mutual influence, resulting in changes in film composition and a slower deposition rate (Effect of the Bilayer Period of Atomic Layer Deposition on the Growth Behavior and Electrical Properties of the Amorphous In-Zn-O Film, Sangbong Lee et al., ACS Appl. Mater. Interfaces 2020, 12, 39372-39380). Although reducing the number of alternations mitigated the delayed deposition of indium oxide on the zinc oxide layer, no devices were fabricated, and the film quality changes were not reflected in device performance. Another paper describes the deposition of IZO thin films using the ALD method, adjusting the elemental composition ratios, and fabricating TFT devices with a device mobility of 30.9 cm⁻¹. 2 / Vs(All-oxide thin-film transistors with channels of mixed InOx-ZnOy formed by plasma-enhanced atomic layer deposition process, Jeong-Mu Lee et al., Journal of Vacuum Science & Technology A, 2019, 37, 060910). This article only optimized the device performance by simply adjusting the metal cation ratio, resulting in low mobility, and did not discuss the device stability. Summary of the Invention

[0007] To address the aforementioned problems, the purpose of this invention is to provide a high-performance atomic layer deposition oxide thin-film transistor and its fabrication method.

[0008] This invention modifies the interface of the active layer film by introducing a two-dimensional material as a modification layer, which effectively reduces the thinness problem caused by lattice mismatch, optimizes the continuous growth performance of the thin film at the stacking transition, and improves the performance of thin film transistor (TFT) devices by utilizing the excellent optical and electrical properties of the material.

[0009] During the alternating growth of multiple materials, lattice mismatch can easily lead to atomic vacancies at the alternating interfaces, reducing the film density. To address the lattice mismatch problem between zinc oxide and indium oxide thin film layers, this invention provides a molybdenum disulfide (MoS2) / ZnO structure for use in thin-film transistors. Two-dimensional MoS2, due to its weak van der Waals interactions and lack of surface dangling bonds, eliminates the requirements for thermal and lattice matching, making it very easy to construct heterojunctions. The hexagonal network structure where Mo and S atoms are covalently bonded is highly stable. Furthermore, this material possesses excellent optical and electrical properties, exhibiting a high current on / off ratio and carrier mobility at room temperature, and is also a direct bandgap semiconductor material. The two-dimensional MoS2 structure not only solves the lattice mismatch problem but also contributes to improved device mobility.

[0010] In the IZO thin film deposited in this invention, zinc oxide grows atomically in a single cycle, exhibiting a two-dimensional structure. Compared to bulk zinc oxide, two-dimensional zinc oxide has a graphene-like lattice structure, similar to the two-dimensional molybdenum disulfide structure, allowing for good lattice contact. A thin molybdenum disulfide layer is deposited at the interface between indium oxide and zinc oxide to eliminate the impact of interface lattice mismatch on thin film deposition and device performance.

[0011] Hafnium disulfide (HfS2) has also been reported as a material whose properties can match those of MoS2.

[0012] This invention uses the above materials to deposit between zinc oxide and indium oxide layers in an IZO thin film via an ALD deposition method, in order to optimize interface properties and improve film quality and device performance.

[0013] The objective of this invention is achieved through the following technical solution:

[0014] A high-performance atomically deposited oxide thin-film transistor, wherein the overall vertical structural unit from bottom to top is: substrate, gate, gate insulating layer, active layer, source and drain, and passivation layer.

[0015] The substrate is selected from alkali-free glass with a thickness of 0.5mm-1.0mm.

[0016] The gate, source, and drain are all made of molybdenum (Mo), a metallic material with a thickness of 100-200 nm.

[0017] The gate insulating layer is selected from a composite film of silicon dioxide and silicon nitride, with a thickness of 200-350 nm.

[0018] The active layer is selected from various ternary metal oxide semiconductors, indium zinc oxide (IZO), with a thickness of 8-12 nm. A two-dimensional material, such as molybdenum disulfide (MoS2) or hafnium disulfide (HfS2), is added as a modification layer during the deposition cycle of the two metal oxides in the active layer.

[0019] The passivation layer is selected from silicon dioxide and has a thickness of 200-300 nm.

[0020] This invention provides a method for fabricating a high-performance atomic layer deposition oxide thin-film transistor, comprising the following steps:

[0021] (1) Clean the alkali-free glass, sputter the metal gate onto it, and etch to achieve patterning;

[0022] (2) A gate insulating layer is deposited on the gate and etched to achieve patterning;

[0023] (3) An active layer is prepared on the gate insulating layer by atomic layer deposition. The preparation process is as follows:

[0024] a. Introduce the first metal precursor into the reaction chamber, purge and clean it, then introduce an oxidant to carry out the oxidation reaction, and purge and clean it again;

[0025] b. Repeat step a n1 times to obtain the first metal oxide film layer;

[0026] c. Introduce the precursor of the modification layer material into the reaction chamber, purge and clean it, introduce the reactants to carry out the reaction, and purge and clean it again;

[0027] d. Repeat step c n² times to obtain the modification layer;

[0028] e. Introduce a second metal precursor into the reaction chamber, purge and clean, then introduce an oxidant to carry out an oxidation reaction, and purge and clean again.

[0029] f. Repeat step e n3 times to obtain the second metal oxide film;

[0030] g. Repeat the af process N times to obtain a multi-component compound film of a certain thickness, and patterning is also achieved by etching;

[0031] (4) Sputter metal source and drain electrodes onto the active layer and etch to achieve patterning;

[0032] (5) Deposit a passivation layer on the source and drain electrodes and pattern it by etching;

[0033] The thin-film transistor device can be obtained by completing the above steps.

[0034] Further, in step (3), the atomic layer deposition process ab is the first metal oxide deposition cycle process, cd is the modification layer deposition cycle process, and ef is the second metal oxide deposition cycle process. These three film deposition processes are repeated to obtain an active layer film with an overlapping structure.

[0035] Furthermore, the precursor materials mentioned in steps a, c, and e of step (3) are each independently any one or more combinations of halides, alkyl compounds, cyclopentadienyl compounds, carbonyl compounds, and alkylamino compounds, with a typical combination being an alkyl compound and a cyclopentadienyl compound. These precursors need to be kept at a certain temperature for gas-phase reaction, with a temperature range of 25-130°C, such as room temperature, 40°C, 60°C, 75°C, 120°C, or 130°C.

[0036] Furthermore, the multi-component thin film in step (3) is prepared within a certain temperature range, such as 200-300℃, or 200℃ or 300℃.

[0037] Furthermore, the oxidation reaction pathways in steps a and c of step (3) can be thermal oxidation by introducing water (H2O), or oxidation assisted by introducing oxygen (O2) and inert gas and using plasma.

[0038] Furthermore, in steps (3), the time for the precursor to enter the reaction chamber in processes a and c is 0.2s-1s, such as 0.2s, 0.6s or 1s.

[0039] Furthermore, in steps (3), the flow rate of the carrier gas introduced into the reaction chamber by the precursor in processes a and c is 10-20 sccm, such as 10 sccm, 15 sccm or 20 sccm.

[0040] Furthermore, in step (3), the range of values ​​for n1 is n 1＝ 1 to 4, such as 1, 2, 3 or 4.

[0041] Furthermore, in step (3), the value range of n2 is n 2＝ 1 to 20, such as 1, 3, 10 or 20.

[0042] Furthermore, in step (3), the value range of n3 is n3 = 10 to 40, such as 10, 20, 30 or 40.

[0043] Furthermore, in step (3), the value range of N is N = 3 to 15, such as 3, 4, 6, 11 or 15.

[0044] Compared with the prior art, the present invention has the following advantages and beneficial effects:

[0045] (1) The present invention adds a two-dimensional material as a modification layer between two materials with mismatched crystal lattices, which solves the problem of atomic-level defects in the thin film caused by the mismatch of crystal lattices at the interface, improves the quality of the thin film, and optimizes the performance of the device.

[0046] (2) In this invention, a two-dimensional modification layer material is added to the two metal oxide deposition cycles. By reconstructing the reaction sites on the substrate surface, the hydroxylation of the reaction sites at the growth interface is more complete, which makes the chemical adsorption of the subsequent precursor and the reaction sites more complete, thereby improving the deposition rate and the density of the film.

[0047] (3) The thin film transistor prepared by the present invention has excellent mobility and device stability, and can be used as a driving unit for flat panel display devices. In the field of new display devices, it can meet the driving requirements of display panels with higher resolution and lower power consumption. Attached Figure Description

[0048] Figure 1 This is a schematic diagram of the structure of the high-performance atomically deposited oxide thin-film transistor prepared by the present invention.

[0049] Figure 2 yes Figure 1 A schematic diagram of the stacked structure of the compound films in the active layer.

[0050] Figure 3 This is a flowchart of the active layer deposition process. Detailed Implementation

[0051] The specific implementation of the present invention will be further described below with reference to embodiments and accompanying drawings, but the implementation and protection of the present invention are not limited thereto. It should be noted that any processes not specifically described in detail below are those that can be implemented or understood by those skilled in the art by referring to existing technology. Reagents or instruments whose manufacturers are not specified are considered to be conventional products that can be purchased commercially.

[0052] like Figure 1 As shown, a high-performance atomically deposited oxide thin-film transistor has the following overall vertical structural units from bottom to top: substrate, gate 100-200nm, gate insulating layer 200-350nm, active layer 8-12nm, source and drain 100-200nm, and passivation layer 200-300nm.

[0053] The structure of active layer deposition in device structure, such as Figure 2As shown, a modification layer is added between the metal oxide layers, and the process is repeated N times as described above to obtain a multi-component compound film with a thickness of 8-12 nm.

[0054] Figure 3 This is a flowchart of the active layer deposition process, involving the deposition process of different materials and the number of cycles.

[0055] The technical solution of the present invention will be further described below with reference to the accompanying drawings and specific embodiments. In the devices prepared in each embodiment, the thickness of other film layers is the same, except that the thickness of the active layer may vary, in order to better reflect the performance impact caused by changes in the active layer.

[0056] Example 0 (Basic comparison, no modification layer):

[0057] Preparation before active layer deposition: The gate and gate insulating layer are sequentially fabricated on the substrate and patterned by etching, serving as the substrate for the ALD deposition process.

[0058] The precursor materials required for the ALD process are kept at the following temperatures: diethylzinc (DEZ) precursor and H2O are kept at room temperature, and cyclopentadienyl indium (InCp) precursor is heated to 75°C.

[0059] Active layer deposition process: The substrate is placed in the ALD equipment and heated to 200°C.

[0060] (1) DEZ is introduced at a carrier gas flow rate of 10 sccm for 0.2 s, followed by a purging time of 20 s. H2O is then introduced for 0.2 s and followed by a purging time of 20 s. After one cycle, a zinc oxide layer of approximately 0.2 nm is obtained.

[0061] (2) InCp is introduced at a carrier gas flow rate of 15 sccm for 0.6 s, followed by a purging time of 20 s. Oxygen is then introduced at a flow rate of 10 sccm, followed by an inert gas initiation process for plasma at a power of 300 W for 15 s, and then a purging time of 20 s. After 10 cycles, an indium oxide layer of approximately 0.5 nm is obtained.

[0062] Repeat steps (1)-(2) 15 times to obtain an IZO thin film with a thickness of about 10.5 nm as the active layer of the TFT device.

[0063] Subsequent device fabrication processes: Patterning is achieved on the active layer through etching, then source and drain electrodes are fabricated and patterned, and finally a passivation layer is deposited and patterned to complete device fabrication.

[0064] Example 1:

[0065] Preparation before active layer deposition: The gate and gate insulating layer are sequentially fabricated on the substrate and the device is patterned to serve as the substrate for the ALD deposition process.

[0066] The precursors required for the ALD process are kept at the following temperatures: DEZ precursor, H2O, and hydrogen sulfide (H2S) precursor are kept at room temperature; InCp precursor is heated to 75°C; and tetrakis(dimethylamide)molybdenum (Mo(NMe2)4) precursor is heated to 60°C.

[0067] Active layer deposition process: The substrate is placed in the ALD equipment and heated to 200°C.

[0068] (1) DEZ is introduced at a carrier gas flow rate of 10 sccm for 0.2 s, followed by a purging time of 20 s. H2O is then introduced for 0.2 s and followed by a purging time of 20 s. After one cycle, a zinc oxide layer with a thickness of approximately 0.2 nm is obtained.

[0069] (2) Mo(NMe2)4 is introduced with a carrier gas flow rate of 20 sccm for 0.6 s and a purging time of 30 s. H2S is then introduced with a carrier gas flow rate of 20 sccm for 1 s and a purging time of 30 s. After one cycle, a MoS2 layer with a thickness of approximately 0.2 nm is obtained.

[0070] (3) InCp is introduced at a carrier gas flow rate of 15 sccm for 0.6 s, followed by a purging time of 20 s. Oxygen is then introduced at a flow rate of 10 sccm, followed by an inert gas ignition process at a power of 300 W for 15 s, and a purging time of 20 s. After 10 cycles, an indium oxide layer of approximately 0.5 nm is obtained.

[0071] Repeat steps (1)-(3) 11 times to obtain a MoS2-modified IZO thin film with a thickness of approximately 9.9 nm as the active layer of the TFT device, with the structure as follows. Figure 2 As shown.

[0072] Subsequent device fabrication processes: Patterning is achieved on the active layer through etching, then source and drain electrodes are fabricated and patterned, and finally a passivation layer is deposited and patterned to complete device fabrication.

[0073] Example 2:

[0074] Preparation before active layer deposition: The gate and gate insulating layer are sequentially fabricated on the substrate and the device is patterned to serve as the substrate for the ALD deposition process.

[0075] The precursors required for the ALD process are kept at the following temperatures: DEZ precursor, H2O, and H2S precursor are kept at room temperature, InCp precursor is heated to 75°C, and molybdenum chloride (MoCl5) precursor is heated to 120°C.

[0076] Active layer deposition process: The substrate is placed in the ALD equipment and heated to 300°C.

[0077] (1) DEZ is introduced at a carrier gas flow rate of 10 sccm for 0.2 s, followed by a purging time of 20 s. H2O is then introduced for 0.2 s and followed by a purging time of 20 s. After one cycle, a zinc oxide layer with a thickness of approximately 0.2 nm is obtained.

[0078] (2) MoCl5 was introduced at a carrier gas flow rate of 20 sccm for 1 s, followed by a purging time of 30 s. H2S was then introduced at a carrier gas flow rate of 20 sccm for 1 s, followed by a purging time of 30 s. After one cycle, a MoS2 layer with a thickness of approximately 0.2 nm was obtained.

[0079] (3) InCp is introduced at a carrier gas flow rate of 15 sccm for 0.6 s, followed by a purging time of 20 s. Oxygen is then introduced at a flow rate of 10 sccm, followed by an inert gas ignition process at a power of 300 W for 15 s, and a purging time of 20 s. After 10 cycles, an indium oxide layer of approximately 0.5 nm is obtained.

[0080] Repeat steps (1)-(3) 11 times to obtain a MoS2-modified IZO thin film with a thickness of approximately 9.9 nm as the active layer of the TFT device, with the structure as follows. Figure 2 As shown.

[0081] Subsequent device fabrication processes: Patterning is achieved on the active layer through etching, then source and drain electrodes are fabricated and patterned, and finally a passivation layer is deposited and patterned to complete device fabrication.

[0082] Example 3:

[0083] Preparation before active layer deposition: The gate and gate insulating layer are sequentially fabricated on the substrate and the device is patterned to serve as the substrate for the ALD deposition process.

[0084] The precursors required for the ALD process are kept at the following temperatures: DEZ precursor, H2O, and H2S precursor are kept at room temperature; InCp precursor is heated to 75°C; and molybdenum hexacarbonyl (Mo(CO)6) precursor is heated to 60°C.

[0085] Active layer deposition process: The substrate is placed in the ALD equipment and heated to 200°C.

[0086] (1) DEZ is introduced at a carrier gas flow rate of 10 sccm for 0.2 s, followed by a purging time of 20 s. H2O is then introduced for 0.2 s and followed by a purging time of 20 s. After one cycle, a zinc oxide layer with a thickness of approximately 0.2 nm is obtained.

[0087] (2) Mo(CO)6 was introduced with a carrier gas flow rate of 20 sccm for 1 s, followed by a purging time of 30 s. H2S was then introduced with a carrier gas flow rate of 20 sccm for 1 s, followed by a purging time of 30 s. After completing 3 cycles, a MoS2 layer with a thickness of approximately 0.2 nm was obtained.

[0088] (3) InCp is introduced at a carrier gas flow rate of 15 sccm for 0.6 s, followed by a purging time of 20 s. Oxygen is then introduced at a flow rate of 10 sccm, followed by an inert gas ignition process at a power of 300 W for 15 s, and a purging time of 20 s. After 10 cycles, an indium oxide layer of approximately 0.5 nm is obtained.

[0089] Repeat steps (1)-(3) 11 times to obtain a MoS2-modified IZO thin film with a thickness of approximately 9.9 nm as the active layer of the TFT device, with the structure as follows. Figure 2 As shown.

[0090] Subsequent device fabrication processes: Patterning is achieved on the active layer through etching, then source and drain electrodes are fabricated and patterned, and finally a passivation layer is deposited and patterned to complete device fabrication.

[0091] Example 4:

[0092] Preparation before active layer deposition: The gate and gate insulating layer are sequentially fabricated on the substrate and the device is patterned to serve as the substrate for the ALD deposition process.

[0093] The precursors required for the ALD process are kept at the following temperatures: DEZ precursor, H2O, and H2S precursor are kept at room temperature, InCp precursor is heated to 75°C, and Hf(NEtMe)4 precursor is heated to 40°C.

[0094] Active layer deposition process: The substrate is placed in the ALD equipment and heated to 200°C.

[0095] (1) DEZ is introduced at a carrier gas flow rate of 10 sccm for 0.2 s, followed by a purging time of 20 s. H2O is then introduced for 0.2 s and followed by a purging time of 20 s. After one cycle, a zinc oxide layer with a thickness of approximately 0.2 nm is obtained.

[0096] (2) Hf(NEtMe)4 was introduced at a carrier gas flow rate of 20 sccm for 0.6 s, followed by a purge and cleaning time of 30 s. H2S was then introduced at a carrier gas flow rate of 20 sccm for 1 s, followed by a purge and cleaning time of 30 s. After completing 3 cycles, an HfS2 layer with a thickness of approximately 0.2 nm was obtained.

[0097] (3) InCp is introduced at a carrier gas flow rate of 15 sccm for 0.6 s, followed by a purging time of 20 s. Oxygen is then introduced at a flow rate of 10 sccm, followed by an inert gas ignition process at a power of 300 W for 15 s, and a purging time of 20 s. After 10 cycles, an indium oxide layer of approximately 0.5 nm is obtained.

[0098] Repeat steps (1)-(3) 11 times to obtain an HfS2-modified IZO thin film as the active layer of the TFT device, with a thickness of approximately 9.9 nm, and the structure is as follows. Figure 2 As shown.

[0099] Subsequent device fabrication processes: Patterning is achieved on the active layer through etching, then source and drain electrodes are fabricated and patterned, and finally a passivation layer is deposited and patterned to complete device fabrication.

[0100] Example 5:

[0101] Preparation before active layer deposition: The gate and gate insulating layer are sequentially fabricated on the substrate and the device is patterned to serve as the substrate for the ALD deposition process.

[0102] The precursors required for the ALD process are kept at the following temperatures: DEZ precursor, H2O, and H2S precursor are kept at room temperature; InCp precursor is heated to 75°C; and HfCl4 precursor is heated to 130°C.

[0103] Active layer deposition process: The substrate is placed in the ALD equipment and heated to 300°C.

[0104] (1) DEZ is introduced at a carrier gas flow rate of 10 sccm for 0.2 s, followed by a purging time of 20 s. H2O is then introduced for 0.2 s and followed by a purging time of 20 s. After one cycle, a zinc oxide layer with a thickness of approximately 0.2 nm is obtained.

[0105] (2) HfCl4 was introduced at a carrier gas flow rate of 20 sccm for 1 s, followed by a purge cleaning time of 30 s. H2S was then introduced at a carrier gas flow rate of 20 sccm for 1 s, followed by a purge cleaning time of 30 s. After 20 cycles, an HfS2 layer with a thickness of approximately 0.2 nm was obtained.

[0106] (3) InCp is introduced at a carrier gas flow rate of 15 sccm for 0.6 s, followed by a purging time of 20 s. Oxygen is then introduced at a flow rate of 10 sccm, followed by an inert gas ignition process at a power of 300 W for 15 s, and a purging time of 20 s. After 10 cycles, an indium oxide layer of approximately 0.5 nm is obtained.

[0107] Repeat steps (1)-(3) 11 times to obtain an HfS2-modified IZO thin film as the active layer of the TFT device, with a thickness of approximately 9.9 nm, and the structure is as follows. Figure 2 As shown.

[0108] Subsequent device fabrication processes: Patterning is achieved on the active layer through etching, then source and drain electrodes are fabricated and patterned, and finally a passivation layer is deposited and patterned to complete device fabrication.

[0109] Example 6:

[0110] Preparation before active layer deposition: The gate and gate insulating layer are sequentially fabricated on the substrate and the device is patterned to serve as the substrate for the ALD deposition process.

[0111] The precursors required for the ALD process are kept at the following temperatures: DEZ precursor, H2O, and H2S precursor are kept at room temperature, InCp precursor is heated to 75°C, and Mo(NMe2)4 precursor is heated to 60°C.

[0112] Active layer deposition process: The substrate is placed in the ALD equipment and heated to 200°C.

[0113] (1) DEZ was introduced at a carrier gas flow rate of 10 sccm for 0.2 s, followed by a purging time of 20 s. H2O was then introduced for 0.2 s, followed by a purging time of 20 s. After two cycles, a zinc oxide layer with a thickness of approximately 0.4 nm was obtained.

[0114] (2) Mo(NMe2)4 is introduced with a carrier gas flow rate of 20 sccm for 0.6 s and a purging time of 30 s. H2S is then introduced with a carrier gas flow rate of 20 sccm for 1 s and a purging time of 30 s. After one cycle, a MoS2 layer with a thickness of approximately 0.2 nm is obtained.

[0115] (3) InCp is introduced at a carrier gas flow rate of 15 sccm for 0.6 s, followed by a purging time of 20 s. Oxygen is then introduced at a flow rate of 10 sccm, followed by an inert gas initiation process for plasma at a power of 300 W for 15 s, and then a purging time of 20 s. After 20 cycles, an indium oxide layer of approximately 1 nm is obtained.

[0116] Repeat steps (1)-(3) 6 times to obtain a MoS2-modified IZO thin film with a thickness of approximately 9.6 nm as the active layer of the TFT device, with the structure as follows. Figure 2 As shown.

[0117] Subsequent device fabrication processes: Patterning is achieved on the active layer through etching, then source and drain electrodes are fabricated and patterned, and finally a passivation layer is deposited and patterned to complete device fabrication.

[0118] Example 7:

[0119] Preparation before active layer deposition: The gate and gate insulating layer are sequentially fabricated on the substrate and the device is patterned to serve as the substrate for the ALD deposition process.

[0120] The precursors required for the ALD process are kept at the following temperatures: DEZ precursor, H2O, and H2S precursor are kept at room temperature, InCp precursor is heated to 75°C, and Mo(NMe2)4 precursor is heated to 60°C.

[0121] Active layer deposition process: The substrate is placed in the ALD equipment and heated to 200°C.

[0122] (1) DEZ was introduced at a carrier gas flow rate of 10 sccm for 0.2 s, followed by a purging time of 20 s. H2O was then introduced for 0.2 s, followed by a purging time of 20 s. After completing 3 cycles, a zinc oxide layer with a thickness of approximately 0.6 nm was obtained.

[0123] (2) Mo(NMe2)4 is introduced with a carrier gas flow rate of 20 sccm for 0.6 s and a purging time of 30 s. H2S is then introduced with a carrier gas flow rate of 20 sccm for 1 s and a purging time of 30 s. After one cycle, a MoS2 layer with a thickness of approximately 0.2 nm is obtained.

[0124] (3) InCp is introduced at a carrier gas flow rate of 15 sccm for 0.6 s, followed by a purging time of 20 s. Oxygen is then introduced at a flow rate of 10 sccm, followed by an inert gas ignition process at a power of 300 W for 15 s, and a purging time of 20 s. After 30 cycles, an indium oxide layer of approximately 1.5 nm is obtained.

[0125] Repeat steps (1)-(3) 5 times to obtain a MoS2-modified IZO thin film with a thickness of approximately 11.5 nm as the active layer of the TFT device, with the structure as follows. Figure 2 As shown.

[0126] Subsequent device fabrication processes: Patterning is achieved on the active layer through etching, then source and drain electrodes are fabricated and patterned, and finally a passivation layer is deposited and patterned to complete device fabrication.

[0127] Example 8:

[0128] Preparation before active layer deposition: The gate and gate insulating layer are sequentially fabricated on the substrate and the device is patterned to serve as the substrate for the ALD deposition process.

[0129] The precursors required for the ALD process are kept at the following temperatures: DEZ precursor, H2O, and H2S precursor are kept at room temperature, InCp precursor is heated to 75°C, and Mo(NMe2)4 precursor is heated to 60°C.

[0130] Active layer deposition process: The substrate is placed in the ALD equipment and heated to 200°C.

[0131] (1) DEZ was introduced at a carrier gas flow rate of 10 sccm for 0.2 s, followed by a purging time of 20 s. H2O was then introduced for 0.2 s, followed by a purging time of 20 s. After completing 4 cycles, a zinc oxide layer with a thickness of approximately 0.8 nm was obtained.

[0132] (2) Mo(NMe2)4 is introduced with a carrier gas flow rate of 20 sccm for 0.6 s and a purging time of 30 s. H2S is then introduced with a carrier gas flow rate of 20 sccm for 1 s and a purging time of 30 s. After one cycle, a MoS2 layer with a thickness of approximately 0.2 nm is obtained.

[0133] (3) InCp is introduced at a carrier gas flow rate of 15 sccm for 0.6 s, followed by a purging time of 20 s. Oxygen is then introduced at a flow rate of 10 sccm, followed by an inert gas ignition process at a power of 300 W for 15 s, and a purging time of 20 s. After 30 cycles, an indium oxide layer of approximately 2 nm is obtained.

[0134] Repeat steps (1)-(3) four times to obtain a MoS2-modified IZO thin film with a thickness of approximately 12 nm as the active layer of the TFT device, with the structure as follows: Figure 2 As shown.

[0135] Subsequent device fabrication processes: Patterning is achieved on the active layer through etching, then source and drain electrodes are fabricated and patterned, and finally a passivation layer is deposited and patterned to complete device fabrication.

[0136] Table 1

[0137] Example 0 10.5nm 8.3nm Example 1 9.9nm 9.5nm Example 2 9.9nm 8.5nm Example 3 9.9nm 9.5nm Example 4 9.9nm 9.6nm Example 5 9.9nm 8.9nm Example 6 9.6nm 9.4nm Example 7 11.5nm 11.4nm Example 8 12nm 11.9nm

[0138] Table 1 shows the theoretical film thickness, which is the sum of the thicknesses of the individual components. The actual film thickness is the measured IZO film thickness. As can be seen from Table 1, in Example 0, the actual film thickness differs significantly from the theoretical thickness due to the influence of the interface between the two materials and lattice mismatch at the reaction sites. Examples 1-8 optimized the film growth at the interface by adding a passivation layer, resulting in more complete growth of both indium oxide and zinc oxide. The lower actual film thickness in Examples 2 and 5 compared to other examples is because the precursor containing Cl in these examples generates HCl byproducts, which have a certain impact on the IZO film. Examples 6-8, in addition to adding a modification layer, reduced the N value (i.e., the number of film layer alternations), resulting in actual film thicknesses closer to the theoretical growth rate.

[0139] Table 2

[0140] Example 0 29.59 2.86 3.70 Example 1 35.30 2.23 0.97 Example 2 36.25 2.18 0.88 Example 3 34.68 2.37 0.96 Example 4 32.15 2.06 0.75 Example 5 33.30 2.18 0.79 Example 6 35.60 1.97 0.62 Example 7 36.30 1.88 0.46 Example 8 37.43 1.65 0.45

[0141] Table 2 shows the mobility of the TFT devices prepared in each embodiment, and the threshold voltage offset values ​​in the heated bias test (PBTS / NBTS). Compared with the pure IZO system sample of Example 0, the TFT devices optimized with the modified layer all achieved higher mobility. Due to differences in deposition conditions and film structure, the mobility varies among the embodiments. In Examples 6-8, the device mobility gradually increased as the number of film layer alternations decreased. Furthermore, compared with the pure IZO system sample of Example 0, by adding a modified layer and reducing the number of interface alternations, the threshold voltage offset of the device in the PBTS test was slightly reduced, and the threshold voltage offset in the NBTS test was significantly reduced, indicating a significant improvement in device stability.

[0142] The specific embodiments described above illustrate the technical solution and beneficial effects of the present invention in detail. It should be understood that the descriptions are merely specific embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A high-performance atomically deposited oxide thin-film transistor, wherein the overall vertical structural unit, from bottom to top, comprises: a substrate, a gate, a gate insulating layer, an active layer, a source / drain electrode, and a passivation layer; characterized in that, A two-dimensional material is added as a modification layer in the active layer during two metal oxide deposition cycles; The active layer is selected from various ternary metal oxide semiconductors, indium zinc oxide, with a thickness of 8-12 nm; the two-dimensional material used as the modification layer is molybdenum disulfide (MoS2) or hafnium disulfide (HfS2). The substrate is alkali-free glass with a thickness of 0.5 mm to 1.0 mm; the gate, source, and drain are all made of molybdenum (Mo) metal with a thickness of 100-200 nm; the gate insulating layer is a composite film of silicon dioxide and silicon nitride with a thickness of 200-350 nm; and the passivation layer is made of silicon dioxide with a thickness of 200-300 nm.

2. The method for fabricating a high-performance atomic deposition oxide thin-film transistor according to claim 1, characterized in that, Includes the following steps: (1) Clean the alkali-free glass, sputter a metal gate onto it, and etch to achieve patterning; (2) A gate insulating layer is deposited on the gate and etched to achieve patterning; (3) An active layer is prepared on the gate insulating layer by atomic layer deposition. The preparation process is as follows: a. Introduce the first metal precursor into the reaction chamber, purge and clean it, then introduce an oxidant to carry out the oxidation reaction, and purge and clean it again; b. Repeat step a n1 times to obtain the first metal oxide film layer; c. Introduce the precursor of the modification layer material into the reaction chamber, purge and clean it, introduce the reactants to carry out the reaction, and purge and clean it again; d. Repeat step c n² times to obtain the modification layer; e. Introduce a second metal precursor into the reaction chamber, purge and clean, then introduce an oxidant to carry out an oxidation reaction, and purge and clean again. f. Repeat step e n3 times to obtain the second metal oxide film; g. Repeat the af process N times to obtain a multi-component compound film, which is then patterned by etching. (4) Sputter metal source and drain electrodes onto the active layer and etch to achieve patterning; (5) Deposit a passivation layer on the source and drain electrodes and pattern it by etching; The thin-film transistor device can be obtained by completing the above steps.

3. The preparation method according to claim 2, characterized in that, Step (3) describes the atomic layer deposition process of the active layer. ab is the first metal oxide deposition cycle, cd is the modification layer deposition cycle, and ef is the second metal oxide deposition cycle. These three film deposition processes are repeated to obtain an active layer film with an overlapping structure.

4. The preparation method according to claim 2, characterized in that, In steps (3), the precursor materials mentioned in processes a, c, and e are each independently one or more combinations of halides, alkyl compounds, cyclopentadienyl compounds, carbonyl compounds, and alkylamino compounds.

5. The preparation method according to claim 2, characterized in that, In steps (3), the precursor materials described in processes a, c, and e need to be kept in a temperature range of 25-130℃ for gas phase reaction; the temperature range of the active layer deposition process in step (3) is 200-300℃.

6. The preparation method according to claim 2, characterized in that, In step (3), the oxidation reaction pathways in processes a and c are either thermal oxidation by introducing water or plasma-assisted oxidation by introducing oxygen and inert gas.

7. The preparation method according to claim 2, characterized in that, In step (3), the time for the precursor to be introduced into the reaction chamber in processes a and c is 0.2s-1s; the flow rate of the carrier gas introduced into the reaction chamber in processes a and c of step (3) is 10-20sccm.

8. The preparation method according to claim 2, characterized in that, In step (3), the value range of n1 is n 1= 1~4; the value range of n2 is n 2= 1~20; the value range of n3 is n3=10~40; the value range of N is N=3~15.

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