A pipeline successive approximation analog-to-digital converter based on switched load capacitors
First-order noise shaping is achieved in the Pipelined-SAR analog-to-digital converter by using load capacitance swapping technology, which solves the shortcomings of traditional analog-to-digital converters in terms of accuracy and power consumption, and improves the speed and accuracy of the converter.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- UNIV OF ELECTRONICS SCI & TECH OF CHINA
- Filing Date
- 2023-02-27
- Publication Date
- 2026-05-29
AI Technical Summary
Traditional pipelined-SAR analog-to-digital converters suffer from accuracy issues due to residual amplifier gain errors in the pipeline and comparator misalignment in SAR. Furthermore, existing noise shaping techniques increase power consumption and reduce speed.
By employing the load capacitor swapping technique, the load capacitor and amplifier feedback capacitor are swapped through timing logic control. The quantized noise signal stored on the load capacitor in the previous cycle is sent back to the operational amplifier to form a first-order noise shaping, thus avoiding the use of active circuits to extract the noise signal.
It improves the accuracy and speed of analog-to-digital converters while reducing power consumption, achieving high-precision and low-power analog-to-digital conversion.
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Figure CN116366061B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of analog integrated circuit technology, specifically a pipelined successive approximation analog-to-digital converter based on switched load capacitance, involving noise shaping circuits, which can be applied to pipelined converters. Background Technology
[0002] In many application areas, the demand for analog-to-digital converters (ADCs) is increasing. ADCs are widely used in wireless charging, the Internet of Things (IoT), automotive electronics, smart homes, and other applications, bridging various electrical functions by converting data from analog to digital. ADCs can be categorized into Flash ADCs, successive approximation (SAR) ADCs, pipelined ADCs, and Sigma-delta ADCs. Currently, in high-speed electrical equipment applications, the high-speed but high-power pipelined ADC is often combined with the low-power but slower successive approximation ADC. The pipelined-SAR ADC combines the advantages of both basic structures.
[0003] Traditional pipelined-SAR architectures typically consist of multiple cascaded sub-ADCs connected by residual amplifiers. This pipelined parallel structure reduces the clock cycle required to complete one data quantization step compared to serial successive approximation analog-to-digital converters, thus improving conversion speed. Each sub-ADC stage uses a single-comparator successive approximation analog-to-digital converter instead of the traditional multi-comparator Flash structure, significantly reducing overall power consumption by decreasing the number of comparators. Furthermore, the capacitor array in the successive approximation analog-to-digital converter can replace the sample-and-hold (S / H) circuitry in the traditional pipeline, reducing static power consumption and avoiding the introduction of active circuitry, thus ensuring relatively constant performance across process corners, power supply voltages, and temperature (PVT).
[0004] However, in terms of accuracy, Pipelined-SAR is affected not only by the gain error of the residual amplifier in the pipeline but also by the comparator offset in SAR affecting the quantization results. The Integrated Circuits Centre at the University of Macau has improved accuracy by applying oversampling and noise shaping techniques from a Sigma-delta analog-to-digital converter to Pipelined-SAR to suppress noise. The drawback is the introduction of additional active circuitry, which increases power consumption and reduces speed. Summary of the Invention
[0005] To address the aforementioned problems and shortcomings, this invention provides a pipelined successive approximation analog-to-digital converter (ADC) based on swapped load capacitors. Timing logic controls the swapping of the load capacitor and the amplifier feedback capacitor. The swapped feedback capacitor then sends the quantization noise signal stored on the load capacitor from the previous cycle back to the operational amplifier, forming first-order noise shaping. This suppresses the impact of second-stage quantization noise on the accuracy of the pipelined-SAR ADC, increasing the effective number of bits. Swapping the load capacitors avoids the use of active circuits to extract noise signals, resulting in low power consumption, high speed, and high accuracy, effectively solving the problems of existing technologies.
[0006] A pipelined successive approximation analog-to-digital converter based on switched load capacitance, employing a fully differential structure, such as... Figure 1 As shown, it includes a first-stage sub-analog-to-digital converter, a residual amplifier, a second-stage sub-analog-to-digital converter, a digital code output circuit, and a switching load capacitor circuit.
[0007] The first-stage sub-analog-to-digital converter samples the input analog signal and performs analog-to-digital conversion. It consists of a capacitor array digital-to-analog converter, a dynamic comparator, and a successive approximation logic circuit.
[0008] The first-stage sub-analog-to-digital converter has two output terminals. The converted digital signal flows into the digital code value output circuit through the successive approximation logic circuit. The residual signal of the upper plate of the capacitor array type digital-to-analog converter flows to the residual amplifier through switch S2.
[0009] The following is combined with Figure 1 and Figure 2 Working principle explanation: The first-stage sub-analog-to-digital converter (ADC) first enters the sampling stage, sampling the input signal Vin through switch S1. At this time, S1 is closed and S2 is open. During the quantization process, i.e., the first-stage sub-analog-to-digital converter converts the analog signal to a digital signal, switches S1 and S2 are open. The analog signal output from the capacitor array ADC is sent to the dynamic comparator. After receiving the analog signal from the capacitor array ADC, the input of the dynamic comparator begins to compare and outputs a high-level or low-level analog signal. The output analog signal flows to the successive approximation logic circuit, which guides the control switch of the capacitor array ADC to switch and convert the next bit of data. After quantization is completed, i.e., the first-stage sub-analog-to-digital converter completes the analog-to-digital conversion process and begins to amplify the residual voltage of the first-stage sub-analog-to-digital converter, switches S1 and S2 are closed. The upper plate of the capacitor array ADC stores the residual signal of the current period. This output signal is received by the input of the residual amplifier via switch S2.
[0010] The residual amplifier adopts a closed-loop switched capacitor structure, consisting of an operational amplifier, a feedback capacitor, and a load capacitor. Its gain is the ratio of the total capacitance of the capacitor array in the first-stage sub-analog-to-digital converter to the feedback capacitor. The negative input terminal of the operational amplifier is connected to the upper plate of the first-stage sub-analog-to-digital converter via switch S2, the positive input terminal is grounded, and the output terminal is connected to the upper plate of the second-stage sub-analog-to-digital converter via switch S3. Capacitor C f1 The capacitor C is connected between the negative input and output terminals of the operational amplifier. f2 One end is grounded, and the other end is connected to the output of the operational amplifier. Capacitor C f1 and C f2 By using a load capacitor switching circuit to control the opening and closing of its switches through timing, the C in the residual amplifier can be realized. f1 and C f2 As an exchange of load capacitance and feedback capacitance, the load capacitance switching circuit is set on the feedback path and output terminal of the residual amplifier.
[0011] When switch S2 is closed, the input signal of the operational amplifier is the residual signal stored on the upper plate after the first-stage sub-analog-to-digital converter has been quantized, which is then amplified to the reference voltage of the second-stage sub-analog-to-digital converter.
[0012] When switch S3 is closed, the output signal of the operational amplifier is sampled by the second-stage sub-analog-to-digital converter, which is then used to initiate the conversion of the analog signal to a digital signal.
[0013] The second-stage sub-analog-to-digital converter consists of a capacitor array type digital-to-analog converter, a dynamic comparator, and a successive approximation logic circuit. The input terminal of the second-stage sub-analog-to-digital converter samples the residual voltage of the first-stage sub-analog-to-digital converter after it has been amplified by the residual amplifier. The second-stage sub-analog-to-digital converter has only one output terminal, and the converted digital signal flows into the digital code value output circuit through the successive approximation logic circuit.
[0014] The following is combined with Figure 1 and Figure 2 Working principle explanation: The second-stage sub-analog-to-digital converter first enters the quantization stage. At this time, switch S3 is opened, and the process of converting analog signals to digital signals begins. The analog signal output from the capacitor array ADC is sent to the dynamic comparator. After receiving the analog signal from the capacitor array ADC, the input of the dynamic comparator begins to compare and outputs a high-level or low-level analog signal. The output signal flows to the successive approximation logic circuit, which guides the control switch of the capacitor array ADC to switch and convert the next bit of data. When the quantization process is completed, switch S3 is closed, and the sampling stage begins, sampling the output signal amplified by the residual amplifier.
[0015] The load capacitor switching circuit is located on the feedback path and output of the residual amplifier. It uses timing control to open and close the switch, thereby swapping the load capacitor and feedback capacitor of the residual amplifier. The basic principle is that the quantization noise of the second-stage sub-analog-to-digital converter from the previous cycle, stored on the load capacitor, is fed to the input of the residual amplifier through the upper plate of the feedback capacitor for processing. This achieves first-order error feedback noise shaping, and finally, a new signal processed by the noise transfer function is collected on the load capacitor in the current cycle, thus improving the overall circuit accuracy.
[0016] Reference Figures 3-6 The switching circuit for the load capacitor contains two sampling cycles in one complete cycle, C f1 With C f2 The capacitors operate in different states, one sampling cycle apart. They follow the sequence of floating at the feedback capacitor, switching to the load capacitor position and sampling the output signal of the residual amplifier together with the second-stage sub-analog-to-digital converter, participating in the quantization process of the second-stage sub-analog-to-digital converter at the load capacitor, and then switching back to the feedback capacitor position.
[0017] Reference Figure 2 Within one sampling period, the load capacitor switching circuit controls capacitor C through switching. f1 C f2 After one exchange and two sampling periods, the capacitor C f1 C f2 Returning to the initial position; based on the basic principle of the pipelined successive approximation analog-to-digital converter structure, the first-stage sub-analog-to-digital converter operates in the order of sampling / holding, quantization, and residual amplifier amplification of the residual voltage. The second-stage sub-analog-to-digital converter does not need to sample the input signal, but instead samples the output signal of the residual amplifier, and only needs to operate in the order of quantization and sampling / holding.
[0018] The digital code output circuit receives digital signals from the first-stage sub-analog-to-digital converter and the second-stage sub-analog-to-digital converter at its input. It employs an inter-stage redundancy structure and integrates the code values internally using digital logic, ultimately outputting a 10-bit digital code value. This increases the actual effective number of bits to [amount missing]. Figure 8 The 12.55 bits shown also demonstrate the effectiveness of this invention in improving the accuracy of pipelined successive approximation analog-to-digital converters.
[0019] Furthermore, as a preferred embodiment, the sampling switch S1 of the first-stage sub-analog-to-digital converter is a bootstrapped switch, which reduces the influence of the input signal on the switch's on-resistance and improves the linearity of the sampling signal. Simultaneously, the capacitor array type digital-to-analog converter uses lower plate sampling to reduce the impact of charge injection in the switch channel on the sampling signal when the control switch is turned on. Considering its application in high-speed fields, the capacitor array weights of the first-stage sub-analog-to-digital converter are set to non-binary to improve setup speed and shorten quantization time. The dynamic comparator of the first-stage sub-analog-to-digital converter incorporates a current injection circuit based on a charge pump structure for comparator offset self-correction, reducing the error caused by the dynamic comparator offset in the first-stage sub-analog-to-digital converter during signal conversion from analog to digital. The successive approximation logic circuit of the first-stage sub-analog-to-digital converter adopts a quasi-static LATCH structure, which reduces the time required for successive approximation logic circuitry in a single quantization cycle through positive feedback latching, thereby improving the overall circuit speed.
[0020] Furthermore, as a preferred option, the operational amplifier in the residual amplifier adopts a folded cascode structure to provide a large swing range of output signal; at the same time, the operational amplifier in the residual amplifier also adopts gain-boost technology to further improve the open-loop gain and reduce the impact of its non-ideal factors on the closed-loop gain accuracy.
[0021] Furthermore, as a preferred option, the capacitor array type digital-to-analog converter of the second-stage sub-analog-to-digital converter uses upper-plate sampling. Compared to lower-plate sampling, this reduces the impact of parasitic capacitance at the lower plate on capacitor weights, thus improving quantization accuracy. Considering its application in high-speed fields, the capacitor array weights of the second-stage sub-analog-to-digital converter are set to non-binary to improve setup speed and shorten quantization time. The dynamic comparator of the second-stage sub-analog-to-digital converter requires high resolution, so a structure with a preamplifier is adopted to improve the speed of analog signal comparison in one operation. The successive approximation logic circuit of the second-stage sub-analog-to-digital converter adopts a quasi-static LATCH structure, using positive feedback latching to reduce the time required for successive approximation logic circuitry in one quantization operation, thereby improving the overall circuit speed.
[0022] Furthermore, as a preferred option, such as Figure 3 As shown, the load capacitor switching circuit is located between the residual amplifier and the second-stage sub-analog-to-digital converter, consisting of switches Sw1-Sw8, S3, and a capacitor C of equal size. f1 C f2 Composition; wherein switches Sw1-Sw4 and capacitor C f1 Connect Sw5-Sw8 to capacitor C f2 Connected, switch S3 is connected to capacitor C f1 The upper plate and capacitor C f2The upper electrode plate. The timing sequence of switches Sw1-Sw8, as follows: Figure 8 As shown, this ultimately achieves the suppression of quantization noise in the second-stage sub-analog-to-digital converter, improving the overall accuracy of the circuit.
[0023] In summary, this invention controls the exchange of the load capacitor and feedback capacitor in the residual amplifier through a load capacitor switching circuit. This extracts the quantization noise from the second-stage sub-analog-to-digital converter in the previous sampling period and performs first-order error feedback noise shaping through the residual amplifier in the current sampling period. This reduces the accuracy impact of unprocessed final-stage quantization noise in traditional pipelined successive approximation analog-to-digital converters. The load capacitor switching circuit, controlled by a clock signal, extracts the quantization noise from the second-stage sub-analog-to-digital converter. Compared to using active circuits, this effectively reduces overall power consumption while increasing the speed at which the pipelined successive approximation analog-to-digital converter completes one data conversion. Attached Figure Description
[0024] Figure 1 This is the circuit schematic diagram of the present invention;
[0025] Figure 2 This is a schematic diagram of the switching circuit for the switching load capacitor of the present invention;
[0026] Figure 3 This is a schematic diagram of state (b) in the flowchart of the switching load capacitor switching circuit of the present invention;
[0027] Figure 4 This is a schematic diagram of state (a) in the flowchart of the switching load capacitor switching circuit of the present invention;
[0028] Figure 5 This is a schematic diagram of state (c) in the flowchart of the switching load capacitor switching circuit of the present invention;
[0029] Figure 6 This is a schematic diagram of state (d) in the flowchart of the switching load capacitor switching circuit of the present invention;
[0030] Figure 7 This is a timing diagram of switches Sw1-8 in the switching circuit of the load capacitor of the present invention;
[0031] Figure 8 This is a schematic diagram of the spectrum analysis of the pre-FFT simulation of the present invention. Detailed Implementation
[0032] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments.
[0033] This embodiment is based on a pipelined successive approximation analog-to-digital converter with switched load capacitance, employing a fully differential structure (e.g., Figure 1As shown, it includes a first-stage sub-analog-to-digital converter, a residual amplifier, a second-stage sub-analog-to-digital converter, a switching load capacitor circuit, and a digital code output circuit.
[0034] The first-stage sub-analog-to-digital converter samples the input analog signal and performs analog-to-digital conversion. It consists of a capacitor array digital-to-analog converter, a dynamic comparator, and successive approximation logic circuitry. The capacitor array digital-to-analog converter itself comprises a capacitor array and control switches. The first-stage sub-analog-to-digital converter has two output terminals. The converted digital signal flows into the digital code value output circuit through the successive approximation logic circuitry, while the residual signal from the upper plate of the capacitor array digital-to-analog converter flows to the residual amplifier via switch S2.
[0035] The following is combined with Figure 1 and Figure 2 To explain the specific working principle, the first-stage sub-analog-to-digital converter (ADC) first enters the sampling stage, sampling the input signal Vin through switch S1. At this time, S1 is closed and S2 is open. During the quantization process, i.e., the first-stage sub-analog-to-digital converter converts the analog signal to a digital signal, switches S1 and S2 are open. The analog signal output from the capacitor array ADC is sent to the dynamic comparator. After receiving the analog signal from the capacitor array ADC, the input of the dynamic comparator begins to compare and outputs a high-level or low-level analog signal. The output signal flows to the successive approximation logic circuit, which guides the control switch of the capacitor array ADC to switch and convert the next bit of data. After quantization is completed, i.e., the first-stage sub-analog-to-digital converter completes the conversion process and begins to amplify the residual voltage of the first-stage sub-analog-to-digital converter, switches S1 and S2 are closed. The upper plate of the capacitor array ADC stores the residual signal of the current period, and this output signal is received by the input of the residual amplifier via switch S2.
[0036] The sampling switch S1 of the first-stage sub-analog-to-digital converter (ADC) is a bootstrapped switch, which reduces the influence of the input signal on the switch's on-resistance and improves the linearity of the sampled signal. Simultaneously, the capacitor array ADC uses lower plate sampling to reduce the impact of charge injection into the switch channel on the sampled signal when the control switch is open. Considering its application in high-speed fields, the capacitor array weights of the first-stage ADC are set to non-binary to improve setup speed and shorten quantization time. The dynamic comparator of the first-stage ADC incorporates a current injection circuit based on a charge pump structure for comparator offset self-correction, reducing the error caused by the dynamic comparator offset during the analog-to-digital conversion. The successive approximation logic circuit of the first-stage ADC adopts a quasi-static LATCH structure, and the positive feedback latching method reduces the time required for successive approximation logic circuitry in a single quantization, thereby improving the overall circuit speed.
[0037] The residual amplifier employs a closed-loop switched-capacitor structure, consisting of an operational amplifier, a feedback capacitor, and a load capacitor. Its gain is the ratio of the total capacitance of the capacitor array in the first-stage sub-analog-to-digital converter to the feedback capacitor. When switch S2 is closed, the input signal to the operational amplifier is the residual signal stored on the upper plate after quantization by the first-stage sub-analog-to-digital converter, which is amplified to the reference voltage of the second-stage sub-analog-to-digital converter. When switch S3 is closed, the output signal is sampled by the second-stage sub-analog-to-digital converter and used to initiate the analog-to-digital conversion.
[0038] The operational amplifier employs a folded cascode structure to provide a wide-swing output signal. Simultaneously, it utilizes gain-boost technology to further enhance the open-loop gain and reduce the impact of non-ideal factors on the closed-loop gain accuracy.
[0039] The second-stage sub-analog-to-digital converter consists of a capacitor array type digital-to-analog converter, a dynamic comparator, and a successive approximation logic circuit. The input terminal of the second-stage sub-analog-to-digital converter samples the residual voltage of the first-stage sub-analog-to-digital converter after it has been amplified by the residual amplifier. The second-stage sub-analog-to-digital converter has only one output terminal, and the converted digital signal flows into the digital code value output circuit through the successive approximation logic circuit.
[0040] The following is combined with Figure 1 and Figure 2Here's a breakdown of the working principle: The second-stage sub-analog-to-digital converter (ADC) first enters the quantization stage. At this time, switch S3 opens, initiating the conversion process from analog to digital signals. The analog signal output from the capacitor array ADC is fed into the dynamic comparator. After receiving the analog signal from the capacitor array ADC, the dynamic comparator's input terminal compares the signals and outputs a high-level or low-level analog signal. The output signal flows to the successive approximation logic circuit, which guides the control switch of the capacitor array ADC to switch and convert the next bit of data. When the quantization process is complete, switch S3 closes, entering the sampling stage, where the output signal amplified by the residual amplifier is sampled.
[0041] The capacitor array type ADC of the second-stage sub-ADC uses upper-plate sampling, which reduces the impact of parasitic capacitance at the lower plate on capacitor weights and improves quantization accuracy compared to lower-plate sampling. Considering its application in high-speed fields, the capacitor array weights of the second-stage sub-ADC are set to non-binary to improve setup speed and shorten quantization time. The dynamic comparator of the second-stage sub-ADC requires high resolution, so a structure with a preamplifier is adopted to improve the speed of analog signal comparison in one operation. The successive approximation logic circuit of the second-stage sub-ADC adopts a quasi-static LATCH structure. Through positive feedback latching, the time required for successive approximation logic circuits in one quantization operation can be reduced, thereby improving the overall circuit speed.
[0042] The switching circuit for the exchanged load capacitor is located on the feedback path and output terminal of the residual amplifier. It uses timing control to open and close the switch, thereby realizing the capacitance C... f1 and C f2 This involves the exchange of the load capacitor and the feedback capacitor. The basic principle is that the quantization noise of the second-stage sub-analog-to-digital converter of the previous cycle, stored on the load capacitor, is sent to the input of the residual amplifier through the upper plate of the feedback capacitor for processing. This achieves first-order error feedback noise shaping, and finally, a new signal processed by the noise transfer function is collected on the load capacitor in the current cycle, thereby improving the accuracy of the overall circuit.
[0043] The switching circuit for the exchanged load capacitor in this embodiment consists of switches Sw1-Sw8, S3, and a capacitor C of equal size. f1 C f2 Composition (e.g.) Figure 3 (as shown); where switches Sw1-Sw4 and capacitor C f1 Connected, with Sw5-Sw8 connected to capacitor C. f2 Connected, switch S3 is connected to capacitor C f1 The upper plate and capacitor C f2 The upper plate. The specific timing sequence of switches Sw1-Sw8 in the load capacitor switching circuit is as follows: Figure 7 As shown, the two sampling cycles of the pipelined successive approximation analog-to-digital converter constitute one complete operating cycle of the load capacitor switching circuit. In the first exchange, switches Sw1, Sw3, Sw5, Sw6, Sw7, and Sw8 are open, and Sw2 and Sw4 are closed. During the first exchange, switches Sw1, Sw3, Sw5, Sw6, and Sw8 are closed, and Sw2, Sw4, and Sw7 are open. In the second exchange, switches Sw1, Sw2, Sw3, Sw4, Sw5, and Sw7 are open, and Sw6 and Sw8 are closed. During the second exchange, switches Sw1, Sw2, Sw4, Sw5, and Sw7 are closed, and Sw3, Sw6, and Sw8 are open.
[0044] Reference Figures 3-6 The switching circuit for the load capacitor contains two sampling cycles in one complete cycle, C f1 With C f2 The capacitors operate in states that differ by one sampling cycle. The sequence is: floating at the feedback capacitor – switching to the load capacitor position and sampling the residual amplifier's output signal together with the second-stage sub-analog-to-digital converter – participating in the quantization process of the second-stage sub-analog-to-digital converter at the load capacitor – switching back to the feedback capacitor position. This ultimately suppresses quantization noise in the second-stage sub-analog-to-digital converter, improving the overall circuit accuracy.
[0045] Reference Figure 2 Within one sampling period, the capacitance C of the load capacitor switching circuit is exchanged. f1 C f2 After one exchange and two sampling periods, the capacitor C f1 C f2 Returning to the initial position; based on the basic principle of the pipelined successive approximation analog-to-digital converter structure, the first-stage sub-analog-to-digital converter operates in the order of sampling / holding, quantization, and residual amplifier amplification of the residual voltage. The second-stage sub-analog-to-digital converter does not need to sample the input signal, but instead samples the output signal of the residual amplifier, and only needs to operate in the order of quantization and sampling / holding.
[0046] For specific workflow details, please refer to... Figure 2 The switching circuit for exchanging load capacitors can be divided into four states:
[0047] (a) First exchange to be made: Refer to Figure 4 At this time, switch S1 is closed and S2 is open, the first-stage sub-analog-to-digital converter is in the sampling / quantization stage, and switch S3 is open, the second-stage sub-analog-to-digital converter is in the quantization stage. In the load capacitor switching circuit, switches Sw1 and Sw3 are open, and Sw2 and Sw4 are closed, and capacitor C... f1Located at the load capacitor, it stores the quantization noise of the second-stage sub-analog-to-digital converter. Switches Sw5-Sw8 are open, and capacitor C... f2 Located at the feedback capacitor and in a floating state, ready for the first exchange.
[0048] (b) First exchange: Refer to Figure 3 At this time, switch S1 is open and S2 is closed. The first-stage sub-analog-to-digital converter sends the residual signal to the residual amplifier for amplification. Switch S3 is closed, and the second-stage sub-analog-to-digital converter samples the output signal of the residual amplifier. In the load capacitor switching circuit, switches Sw1 and Sw3 are closed, and Sw2 and Sw4 are open, allowing capacitor C to... f1 Located at the feedback capacitor, it participates in the residual amplifier to amplify the first-stage residual signal. Simultaneously, it feeds the quantization noise of the second-stage sub-analog-to-digital converter sampled in the switching state into the input of the residual amplifier, forming a first-order error feedback noise shaping. Switches Sw5 and Sw7 are open, while Sw6 and Sw8 are closed, and capacitor C... f2 Located at the load capacitor, it participates in the residual amplifier to amplify the residual signal of the first-stage sub-analog-to-digital converter.
[0049] (c) Second exchange to be made: Refer to Figure 5 At this time, switch S1 is closed and S2 is open, the first-stage sub-analog-to-digital converter is in the sampling / quantization stage, switch S3 is open, and the second-stage sub-analog-to-digital converter is in the quantization stage. Switches Sw1-Sw4 of the load capacitor switching circuit are open, and capacitor C... f1 Located at the feedback capacitor and in a floating state, switches Sw5 and Sw7 are open, while Sw6 and Sw8 are closed, and capacitor C... f2 Located at the load capacitor, it stores the quantization noise of the second-stage sub-analog-to-digital converter, in preparation for the second exchange.
[0050] (d) Second exchange: Refer to Figure 6 At this time, switch S1 is open and S2 is closed. The first-stage sub-analog-to-digital converter sends the residual signal to the residual amplifier for amplification. Switch S3 is closed, and the second-stage sub-analog-to-digital converter samples the output signal of the residual amplifier. In the load capacitor switching circuit, switches Sw1 and Sw3 are open, and Sw2 and Sw4 are closed, and capacitor C... f1 Located at the load capacitor, it participates in the residual amplifier to amplify the residual signal of the first-stage sub-analog-to-digital converter. Switches Sw5 and Sw7 are closed, and Sw6 and Sw8 are open. Capacitor C f2 Located at the feedback capacitor, it participates in the residual amplifier to amplify the first-stage residual signal, and at the same time, it also sends the quantization noise of the second-stage sub-analog-to-digital converter sampled in the state to be switched to the input of the residual amplifier, forming a first-order error feedback noise shaping.
[0051] The digital code output circuit receives digital signals from the first-stage sub-analog-to-digital converter and the second-stage sub-analog-to-digital converter at its input. It employs an inter-stage redundancy structure and integrates the code values internally using digital logic, ultimately outputting a 10-bit digital code value. This increases the actual effective number of bits to [amount missing]. Figure 8 The 12.55 bits shown also demonstrate the effectiveness of this invention in improving the accuracy of pipelined successive approximation analog-to-digital converters.
[0052] After performing an FFT transform on the output codeword at a power supply voltage of 1.8V and a TT Corner temperature of 65℃, the acquired signal spectrum was obtained by simulating 1024 sampling points, as shown below. Figure 8 As shown, the pipelined successive approximation analog-to-digital converter based on the switched load capacitor of this invention achieves a signal-to-noise ratio (SNDR) of 77.30 dB, an effective bit depth of approximately 12.55, and an SFDR of 90.81 dB with an input signal bandwidth of 49.71 MHz and an oversampling rate of 8x. Compared to the circuit without the switched load capacitor, this represents a 15.14 dB improvement in SNDR and a 2.5 bit improvement in effective bit depth. This embodiment effectively improves accuracy, and simulations verify the feasibility of the circuit structure of this invention.
[0053] As can be seen from the above embodiments, the present invention extracts the quantization noise of the second-stage sub-analog-to-digital converter in the previous sampling period by switching the load capacitor, thereby achieving first-order error feedback noise shaping. This reduces the accuracy impact caused by the unprocessed final-stage quantization noise in traditional pipelined successive approximation analog-to-digital converters. The switching load capacitor circuit controls the switching via a clock signal to extract the quantization noise of the second-stage sub-analog-to-digital converter, avoiding the use of additional active circuits to extract noise signals, improving the overall circuit speed while reducing power consumption. This structure integrates the advantages of pipelined successive approximation analog-to-digital converters and noise shaping structures, achieving high speed, high accuracy, and low power consumption.
Claims
1. A pipelined successive approximation analog-to-digital converter based on switched load capacitance, characterized in that: It adopts a fully differential structure, including a first-stage sub-analog-to-digital converter, a residual amplifier, a second-stage sub-analog-to-digital converter, a digital code output circuit, and a switching circuit for the load capacitor. The first-stage sub-analog-to-digital converter consists of a capacitor array digital-to-analog converter, a dynamic comparator, and a successive approximation logic circuit; it samples the input analog signal and performs analog-to-digital conversion. The first-stage sub-analog-to-digital converter has two output terminals. The converted digital signal flows into the digital code value output circuit through the successive approximation logic circuit. The residual signal of the upper plate of the capacitor array type digital-to-analog converter flows to the residual amplifier through switch S2. Specific workflow: The first-stage sub-analog-to-digital converter (ADC) first enters the sampling stage, sampling the input signal Vin through switch S1. At this time, S1 is closed and S2 is open. During the quantization process, i.e., the first-stage sub-analog-to-digital converter converts the analog signal to a digital signal, switches S1 and S2 are open. The analog signal output from the capacitor array ADC is sent to the dynamic comparator. After receiving the analog signal from the capacitor array ADC, the input of the dynamic comparator begins to compare and outputs a high-level or low-level analog signal. The output analog signal flows to the successive approximation logic circuit, which guides the control switch of the capacitor array ADC to switch and convert the next bit of data. After quantization is completed, i.e., the first-stage sub-analog-to-digital converter completes the conversion process from analog to digital signal and begins to amplify the residual voltage of the first-stage sub-analog-to-digital converter, switches S1 and S2 are closed. The upper plate of the capacitor array ADC stores the residual signal of the current period, which is received by the input of the residual amplifier via switch S2. The residual amplifier adopts a closed-loop switched capacitor structure, consisting of an operational amplifier, a feedback capacitor, and a load capacitor. Its gain is the ratio of the total capacitance of the capacitor array in the first-stage sub-analog-to-digital converter to the feedback capacitor. The negative input terminal of the operational amplifier is connected to the upper plate of the first-stage sub-analog-to-digital converter via switch S2, the positive input terminal is grounded, and the output terminal is connected to the upper plate of the second-stage sub-analog-to-digital converter via switch S3. Capacitor C f1 The capacitor C is connected between the negative input and output terminals of the operational amplifier. f2 One end is grounded, and the other end is connected to the output of the operational amplifier; capacitor C f1 and capacitor C f2 By using a load capacitor switching circuit to control the opening and closing of its switches through timing, the C in the residual amplifier can be realized. f1 and C f2 As an exchange of load capacitance and feedback capacitance, the load capacitance switching circuit is set on the feedback path and output terminal of the residual amplifier. When switch S2 is closed, the input signal of the operational amplifier is the residual signal stored on the upper plate after the first-stage sub-analog-to-digital converter has completed quantization, which is then amplified to the reference voltage of the second-stage sub-analog-to-digital converter. When switch S3 is closed, the output signal of the operational amplifier is sampled by the second-stage sub-analog-to-digital converter, which is used to start the conversion of the analog signal to the digital signal. The second-stage sub-analog-to-digital converter consists of a capacitor array type digital-to-analog converter, a dynamic comparator, and a successive approximation logic circuit. The input terminal of the second-stage sub-analog-to-digital converter samples the residual voltage of the first-stage sub-analog-to-digital converter after it has been amplified by the residual amplifier. The second-stage sub-analog-to-digital converter has only one output terminal, and the converted digital signal flows into the digital code value output circuit through the successive approximation logic circuit. Specific workflow: The second-stage sub-analog-to-digital converter first enters the quantization stage. At this time, switch S3 is opened, and the process of converting analog signals to digital signals begins. The analog signal output from the capacitor array digital-to-analog converter is sent to the dynamic comparator. After receiving the analog signal from the capacitor array digital-to-analog converter, the input of the dynamic comparator begins to compare and outputs a high-level or low-level analog signal. The output signal flows to the successive approximation logic circuit, which guides the control switch of the capacitor array digital-to-analog converter to switch and convert the next bit of data. When the quantization process is completed, switch S3 is closed, and the sampling stage begins, sampling the output signal amplified by the residual amplifier. The switching circuit for the load capacitor is located on the feedback path and output terminal of the residual amplifier. It uses timing control to open and close the switch, thereby controlling the capacitance C in the residual amplifier. f1 and C f2 As a result of the exchange between the load capacitor and the feedback capacitor, the basic principle is to transfer the quantization noise of the second-stage sub-analog-to-digital converter of the previous cycle stored on the load capacitor to the input of the residual amplifier through the exchange of capacitor positions. This achieves first-order error feedback noise shaping and finally collects a new signal processed by the noise transfer function on the load capacitor in the current cycle, thereby improving the accuracy of the overall circuit. The switching circuit for exchanging load capacitors contains two sampling cycles in one complete cycle, C f1 With C f2 The capacitors operate in states that differ by one sampling cycle, following the sequence: floating at the feedback capacitor – switching to the load capacitor position and sampling the residual amplifier's output signal together with the second-stage sub-analog-to-digital converter – participating in the quantization process of the second-stage sub-analog-to-digital converter at the load capacitor – switching back to the feedback capacitor position. Within one sampling cycle, the load capacitor switching circuit controls capacitor C through switching. f1 C f2 After one exchange and two sampling periods, the capacitor C f1 C f2 Returning to the initial position; the first-stage sub-analog-to-digital converter operates in the order of sample / hold, quantization, and residual amplifier amplification of the residual voltage. The second-stage sub-analog-to-digital converter does not need to sample the input signal, but instead samples the output signal of the residual amplifier, and only needs to operate in the order of quantization and sample / hold. The input terminal of the digital code value output circuit receives digital signals from the first-stage sub-analog-to-digital converter and the second-stage sub-analog-to-digital converter. It adopts an inter-stage redundancy structure and integrates code values internally through digital logic, ultimately outputting a 10-bit digital code value.
2. The pipelined successive approximation analog-to-digital converter based on switched load capacitance as described in claim 1, characterized in that: The sampling switch S1 of the first-stage sub-analog-to-digital converter is a gate voltage bootstrap circuit to reduce the influence of the input signal on the switch conduction resistance and improve the linearity of the sampling signal. At the same time, the capacitor array type digital-to-analog converter uses lower plate sampling to reduce the influence of charge injection in the switch channel on the sampling signal when the control switch is turned on.
3. The pipelined successive approximation analog-to-digital converter based on switched load capacitance as described in claim 1, characterized in that: The capacitor array weights of the first-stage sub-analog-to-digital converter are set to non-binary to improve setup speed and shorten quantization time. The dynamic comparator of the first-stage sub-analog-to-digital converter adds a current injection circuit based on a charge pump structure to self-correct comparator offset and reduce the error caused by the dynamic comparator offset of the first-stage sub-analog-to-digital converter in the signal conversion from analog to digital. The successive approximation logic circuit of the first-stage sub-analog-to-digital converter adopts a quasi-static LATCH structure and uses positive feedback latching to reduce the time required for successive approximation logic circuit in one quantization, thereby improving the overall speed of the circuit.
4. The pipelined successive approximation analog-to-digital converter based on switched load capacitance as described in claim 1, characterized in that: The operational amplifier employs a folded cascode structure to provide a wide-swing output signal; at the same time, the operational amplifier also uses Gain-Boost technology to further enhance the open-loop gain.
5. The pipelined successive approximation analog-to-digital converter based on switched load capacitance as described in claim 1, characterized in that: The capacitor array type digital-to-analog converter of the second-stage sub-analog converter uses upper plate sampling to reduce the influence of parasitic capacitance at the lower plate on capacitor weight and improve quantization accuracy.
6. The pipelined successive approximation analog-to-digital converter based on switched load capacitance as described in claim 1, characterized in that: The capacitor array weights of the second-stage sub-analog-to-digital converter are set to non-binary to improve setup speed and shorten quantization time; the dynamic comparator of the second-stage sub-analog-to-digital converter adopts a structure with a preamplifier to improve the speed of analog signal comparison; the successive approximation logic circuit of the second-stage sub-analog-to-digital converter adopts a quasi-static LATCH structure, and reduces the time required for successive approximation logic circuit in one quantization through positive feedback latching, thereby improving the overall speed of the circuit.
7. The pipelined successive approximation analog-to-digital converter based on switched load capacitance as described in claim 1, characterized in that: The switching circuit for the exchanged load capacitor consists of switches Sw1-Sw8, S3, and a capacitor C of equal size. f1 C f2 The structure consists of switches Sw1-Sw4 and capacitor C. f1 Connect Sw5-Sw8 to capacitor C f2 Connected, switch S3 is connected to capacitor C f1 The upper plate and capacitor C f2 The upper electrode plate.