A TDD power amplifier control circuit and device

Abstract

The application discloses a TDD power amplifier control circuit and equipment, and relates to the technical field of wireless communication. The control circuit comprises a control source anti-same-high control circuit. The control source anti-same-high control circuit is used for receiving a first control source signal and a second control source signal sent by a synchronization equipment, and when the first control source signal and the second control source signal are both high level, corresponding first control signals of high level and second control signals of low level are output. The level of the control source signal can be controlled to simultaneously control uplink and downlink switches and uplink and downlink switching switches, and the correctness of the switch logic is ensured, and the reliability of the overall system is ensured.

Description

Technical Field

[0001] This invention relates to the field of wireless communication technology, and more specifically to a TDD power amplifier control circuit and device. Background Technology

[0002] TDD is a time-division duplex communication mode. The transmitter and receiver share a single radio frequency (RF) port, with uplink and downlink using different time slots. During the downlink time slot, the amplified downlink signal is output through the shared RF port; during the uplink time slot, the uplink signal is input through the shared RF port. To achieve this different time slot communication mode, on the one hand, transmit / receive isolation circuits are used to increase the isolation between the uplink and downlink, avoiding signal quality problems or even device damage caused by crosstalk between uplink and downlink signals. On the other hand, software controls the uplink and downlink switching levels to prevent simultaneous RF signal activation. However, in reality, software operation has a probability of failure or error; simultaneous RF signal activation may damage the equipment. Therefore, it is necessary to add hardware anti-simultaneous activation circuitry to increase reliability. Summary of the Invention

[0003] To address one or more of the aforementioned problems, this invention proposes a TDD power amplifier control circuit and device, which adds a control source anti-simultaneous-high-level control circuit to ensure that the uplink and downlink amplifier transistors do not operate simultaneously. The uplink and downlink links and the uplink / downlink switching switch can be simultaneously controlled in hardware by controlling the level of the control source signal, ensuring the correctness of the switching logic and guaranteeing the reliability of the overall system.

[0004] According to one aspect of the present invention, a TDD power amplifier control circuit is provided for controlling a TDD module, the TDD module including a downlink, an uplink, a circulator, and an uplink / downlink switching switch, the circulator being connected to the downlink and the uplink / downlink switching switch respectively, the uplink being connected to the uplink / downlink switching switch, characterized in that the control circuit includes:

[0005] The control source anti-high-level control circuit is used to receive the first control source signal and the second control source signal sent by the synchronization device, and outputs a high-level first control signal and a low-level second control signal when both the first control source signal and the second control source signal are high-level.

[0006] The amplifier tube TDD control circuit is used to receive the first control signal and the second control signal, amplify the voltage value of the first control signal to a preset value and output a third control signal to the downlink and the uplink / downlink switching switch, and amplify the voltage value of the second control signal to a preset value and output a fourth control signal to the uplink and the uplink / downlink switching switch;

[0007] The downlink switches on and off according to the received third control signal, the uplink / downlink switching switch switches states according to the received third and fourth control signals, and the uplink switch switches on and off according to the received fourth control signal.

[0008] In some embodiments, the control source anti-high-level control circuit includes: a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a seventh resistor, and a first NPN transistor. The first terminal of the first resistor is connected to a first voltage terminal; the second terminal of the first resistor is connected to the first terminal of the third resistor and a first control source signal input terminal; the second terminal of the third resistor is connected to the first terminal of the fifth resistor; the first terminal of the second resistor is grounded; the second terminal of the second resistor is connected to the first terminal of the fourth resistor and a second control source signal input terminal; the second terminal of the fourth resistor is connected to the collector of the first NPN transistor and the first terminal of the seventh resistor; the second terminal of the seventh resistor is connected to a second control signal output terminal; the base of the first NPN transistor is connected to the second terminal of the fifth resistor; and the emitter of the first NPN transistor is grounded. This effectively prevents the output of two high-level control signals.

[0009] In some embodiments, the control source anti-high-frequency control circuit further includes: a first adjustment unit, which is electrically connected to the amplifier tube TDD control circuit, and the first adjustment unit is used to adjust the power-on and power-off delay of the first control source signal.

[0010] In some embodiments, the first adjustment unit includes a first capacitor and a sixth resistor. The first terminal of the first capacitor is connected to the first terminal of the sixth resistor and the first control signal output terminal, and the second terminal of the first capacitor is grounded. The second terminal of the sixth resistor is connected to a third resistor and a fifth resistor.

[0011] In some embodiments, the amplifier tube TDD control circuit includes:

[0012] A first control circuit is used to receive a first control signal, amplify the voltage value of the first control signal to a preset value, and then output a third control signal to the downlink and the uplink / downlink switching switch.

[0013] The second control circuit is used to receive the second control signal, amplify the voltage value of the second control signal to a preset value, and then output a fourth control signal to the uplink and the uplink / downlink switching switch.

[0014] The downlink switch switches on and off according to the received third control signal, the uplink / downlink switching switch switches states according to the received third and fourth control signals, and the uplink switch switches on and off according to the received fourth control signal. The first and second control circuits have the same structure.

[0015] In some embodiments, the first control circuit includes a second PMOS transistor, a third NPN transistor, an eighth resistor, an eleventh resistor, and a fifteenth resistor. The base of the third NPN transistor is connected to the first terminal of the eighth resistor and a first control signal input terminal. The collector of the third NPN transistor is connected to the gate of the second PMOS transistor and the first terminal of the eleventh resistor. The emitter of the third NPN transistor is grounded, and the second terminal of the eighth resistor is grounded. The source of the second PMOS transistor is connected to the second terminal of the eleventh resistor and a second voltage terminal. The drain of the second PMOS transistor is connected to the first terminal of the fifteenth resistor. The second terminal of the fifteenth resistor is connected to a third control signal output terminal.

[0016] The second control circuit includes a first PMOS transistor, a second NPN transistor, a ninth resistor, a tenth resistor, and a fourteenth resistor. The base of the second NPN transistor is connected to the first terminal of the ninth resistor and the second control signal input terminal. The collector of the second NPN transistor is connected to the gate of the first PMOS transistor and the first terminal of the tenth resistor. The emitter of the second NPN transistor is grounded, and the second terminal of the ninth resistor is grounded. The source of the first PMOS transistor is connected to the second terminal of the tenth resistor and the third voltage terminal. The drain of the first PMOS transistor is connected to the first terminal of the fourteenth resistor. The second terminal of the fourteenth resistor is connected to the fourth control signal terminal.

[0017] In some embodiments, the first control circuit further includes a second adjustment unit connected to a second PMOS transistor, the second adjustment unit being used to control the power-on and power-off delay of the third control signal;

[0018] The second control circuit further includes a third adjustment unit, which is connected to the first PMOS transistor and is used to control the power-on and power-off delay of the fourth control signal.

[0019] In some embodiments, the second adjustment unit includes a third capacitor and a thirteenth resistor, wherein the first terminal of the thirteenth resistor is connected to the drain of the second PMOS transistor, the first terminal of the third capacitor is connected to the first terminal of the fifteenth resistor, and the second terminal of the thirteenth resistor and the second terminal of the third capacitor are grounded at the same point; and / or

[0020] The third adjustment unit includes a second capacitor and a twelfth resistor. The first end of the twelfth resistor is connected to the drain of the first PMOS transistor, the first end of the second capacitor, and the first end of the fourteenth resistor. The second end of the twelfth resistor and the second end of the second capacitor are grounded at the same point.

[0021] According to another aspect of the present invention, a TDD power amplifier control device is provided, including the above-described TDD power amplifier control circuit and TDD module.

[0022] In some implementations, when both the first control signal and the second control signal are low, both the uplink and downlink are closed, and the uplink / downlink switching switch is not turned on; when the first control signal is low and the second control signal is high, the uplink is on, the downlink is off, and the uplink / downlink switching switch is switched to uplink mode; when the first control signal is high and the second control signal is low, the uplink is off, the downlink is on, and the uplink / downlink switching switch is switched to downlink mode. Attached Figure Description

[0023] Figure 1 This is a schematic diagram of the structure of a TDD power amplifier control device according to an embodiment of the present invention;

[0024] Figure 2 This is the circuit diagram of the TDD power amplifier control circuit.

[0025] Figure 3 This is a circuit diagram of a TDD power amplifier control device according to an embodiment of the present invention. Detailed Implementation

[0026] The present invention will now be described in further detail with reference to the accompanying drawings.

[0027] Figure 1-3 The diagram schematically illustrates a TDD power amplifier control circuit and device according to one embodiment of the present invention. Figure 1 The diagram schematically illustrates a TDD power amplifier control device according to one embodiment of the present invention.

[0028] like Figure 1 As shown, the control device includes a TDD power amplifier control circuit 100, an uplink 110, a downlink 111, and an uplink / downlink switching switch. The TDD power amplifier control circuit 100 is connected between the uplink 110, the downlink 111, and the uplink / downlink switching switch.

[0029] The TDD radio frequency signal generates a pair of control source signals through a synchronization device. The TDD power amplifier control circuit 100 receives the first control source signal and the second control source signal, and outputs a third control signal and a fourth control signal to the uplink 110, the downlink 111, and the uplink / downlink switching switch.

[0030] Uplink 110 is used to receive a fourth control signal and switch on and off according to the received fourth control signal;

[0031] Downlink 111 is used to receive a third control signal and switch on and off according to the received third control signal;

[0032] The uplink / downlink switching switch receives a third control signal and a fourth control signal, and switches states based on the received third and fourth control signals. State switching includes switching to uplink mode, downlink mode, or disabling the switch.

[0033] Figure 3 A TDD power amplifier control device according to one embodiment of the present invention is schematically shown. For example... Figure 3 As shown, both uplink 110 and downlink 111 are sequentially connected to a circulator GL1 and a shared RF port PA_OUT / LNA_IN; the circulator GL1 is connected to the downlink 111 and the uplink / downlink switching switch, and the uplink 110 is connected to the uplink / downlink switching switch; wherein, the shared RF port PA_OUT / LNA_IN is the input terminal of uplink 110 and the output terminal of downlink 111.

[0034] The uplink 110 includes: an uplink amplifier U2, a second inductor L2, an eleventh capacitor C11, a twelfth capacitor C12, a thirteenth capacitor C13, and a fourteenth capacitor C14. The first terminal of the thirteenth capacitor C13 is connected to the output terminal of the uplink 110, and the second terminal of the thirteenth capacitor C13 is connected to the third terminal of the uplink amplifier U2 and the first terminal of the second inductor L2. The first terminal of the eleventh capacitor C11 is connected to the first terminal of the twelfth capacitor C12, the second terminal of the second inductor L2, and the third voltage terminal. The second terminal of the eleventh capacitor C11 and the second terminal of the twelfth capacitor C12 are grounded. The first terminal of the uplink amplifier U2 is connected to the first terminal of the fourteenth capacitor C14, and the second and fourth terminals of the uplink amplifier U2 are both grounded. The second terminal of the fourteenth capacitor C14 is connected to the uplink and downlink common circuit 112.

[0035] The uplink / downlink shared circuit 112 includes: a circulator GL1, an uplink / downlink switching switch U3, an eighth capacitor C8, a ninth capacitor C9, a tenth capacitor C10, a fifteenth capacitor C15, a sixteenth capacitor C16, a seventeenth resistor R17, and an eighteenth resistor R18. In this embodiment, the third control signal +5V_PA is input to the uplink / downlink switching switch U3 through the first terminal of the switch, and the fourth control signal +5V_LNA is input to the switch through the second terminal of the switch. The first terminal of the uplink / downlink switch U3 is connected to the first terminal of the seventeenth resistor R17 and the first terminal of the tenth capacitor C10. The second terminal of the uplink / downlink switch U3 is connected to the first terminal of the eighteenth resistor R18 and the first terminal of the eighth capacitor C8. The third terminal of the uplink / downlink switch U3 is connected to the first terminal of the ninth capacitor C9. The fourth and ninth terminals of the uplink / downlink switch U3 are grounded. The fifth terminal of the uplink / downlink switch U3 is connected to the first terminal of the fifteenth capacitor C15. The sixth and seventh terminals of the uplink / downlink switch U3 are grounded. The eighth terminal of the uplink / downlink switch U3 is connected to the first terminal of the sixteenth capacitor C16. The second terminal of the fifteenth capacitor C15 is connected to the second terminal of the fourteenth capacitor C14.

[0036] The second terminal of the ninth capacitor C9 is connected to the third terminal of the circulator GL1; the second terminal of the eighth capacitor C8 is grounded; the second terminal of the eighteenth resistor R18 is connected to the third voltage terminal; the second terminal of the tenth capacitor C10 is grounded; the second terminal of the seventeenth resistor R17 is connected to the voltage +5V_PA; the first terminal of the sixteenth resistor R16 is connected to the second terminal of the sixteenth capacitor C16; and the second terminal of the sixteenth resistor R16 is grounded.

[0037] The second terminal of circulator GL1 is connected to the shared RF port PA_OUT / LNA_IN. Circulator GL1 enables unidirectional signal circulation. In this embodiment, the voltage at the third voltage terminal is 5V.

[0038] Downlink 111 includes: a downlink amplifier U1, a first inductor L1, a fourth capacitor C4, a fifth capacitor C5, a sixth capacitor C6, and a seventh capacitor C7. The first terminal of the sixth capacitor C6 is connected to the input terminal of downlink 111, and the second terminal of the sixth capacitor C6 is connected to the first terminal of the downlink amplifier U1. The third terminal of the downlink amplifier U1 is connected to the first terminal of the seventh capacitor C7 and the first terminal of the first inductor L1. The second and fourth terminals of the downlink amplifier U1 are both grounded. The first terminal of the fourth capacitor C4 is connected to the first terminal of the fifth capacitor C5, the second terminal of the first inductor L1, and the fourth voltage terminal. The second terminal of the fourth capacitor C4 and the second terminal of the fifth capacitor C5 are grounded. The second terminal of the seventh capacitor C7 is connected to the first terminal of the circulator GL1. In this embodiment, the voltage at the fourth voltage terminal is 5V. It can also be adjusted to 12V or 28V depending on the circuit selection. When the third control signal is high and the fourth control signal is low, the downlink amplifier U1 is on, the uplink amplifier U2 is off, and the uplink / downlink switch U3 is switched to the sixteenth resistor R16. The overall link is such that downlink 111 is on and uplink 110 is off, with high isolation between them. When the third control signal is low and the fourth control signal is high, the downlink amplifier U1 is off and the uplink amplifier U2 is on. The uplink / downlink switch U3 is switched to the fifteenth capacitor C15. The overall link is such that downlink 111 is off and uplink 110 is on, with the shared RF port PA_OUT / LNA_IN connected to uplink 110.

[0039] When either the first control source signal or the second control source signal is high, the downlink amplifier U1 or the uplink amplifier U2 is in the working state. When either signal is low, the corresponding amplifier is in the off state. This ensures that the uplink amplifier U2 and the downlink amplifier U1 will not be operating simultaneously.

[0040] Figure 2 A TDD power amplifier control circuit according to an embodiment of the present invention is schematically shown. A TDD power amplifier control circuit 100 includes:

[0041] The control source anti-same-high control circuit 101 is used to output a first control signal and a second control signal according to the received first control source signal and second control source signal respectively. In this embodiment, the first control source signal is TDD_TX and the second control source signal is TDD_RX.

[0042] The control source anti-high-voltage control circuit 101 includes: a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, a first capacitor C1, and a first NPN transistor K1. The first end of the first resistor R1 is connected to a first voltage terminal, and the second end of the first resistor R1 is connected to the first end of the third resistor R3 and the first control source signal input terminal. The second end of the third resistor R3 is connected to the first end of the fifth resistor R5 and the second end of the sixth resistor R6. The first end of the first capacitor C1 is connected to the first end of the sixth resistor R6 and the first control signal output terminal, and the second end of the first capacitor C1 is connected to ground. The first end of the second resistor R2 is grounded, and the second end of the second resistor R2 is connected to the first end of the fourth resistor R4 and the second control source signal input terminal. The second end of the fourth resistor R4 is connected to the collector of the first NPN transistor K1 and the first end of the seventh resistor R7. The second end of the seventh resistor R7 is connected to the second control signal output terminal. The base of the first NPN transistor K1 is connected to the second end of the fifth resistor R5, and the emitter of the first NPN transistor K1 is grounded. In this embodiment, the voltage at the first voltage terminal is 3.3V.

[0043] The emitter of the first NPN transistor K1 is grounded. When both the first control source signal TDD_TX and the second control source signal TDD_RX are high, the collector and emitter of the first NPN transistor K1 are in a conducting state, meaning the collector of the first NPN transistor K1 is grounded after conducting to the emitter. The second control source signal TDD_RX is grounded through the first NPN transistor K1, thus becoming low, effectively preventing both the first and second output control signals from being high. Optionally, the first capacitor C1 and the sixth resistor R6 can be used to adjust the power-on and power-off delay of the first control source signal TDD_TX, thereby affecting the power-on and power-off timing of the amplifier transistor TDD control circuit 102.

[0044] The amplifier tube TDD control circuit 102, which is electrically connected to the control source anti-high-level control circuit 101, is used to output a third control signal and a fourth control signal based on the received first control signal and second control signal.

[0045] The amplifier tube TDD control circuit 102 includes a first control circuit and a second control circuit, and the first control circuit and the second control circuit have the same structure.

[0046] A first control circuit receives a first control signal, amplifies the voltage value of the first control signal to a preset value, and then outputs a third control signal to the downlink and the uplink / downlink switching switch. A second control circuit receives a second control signal, amplifies the voltage value of the second control signal to a preset value, and then outputs a fourth control signal to the uplink and the uplink / downlink switching switch.

[0047] The first control circuit includes a second PMOS transistor D2, a third NPN transistor K3, a third capacitor C3, an eighth resistor R8, an eleventh resistor R11, a thirteenth resistor R13, and a fifteenth resistor R15. The base of the third NPN transistor K3 is connected to the first terminal of the eighth resistor R8 and the first control signal input terminal. The collector of the third NPN transistor K3 is connected to the gate of the second PMOS transistor D2 and the first terminal of the eleventh resistor R11. The emitter of the third NPN transistor K3 is grounded, and the second terminal of the eighth resistor R8 is grounded. The source of the second PMOS transistor D2 is connected to the eleventh resistor R11 and the second voltage terminal. The drain of the second PMOS transistor D2 is connected to the first terminal of the thirteenth resistor R13, the first terminal of the third capacitor C3, and the first terminal of the fifteenth resistor R15. The second terminal of the fifteenth resistor R15 is connected to the third control signal terminal, and the second terminal of the thirteenth resistor R13 and the second terminal of the third capacitor C3 are grounded.

[0048] The second control circuit includes a first PMOS transistor D1, a second NPN transistor K2, a second capacitor C2, a ninth resistor R9, a tenth resistor R10, a twelfth resistor R12, and a fourteenth resistor R14. The base of the second NPN transistor K2 is connected to the first terminal of the ninth resistor R9 and the second control signal input terminal. The collector of the second NPN transistor K2 is connected to the gate of the first PMOS transistor D1 and the first terminal of the tenth resistor R10. The emitter of the second NPN transistor K2 is grounded, and the second terminal of the ninth resistor R9 is grounded. The source of the first PMOS transistor D1 is connected to the second terminal of the tenth resistor R10 and the third voltage terminal. The drain of the first PMOS transistor D1 is connected to the first terminal of the twelfth resistor R12, the first terminal of the second capacitor C2, and the first terminal of the fourteenth resistor R14. The second terminal of the fourteenth resistor R14 is connected to the fourth control signal output terminal, and the second terminals of the twelfth resistor R12 and the second terminal of the second capacitor C2 are grounded. In this embodiment, the voltages of the second and third voltage terminals are both 5V.

[0049] When the first control signal TX is high, the collector and emitter of the third NPN transistor K3 are in the ON state, the gate of the second PMOS transistor D2 is low, and the source to drain of the second PMOS transistor D2 is connected, resulting in a high-level output of the voltage +5V_PA. In this embodiment, the third control signal terminal is voltage +5V_PA, and the fourth control signal terminal is voltage +5V_LNA.

[0050] When the first control signal TX is low, the collector and emitter of the third NPN transistor K3 are not conducting, the gate of the second PMOS transistor D2 is high, the source and drain of the second PMOS transistor D2 are not conducting, and the voltage +5V_PA outputs a low level.

[0051] Optionally, the power-down timing of the +5V_PA output level can be adjusted using the thirteenth resistor R13 and the third capacitor C3.

[0052] When the second control signal RX is high, the collector and emitter of the second NPN transistor K2 are in the ON state, the gate of the first PMOS transistor D1 is in the OFF state, and the source to drain of the first PMOS transistor D1 is ON, resulting in a high-level output from +5V_LNA. In this embodiment, the fourth control signal is +5V_LNA.

[0053] When the second control signal RX is low, the collector and emitter of the second NPN transistor K2 are not conducting, the gate of the first PMOS transistor D1 is high, the source and drain of the first PMOS transistor D1 are not conducting, and the +5V_LNA output is low.

[0054] Optionally, the power-down timing of the +5V_UPA output level can be adjusted using the twelfth resistor R12 and the second capacitor C2.

[0055] The first control source signal TDD_TX and the second control source signal TDD_RX can have four logical combinations as shown in Table 1.

[0056] Table 1

[0057]

[0058] When both the first control source signal TDD_TX and the second control source signal TDD_RX are high, the second control source signal TDD_RX will become low after passing through the control source anti-high-level circuit. When the first control signal is high, the third control signal is high; when the first control signal is low, the third control signal is low. When the second control signal is high, the fourth control signal is high; when the second control signal is low, the fourth control signal is low.

[0059] In this embodiment, the first control signal and the second control signal output after passing through the control source anti-same-high circuit are TX and RX, respectively.

[0060] The logic levels of the first control signal TX and the second control signal RX are shown in Table 2.

[0061] Table 2

[0062]

[0063] The first control signal TX and the second control signal RX, after passing through the amplifier tube TDD control circuit 102, control the switching of the downlink amplifier tube U1, the switching of the uplink amplifier tube U2, and the pointing logic of the uplink / downlink switching switch, as shown in Table 3.

[0064] Table 3

[0065]

[0066] As shown in Table 3, when both the first and second control signals are low, both uplink 110 and downlink 111 are closed, and the uplink / downlink switching switch is not activated. When the first control signal is low and the second control signal is high, uplink 110 is activated, downlink 111 is closed, and the uplink / downlink switching switch is switched to uplink mode. When the first control signal is high and the second control signal is low, uplink 110 is closed, and the uplink / downlink switching switch is switched to downlink mode. In uplink mode, the signal path is: common RF port PA_OUT / LNA_IN input, circulator GL1, ninth capacitor C9, uplink / downlink switching switch U3, fifteenth capacitor C15, fourteenth capacitor C14, uplink amplifier U2, thirteenth capacitor C13, and LNA OUT output. In downlink mode, the signal path is: PA IN input, sixth capacitor C6, downlink amplifier U1, seventh capacitor C7, circulator GL1, and output through the common RF port PA_OUT / LNA_IN.

[0067] The above descriptions are merely some embodiments of the present invention. Those skilled in the art can make various modifications and improvements without departing from the inventive concept of the present invention, and these all fall within the scope of protection of the present invention.

Claims

1. A TDD power amplifier control circuit for controlling a TDD module, the TDD module comprising a downlink, an uplink, a circulator, and an uplink / downlink switching switch, the circulator being connected to the downlink and the uplink / downlink switching switch respectively, the uplink being connected to the uplink / downlink switching switch, characterized in that, The control circuit includes: A control source anti-high-level control circuit is used to receive a first control source signal and a second control source signal sent by a synchronization device, and outputs a high-level first control signal and a low-level second control signal when both the first and second control source signals are high. The control source anti-high-level control circuit includes: a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a seventh resistor, and a first NPN transistor. The first end of the first resistor is connected to a first voltage terminal; the second end of the first resistor is connected to the first end of the third resistor and the first control source signal input terminal; the second end of the third resistor is connected to the first end of the fifth resistor; the first end of the second resistor is grounded; the second end of the second resistor is connected to the first end of the fourth resistor and the second control source signal input terminal; the second end of the fourth resistor is connected to the collector of the first NPN transistor and the first end of the seventh resistor; the second end of the seventh resistor is connected to the second control signal output terminal; the base of the first NPN transistor is connected to the second end of the fifth resistor; and the emitter of the first NPN transistor is grounded. The amplifier tube TDD control circuit is used to receive the first control signal and the second control signal, amplify the voltage value of the first control signal to a preset value and output a third control signal to the downlink and the uplink / downlink switching switch, and amplify the voltage value of the second control signal to a preset value and output a fourth control signal to the uplink and the uplink / downlink switching switch; The downlink switches on and off according to the received third control signal, the uplink / downlink switching switch switches states according to the received third and fourth control signals, and the uplink switch switches on and off according to the received fourth control signal.

2. The TDD power amplifier control circuit according to claim 1, characterized in that, The control source anti-high-frequency control circuit further includes: a first adjustment unit, which is electrically connected to the amplifier tube TDD control circuit, and the first adjustment unit is used to adjust the power-on and power-off delay of the first control source signal.

3. The TDD power amplifier control circuit according to claim 2, characterized in that, The first adjustment unit includes a first capacitor and a sixth resistor. The first end of the first capacitor is connected to the first end of the sixth resistor and the first control signal output terminal, and the second end of the first capacitor is grounded. The second end of the sixth resistor is connected to the third resistor and the fifth resistor.

4. A TDD power amplifier control circuit according to any one of claims 1-3, characterized in that, The amplifier tube TDD control circuit includes: The first control circuit is used to receive the first control signal, amplify the voltage value of the first control signal to a preset value, and then output the third control signal. The second control circuit is used to receive the second control signal, amplify the voltage value of the second control signal to a preset value, and then output the fourth control signal.

5. The TDD power amplifier control circuit according to claim 4, characterized in that, The first control circuit includes a second PMOS transistor, a third NPN transistor, an eighth resistor, an eleventh resistor, and a fifteenth resistor. The base of the third NPN transistor is connected to the first terminal of the eighth resistor and the first control signal input terminal. The collector of the third NPN transistor is connected to the gate of the second PMOS transistor and the first terminal of the eleventh resistor. The emitter of the third NPN transistor is grounded, and the second terminal of the eighth resistor is grounded. The source of the second PMOS transistor is connected to the second terminal of the eleventh resistor and the second voltage terminal. The drain of the second PMOS transistor is connected to the first terminal of the fifteenth resistor. The second terminal of the fifteenth resistor is connected to the third control signal output terminal. The second control circuit includes a first PMOS transistor, a second NPN transistor, a ninth resistor, a tenth resistor, and a fourteenth resistor. The base of the second NPN transistor is connected to the first terminal of the ninth resistor and the second control signal input terminal. The collector of the second NPN transistor is connected to the gate of the first PMOS transistor and the first terminal of the tenth resistor. The emitter of the second NPN transistor is grounded, and the second terminal of the ninth resistor is grounded. The source of the first PMOS transistor is connected to the second terminal of the tenth resistor and the third voltage terminal. The drain of the first PMOS transistor is connected to the first terminal of the fourteenth resistor. The second terminal of the fourteenth resistor is connected to the fourth control signal output terminal.

6. The TDD power amplifier control circuit according to claim 5, characterized in that, The first control circuit further includes a second adjustment unit, which is connected to a second PMOS transistor. The second adjustment unit is used to control the power-on and power-off delay of the third control signal. The second control circuit further includes a third adjustment unit, which is connected to the first PMOS transistor and is used to control the power-on and power-off delay of the fourth control signal.

7. A TDD power amplifier control circuit according to claim 6, characterized in that, The second adjustment unit includes a third capacitor and a thirteenth resistor. The first end of the thirteenth resistor is connected to the drain of the second PMOS transistor, the first end of the third capacitor is connected to the first end of the fifteenth resistor, and the second end of the thirteenth resistor is connected to the second end of the third capacitor and grounded. The third adjustment unit includes a second capacitor and a twelfth resistor. The first end of the twelfth resistor is connected to the drain of the first PMOS transistor, the first end of the second capacitor, and the first end of the fourteenth resistor. The second end of the twelfth resistor is grounded to the second end of the second capacitor.

8. A TDD power amplifier control device, characterized in that, The TDD power amplifier control device includes the TDD power amplifier control circuit and TDD module as described in any one of claims 1-7.

9. A TDD power amplifier control device according to claim 8, characterized in that, When both the first and second control signals are low, both the uplink and downlink are closed, and the uplink / downlink switching switch is not activated. When the first control signal is low and the second control signal is high, the uplink is activated, the downlink is closed, and the uplink / downlink switching switch is switched to uplink mode. When the first control signal is high and the second control signal is low, the uplink is closed, the downlink is activated, and the uplink / downlink switching switch is switched to downlink mode.

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