Video encoding method and corresponding electronic device

Abstract

A video coding method and related electronic device are provided. The video coding method includes receiving original pixel data of a pixel block to be encoded into a bitstream; identifying a plurality of candidate bi-prediction positions including a center position, a first set of offset positions, and a second set of offset positions; calculating a distortion value for each of the plurality of candidate bi-prediction positions based on a plurality of possible weighting parameter values, wherein: (i) the distortion value is calculated for the center position, (ii) the distortion value is calculated for the first set of offset positions, and (iii) the distortion value is calculated for the second set of offset positions; selecting a weighting parameter value for the candidate bi-prediction positions based on the calculated distortion values; and encoding the current block using bi-prediction based on the selected weighting parameter value. The video coding method and the corresponding electronic device of the present application can be shared by a plurality of different codec tools.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to video coding. In particular, the present disclosure relates to a hardware architecture configured to support multiple different coding modes. BACKGROUND

[0002] Unless otherwise indicated herein, the methods described in this section are not prior art to the claims listed below and are not admitted to be prior art by inclusion in this section.

[0003] High Efficiency Video Coding (HEVC) is an international video coding standard developed by the Joint Collaborative Team - Video Coding (JCT-VC). HEVC is based on a hybrid block-based motion-compensated DCT-like transform coding architecture. The basic unit of compression, called a coding unit (CU), is a 2Nx2N square block, each of which can be recursively split into four smaller CUs until a predefined minimum size is reached. Each CU contains one or more prediction units (PUs).

[0004] To achieve the best coding efficiency of the hybrid coding architecture in HEVC, each PU has two prediction modes, namely intra prediction and inter prediction. For the intra prediction mode, spatially neighboring reconstructed pixels can be used to generate directional predictions. There are up to 35 directions in HEVC. For the inter prediction mode, temporally reconstructed reference frames can be used to generate motion-compensated predictions. There are three different modes, including Skip, Merge, and Inter-Advanced Motion Vector Prediction (AMVP) modes.

[0005] When a PU is coded in the inter-AMVP mode, the motion-compensated prediction is performed with a transmitted motion vector difference (MVD) that can be used together with a motion vector predictor (MVP) to derive a motion vector (MV). To decide the MVP in the inter-AMVP mode, an advanced motion vector prediction (AMVP) scheme is used to select a motion vector predictor in an AMVP candidate set including two spatial MVPs and one temporal MVP. Therefore, in the AMVP mode, the MVP index of the MVP and the corresponding MVD need to be coded and transmitted. In addition, the inter-prediction direction and the reference frame index of each list should also be coded and transmitted to specify the prediction direction in bi-prediction and uni-prediction of list 0 (L0) and list 1 (L1).

[0006] When the PU is encoded in skip or merge modes, no motion information is transmitted except for the merge index of the selected candidate. This is because skip and merge modes utilize a motion inference method (MV = MVP + MVD, where MVD is zero) to obtain motion information from spatially adjacent blocks (spatial candidates) or temporally adjacent blocks (temporal candidates) located in the co-located image, where the co-located image is the first reference image in list 0 or list 1, signaled in the slice header. In the case of a skip PU, the residual signal is also ignored. To determine the merge index for skip and merge modes, a merge scheme is used to select motion vector predictors from a merge candidate set containing four spatial MVPs and one temporal MVP. [Summary of the Invention]

[0007] In view of the above, the present invention provides the following technical solution:

[0008] This invention provides a video encoding method, comprising: receiving raw pixel data of a pixel block to encode the current block of a current image of a video into a bitstream; identifying a plurality of candidate bidirectional prediction positions including a center position, a first set of offset positions, and a second set of offset positions; calculating a distortion value for each of the plurality of candidate bidirectional prediction positions based on a plurality of possible weighted parameter values, wherein: (i) the distortion value calculated for the center position is calculated based on each of the plurality of possible weighted parameter values, (ii) the distortion value calculated for the first set of offset positions is calculated based on a first subset of the plurality of possible weighted parameter values, and (iii) the distortion value calculated for the second set of offset positions is calculated based on a second subset of the plurality of possible weighted parameter values, wherein the first subset of the plurality of possible weighted parameter values ​​is different from the second subset of the plurality of possible weighted parameter values; selecting a weighted parameter value for a candidate bidirectional prediction position based on the calculated distortion values ​​of the plurality of candidate bidirectional prediction positions of the current block; and encoding the current block using bidirectional prediction based on the selected weighted parameter value.

[0009] The present invention also provides an electronic device, comprising: an encoder circuit configured to perform operations including: receiving raw pixel data of a pixel block for encoding a current block of a current image of a video into a bitstream; identifying a plurality of candidate bidirectional prediction positions including a center position, a first set of offset positions, and a second set of offset positions; calculating a distortion value for each of the plurality of candidate bidirectional prediction positions based on a plurality of possible weighted parameter values, wherein: (i) the distortion value calculated for the center position is calculated based on each of the plurality of possible weighted parameter values, (ii) the distortion value calculated for the first set of offset positions is calculated based on a first subset of the plurality of possible weighted parameter values, and (iii) the distortion value calculated for the second set of offset positions is calculated based on a second subset of the plurality of possible weighted parameter values, wherein the first subset of the plurality of possible weighted parameter values ​​is different from the second subset of the plurality of possible weighted parameter values; selecting a weighted parameter value for a candidate bidirectional prediction position based on the calculated distortion values ​​of the plurality of candidate bidirectional prediction positions for the current block; and encoding the current block using bidirectional prediction based on the selected weighted parameter value.

[0010] The video encoding method and corresponding electronic equipment of the present invention can be shared by multiple different encoding and decoding tools. [Attached Image Description]

[0011] Embodiments of the invention are illustrated in conjunction with the accompanying drawings, which are included and form part of this specification, and together with the description, serve to explain the principles of the invention:

[0012] Figure 1 This conceptually illustrates a portion of a video encoder that uses LC-RDO and HC-RDO stages to select encoding / decoding tools and / or prediction candidates for encoding / decoding the current block.

[0013] Figure 2 The components of LC-RDO are explained conceptually.

[0014] Figure 3 An example implementation of an LC-RDO with shared circuitry for multiple different codec tools is illustrated.

[0015] Figure 4 This provides a conceptual explanation of mirror matching in DMVR.

[0016] Figure 5 The concept illustrates how to align the four AMVR precisions by aligning their center MV.

[0017] Figure 6 The illustration shows various candidate modes of the SBT used to divide the transform block into a coding part and a zero part.

[0018] Figure 7The concept illustrates the interleaving search pattern used to find the optimal BCW weighted parameter values.

[0019] Figure 8 The illustration shows an example video encoder that can use LC-RDO and HC-RDO stages to select the codec tool and / or prediction candidate for encoding and decoding the current block.

[0020] Figure 9 The diagram illustrates the portion of the video encoder that implements LC-RDO and HC-RDO.

[0021] Figure 10 This conceptually illustrates the process of finding weighted parameter values ​​when encoding a coded block using BCW.

[0022] Figure 11 An electronic system implementing some embodiments of the present disclosure is conceptually illustrated.

Detailed Implementation Methods

[0023] Numerous specific details are set forth in the following description. However, it should be understood that embodiments of the invention can be practiced without these specific details. In other instances, well-known circuits, structures, and techniques have not been shown in detail so as not to obscure the understanding of this specification. However, those skilled in the art will understand that the invention can be practiced without such specific details. Those skilled in the art with the included description will be able to implement appropriate functionality without excessive experimentation.

[0024] The following description is the best intended mode for carrying out the invention. This description is intended to illustrate the general principles of the invention and should not be construed as limiting. The scope of the invention is best determined by referring to the appended claims.

[0025] In the detailed description that follows, numerous specific details are illustrated by way of examples to provide a thorough understanding of the teachings. Any variations, derivations, and / or extensions based on the teachings described herein are within the scope of this disclosure. In some cases, well-known methods, processes, components, and / or circuits related to one or more example implementations disclosed herein may be described at a relatively general level without detailed description to avoid unnecessarily obscuring aspects of the teachings of this disclosure.

[0026] The latest video codec standard, Versatile Video Coding (VVC), introduces numerous new codec tools to improve encoding and decoding efficiency. Examples of these tools include Advanced Motion Vector Prediction (AMVP), Geometric Prediction Mode (GPM), Adaptive Motion Vector Resolution (AMVR), Merge Mode with Motion Vector Difference (MMVD), Decoder-side Motion Vector Refinement (DMVR), Bi-prediction with CU-level Weights (BCW), and Sub-Block Transform (SBT). High-performance video encoders in the VVC standard can achieve high encoding and decoding gain by supporting as many of these tools as possible. However, designing dedicated hardware circuitry for each tool is highly inefficient.

[0027] Some embodiments of this disclosure provide a video encoder including circuitry configured to be shared by multiple different codec tools. The video encoder may include a low-complexity (LC) rate-distortion optimization stage (LC-RDO) as a first-stage RDO and a high-complexity (HC) rate-distortion optimization stage (HC-RDO) as a second-stage RDO. The video encoder attempts various codec tools and selects the one with the lowest RD-cost. Since a codec tool may have multiple possible candidates, the LC-RDO stage is used to select the candidate with the lowest RD-cost. In some embodiments, the LC-RDO stage performs simpler transformations, such as the Sum of Absolute Difference (SAD) or the Sum of Absolute Transformed Difference (SATD), to simplify distortion calculation. LC-RDO can select candidates by performing simpler transformations and / or by not performing a full search. The HC-RDO stage then uses the candidates provided by LC-RDO to finally determine the selection of the encoding / decoding tool used to encode the current CU, including by performing standard transforms such as DCT2.

[0028] In some embodiments, LC-RDO includes circuitry configured to be shared by multiple different codec tools. Therefore, in order to encode a CU, a video encoder can implement LC-RDO for multiple different codec tools in multiple different configurations. In some embodiments, for each codec tool, LC-RDO identifies an optimal candidate for HC-RDO.

[0029] Figure 1 The concept illustration shows a portion of a video encoder 100 that uses LC-RDO stage 110 and HC-RDO stage 120 to select encoding / decoding tools and / or prediction candidates for encoding / decoding the current block.

[0030] As shown in the figure, LC-RDO 110 and HC-RDO 120 together perform RDO functionality for video encoder 100, ensuring that the current block is encoded using the codec tool and prediction candidate with the lowest cost in terms of rate and distortion. LC-RDO stage 110 examines the codec tool and prediction candidate to provide intermediate results to HC-RDO stage 120. The intermediate results produced by LC-RDO 110 may include information such as the identity of the best prediction candidate for a particular codec tool and its associated cost. HC-RDO can use the intermediate results to produce the final codec tool selection and prediction candidate selection. Video encoder 100 then uses the codec tool and prediction candidate selection to encode the current block.

[0031] Both LC-RDO 110 and HC-RDO 120 can retrieve data from data cache 130, which may include storage of pixel data for the current image (reconstructed or original source) and several reference images. Data cache 130 may also include storage for reference motion information, such as motion vectors previously used for other CUs. LC-RDO and HC-RDO can selectively retrieve data from data cache 130 based on the current block location and the encoding / decoding tools and prediction candidates being examined.

[0032] LC-RDO 110 includes circuitry shared by different codec tools and can be configured to generate intermediate results for different codec tools. Therefore, the same LC-RDO 110 can be configured in a first configuration 111 to generate a first intermediate result 121 for a first codec tool, and then in a second configuration 112 to generate a second intermediate result 122 for a second encoding tool, etc. HC-RDO 120 uses the intermediate results from the different codec tools to ultimately determine the selection of the codec tool and / or prediction candidate for encoding the current block. In the figures, codec tool configurations 111-114 are used by LC-RDO 110 to generate intermediate results 121-124 for HC-RDO 120, respectively.

[0033] In some embodiments, LC-RDO stage 110 may perform at least some of the following operations: (1) fetching data from data cache 130, (2) generating candidates, (3) calculating distortion using low-complexity transformations, and (4) comparing the RD costs of different candidates. The winning candidate identified by LC-RDO stage 110 is then provided to HC-RDO stage 120. The same four operations of LC-RDO can be used to identify the best candidate for different codec tools (e.g., AMVP, MMVD, and GPM).

[0034] Figure 2The components of LC-RDO are conceptually explained. The circuitry of LC-RDO is configured using configuration data 200 for a specific codec tool to determine the best candidate codec tool and provide the cost of using that candidate.

[0035] For each of the several candidates, LC-RDO 110 retrieves data from data cache 130, applies interpolation 210, performs distortion calculation 220, and performs rate calculation 230. Based on the distortion and rate calculations, LC-RDO 110 determines the cost value for each candidate. An overall comparator (also known as a candidate comparator) 240 compares the cost values ​​of the different candidates to determine the best candidate for a given codec tool.

[0036] LC-RDO 110 performs operations 210-230 according to configuration data 200. Configuration data 200 can also configure LC-RDO to omit one or more of steps 210-230. In some embodiments, LC-RDO may have circuitry configurable to examine multiple candidates in parallel (e.g., there are independent groups of circuitry capable of examining different candidates simultaneously). In some embodiments, LC-RDO may have circuitry shared by different candidates and can be configured to examine each candidate sequentially.

[0037] Figure 3 An example implementation of an LC-RDO 110 with shared circuitry for multiple different codec tools is illustrated. The LC-RDO 110 includes an L0 unidirectional prediction section 301, an L0 bidirectional prediction section 302, an L1 unidirectional prediction section 303, and an L1 bidirectional prediction section 304. When configured for a codec tool, the circuitry of each section calculates the distortion and rate of its candidate components. Each section has one or more local comparators to determine the best candidate with the lowest cost for that section. An overall comparator 240 compares the best candidates of the four sections 301-304 to identify the overall best candidate for a given codec tool based on the cost derived from the calculated distortion and rate.

[0038] As shown in the figure, the L0 unidirectional prediction section 301 includes an interpolation filter 310, a SATD array 320, rate calculators 331-334, and a local comparator 340. The interpolation filter 310 receives reference samples (“reference data”) and generates filtered reference samples (e.g., for fractional positions) using a horizontal filter array 311, a shift register 312, a vertical filter array 313, and an interpolation buffer 314. A reference image buffer 315 stores pixel data of a reference image as reference samples. The interpolation filter 310 can provide outputs from any of the components 311-314, and the SATD array 320 can use any of these outputs for its distortion calculation. The SATD array 320 performs distortion calculations based on the source data (from the video source) and the (unidirectional) filtered reference samples from the interpolation filter 310. The SATD array 320 can also perform distortion calculations based on a mixture of reference samples from the L0 bidirectional prediction section 302. The output of the SATD array 320 is provided to quarter-pixel, half-pixel, 1-pixel, and 4-pixel comparators 341-344.

[0039] The outputs of rate calculators 331-334, along with the output of SATD array 320, are fed to comparators 341-344. Comparators 341-344 sequentially provide cost values ​​for different candidates at different pixel resolutions. Local comparator 340 compares these different candidates and identifies the best candidate for L0 unidirectional prediction.

[0040] The L0 bidirectional prediction section 302 includes a bidirectional prediction mixing module 319, a bidirectional prediction SATD array 325, a rate calculator 335, and a bidirectional prediction comparator 345. The bidirectional prediction mixing module 319 performs a weighted average to mix reference sample pixels from two reference images at two different time locations (e.g., two uni-predictors for L0 and L1). The bidirectional prediction SATD array 325 calculates the distortion in the mixed reference samples and provides the distortion values ​​to the bidirectional prediction comparator 345 and the rate calculator 335. In some embodiments, the SATD array 320 can be reused for distortion calculation when performing L0 bidirectional prediction, and comparators 331-334 can also be reused.

[0041] This figure illustrates the components of L0 bidirectional and L0 unidirectional prediction sections 301 and 302. The components of L1 unidirectional prediction section 303 and L1 bidirectional prediction section 304 are not shown because they are similar to the components of L0 unidirectional prediction section 301 and L0 bidirectional prediction section 302.

[0042] Each candidate is associated with a cost value calculated based on the distortion and rate values. The overall comparator 240 compares the best candidates from the L0 one-way prediction section 301, the L0 two-way prediction section 302, the L1 one-way prediction section 303, and the L1 two-way prediction section 304.

[0043] Various components / circuits of the LC-RDO 110 can be shared by different codec tools. In some embodiments, at least some components of the LC-RDO can be configured to identify the lowest cost candidates for various codec tools.

[0044] Merging with Motion Vector Difference (MMVD) is a codec tool used by the Universal Video Coding (VVC) standard. Unlike regular merging patterns (where implicitly derived motion information is directly used to generate prediction samples for the current CU), in MMVD, the derived motion information is further refined using motion vector difference (MVD). MMVD also expands the candidate list of merging patterns by adding additional MMVD candidates based on predefined offsets (also known as MMVD offsets).

[0045] In some embodiments, the circuitry of the LC-RDO 110 can be used to identify candidate MMVD modes. For example, the horizontal filter array 311 and the vertical filter array 313 are configurable universal coefficient filters for MMVD modes. The reference image buffer 315 is large enough to store the reference samples required for MMVD. The shift register 312 and the interpolation buffer 314 are also large enough to accommodate the temporary results of vertical and horizontal filtering. The bidirectional prediction mixing module 319 and the bidirectional prediction SATD array 325 of the bidirectional prediction section can be directly used for MMVD distortion calculation. The overall comparator 240 can also be reused for MMVD.

[0046] Decoder-side Motion Vector Refinement (DMVR) is an encoding / decoding tool that can be applied to regular merge candidates. According to DMVR, the decoder refines the MV according to predefined steps: (i) splitting the current CU into multiple 16x16 / 8x16 / 16x8 sub-blocks, (ii) generating 25 integer offset refinement candidates around the regular merge candidates using a bilinear filter, (iii) calculating the even-row SAD cost through mirror matching, and (iv) applying fractional offset refinement if predefined conditions are met. (See figure.) Figure 4 This diagram illustrates mirror matching in DMVR conceptually. The figure shows mirror matching between the 25 refinement candidate positions of the L0 merged MV and the 25 refinement candidate positions of the L1 merged MV.

[0047] The process of deriving the DMVR MV offset shares many similarities with the LC-RDO stage. Therefore, the circuitry of the LC-RDO 110 stage can be shared or reused with the DMVR, although some modules may be configured differently from other codec tools. For the DMVR, the LC-RDO can be configured to (i) read data from the buffer, (ii) generate bilinear candidates, (iii) calculate the SAD cost for even-numbered rows, and (iv) compare the cost of each candidate for fractional refinement and output a refined merged MV. The refined merged MV is provided to the HC-RDO 120. For example, the horizontal filter array 311 and the vertical filter array 313 can be configured to perform bilinear filtering. The SATD array 320 can be configured to calculate the SAD cost for even-numbered rows. The bidirectional mixing module 319 can be configured to support mirror matching. The reference picture buffer 315, shift register 312, interpolation buffer 314, and local comparator 340 can be directly reused in the DMVR. Comparators 341-344 can be configured to perform fractional refinement, such as constructing an error surface and then finding the offset with minimum cost on the error surface.

[0048] Adaptive Motion Vector Resolution (AMVR) allows encoding motion vector differences (MVD) with different precisions. There are four AMVR precisions in VVC: four-sample (4-pel), integer-sample (1-pel), half-sample (H-pel), and quarter-sample (Q-pel). In some embodiments, Figure 3 The example architecture of the LC-RDO 110 can be directly shared with AMVR, where the four comparators 331-334 correspond to four AMVR precisions. More generally, the four AMVR precisions are handled by four separate PE calls (e.g., using four separate hardware processing elements).

[0049] In some embodiments, LC-RDO can perform different AMVR accuracies in a single PE call (using the same processing element), specifically by aligning the center MV of different AMVR accuracies and performing RDO together. Figure 5 This diagram conceptually illustrates aligning four AMVR precisions by aligning their center MV. Each circle in the diagram represents a pixel location (integer and fraction). Circles labeled "Q" are quarter-pixel locations interpolated using an 8-tap filter, while circles labeled "H" are half-pixel locations interpolated using a 6-tap filter. Circles labeled "HQ" are locations where interpolation is performed on the half-pixel and quarter-pixel locations. Circles labeled "1" and "4" are the 1-pixel and 4-pixel locations, respectively, where no interpolation is required.

[0050] By aligning the four precisions at their center MV, all four AMVR precisions can be executed by a single PE call or by a subset of AMVR precisions (e.g., 1 pixel, 1 / 2 pixel, and 1 / 4 pixel, but no 4 pixels) into a single PE call. Experience shows that under certain conditions, this has little impact on BD rate. It can be observed that AMVR side information becomes less important when the current CU size is large. Partial interpolation results for the four different precisions can be shared to further reduce hardware costs.

[0051] Sub-block Transform (SBT) is an encoding / decoding tool for CUs (Continuous Code Units) used for inter-frame prediction. It allows the video encoder to perform a transform on only a portion of the residual block or transform block. The coded portion of the transform block is encoded using an implicitly determined transform. The non-coded portion is zeroed out. SBT specifies several different candidate modes for dividing the transform block into coded and non-coded portions. Figure 6 The diagram illustrates various candidate patterns of the SBT used to divide the transform block into a coded portion and a zero portion. In the diagram, for each candidate SBT pattern, the coded portion of the transform block is labeled "A," and the non-coded portion is labeled "0." The width of the transform block is called tbWidth. The width of the coded portion is called trafoWidth.

[0052] Figure 6 Various candidate modes for the SBT can be enabled or disabled via `cu_sbt_quad_flag`, `cu_sbt_horizontal_flag`, and `cu_sb_pos_flag`. `cu_sbt_quad_flag` indicates whether `trafoWidth:(tbWidth-trafoWidth)` can be 2:2, 1:3, or 3:1. `cu_sbt_horizontal_flag` indicates whether the transform block is horizontally or vertically split for the SBT. `cu_sb_pos_flag` indicates whether the left / top sub-block has non-zero transform coefficients and the right / bottom sub-block is zeroed out, or whether the right / bottom sub-block has non-zero transform coefficients and the left / top sub-block is zeroed out.

[0053] Instead of trying all possible candidate patterns for SBT in the HC-RDO stage, in some embodiments, the LC-RDO stage is used to identify candidate patterns with the minimum cost for encoding the transform block. In some embodiments, LC-RDO calculates the residual cost of each candidate pattern for SBT by a weighted average of the SSD of the transform coded portion and the SSD of the return-to-zero portion. Specifically, the cost of each candidate pattern is calculated as follows:

[0054] .S1 = SSD(residual trans 2 ),

[0055] .S 2＝SSD (r e sidual zero 2 )

[0056]

[0057] The LC-RDO selects the candidate mode with the lowest cost (calculated according to Equation 1) for testing in the HC-RDO. This is called SBT preselection. Therefore, in some embodiments, instead of having the HC-RDO try every possible candidate mode of SBT, the video encoder can perform SBT preselection at the LC-RDO. The HC-RDO then selects candidates based on the results of the SBT preselection.

[0058] The LC-RDO 110 can be configured to perform SBT pre-selection. Specifically, the residuals of each candidate mode of the SBT can be provided to the SATD array 320, which can then calculate the cost of each candidate mode according to Equation 1 above.

[0059] Bidirectional prediction with CU-level weights (BCW) is an encoding / decoding tool used to enhance bidirectional prediction. BCW allows different weights to be applied to L0 and L1 predictions before combining them to generate bidirectional predictions for the CU. For a CU to be encoded by BCW, a weighting parameter w is sent to the L0 and L1 predictions so that the bidirectional prediction result P can be calculated based on w according to the following formula. bi-pred :

[0060] ·P bi-pred =((8-w)*P0+w*P1+4)》3(Eq·2)

[0061] P0 represents the pixel value predicted by L0 MV (or L0 prediction). P1 represents the pixel value predicted by L1 MV (or L1 prediction). bi-predThis is the weighted average of P0 and P1 based on w. For low-latency images, i.e., images using reference frames with a small picture order count (POC), possible values ​​for w include {-2, 3, 4, 5, 10}. For non-low-latency images, possible values ​​for w include {3, 4, 5}. In some embodiments, instead of searching all possible values ​​of w for all candidate bidirectional prediction MV positions, the LC-RDO stage can employ an interleaving search pattern to find the optimal value of the BCW weighting parameter w in order to find the best w for encoding and decoding the current CU.

[0062] Figure 7 The diagram conceptually illustrates the interleaved search pattern used to find the optimal BCW weighted parameter values. In the figure, weight indices (BCWIdx) 0, 1, 2, 3, and 4 correspond to possible BCW weight parameter values ​​of -2, 3, 4, 5, and 10, respectively. The search pattern is used for an array or permutation of candidate bidirectional predicted MV positions. The candidate bidirectional predicted MV positions in the permutation include a center position 700 and multiple vertical and / or horizontal offset positions (±1, ±2, etc.) based on the center position 700.

[0063] For each candidate bidirectional prediction MV location, LC-RDO calculates the distortion value corresponding to each possible w value for that location. As shown in the figure, at the central bidirectional prediction MV location 700, the LC-RDO stage attempts to find the optimal value of w by trying weight indices 0, 1, 2, 3, and 4, corresponding to BCW weight values ​​of -2, 3, 4, 5, and 10, respectively. For each of the candidate bidirectional prediction MV locations that are offset locations from the center location, the BCW weights are selectively examined. At the first type of offset location, the LC-RDO stage tries weight indices (BCWIdx) 0, 2, and 3, which correspond to weight parameter values ​​of -2, 4, and 5, respectively. At the second type of offset location, the LC-RDO stage tries weight indices 1, 2, and 4, which correspond to BCW weight values ​​of 3, 4, and 10, respectively.

[0064] LC-RDO calculates the distortion of possible w values ​​for candidate bidirectional prediction locations by using the w value to compute the bidirectional prediction (Pbi_pred) of the current block, which is a weighted average of the L0 prediction (P0) based on L0 MV and the L1 prediction (P1) based on L1 MV (Equation 2). L0 and L1 MV are identified based on candidate bidirectional prediction locations. The distortion of possible w values ​​is the difference between the original pixel data of the current block and the bidirectional prediction.

[0065] As shown in the figure, the two types of offset positions are arranged in an alternating pattern. Specifically, the first type of offset position is located at the upper right, upper left, lower right, and lower left of the center position 700, while the second type of offset position is located above, to the right, to the left, and at the bottom of the center position 700. The pattern is expanded such that each offset position of one type has diagonally adjacent positions of the same type (upper right, upper left, lower right, lower left) and horizontally and vertically adjacent positions of opposite types (above, right, left, and bottom).

[0066] Typically, LC-RDO attempts all possible BCW weighted parameter values ​​only at the center location. For all other candidate bidirectional prediction MV locations (offset locations), LC-RDO attempts only a subset of possible weighted parameter values. Furthermore, offset locations are grouped into different groups (e.g., based on the interleaving mode), and LC-RDO attempts different subsets of possible w values ​​for each offset location group. Going further, BCWIdx = 2 (or w = 4) is attempted for all candidate bidirectional prediction MV locations because BCWIdx = 2 corresponds to equally weighted L1 and L0 predictions when calculating the bidirectional prediction results.

[0067] By reducing the number of possible w values ​​checked according to the interleaving mode, the video encoder can reduce the number of SATD operations performed in finding the optimal bidirectional prediction MV position and the optimal BCW weighting parameter values ​​to obtain the optimal bidirectional prediction MV position.

[0068] As described above, the LC-RDO 110 is a hardware circuit that can be shared by multiple different codec tools, including BCW. The bidirectional mixing module 319 can be used to calculate the weighted average of the L0 and L1 predictions of the BCW. The bidirectional SATD array 325 can be used to calculate the distortion values ​​at various bidirectional prediction MV locations with different weighted parameter values. The bidirectional prediction comparator 345 can be used to identify the optimal weighted parameter values ​​and the optimal bidirectional prediction MV location by comparing the costs associated with different weighted parameter values ​​at different candidate bidirectional prediction MV locations.

[0069] Example video encoder

[0070] Figure 8An example video encoder 800 is illustrated, which can use LC-RDO and HC-RDO stages to select the encoding / decoding tool and / or prediction candidate for encoding / decoding the current block. As shown, the video encoder 800 receives an input video signal from a video source 805 and encodes the signal into a bitstream 895. The video encoder 800 has several components or modules for encoding the signal from the video source 805, including at least some of the following: a transform module 810, a quantization module 811, an inverse quantization module 814, an inverse transform module 815, an intra-picture estimation module (also called an intra-frame estimation module) 820, an intra-frame prediction module 825, a motion compensation module 830, a motion estimation module 835, a loop filter 845, a reconstructed picture buffer 850, an MV buffer 865, an MV prediction module 875, and an entropy encoder 890. The motion compensation module 830 and the motion estimation module 835 are part of the inter-frame prediction module 840.

[0071] In some embodiments, modules 810-890 are software instruction modules executed by one or more processing units (e.g., processors) of a computing device or electronic device. In some embodiments, modules 810-890 are hardware circuit modules implemented by one or more integrated circuits (ICs) of an electronic device. Although modules 810-890 are shown as separate modules, some modules may be combined into a single module.

[0072] Video source 805 provides a raw video signal that presents pixel data for each video frame without compression. Subtractor 808 calculates the difference between the raw video pixel data from video source 805 and the predicted pixel data 813 from motion compensation module 830 or intra-frame prediction module 825. Transform module 810 converts the difference (or residual pixel data or residual signal 808) into transform coefficients 816 (e.g., by performing a discrete cosine transform or DCT). Quantization module 811 quantizes the transform coefficients into quantized data (or quantized coefficients) 812, which is encoded into a bitstream 895 by entropy encoder 890.

[0073] Inverse quantization module 814 inverse quantizes the quantized data (or quantized coefficients) 812 to obtain transform coefficients, and inverse transform module 815 performs an inverse transform on the transform coefficients to produce a reconstructed residual 819. The reconstructed residual 819 is added together with the predicted pixel data 813 to produce reconstructed pixel data 817. In some embodiments, the reconstructed pixel data 817 is temporarily stored in a line buffer (not shown) for intra-image prediction and spatial MV prediction. The reconstructed pixels are filtered by a loop filter 845 and stored in a reconstructed image buffer 850. In some embodiments, the reconstructed image buffer 850 is external memory to the video encoder 800. In some embodiments, the reconstructed image buffer 850 is internal memory to the video encoder 800.

[0074] The intra-image estimation module 820 performs intra-frame prediction based on the reconstructed pixel data 817 to generate intra-frame prediction data. The intra-frame prediction data is provided to the entropy encoder 890 to be encoded into a bitstream 895. The intra-frame prediction data is also used by the intra-frame prediction module 825 to generate predicted pixel data 813.

[0075] The motion estimation module 835 performs inter-frame prediction by generating MVs (Motion Values) to reference pixel data of previously decoded frames stored in the reconstructed image buffer 850. These MVs are provided to the motion compensation module 830 to generate predicted pixel data.

[0076] Instead of encoding the complete actual MV in the bitstream, the video encoder 800 uses MV prediction to generate a predicted MV, and the difference between the MV used for motion compensation and the predicted MV is encoded as residual motion data and stored in the bitstream 895.

[0077] The MV prediction module 875 generates a predicted MV based on a reference MV generated for encoding a previous video frame, i.e., a motion-compensated MV used to perform motion compensation. The MV prediction module 875 retrieves the reference MV from the previous video frame from the MV buffer 865. The video encoder 800 stores the MV generated for the current video frame in the MV buffer 865 as a reference MV for generating the predicted MV.

[0078] The MV prediction module 875 uses a reference MV to create the predicted MV. The predicted MV can be calculated by spatial MV prediction or temporal MV prediction. The entropy encoder 890 encodes the difference (residual motion data) between the predicted MV and the motion-compensated MV (MC MV) of the current frame into the bitstream 895.

[0079] The entropy encoder 890 encodes various parameters and data into a bitstream 895 using entropy encoding techniques such as context-adaptive binary arithmetic codec (CABAC) or Huffman coding. The entropy encoder 890 encodes various header elements, flags, along with quantized transform coefficients 812 and residual motion data, as syntax elements into the bitstream 895. The bitstream 895 is then stored in a storage device or transmitted to the decoder via a communication medium such as a network.

[0080] The loop filter 845 performs filtering or smoothing operations on the reconstructed pixel data 817 to reduce coded artifacts, particularly at the boundaries of pixel blocks. In some embodiments, the filtering operation performed includes Sample Adaptive Offset (SAO). In some embodiments, the filtering operation includes Adaptive Loop Filter (ALF).

[0081] Figure 9 This figure illustrates portions of a video encoder 800 that implements LC-RDO and HC-RDO. Specifically, it illustrates components of the inter-frame prediction module 840 of the video encoder 800. As shown, the inter-frame prediction module 840 includes LC-RDO 110 and HC-RDO 120 for performing rate distortion optimization to identify the most suitable codec tools and / or prediction candidates.

[0082] RDO stages 110 and 120 both receive source pixel data from video source 805, reference pixel data from reconstructed image buffer 850, and reference MV data from MV buffer 865. LC-RDO 110 uses the received data to identify prediction candidates and calculate the cost (e.g., rate and distortion) for various codec tools. LC-RDO 110 can identify the prediction candidate with the best cost for each codec tool as an intermediate RDO result for HC-RDO 120. HC-RDO 120 sequentially performs the selection of codec tools and prediction candidates. Motion compensation module 830 (which may be part of HC-RDO 120) uses the selected codec tool and prediction candidate to perform motion compensation and produce prediction pixel data 813.

[0083] Figure 10 The process 1000 for finding weighting parameter values ​​when encoding a coded block using BCW is conceptually illustrated. In some embodiments, one or more processing units (e.g., processors) of a computing device implement encoder 800 and execute process 1000 by executing instructions stored in a computer-readable medium. In some embodiments, an electronic device implementing encoder 800, specifically LC-RDO stage 110, executes process 1000.

[0084] The encoder (at block 1010) receives the raw pixel data of the pixel block as the current block of the current picture of the video is encoded into the bitstream.

[0085] The encoder (at block 1020) identifies multiple candidate bidirectional prediction locations, including a center location, a first set of offset locations, and a second set of offset locations. The first set of offset locations and the second set of offset locations are offset locations from the center location. In some embodiments, the first set of offset locations and the second set of offset locations are interleaved with each other.

[0086] The encoder (at block 1030) calculates the distortion value for the center position based on each of several possible weighting parameter values. The encoder (at block 1040) calculates the distortion value for each of the first set of offset positions based on a first subset of the possible weighting parameter values. The encoder (at block 1050) calculates the distortion value for each of the second set of offset positions based on a second distinct subset of the possible weighting parameter values.

[0087] In some embodiments, the encoder calculates distortion values ​​based on weighted parameter values ​​at candidate bidirectional prediction locations. Bidirectional predictions are calculated using weighted parameter values ​​that are a weighted average of a first prediction based on a first motion vector and a second prediction based on a second motion vector (e.g., according to Equation 2). First and second motion vectors are identified based on the candidate bidirectional prediction locations. The distortion of possible weighted parameter values ​​at candidate bidirectional prediction locations represents the difference between the raw pixel data of the current block and the bidirectional predictions calculated based on the possible weighted parameter values ​​at the candidate bidirectional prediction locations.

[0088] In some embodiments, several possible weighted parameter values ​​include a first, second, third, fourth, and fifth value. For BCW codec tools, these five possible weighted parameter values ​​correspond to -2, 3, 4, 5, and 10. A first subset of the multiple possible weighted parameter values ​​includes the second, third, and fifth values ​​(3, 4, and 10). A second subset of the multiple possible weighted parameter values ​​includes the first, third, and fourth values ​​(-2, 4, and 5). In some embodiments, the first and second subsets of the possible weighted parameter values ​​share a single possible weighted parameter value (the third value, i.e., 4). A shared possible weighted parameter value corresponds to equal weighting of the first and second predictions (according to Equation 2).

[0089] The encoder (at block 1060) selects the weighted parameter values ​​for candidate bidirectional prediction positions based on the calculated distortion values ​​of multiple candidate bidirectional prediction positions for the current block. The encoder (at block 1070) encodes the current block using bidirectional prediction based on the selected weighted parameter values ​​and the selected candidate bidirectional prediction positions.

[0090] Example electronic system

[0091] Many of the aforementioned features and applications are implemented as software processes, which are specified as a set of instructions recorded on a computer-readable storage medium (also known as a computer-readable medium). When these instructions are executed by one or more computing or processing units (e.g., one or more processors, processor cores, or other processing units), they cause the processing unit to perform the actions indicated in the instructions. Examples of computer-readable media include, but are not limited to, CD-ROMs, flash drives, random access memory (RAM) chips, hard disk drives, erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), etc. Computer-readable media do not include carrier waves and electronic signals transmitted wirelessly or via wired connections.

[0092] In this specification, the term "software" means including firmware residing in read-only memory or an application stored in magnetic storage, which can be read into memory for processor processing. Furthermore, in some embodiments, multiple software inventions may be implemented as sub-parts of a larger program while retaining distinct software inventions. In some embodiments, multiple software inventions may also be implemented as separate programs. Finally, any combination of separate programs that together implement the software inventions described herein is within the scope of this disclosure. In some embodiments, when a software program is installed to run on one or more electronic systems, one or more specific machine implementations are defined to execute and perform the operations of the software program.

[0093] Figure 11 An electronic system 1100 implementing some embodiments of the present disclosure is conceptually illustrated. The electronic system 1100 may be a computer (e.g., a desktop computer, personal computer, tablet computer, etc.), a telephone, a PDA, or any other type of electronic device. Such an electronic system includes various types of computer-readable media and interfaces for various other types of computer-readable media. The electronic system 1100 includes a bus 1105, a processing unit 1110, a graphics processing unit (GPU) 1115, system memory 1120, a network 1125, read-only memory 1130, permanent storage device 1135, input device 1140, and output device 1145.

[0094] Bus 1105 collectively represents all system, peripheral, and chipset buses that communicate with the numerous internal devices of electronic system 1100. For example, bus 1105 communicates with processing unit 1110 and GPU 1115, read-only memory 1130, system memory 1120, and permanent storage device 1135.

[0095] From these different memory units, processing unit 1110 retrieves instructions to be executed and data to be processed in order to perform the processes of this disclosure. In different embodiments, the processing unit may be a single-processor or a multi-core processor. Some instructions are passed to GPU 1115 and executed thereon. GPU 1115 may offload various computations or supplement image processing provided by processing unit 1110.

[0096] Read-only memory (ROM) 1130 stores static data and instructions used by processing unit 1110 and other modules of the electronic system. On the other hand, permanent storage device 1135 is a read-write storage device. This device is a non-volatile storage unit that stores instructions and data even when the electronic system 1100 is turned off. Some embodiments of this disclosure use mass storage devices (e.g., magnetic disks or optical disks and their corresponding disk drives) as permanent storage device 1135.

[0097] Other embodiments use removable storage devices (e.g., floppy disks, flash memory devices, etc., and their corresponding disk drives) as permanent storage devices. Like permanent storage device 1135, system memory 1120 is a read-write storage device. However, unlike storage device 1135, system memory 1120 is volatile read-write memory, such as random access memory. System memory 1120 stores some instructions and data used by the processor during runtime. In some embodiments, processes according to this disclosure are stored in system memory 1120, permanent storage device 1135, and / or read-only memory 1130. For example, various memory units include instructions for processing multimedia clips, as described in some embodiments. From these different memory units, processing unit 1110 retrieves instructions to be executed and data to be processed in order to perform processes of some embodiments.

[0098] Bus 1105 is also connected to input and output devices 1140 and 1145. Input device 1140 enables a user to transmit information and select commands to the electronic system. Input device 1140 includes an alphanumeric keypad and a pointing device (also known as a "cursor control device"), a camera (e.g., a webcam), a microphone, or similar devices for receiving voice commands, etc. Output device 1145 displays images or other output data generated by the electronic system. Output device 1145 includes printers and display devices, such as cathode ray tube (CRT) or liquid crystal display (LCD), and speakers or similar audio output devices. Some embodiments include devices that function as both input and output devices, such as touchscreens.

[0099] Finally, as Figure 11As shown, bus 1105 also couples electronic system 1100 to network 1125 via a network adapter (not shown). In this way, the computer can be part of a computer network (e.g., a local area network (“LAN”), a wide area network (“WAN”), or an intranet, or a network of networks, such as the Internet). Any or all components of electronic system 1100 can be used in conjunction with this disclosure.

[0100] Some embodiments include machine-readable or computer-readable media (or computer-readable storage media, machine-readable media, or machine-readable storage media). Examples of such computer-readable media include RAM, ROM, read-only optical disc (CD-ROM), recordable optical disc (CD-R), rewritable optical disc (CD-RW), read-only digital versatile optical disc (e.g., DVD-ROM, dual-layer DVD-ROM), various recordable / rewritable DVDs (e.g., DVD-RAM, DVD-RW, DVD+RW, etc.), flash memory (e.g., SD card, mini-SD card, microSD card, etc.), magnetic and / or solid-state hard disk drives, read-only and recordable... Optical discs, high-density optical discs, any other optical or magnetic media, and floppy disks. Computer-readable media may store computer programs that can be executed by at least one processing unit and include a set of instructions for performing various operations. Examples of computer programs or computer code include machine code, such as machine code generated by a compiler, and files that include high-level code executed by a computer, electronic components, or a microprocessor using an interpreter.

[0101] While the above discussion primarily concerns microprocessors or multi-core processors that execute software, many of the aforementioned features and applications are implemented by one or more integrated circuits, such as application-specific integrated circuits (ASICs) or field-programmable gate arrays (FPGAs). In some embodiments, such integrated circuits execute instructions stored on the circuit itself. Furthermore, some embodiments execute software stored in a programmable logic device (PLD), ROM, or RAM device.

[0102] As used in this specification and any claim of this application, the terms "computer," "server," "processor," and "memory" refer to electronic or other technical devices. These terms do not include people or groups of people. For illustrative purposes, the term "display" indicates display on an electronic device. As used in this specification and any claim of this application, the terms "computer-readable medium," "computer-readable medium," and "machine-readable medium" are entirely limited to tangible physical objects that store information in a computer-readable form. These terms do not include any wireless signals, wired download signals, or any other temporary signals.

[0103] Although this disclosure has been described with reference to many specific details, those skilled in the art will recognize that this disclosure may be implemented in other specific forms without departing from the spirit of this disclosure. Furthermore, many figures (including...) Figure 10 This invention conceptually illustrates the process. Specific operations of these processes may not be performed in the exact order shown and described. Specific operations may not be performed in a continuous series of operations, and different specific operations may be performed in different embodiments. Furthermore, the process may be implemented using multiple sub-processes or as part of a larger macro-process. Therefore, those skilled in the art will understand that this disclosure is not limited to the foregoing illustrative details, but is defined by the appended claims.

[0104] The subjects described herein sometimes illustrate different components contained within or connected to other different components. It should be understood that the architectures depicted are merely exemplary, and many other architectures can actually be implemented to achieve the same functionality. Conceptually, any arrangement of components achieving the same function is effectively “associated” to achieve the desired function. Therefore, any two components combined in this document to obtain a particular function can be considered “associated” with each other to achieve the desired function, regardless of the architecture or intermediate components. Similarly, any two such associated components can also be considered “operably connected” or “operably coupled” with each other to achieve the desired function, and any two components that can be suchly associated can also be considered “operably coupled” with each other to achieve the desired function. Specific examples of “operably coupled” include, but are not limited to: physically connectable and / or physically interacting components, and / or wirelessly interactable and / or logically interactable components.

[0105] Furthermore, regarding the use of virtually any plural and / or singular terms in this document, those skilled in the art can convert plural to singular and / or singular to plural, provided it is appropriate for the context and / or application. For clarity, various singular / plural permutations may be explicitly described herein.

[0106] Those skilled in the art will understand that, generally, the terms used herein, particularly those used in the appended claims (e.g., the subject of the appended claims), are intended as “open-ended” terms (e.g., the term “comprising” should be interpreted as “comprising but not limited to”, the term “having” should be interpreted as “having at least”, the term “comprising” should be interpreted as “comprising but not limited to”, etc.). Those skilled in the art will also understand that if a specific number of the objects of the claims is intended, such intention will be explicitly stated in the claims; in the absence of such a statement, such intention does not exist. For example, to aid understanding, the appended claims may include the use of introductory phrases such as “at least one” and “one or more” to introduce the objects of the claims. However, the use of such phrases should not be interpreted as limiting any claim containing such an indefinite article "a (a) or an" to an invention containing only one such claim, even if the same claim contains the introductory phrases "one or more" or "at least one" and indefinite articles such as "a (a)" or "an" (e.g., "a (a)" and / or "an" should generally be interpreted as meaning "at least one" or "one or more"); the same applies to the use of definite articles to introduce the claim. Furthermore, even if a specific number of the claimed claims is explicitly stated, those skilled in the art will recognize that such a statement should generally be interpreted as meaning at least the stated number (e.g., a statement containing only "two claims" without other modifiers generally means at least two claims, or two or more claims). Furthermore, when using idioms such as "at least one of A, B, and C," such a structure is generally intended to convey the meaning of the idiom as understood by a person skilled in the art (e.g., "a system having at least one of A, B, and C" would include, but is not limited to, systems having a single A, a single B, a single C, A and B together, A and C together, B and C together, and / or A, B, and C together, etc.). When using idioms such as "at least one of A, B, or C," such a structure is generally intended to convey the meaning of the idiom as understood by a person skilled in the art (e.g., "a system having at least one of A, B, or C" would include, but is not limited to, systems having a single A, a single B, a single C, A and B together, A and C together, B and C together, and / or A, B, and C together, etc.). Those skilled in the art will further understand that, whether in the specification, claims, or drawings, virtually arbitrary extractives and / or phrases representing two or more alternative terms should be understood to consider the possibility of including one, any, or all two terms.For example, the phrase “A or B” should be understood as including the possibility of “A”, “B”, or “A and B”.

[0107] As can be understood from the foregoing, various embodiments of this disclosure have been described herein for illustrative purposes, and various modifications may be made without departing from the scope and spirit of this disclosure. Therefore, the various embodiments disclosed herein are not intended to be limiting, and the true scope and spirit are indicated by the appended claims.

Claims

1. A video encoding method, comprising: The raw pixel data of the received pixel blocks is encoded into the bitstream as the current block of the current image in the video; Identify multiple candidate bidirectional prediction locations, including the center location, the first set of offset locations, and the second set of offset locations; The distortion value of each of the plurality of candidate bidirectional prediction locations is calculated based on a plurality of possible weighted parameter values, wherein: (i) the distortion value calculated for the center location is calculated based on each of the plurality of possible weighted parameter values, (ii) the distortion value calculated for the first set of offset locations is calculated based on a first subset of the plurality of possible weighted parameter values, and (iii) the distortion value calculated for the second set of offset locations is calculated based on a second subset of the plurality of possible weighted parameter values, wherein the first subset of the plurality of possible weighted parameter values ​​is different from the second subset of the plurality of possible weighted parameter values; Based on the calculated distortion values ​​of the multiple candidate bidirectional prediction positions for the current block, a weighted parameter value for the candidate bidirectional prediction position is selected; and The current block is encoded using bidirectional prediction based on the selected weighting parameter value.

2. The video encoding method as described in claim 1, characterized in that, The first set of offset positions and the second set of offset positions are intertwined.

3. The video encoding method as described in claim 1, characterized in that, Calculating the distortion value for encoding and decoding the current block based on the weighted parameter value at the candidate bidirectional prediction position includes: calculating bidirectional prediction using the weighted parameter value, wherein the bidirectional prediction is the average of a first prediction based on a first motion vector and a second prediction based on a second motion vector, wherein the first motion vector and the second motion vector are identified based on the candidate bidirectional prediction position.

4. The video encoding method as described in claim 3, characterized in that, The first subset and the second subset of the multiple possible weighted parameter values ​​share a single possible weighted parameter value.

5. The video encoding method as described in claim 4, characterized in that, Calculating the distortion value for encoding and decoding the current block based on the shared possible weighting parameter value includes equally weighting the first and second predictions.

6. The video encoding method as described in claim 3, characterized in that, The distortion value of the possible weighting parameter at the candidate bidirectional prediction location is the difference between the original pixel data of the current block and the bidirectional prediction calculated based on the possible weighting parameter at the candidate bidirectional prediction location.

7. The video encoding method as described in claim 1, characterized in that: These multiple possible weighted parameter values ​​include the first, second, third, fourth, and fifth values. This first subset of the multiple possible weighted parameter values ​​includes the second, third, and fifth values. This second subset of the multiple possible weighted parameter values ​​includes the first, third, and fourth values.

8. The video encoding method as described in claim 1, characterized in that, The distortion value is calculated by a circuit shared by multiple different codec tools.

9. An electronic device, comprising: Encoder circuitry, configured to perform operations, including: The raw pixel data of the received pixel blocks is encoded into the bitstream as the current block of the current image in the video; Identify multiple candidate bidirectional prediction locations, including the center location, the first set of offset locations, and the second set of offset locations; The distortion value of each of the plurality of candidate bidirectional prediction locations is calculated based on a plurality of possible weighted parameter values, wherein: (i) the distortion value calculated for the center location is calculated based on each of the plurality of possible weighted parameter values, (ii) the distortion value calculated for the first set of offset locations is calculated based on a first subset of the plurality of possible weighted parameter values, and (iii) the distortion value calculated for the second set of offset locations is calculated based on a second subset of the plurality of possible weighted parameter values, wherein the first subset of the plurality of possible weighted parameter values ​​is different from the second subset of the plurality of possible weighted parameter values; Based on the calculated distortion values ​​of the multiple candidate bidirectional prediction positions for the current block, a weighted parameter value for the candidate bidirectional prediction position is selected; and The current block is encoded using bidirectional prediction based on the selected weighting parameter value.

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