Switching transistor state detection circuit and motor controller

Abstract

The application provides a switch tube state detection circuit and a motor controller. The switch tube state detection circuit comprises a state extraction circuit, a state comparison circuit and a driving circuit. One end of the state extraction circuit is connected with the collector of a switch tube to be detected, and is used for generating a switching signal. The other end of the state extraction circuit is connected with one end of the state comparison circuit. One end of the driving circuit is connected with the base of the switch tube to be detected and one end of the state comparison circuit respectively, and is used for sending a driving signal. The other end of the state comparison circuit is connected with the other end of the driving circuit, which is used for confirming the switching condition of the switch tube to be detected according to the driving signal and the switching signal, and generating a fault signal when the driving signal is consistent with the switching signal, and sending the fault signal to the driving circuit to make the driving circuit perform fault processing according to the fault signal. The application can not only detect the switching condition of the switch tube to be detected, but also perform fault processing to protect the switch tube to be detected.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of power electronics, and particularly relates to a switching tube state detection circuit and a motor controller. BACKGROUND

[0002] The motor controller of an electric vehicle is developed based on the ISO26262 functional safety standard. In order to achieve a torque safety ASIL level of C or D, it is necessary to monitor the execution of an IGBT switching tube. The commonly used monitoring method is a voltage comparison detection method and a gate level state detection method of a driving chip. For the voltage comparison detection method, it is easy to trigger an error, and additional peripheral devices and MCU operations are required, which leads to an increase in the cost of the motor controller. For the gate level state detection method of the driving chip, it can only detect the loss of a gate level signal and cannot detect the switching state of the IGBT switching tube. SUMMARY

[0003] The present application provides a switching tube state detection circuit and a motor controller, and aims to solve the problems of high cost and inability to detect the switching state of an IGBT switching tube in the current detection method for monitoring an IGBT switching tube to be detected.

[0004] In a first aspect, the present application provides a switching tube state detection circuit, which comprises a state extraction circuit, a state comparison circuit and a driving circuit. One end of the state extraction circuit is connected to the collector of a switching tube to be detected, for extracting the working state of the switching tube to be detected and generating a switching signal. The other end of the state extraction circuit is connected to one end of the state comparison circuit, for sending the switching signal to the state comparison circuit. One end of the driving circuit is connected to the base of the switching tube to be detected and one end of the state comparison circuit, for sending a driving signal. The other end of the state comparison circuit is connected to the other end of the driving circuit, for confirming the switching state of the switching tube to be detected according to the driving signal and the switching signal, and generating a fault signal when the driving signal is consistent with the switching signal, and sending the fault signal to the driving circuit to make the driving circuit perform fault processing according to the fault signal.

[0005] Further, the state extraction circuit comprises a first diode and a first resistor. The anode of the first diode is connected to one end of the state comparison circuit and one end of the first resistor, and the cathode of the first diode is connected to the collector of the switching tube to be detected. The other end of the first resistor is connected to a power supply end.

[0006] Furthermore, the state comparison circuit includes a first fault detection circuit and a second fault detection circuit; one input terminal of each of the first fault detection circuit and the second fault detection circuit is connected to the positive terminal of the first diode, the other input terminal of each of the first fault detection circuit and the second fault detection circuit is connected to one end of the driving circuit, and the output terminal of each of the first fault detection circuit and the second fault detection circuit is connected to the other end of the driving circuit.

[0007] Furthermore, the first fault detection circuit includes a first switching transistor and a second switching transistor; the gate of the first switching transistor is connected to the positive terminal of the first diode, the source of the first switching transistor is connected to the drain of the second switching transistor, the drain of the first switching transistor is connected to the driving circuit, the gate of the second switching transistor is connected to the driving circuit, and the source of the second switching transistor is grounded.

[0008] Furthermore, both the first switch and the second switch are NMOS transistors.

[0009] Furthermore, the second fault detection circuit includes a third switch and a fourth switch; the gate of the third switch is connected to the positive terminal of the first diode, the drain of the third switch is connected to the source of the fourth switch, the source of the third switch is connected to the driving circuit, the gate of the fourth switch is connected to the driving circuit, and the drain of the fourth switch is grounded.

[0010] Furthermore, both the third and fourth switching transistors are PMOS transistors.

[0011] Furthermore, the first fault detection circuit also includes a first capacitor, one end of which is connected to the drain of the first switching transistor, and the other end of which is grounded.

[0012] Furthermore, the second fault detection circuit also includes a second capacitor, one end of which is connected to the source of the third switching transistor, and the other end of which is grounded.

[0013] In a second aspect, the present invention also provides a motor controller, which includes the switching transistor state detection circuit described in any of the above claims.

[0014] The switch tube state detection circuit and the motor controller can extract the working state of the switch tube to be detected through the state extraction circuit and generate a switch signal according to the working state, send the switch signal to the state comparison circuit, drive the switch-on and switch-off of the switch tube to be detected through the drive signal of the drive circuit, and the drive signal is also sent to the state comparison circuit. The state comparison circuit confirms the switching condition of the switch tube to be detected according to the drive signal and the switch signal, and when the drive signal is consistent with the switch signal, a fault signal can also be generated and sent to the drive circuit, so that the circuit can be processed. The circuit can not only confirm the switching condition of the switch tube to be detected, but also can be processed, and the hardware state protection of the switch tube is realized. BRIEF DESCRIPTION OF DRAWINGS

[0015] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0016] Figure 1 is a block schematic diagram of the switch tube state detection circuit provided by an embodiment of the present application;

[0017] Figure 2 is a circuit diagram of the switch tube state detection circuit provided by an embodiment of the present application; and

[0018] Figure 3 is a block schematic diagram of the switch tube state detection circuit provided by another embodiment of the present application. DETAILED DESCRIPTION

[0019] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are some embodiments of the present application, not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present application.

[0020] It should be understood that when used in the specification and the appended claims, the terms "comprise" and "include" indicate the presence of described features, integers, operations, elements and / or components, but do not exclude one or more other features, integers, operations, elements, components and / or sets thereof.

[0021] It should also be understood that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used in this specification and the appended claims, the singular forms "a," "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. It will be further understood that the terms "and / or," "and / or," as used herein, refer to and encompass any and all possible combinations of one or more of the associated items, including if no item is named in the combination.

[0022] Referring to Figures 1 to 3 , Figure 1 is a block diagram of a switch tube state detection circuit according to an embodiment of the present application; Figure 2 is a circuit diagram of a switch tube state detection circuit according to an embodiment of the present application; Figure 3 is a block diagram of a switch tube state detection circuit according to another embodiment of the present application. As shown in Figure 1 , the switch tube state detection circuit includes a state extraction circuit 10, a state comparison circuit 30, and a driving circuit 20. One end of the state extraction circuit 10 is connected to the collector of a switch tube Q5 to be detected, for extracting the working state of the switch tube Q5 to be detected and generating a switch signal. The other end of the state extraction circuit 10 is connected to one end of the state comparison circuit 30, for sending the switch signal to the state comparison circuit 30. One end of the driving circuit 20 is connected to the base of the switch tube Q5 to be detected and one end of the state comparison circuit 30, for sending a driving signal. The other end of the state comparison circuit 30 is connected to the other end of the driving circuit 20, for confirming the switching condition of the switch tube Q5 to be detected according to the driving signal and the switch signal, and generating a fault signal when the driving signal is consistent with the switch signal, and sending the fault signal to the driving circuit 20 to make the driving circuit 20 perform fault processing according to the fault signal.

[0023] The switch tube Q5 to be detected can be an IGBT tube. The state extraction circuit 10 is connected with the switch tube Q5 to be detected, and can extract the working state of the switch tube Q5 to be detected. The working state can include conduction and turn-off, and a corresponding switch signal is generated. The driving circuit 20 is used for sending a driving signal. The driving circuit 20 can include a driving chip. The chip has an isolation amplification function, and can amplify the corresponding control signal. The driving circuit 20 is also connected with the MCU, and is used for receiving the control signal of the MCU, and sending the driving signal according to the control signal. The driving signal drives the conduction and turn-off of the switch tube Q5 to be detected on one hand, and enters the state comparison circuit 30 on the other hand. After receiving the driving signal and the switch signal, the state comparison circuit 30 judges the state of the switch tube Q5 to be detected, and generates a corresponding signal, for example, a level signal, to the driving circuit 20. The switching condition of the switch tube Q5 to be detected includes normal conduction, normal turn-off, abnormal conduction and abnormal turn-off. The state comparison circuit 30 can confirm that the switch tube Q5 to be detected is in which kind of switching condition according to the driving signal and the switch signal. When the driving signal and the switch signal are consistent, a fault signal is generated. For example, when the driving signal is a low level, and the switch signal is also a low level, the fault signal is generated, and is sent to the driving circuit 20. When receiving the fault signal, the driving circuit 20 controls the motor controller to enter a safe state, realizes the hardware state protection of the switch tube Q5 to be detected, and also sends the fault signal to the MCU, so that the MCU can be processed subsequently.

[0024] The driving signal can be a high-low level. If the switch tube Q5 to be detected receives a high level conduction and a low level turn-off, when the driving signal is a high level, the base of the switch tube Q5 to be detected receives a high level, the Vge driving level of the switch tube Q5 to be detected is 1, the switching state of Vce is 0, the level signal extracted by the state extraction circuit 10 is a low level, and the low level is sent to the state comparison circuit 30. The state comparison circuit 30 receives the low level extracted from the state extraction circuit 10 on one hand, and receives the high level sent from the driving circuit 20 on the other hand, and compares the low level and the high level to confirm the switching condition of the switch tube Q5 to be detected. If the driving signal is a low level signal, the switch tube Q5 to be detected outputs a high level signal, the state extraction circuit 10 extracts a high level signal, the state comparison circuit 30 receives the high level signal from the state extraction circuit 10 and the low level signal from the driving circuit 20 respectively, and confirms them.

[0025] Referring to Figure 2As a further example, the state extraction circuit 10 comprises a first diode D1 and a first resistor R1; a positive electrode of the first diode D1 is connected with one end of the state comparison circuit 30 and one end of the first resistor R1 respectively, a negative electrode of the first diode D1 is connected with a collector of the switch tube Q5 to be detected, and the other end of the first resistor R1 is connected with a power supply end.

[0026] Wherein, the negative electrode of the first diode D1 is connected with the collector of the switch tube Q5 to be detected, for extracting the working state of the switch tube Q5 to be detected. When the driving signal is high level, the switch tube Q5 to be detected outputs low level, and the positive electrode of the first diode D1 outputs low level to the state comparison circuit 30; when the driving signal is low level, the switch tube Q5 to be detected outputs high level, and the positive electrode of the first diode D1 outputs high level to the state comparison circuit 30. Figure 2 HV_DC is a high-voltage bus power supply, and VON_U_H is a driving power supply.

[0027] Referring to Figure 3 As a further example, the state comparison circuit 30 comprises a first fault detection circuit 31 and a second fault detection circuit 32; one input end of the first fault detection circuit 31 and the second fault detection circuit 32 is connected with the positive electrode of the first diode D1, the other input end of the first fault detection circuit 31 and the second fault detection circuit 32 is connected with one end of the driving circuit 20, and the output end of the first fault detection circuit 31 and the second fault detection circuit 32 is connected with the other end of the driving circuit 20.

[0028] The first fault detection circuit 31 and the second fault detection circuit 32 are connected with the driving chip of the driving circuit 20, for example, connected with the Gate Monitor module of the driving chip. When the driving signal is high level, the to-be-detected switch tube Q5 is turned on, and a low level is output, the first diode D1 extracts the low level signal and outputs the low level to the first fault detection circuit 31 and the second fault detection circuit 32, at the same time, the driving circuit 20 outputs high level to the first fault detection circuit 31 and the second fault detection circuit 32, and the first fault detection circuit 31 and the second fault detection circuit 32 output corresponding signals according to the low level and the high level respectively to confirm whether the to-be-detected switch tube Q5 has a fault. For example, when the driving signal is high level, and the first fault detection circuit 31 and the second fault detection circuit 32 output high level, the to-be-detected switch tube Q5 is normally turned on. If the driving signal is high level, and the first fault detection circuit 31 outputs low level, the to-be-detected switch tube Q5 is abnormally turned off. When the driving signal is low level, and the first fault detection circuit 31 and the second fault detection circuit 32 output high level, it indicates that the to-be-detected switch tube Q5 is normally turned off, if the driving signal is low level, and the second fault detection circuit 32 outputs low level, it indicates that the to-be-detected switch tube Q5 is abnormally turned on. In summary, when the driving signal is consistent with the switch signal, it indicates that the to-be-detected switch tube Q5 has a fault. The driving circuit 20 can confirm the switching condition of the to-be-detected switch according to the received level signals of the first fault detection circuit 31 and the second switch circuit.

[0029] Referring to Figure 2 As a further embodiment, the first fault detection circuit 31 comprises a first switch tube Q1 and a second switch tube Q2; the gate of the first switch tube Q1 is connected with the anode of the first diode D1, the source of the first switch tube Q1 is connected with the drain of the second switch tube Q2, the drain of the first switch tube Q1 is connected with the driving circuit 20, the gate of the second switch tube Q2 is connected with the driving circuit 20, and the source of the second switch tube Q2 is grounded.

[0030] As a further embodiment, the first switch tube Q1 and the second switch tube Q2 are both NMOS tubes.

[0031] The state of the switch Q5 under test can include normal conduction, normal off, abnormal conduction, and abnormal off. Both the first switch Q1 and the second switch Q2 of the first fault detection circuit 31 are NMOS transistors. NMOS transistors conduct when they receive a high level and turn off when they receive a low level. Therefore, when the drive signal is high, the second switch Q2 of the first fault detection circuit 31 receives a high level and conducts. The switch Q5 under test outputs a low level, the first diode D1 outputs a low level, and the first switch Q1 of the first fault detection circuit 31 receives a low level and turns off. Figure 2 As shown, at this time, the first fault detection circuit 31 outputs a high level. If the second fault detection circuit 32 also outputs a high level at the same time, it indicates that the switch Q5 under test is conducting normally. If the drive signal is low, the switch Q5 under test outputs a low level, and the first diode D1 outputs a low level. Then, the first switch Q1 of the first fault detection circuit 31 receives a low level and turns off, the second switch Q2 turns off, and the first fault detection circuit 31 outputs a low level. If the second fault detection circuit 32 outputs a low level at this time, it indicates that the switch Q5 under test is abnormally conducting. When the drive signal is low, the output of the switch Q5 under test is high, the output of the first diode D1 is high, the first switch Q1 of the first fault detection circuit 31 is turned on, the second switch Q2 of the first fault detection circuit 31 is turned off, and the first fault detection circuit 31 outputs a high level to the drive circuit 20. If the output of the second fault detection circuit 32 is high, it indicates that the switch Q5 under test is normally turned off. If the drive signal is high, the output of the switch Q5 under test is high, the first switch Q1 and the second switch Q2 of the first fault detection circuit 31 are both turned on, and the output of the first fault detection circuit 31 is low, it indicates that the switch Q5 under test is abnormally turned off.

[0032] As a further embodiment, the second fault detection circuit 32 includes a third switch Q3 and a fourth switch Q4; the gate of the third switch Q3 is connected to the positive terminal of the first diode D1, the drain of the third switch Q3 is connected to the source of the fourth switch Q4, the source of the third switch Q3 is connected to the driving circuit 20, the gate of the fourth switch Q4 is connected to the driving circuit 20, and the drain of the fourth switch Q4 is grounded.

[0033] As a further embodiment, both the third switch Q3 and the fourth switch Q4 are PMOS transistors.

[0034] The state of the switch tube Q5 to be detected can include normal conduction, normal turn-off, abnormal conduction and abnormal turn-off, the third switch tube Q3 and the fourth switch tube Q4 are PMOS tubes, and the PMOS tube is turned on when receiving a low level. When the drive signal is high, the switch tube Q5 to be detected outputs a low level, the first diode D1 outputs a low level, the third switch tube Q3 is turned on, the fourth switch tube Q4 is turned off, and the second fault detection circuit 32 outputs a high level. If the first fault detection circuit 31 outputs a high level, the switch tube Q5 to be detected is normally conducted. If the drive signal is low, the switch tube Q5 to be detected outputs a low level, the first diode D1 outputs a low level, the third switch tube Q3 and the fourth switch tube Q4 are both turned on, and the second fault detection circuit 32 outputs a low level, indicating that the switch tube Q5 to be detected is abnormally conducted. When the drive signal is low, the switch tube Q5 to be detected outputs a high level, the first diode D1 outputs a high level, the third switch tube Q3 is turned off, the fourth switch tube Q4 is turned on, and if the first fault detection circuit 31 outputs a high level, it indicates that the switch tube Q5 to be detected is normally turned off. If the drive signal outputs a high level, the switch tube Q5 to be detected outputs a high level, the first diode D1 outputs a high level, the third switch tube Q3 and the fourth switch tube Q4 are both turned off, and the second fault detection circuit 32 outputs a high level. If the first fault detection circuit 31 outputs a low level at this time, it indicates that the switch tube Q5 to be detected is abnormally turned off. The first switch tube Q1 and the second switch tube Q2 in the first fault detection circuit 31 are set as NMOS tubes, and the third switch tube Q3 and the fourth switch tube Q4 of the second fault detection circuit 32 are set as PMOS tubes, which can provide 2 times Vgs(th) threshold voltage when the switch tube Q5 to be detected is turned on and turned off, and can well avoid the mis-triggering caused by the overlapping area of the switch tube Q5 to be detected. As shown in Table 1, Table 1 is the on and off state of the switch tube Q5 to be detected, Vge drive signal is the drive signal sent by the drive circuit 20, Vce switch signal is the signal sent by the switch tube Q5 to be detected, Fault_IGBT_OC is the signal output by the first fault detection circuit 31, and Fault_IGBT_SC is the signal output by the second fault detection circuit 32. As can be seen from Table 1, when the first fault detection circuit 31 and the second fault detection circuit 32 both output a high level, the switch tube Q5 to be detected is normally conducted or normally turned off. When one of the first fault detection circuit 31 and the second fault detection circuit 32 outputs a low level, it indicates that the switch tube Q5 to be detected is abnormally conducted or abnormally turned off. Specifically, when the Vge drive signal is low and the switch tube Q5 to be detected outputs low, the first fault detection circuit 31 outputs a high level, and the second fault detection circuit 32 outputs a low level, the switch tube Q5 to be detected is abnormally conducted. When the Vge drive signal is low and the switch tube Q5 to be detected outputs high, the first fault detection circuit 31 and the second fault detection circuit 32 both output a high level, and the switch tube Q5 to be detected is normally turned off.When the Vge driving signal is high, the output of the to-be-detected switch tube Q5 is low, the first fault detection circuit 31 and the second fault detection circuit 32 both output high, and the to-be-detected switch tube Q5 is normally turned on; when the Vge driving signal is high, the output of the to-be-detected switch tube Q5 is high, the first fault detection circuit 31 outputs low, and the second fault detection circuit 32 outputs high, and the to-be-detected switch tube Q5 is abnormally turned off. The fault signal is filtered and sent to the driving circuit.

[0035] Table 1

[0036]

[0037] As a further embodiment, the first fault detection circuit 31 further comprises a first capacitor C1, one end of the first capacitor C1 being connected with the drain of the first switch tube Q1, and the other end being grounded.

[0038] As a further embodiment, the second fault detection circuit 32 further comprises a second capacitor C2, one end of the second capacitor C2 being connected with the source of the third switch tube Q3, and the other end being grounded.

[0039] As shown in the formula (1), the first capacitor C1 and the second capacitor C2 are both used for filtering the output signal. Figure 2

[0040] The application further provides a motor controller, which comprises a state extraction circuit 10, a state comparison circuit 30 and a driving circuit 20; one end of the state extraction circuit 10 is connected with the collector of a to-be-detected switch tube Q5, for extracting the working state of the to-be-detected switch tube Q5 and generating a switching signal, and the other end of the state extraction circuit 10 is connected with one end of the state comparison circuit 30, for sending the switching signal to the state comparison circuit 30; one end of the driving circuit 20 is connected with the base of the to-be-detected switch tube Q5 and one end of the state comparison circuit 30, respectively, for sending a driving signal; the other end of the state comparison circuit 30 is connected with the other end of the driving circuit 20, for confirming the switching condition of the to-be-detected switch tube Q5 according to the driving signal and the switching signal, and when the driving signal is consistent with the switching signal, generating a fault signal and sending the fault signal to the driving circuit 20 to make the driving circuit 20 perform fault processing according to the fault signal.

[0041] ​The switch tube state detection circuit and the motor controller can extract the working state of the switch tube to be detected through the state extraction circuit, and send a switch signal to the state comparison circuit, so that the state comparison circuit confirms whether the switch tube to be detected has a fault according to the switch signal and the driving signal, and the switch state of the switch tube can be confirmed while the fault is detected, and the cost is low.

[0042] The above merely provides a specific implementation of the present application, but the protection scope of the present application is not limited thereto, and any skilled person in the art can easily think of various equivalent modifications or replacements within the technical range disclosed by the present application, and these modifications or replacements shall be encompassed within the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A switch tube state detection circuit applied to a motor controller, characterized in that, The switch tube state detection circuit comprises a state extraction circuit, a state comparison circuit and a driving circuit; One end of the state extraction circuit is connected with a collector of a switch tube to be detected, for extracting a working state of the switch tube to be detected and generating a switch signal, and the other end of the state extraction circuit is connected with one end of the state comparison circuit, for sending the switch signal to the state comparison circuit; One end of the driving circuit is connected with a base of the switch tube to be detected and one end of the state comparison circuit, for sending a driving signal; The other end of the state comparison circuit is connected with the other end of the driving circuit, for confirming a switch condition of the switch tube to be detected according to the driving signal and the switch signal, and generating a fault signal when the driving signal is consistent with the switch signal, and sending the fault signal to the driving circuit to make the driving circuit perform fault processing according to the fault signal; The state comparison circuit comprises a first fault detection circuit and a second fault detection circuit; One input end of the first fault detection circuit and the second fault detection circuit is connected with a positive electrode of a first diode of the state extraction circuit, the other input end of the first fault detection circuit and the second fault detection circuit is connected with one end of the driving circuit, and the output end of the first fault detection circuit and the second fault detection circuit is connected with the other end of the driving circuit.

2. The switch tube state detection circuit according to claim 1, wherein The state extraction circuit comprises the first diode and a first resistor; The positive electrode of the first diode is connected with one end of the state comparison circuit and one end of the first resistor, the negative electrode of the first diode is connected with the collector of the switch tube to be detected, and the other end of the first resistor is connected with a power supply end.

3. The switch tube state detection circuit according to claim 1, wherein The first fault detection circuit comprises a first switch tube and a second switch tube; The gate of the first switch tube is connected with the positive electrode of the first diode, the source of the first switch tube is connected with the drain of the second switch tube, the drain of the first switch tube is connected with the driving circuit, the gate of the second switch tube is connected with the driving circuit, and the source of the second switch tube is grounded.

4. The switch tube state detection circuit according to claim 3, wherein The first switch tube and the second switch tube are both NMOS tubes.

5. The switch tube state detection circuit according to claim 1, wherein The second fault detection circuit comprises a third switch tube and a fourth switch tube; The gate of the third switch tube is connected with the positive electrode of the first diode, the drain of the third switch tube is connected with the source of the fourth switch tube, the source of the third switch tube is connected with the driving circuit, the gate of the fourth switch tube is connected with the driving circuit, and the drain of the fourth switch tube is grounded.

6. The switch tube state detection circuit according to claim 5, wherein The third switch tube and the fourth switch tube are both PMOS tubes.

7. The switch tube state detection circuit according to claim 3, wherein The first fault detection circuit further comprises a first capacitor, one end of the first capacitor is connected with the drain of the first switch tube, and the other end of the first capacitor is grounded.

8. The switch tube state detection circuit according to claim 5, wherein The second fault detection circuit further comprises a second capacitor, one end of the second capacitor is connected with the source of the third switch tube, and the other end of the second capacitor is grounded.

9. An electric machine controller characterized by The switch tube state detection circuit comprises a switch tube state detection circuit according to any one of claims 1 to 8.

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