Display device including pixel driving circuit

Abstract

Disclosed is a display device including a light emitting element; and a pixel driving circuit connected to the light emitting element and configured to include a first node, a second node, a third node, and a fourth node, wherein the pixel driving circuit includes a driving transistor connected to the first node to the third node, a plurality of switching transistors, and a storage capacitor. Among the plurality of switching transistors, a switching transistor connected to a source node of the driving transistor is controlled by a second scan signal and is configured to apply a data voltage to the source node of the driving transistor, and the second scan signal can be applied one or more times during one frame.

Description

Technical Field

[0001] This disclosure relates to a display device including pixel driving circuitry. Background Technology

[0002] With the development of information technology, the market for display devices, as the medium connecting users with information, has grown. Beyond transmitting text-centric information between users, various forms of communication have seen positive development. As the types of information change, the performance of display devices used to display information has also evolved. Therefore, display devices such as organic light-emitting diode (OLED) displays, micro-LED displays, liquid crystal displays, and quantum dot displays are being used in a diversified manner, and high-resolution display devices to improve information clarity are being actively researched and developed.

[0003] A display device includes: a display panel including a plurality of sub-pixels; a driving circuit supplying signals for driving the display panel; and a power supply unit for supplying power to the display panel. The driving circuit includes a gate driving circuit for supplying gate signals to the display panel and a data driving circuit for supplying data signals to the display panel.

[0004] For example, when gate signals and data signals are supplied to the sub-pixels of a display device, the display device can display an image by causing the light-emitting elements of the selected sub-pixels to emit light. The light-emitting elements can be implemented based on organic or inorganic materials.

[0005] Display devices display images based on light generated from light-emitting elements in sub-pixels, thus offering various advantages. However, to improve image quality, it is necessary to increase the precision of the pixel driving circuitry used to control the light emission in the sub-pixels. For example, the precision of the pixel driving circuitry can be improved by compensating for the threshold voltage of the driving transistors included in the pixel driving circuitry.

[0006] The background information described above may be reserved for the inventor's derivation of this disclosure, or it may be technical information obtained through implementing embodiments of this disclosure. However, the background information described above may not be prior art disclosed to the public prior to this application. Summary of the Invention

[0007] The pixel driving circuit of the display device divides a horizontal time period 1H into an initialization period, a sampling period, a holding period, and an emission period, and compensates for the deviation of the threshold voltage of the driving transistor during the sampling period.

[0008] As the resolution and / or driving frequency of display devices increase, sampling time cannot be adequately guaranteed, resulting in image quality defects such as blemishes, afterimages, and crosstalk.

[0009] To address the aforementioned issues, extending the sampling time of the pixel driving circuit improves image quality defects such as blemishes, image retention, and crosstalk. However, when a black signal is applied, such as at low grayscale, the light-emitting device emits light undesirably. Therefore, it can be identified that the light-emitting device cannot achieve a black gradient and cannot reduce the voltage of the source node of the driving transistor while ensuring sufficient sampling time.

[0010] One object of this specification is to provide a display device including a pixel driving circuit that can adequately ensure the sampling period before the light emission period arrives and reduce the voltage of the source node of the driving transistor.

[0011] According to one aspect of this disclosure, the above and other objectives can be achieved by providing a display device comprising: a light-emitting element; and a pixel driving circuit connected to the light-emitting element and configured to include a first node, a second node, a third node, and a fourth node, wherein the pixel driving circuit includes: a driving transistor connected to the first node, the second node, and the third node; a first transistor connected to a first scan signal line and connected between the first node and the second node; a second transistor connected to a second scan signal line and connected between the third node and a data line; a third transistor connected to the first scan signal line and connected between the first node and an initialization voltage line; a fourth transistor connected to a second light-emitting control line and connected between the second node and the first driving voltage line; a fifth transistor connected to the first light-emitting control line and connected between the third node and the fourth node; and a storage capacitor disposed between the first node and the fourth node, wherein a second scan signal is applied once or multiple times during a frame period via the second scan signal line.

[0012] In addition to the effects described above, those skilled in the art will clearly understand other advantages and features of this disclosure through the above description. Attached Figure Description

[0013] The above and other objects, features, and other advantages of this disclosure will become clearer from the following detailed embodiments, taken in conjunction with the accompanying drawings, in which:

[0014] Figure 1 This is a block diagram of a display device according to an embodiment of the present disclosure;

[0015] Figure 2 This is a circuit diagram of a pixel driving circuit and a light-emitting device according to an embodiment of the present disclosure;

[0016] Figure 3 This is a waveform diagram of the gate signal and the voltage of a specific node in a pixel driving circuit according to an embodiment of the present disclosure;

[0017] Figure 4 This is a waveform diagram of the gate signal and the voltage of a specific node in a pixel driving circuit according to another embodiment of the present disclosure;

[0018] Figure 5 This is a diagram illustrating a dither driving method according to an embodiment of the present disclosure;

[0019] Figure 6 This is a circuit diagram of a pixel driving circuit and a light-emitting device according to another embodiment of the present disclosure; and

[0020] Figure 7 This is a circuit diagram of a pixel driving circuit and a light-emitting device according to another embodiment of the present disclosure. Detailed Implementation

[0021] The advantages and features of this disclosure, and its implementation methods, will be illustrated by the embodiments described below in conjunction with the accompanying drawings. However, this disclosure may be implemented in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to make this disclosure thorough and complete, and to fully convey the scope of this disclosure to those skilled in the art. Furthermore, this disclosure is limited only by the scope of the claims.

[0022] The shapes, dimensions, ratios, angles, and quantities disclosed in the accompanying drawings used to describe embodiments of this disclosure are merely examples, and therefore, this disclosure is not limited to the details shown. Throughout the specification, the same reference numerals refer to the same elements. In the following description, detailed descriptions of relevant known functions or configurations will be omitted where it is determined that such descriptions would unnecessarily obscure the focus of this disclosure.

[0023] When using the terms "comprising," "having," and "including" as described in this specification, another component may be added unless "only" is used. Unless otherwise stated, singular terms may include plural forms.

[0024] When interpreting components, even without an explicit description of the error range, the component is interpreted as including the error range.

[0025] When describing positional relationships, for example, when the positional relationship is described as "on top of," "above," "below," and "below," and "adjacent to," one or more parts may be arranged between two other parts unless "exactly" or "directly" is used.

[0026] When describing temporal relationships, such as when time sequence is described as “after,” “following,” “next,” and “before,” discontinuous cases may be included unless “exactly” or “directly” is used.

[0027] It should be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0028] The term "at least one" should be understood to include any and all combinations of one or more of the related listed items. For example, "at least one of the first, second, and third items" means a combination of two or more items from the first, second, and third items, as well as all items proposed from the first, second, or third item.

[0029] As will be fully understood by those skilled in the art, the features of the various embodiments of this disclosure may be combined or integrated with each other in part or in whole, and may interoperate with each other in various ways and be technically driven. Embodiments of this disclosure may be implemented independently of each other or may be implemented jointly in an interdependent manner.

[0030] In the following, preferred embodiments of the pixel driving circuit and the display device including the pixel driving circuit according to the present disclosure will be described in detail with reference to the accompanying drawings. Wherever possible, the same reference numerals will be used throughout the drawings to refer to the same or similar parts. Since the scale of each element shown in the drawings differs from the actual scale for ease of description, the present disclosure is not limited to the scale shown.

[0031] In this specification, the pixel driving circuit and gate driving circuit formed on the substrate of the display panel can be implemented as N-type transistors or P-type transistors. For example, the transistor can be implemented as a transistor having an N-type or P-type metal-oxide-semiconductor field-effect transistor (MOSFET) structure. A transistor is a three-electrode device including a gate, a source, and a drain. The source and drain of a transistor are not fixed, and the source and drain of a transistor can be changed according to the applied voltage. For example, one of the source and drain may be referred to as the first source / drain, and the other may be referred to as the second source / drain, but is not limited thereto.

[0032] The gate signal of a transistor used as a switching element can swing between a gate on-state voltage and a gate off-state voltage. The gate on-state voltage is set to the voltage that turns the transistor on, and the gate off-state voltage is set to the voltage that turns the transistor off. In the case of an N-type transistor, the gate on-state voltage can be a gate high voltage VGH with a first voltage level, and the gate off-state voltage can be a gate low voltage VGL with a second voltage level lower than the gate high voltage VGH. In the case of a P-type transistor, the gate on-state voltage can be a gate low voltage VGL with a second voltage level, and the gate off-state voltage can be a gate high voltage VGH with a first voltage level.

[0033] A first gate control line, a second gate control line, a third gate control line, and a fourth gate control line may be provided between the gate driving circuit and the pixel driving circuit.

[0034] Figure 1 This is a block diagram of a display device according to an embodiment of the present disclosure.

[0035] refer to Figure 1 According to an embodiment of the present disclosure, a display device 100 may include: a display panel 110, wherein a plurality of data lines DL and a plurality of gate lines GL are disposed in the display panel 110, and a plurality of pixels PX connected to the plurality of data lines DL and the plurality of gate lines GL are arranged thereon; and a driving circuit, the driving circuit being used to provide driving signals to the display panel 110.

[0036] Although multiple pixels PX are shown arranged in a matrix structure to form a pixel array, this disclosure is not limited thereto, and pixels can be arranged in various structures.

[0037] The driving circuit may include: a data driving circuit 120 for providing data signals to multiple data lines DL; a gate driving circuit GD for providing gate signals to multiple gate lines GL; and a controller 130 (or timing controller) for controlling the data driving circuit 120 and the gate driving circuit GD.

[0038] The display panel 110 may include a display area DA for displaying images and a non-display area NDA disposed around the display area DA. The display area DA has a plurality of pixels PX, a data line DL for providing data signals to the plurality of pixels PX, and a gate line GL for providing gate signals.

[0039] Multiple gate lines GL, disposed in the display area DA, can extend to the non-display area NDA and be electrically connected to the gate drive circuit GD. The gate lines GL electrically connect multiple pixels PX disposed in a first direction (or row direction) to the gate drive circuit GD. Additionally, gate drive lines required to generate various gate signals or drive multiple pixels PX can be disposed in the non-display area NDA. For example, the gate drive lines may include: one or more high-level gate voltage lines for supplying a high-level gate voltage to the gate drive circuit GD; one or more low-level gate voltage lines for supplying a low-level gate voltage to the gate drive circuit GD; multiple clock lines for supplying multiple clock signals to the gate drive circuit GD; and one or more start-up lines for supplying one or more start-up signals to the gate drive circuit GD.

[0040] Multiple data lines DL disposed in the display area DA can extend to the non-display area NDA and can be electrically connected to the data driving circuit 120. The data lines DL can electrically connect the data driving circuit 120 to multiple pixels PX disposed in a second direction (or column direction) intersecting the first direction. The data lines DL can be implemented as a single line, or multiple wirings can be connected via contact holes using connecting wires.

[0041] In the display panel 110, multiple data lines DL and multiple gate lines GL are arranged together with the pixel array. As described above, the multiple data lines DL and multiple gate lines GL can be arranged in rows or columns, respectively. For ease of description, it is assumed that the multiple data lines DL are arranged in columns and the multiple gate lines GL are arranged in rows.

[0042] The controller 130 (or timing controller) can start scanning the data signal according to the timing implemented in each frame, convert the input image data from the outside according to the data signal format used in the data drive circuit 120, output the converted image data, and control the data drive circuit 120 synchronously with the scanning signal.

[0043] The controller 130 can receive timing signals, including vertical synchronization signals, horizontal synchronization signals, input data enable signals, clock signals, etc., as well as input image data from the outside. The controller 130, which receives timing signals, can generate and output control signals for controlling the data drive circuit 120 and the gate drive circuit GD.

[0044] For example, controller 130 can output various data control signals, including source start pulse, source sampling clock, and source output enable signal, to control data drive circuit 120. The source start pulse can control the start time of data sampling in one or more data signal generation circuits constituting data drive circuit 120. The source sampling clock is a clock signal used to control the sampling time of data in each data signal generation circuit. The source output enable signal can control the output time of data drive circuit 120.

[0045] Additionally, the controller 130 can output gate control signals, including a gate start pulse, a gate shift clock, and a gate output enable signal, to control the gate drive circuit GD. The gate start pulse controls the start time of operation of one or more gate signal generation circuits constituting the gate drive circuit GD. The gate shift clock, i.e., the clock signal commonly input to one or more gate signal generation circuits, controls the shift timing of the scan signal. The gate output enable signal specifies the timing information for one or more gate signal generation circuits.

[0046] The controller 130 may be a timing controller used in conventional display device technology or a control device that includes a timing controller to further perform other control functions.

[0047] The controller 130 can be implemented as a separate component from the data drive circuit 120, or it can be integrated with the data drive circuit 120 and implemented as an integrated circuit.

[0048] The data driving circuit 120 may include one or more data signal generation circuits. These data signal generation circuits may include shift registers, latch circuits, digital-to-analog converters, output buffers, etc. If necessary, the data signal generation circuits may also include analog-to-digital converters.

[0049] The data signal generation circuit can be connected to the pads of the display panel 110 via tape automated bonding (TAB), chip-on-glass (COG), or chip-on-panel (COP) methods, or it can be directly mounted on or integrated with the display panel 110. Furthermore, multiple data signal generation circuits can be implemented using a chip-on-film (COF) method mounted on the source circuit film connected to the display panel 110.

[0050] The gate drive circuit GD sequentially supplies gate signals to multiple gate lines GL, thereby driving multiple pixels PX connected to the multiple gate lines GL. The gate drive circuit GD may include shift registers, level shifters, etc.

[0051] The gate drive circuit (GD) can be connected to the pads of the display panel 110 via a tape-on-brush (TAB) method, a chip-on-glass (COG) method, or a chip-on-panel (COP) method, or it can be implemented using an in-panel gate-in-place (GIP) method and can be directly disposed on the display panel 110. Furthermore, multiple gate signal generation circuits can be mounted on a gate circuit film connected to the display panel 110 and can be implemented using a chip-on-film (COF) method. The gate drive circuit (GD) may include multiple gate signal generation circuits, which can be implemented using the GIP method and disposed in the non-display area (NDA) of the display panel 110.

[0052] Under the control of controller 130, gate drive circuit GD can sequentially supply gate signals with a high gate voltage VGH (a first voltage level for turning on or off the transistor) or a low gate voltage VGL (a second voltage level for turning on or off the transistor) to multiple gate lines GL. When a signal is supplied to a specific gate line through gate drive circuit GD, data drive circuit 120 can convert image data received from controller 130 into analog data signals and supply the analog data signals to multiple data lines DL.

[0053] The data driving circuit 120 can be disposed on one side of the display panel 110. For example, the data driving circuit 120 can be disposed on the upper, lower, left, or right side of the display panel 110. Alternatively, depending on the driving method, panel design method, etc., the data driving circuit 120 can be disposed on both sides of the display panel 110. For example, the data driving circuit 120 can be disposed on the upper and lower sides of the display panel 110, or on the left and right sides of the display panel 110.

[0054] The gate driving circuit GD can be disposed on one side of the display panel 110. For example, the gate driving circuit GD can be disposed on the upper, lower, left, or right side of the display panel 110. Alternatively, depending on the driving method, panel design method, etc., the gate driving circuit GD can be disposed on both sides of the display panel 110. For example, the gate driving circuit GD can be disposed on the upper and lower sides of the display panel 110, or on the left and right sides of the display panel 110. The gate driving circuit GD can be formed in the left and / or right non-display area NDA of the substrate along with the manufacturing process of the thin-film transistor of the pixel PX, and can operate according to a single feeding method to supply gate signals to each of the multiple gate lines GL. Alternatively, the gate driving circuit GD can be formed in each of the left and right non-display areas NDA of the substrate, and can operate according to a double feeding method to supply gate signals to each of the multiple gate lines GL. Alternatively, the gate drive circuit GD can be formed in each of the non-display areas NDA on the left and right sides of the substrate, and can operate according to the interlacing method of the double-fed method to supply gate signals to each of the multiple gate lines GL.

[0055] The diagram shows multiple gate lines GL disposed in a first direction (or row direction) and multiple data lines DL disposed in a second direction (or column direction) intersecting the first direction. Therefore, it is assumed that the data driving circuit 120 is disposed on the upper side of the display panel 110, and the gate driving circuit GD is disposed on the left and right sides of the display panel 110.

[0056] The multiple gate lines GL disposed on the display panel 110 may include multiple first gate control lines, multiple second gate control lines, and multiple third gate control lines. The first gate control lines, second gate control lines, and third gate control lines are lines that transmit different types of gate signals to the gates of different transistors. For example, the first gate control line may be a line for transmitting a first light emission control signal, the second gate control line may be a line for transmitting a second light emission control signal, and the third gate control line may be a line for transmitting a scan signal.

[0057] Therefore, the gate drive circuit GD may include: a plurality of first light emission control drive circuits configured to output a first light emission control signal to a first gate control line of the gate line GL; a plurality of second light emission control drive circuits configured to output a second light emission control signal to a second gate control line; and a plurality of scan drive circuits configured to output a scan signal to a third gate control line.

[0058] A frame period is defined as the time interval during which gate signals and data signals, including a first light emission control signal, a second light emission control signal, and a scan signal, are applied to all pixels PX located in the second direction (or column direction) of the display area DA. A frame period can be divided into a scan period and a light emission period. During the scan period, data is scanned in each pixel PX connected to a gate line GL, and input image data is written to each pixel PX. During the light emission period, after the scan period, the pixel PX is turned on according to the first and second light emission control signals. During the light emission period, the pixel PX can be repeatedly turned on and off. The scan period may include an initialization period, a sampling period, etc. The sampling period may include a programming period. During the scan period, the nodes included in the pixel driving circuit are initialized, threshold voltage compensation of the driving transistors is performed, and data voltage is charged. During the light emission period, the light emission operation is performed. The scan period consists of only a few horizontal scan periods, while the light emission period occupies the majority of a frame period.

[0059] Figure 2 This is a circuit diagram of a pixel driving circuit and a light-emitting element according to an embodiment of the present disclosure.

[0060] refer to Figure 2 The display device 100 according to embodiments of the present disclosure may include a display panel 110, wherein the display panel 110 may include a plurality of sub-pixels SP constituting a unit pixel PX. Each of the plurality of sub-pixels SP may include a light-emitting element ED and a pixel driving circuit for driving the light-emitting element ED.

[0061] like Figure 2 As shown, the pixel driving circuit of the sub-pixel SP can be constructed using a 6T1C transistor, but is not limited to this. The transistors disposed in the pixel driving circuit can be N-type transistors, but are not limited to this. The pixel driving circuit of the sub-pixel SP can be constructed using P-type transistors or a combination of N-type and P-type transistors.

[0062] The pixel driving circuit of the sub-pixel SP may include: a driving element for supplying driving current to the light-emitting element ED; a scanning element for transmitting the voltages Data and Vini required to drive the display device to the sub-pixel SP at a predetermined time according to a scanning signal; a light-emitting control element for controlling whether the light-emitting element ED emits light; and a storage capacitor Cst for storing the voltages Data and Vini required to drive the display device.

[0063] like Figure 2As shown, the driving element may include a driving transistor DT. The scanning element may include a first transistor T1 (or a first switching transistor), a second transistor T2 (or a second switching transistor), and a third transistor T3 (or a third switching transistor). The light-emitting control element may include a fourth transistor T4 (or a first light-emitting control transistor) and a fifth transistor T5 (or a second light-emitting control transistor).

[0064] The light-emitting element (ED) may include a first electrode (anode or pixel electrode) and a second electrode (cathode or common electrode). The first electrode may correspond to or be connected to the fourth node N4. A second driving voltage EVSS (or common voltage), which is a low-potential voltage, may be applied to the second electrode. For example, the ED may be disposed between the fourth node N4 and the line to which the second driving voltage EVSS is applied, and may be electrically connected thereto. For example, the ED may be an organic light-emitting diode (OLED), a light-emitting diode (LED), or a quantum dot light-emitting diode (QLED).

[0065] The driving transistor DT can be connected to a first node N1, a second node N2, and a third node N3, and can be controlled according to the voltage of the first node N1. The driving transistor DT may include a gate, a drain (or a first source / drain), and a source (or a second source / drain). The gate (or gate node) of the driving transistor DT can be connected to the first node N1, the drain (or drain node) can be connected to the second node N2, and the source (or source node) can be connected to the third node N3. For example, a first driving voltage EVDD, as a high-potential voltage, can be applied to the drain of the driving transistor DT. The source of the driving transistor DT can be electrically connected to the first electrode (or anode) of the light-emitting element ED.

[0066] The first transistor T1 (or the first switching transistor) can be controlled by the first scan signal SC1 and can be connected between the first node N1 and the second node N2. The first transistor T1 may include a gate, a drain (or a first source / drain), and a source (or a second source / drain). The gate (or gate node) of the first transistor T1 can be applied with the first scan signal SCAN1, the drain (or drain node) can be connected to the second node N2, and the source (or source node) can be connected to the first node N1.

[0067] The second transistor T2 (or the second switching transistor) can be controlled by the second scan signal SC2 and can be connected between the third node N3 and the line where the data voltage Data is applied. The second transistor T2 may include a gate, a drain (or a first source / drain), and a source (or a second source / drain). The gate (or gate node) of the second transistor T2 can be supplied with the second scan signal SC2, the drain (or drain node) can be supplied with the data voltage Data, and the source (or source node) can be connected to the third node N3.

[0068] The third transistor T3 (or the third switching transistor) can be controlled by the first scan signal SC1 and can be connected between the line to which the initialization voltage Vini is applied and the fourth node N4. The third transistor T3 may include a gate, a drain (or a first source / drain), and a source (or a second source / drain). The gate (or gate node) of the third transistor T3 can be applied with the first scan signal SC1, the drain (or drain node) can be applied with the initialization voltage Vini, and the source (or source node) can be connected to the fourth node N4.

[0069] The storage capacitor Cst can be connected between the first node N1 and the fourth node N4. The storage capacitor Cst can store and hold the data voltage Data for one frame.

[0070] The fourth transistor T4 (or the first light-emitting control transistor) can be controlled by the second light-emitting control signal EM2 and can be connected between the line to which the first driving voltage EVDD, which is applied as a high potential voltage, is applied and the second node N2. The fourth transistor T4 may include a gate, a drain (or a first source / drain), and a source (or a second source / drain). The gate (or gate node) of the fourth transistor T4 can be supplied with the second light-emitting control signal EM2, the drain (or drain node) can be supplied with the first driving voltage EVDD, and the source (or source node) can be connected to the second node N2.

[0071] The fifth transistor T5 (or the second light-emitting control transistor) can be controlled by the first light-emitting control signal EM1 and can be connected between the third node N3 and the fourth node N4. The fifth transistor T5 may include a gate, a drain (or a first source / drain), and a source (or a second source / drain). The gate (or gate node) of the fifth transistor T5 can be applied with the first light-emitting control signal EM1, the drain (or drain node) can be connected to the third node N3, and the source (or source node) can be connected to the fourth node N4.

[0072] Figure 3 This is a waveform diagram of the gate signal and the voltage of a specific node in a pixel driving circuit according to an embodiment of the present disclosure.

[0073] Combination Figure 2 refer to Figure 3 According to one embodiment of the present disclosure, the pixel driving circuit can be divided into a first interval ①, a second interval ②, a third interval ③, a fourth interval ④, a fifth interval ⑤, and a sixth interval ⑥, and driven simultaneously. For example, each sub-pixel SP arranged in the (n)th horizontal line can be written with a data voltage Data through the first interval ①, the second interval ②, the third interval ③, the fourth interval ④, the fifth interval ⑤, and the sixth interval ⑥. The timing of each of the first interval ①, the second interval ②, the third interval ③, the fourth interval ④, the fifth interval ⑤, and the sixth interval ⑥ can vary according to embodiments of the present disclosure, but is not limited thereto.

[0074] The gate signals input to the pixel driving circuit may include a first light emission control signal EM1, a second light emission control signal EM2, a first scan signal SC1, and a second scan signal SC2 applied through the gate line GL.

[0075] The first light emission control signal EM1 can have a high gate voltage of a first voltage level in the fifth interval ⑤ and the sixth interval ⑥, and can have a low gate voltage of a second voltage level different from the first voltage level in the first interval ①, the second interval ②, the third interval ③ and the fourth interval ④.

[0076] The second light emission control signal EM2 can have a gate high voltage of the first voltage level in the first interval ① and the sixth interval ⑥, and can have a gate low voltage of the second voltage level in the second interval ②, the third interval ③, the fourth interval ④ and the fifth interval ⑤.

[0077] The first scan signal SC1 can have a gate high voltage of a first voltage level in the first interval ①, the second interval ②, and the third interval ③, and can have a gate low voltage of a second voltage level in the fourth interval ④, the fifth interval ⑤, and the sixth interval ⑥.

[0078] The second scan signal SC2 can have a gate high voltage of the first voltage level in the second interval ②, and can have a gate low voltage of the second voltage level in the first interval ①, the third interval ③, the fourth interval ④, the fifth interval ⑤ and the sixth interval ⑥.

[0079] When the first interval ① begins, the first scan signal SC1 rises to have a high gate voltage, the second light emission control signal EM2 remains at the high gate voltage, and the first light emission control signal EM1 and the second scan signal SC2 can remain at a low gate voltage.

[0080] During the first interval ①, the second light emission control signal EM2 remains at a high gate voltage, thereby turning on the fourth transistor T4. As the first scan signal SC1 becomes a high gate voltage, the first transistor T1 turns on, allowing the first driving voltage EVDD to be applied to the first node N1 through the fourth transistor T4 and the first transistor T1. The first node N1 is the gate node of the driving transistor DT. Therefore, the driving transistor DT can turn on.

[0081] Furthermore, during the first interval ①, as the first scan signal SC1 becomes a gate high voltage, the third transistor T3 is turned on, and the initialization voltage Vini can be applied to the fourth node N4 through the third transistor T3.

[0082] Therefore, the anode of the light-emitting element ED connected to the fourth node N4 can be initialized by the initialization voltage Vini, and the first driving voltage EVDD and the initialization voltage Vini can be applied to the two ends of the storage capacitor Cst connected between the first node N1 and the fourth node N4.

[0083] When the second interval ② begins, the second scan signal SC2 rises to have a high gate voltage, the first scan signal SC1 remains at a high gate voltage, the first light emission control signal EM1 remains at a low gate voltage, and the second light emission control signal EM2 can be reduced to a low gate voltage.

[0084] During the second interval ②, the first scan signal SC1 remains at a high gate voltage, thereby turning on the first transistor T1 and the third transistor T3. As the second scan signal SC2 becomes a high gate voltage, the second transistor T2 turns on, allowing the data voltage Data to be applied to the third node N3 through the second transistor T2. The third node N3 is the source node of the driving transistor DT.

[0085] Since the driving transistor DT is in a diode connection state connecting the first node N1 and the second node N2, the sampling of the threshold voltage Vth of the driving transistor DT begins, thereby increasing the voltage of the first node N1 to the data voltage Data or higher.

[0086] When the third interval ③ begins, the first scan signal SC1 remains at a high gate voltage, thereby reducing the second scan signal SC2 to a low gate voltage, and the first light emission control signal EM1 and the second light emission control signal EM2 can remain at a low gate voltage.

[0087] During the third interval ③, when the second scan signal SC2 transitions to a gate low voltage state, the first scan signal SC1 remains in a gate high voltage state, and the diode connection between the first node N1 and the second node N2 of the driving transistor DT is maintained, thereby increasing the sampling period of the threshold voltage Vth of the driving transistor DT. Therefore, the gate node of the driving transistor DT can be in the sum of the data voltage Data and the threshold voltage Vth of the driving transistor DT, and the voltage of the floating third node N3 can rise to a specified level while the second transistor T2 is turned off.

[0088] Furthermore, during the third interval ③, the storage capacitor Cst can be charged by the potential difference between the total voltage of the data voltage Data and the threshold voltage Vth and the initialization voltage Vini.

[0089] When the fourth interval ④ begins, the first scan signal SC1 drops to a low gate voltage, and the first light emission control signal EM1, the second light emission control signal EM2, and the second scan signal SC2 can remain at a low gate voltage. During the fourth interval ④, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 in the pixel driving circuit can all be turned off.

[0090] Therefore, each of the first node N1, the second node N2, the third node N3, and the fourth node N4 sampled or written in the second interval ② and the third interval ③ can be floated, and the voltage of each node can remain unchanged.

[0091] When the fifth interval ⑤ begins, the first scan signal SC1, the second scan signal SC2, and the second light emission control signal EM2 can be kept in a low gate voltage state, and the first light emission control signal EM1 can be raised to have a high gate voltage.

[0092] During the fifth interval (⑤), as the first light-emitting control signal EM1 becomes a high gate voltage, the fifth transistor T5 can be turned on. At this time, the voltage of the fourth node N4, which is connected to the anode of the light-emitting element ED, can be boosted while the potential difference (Data+Vth–Vini) between the two ends of the storage capacitor Cst is maintained.

[0093] When the boost voltage of the fourth node N4 is equal to or greater than the voltage value at which the driving current can flow through the light-emitting element ED, the light-emitting element ED can emit light. The minimum voltage value at which the driving current can flow through the light-emitting element ED can be the voltage (EVSS+EVth) corresponding to the value in the second driving voltage EVSS that is higher than the threshold voltage EVth of the light-emitting element ED. In this case, when the applied data voltage Data is a black signal, the boost voltage of the fourth node N4 does not exceed the threshold voltage EVth, so the light-emitting element ED can not emit light.

[0094] When the sixth interval ⑥ begins, the second light emission control signal EM2 rises to have a high gate voltage, thereby keeping the first light emission control signal EM1 at a high gate voltage and keeping the first scan signal SC1 and the second scan signal SC2 at a low gate voltage.

[0095] During the sixth interval (⑥), as the second light-emitting control signal EM2 becomes a high gate voltage, the fourth transistor T4 can be turned on. Therefore, the drive current can be supplied to the light-emitting element ED through the fourth transistor T4, the drive transistor DT, and the fifth transistor T5, allowing the light-emitting element ED to emit light. As described above, when the applied data voltage Data is a black signal, the boost voltage of the fourth node N4 does not exceed the threshold voltage EVth of the light-emitting element ED, thus the light-emitting element ED can remain off.

[0096] According to one embodiment of this disclosure, since the gate high voltage of the first scan signal SC1 is maintained for a predetermined period of time in the third interval ③, the time period during which the threshold voltage Vth of the driving transistor DT is sampled can be extended, thereby overcoming image quality defects such as blemishes, afterimages and crosstalk in the image.

[0097] According to one embodiment of this disclosure, when the data voltage Data is a signal representing grayscale, the image quality can be improved due to the extended sampling period. However, if the data voltage Data is a black signal representing black grayscale, the voltage of the third node N3 of the driving transistor DT may increase slightly due to the extended sampling period, so that the light-emitting element ED may emit light even through a black signal.

[0098] Therefore, the inventors of this disclosure have invented a display device including a pixel driving circuit that, by extending the sampling period, prevents the light-emitting element (ED) from unintendedly emitting light when a black signal is applied. Reference will be made below to... Figures 4 to 7 The description includes a display device with pixel driving circuitry having improved black-to-grayscale characteristics.

[0099] Figure 4 This is a waveform diagram of the gate signal and the voltage of a specific node in a pixel driving circuit according to another embodiment of the present disclosure. Figure 5 This is a diagram illustrating a dithering driving method for a display device according to another embodiment of the present disclosure.

[0100] Combination Figure 2 refer to Figure 4 According to another embodiment of this disclosure, the pixel driving circuit can be driven simultaneously by being divided into a first interval ①, a second interval ②, a third interval ③, a fourth interval ④, a fifth interval ⑤, a sixth interval ⑥, and a seventh interval ⑦. For example, each sub-pixel SP arranged in the (n)th horizontal line can be written with a data voltage Data through the first interval ①, the second interval ②, the third interval ③, the fourth interval ④, the fifth interval ⑤, the sixth interval ⑥, and the seventh interval ⑦. The timing of each of the first interval ①, the second interval ②, the third interval ③, the fourth interval ④, the fifth interval ⑤, the sixth interval ⑥, and the seventh interval ⑦ can vary according to embodiments of this disclosure, but is not limited thereto.

[0101] The gate signals input to the pixel driving circuit may include a first light emission control signal EM1, a second light emission control signal EM2, a first scan signal SC1, and a second scan signal SC2 applied through the gate line GL.

[0102] The first light emission control signal EM1 can have a high gate voltage of a first voltage level in the fifth interval ⑤ and the sixth interval ⑥, and can have a low gate voltage of a second voltage level different from the first voltage level in the first interval ①, the second interval ②, the third interval ③ and the fourth interval ④.

[0103] The second light emission control signal EM2 can have a high gate voltage of the first voltage level in the first interval ① and the sixth interval ⑥, and can have a low gate voltage of the second voltage level in the second interval ②, the third interval ③, the fourth interval ④, and the fifth interval ⑤.

[0104] The first scan signal SC1 can have a gate high voltage of a first voltage level in the first interval ①, the second interval ② and the third interval ③, and can have a gate low voltage of a second voltage level in the fourth interval ④, the fifth interval ⑤ and the sixth interval ⑥.

[0105] The second scan signal SC2 can have a gate high voltage of the first voltage level in the second interval ② and the seventh interval ⑦, and can have a gate low voltage of the second voltage level in the first interval ①, the third interval ③, the fourth interval ④, and the sixth interval ⑥. The seventh interval ⑦ can partially overlap with the fifth interval ⑤.

[0106] Except for the parts of the fifth interval ⑤ and the seventh interval ⑦ that overlap with the fifth interval ⑤. Figure 4 waveform diagram and Figure 3 The waveforms are the same, so the descriptions of the identical parts are omitted.

[0107] When the fifth interval ⑤ begins, the first scan signal SC1, the second scan signal SC2, and the second light emission control signal EM2 can be kept in a low gate voltage state, and the first light emission control signal EM1 can be raised to have a high gate voltage.

[0108] During the fifth interval (⑤), as the first light-emitting control signal EM1 becomes a high gate voltage, the fifth transistor T5 can be turned on. At this time, the voltage of the fourth node N4, which is connected to the anode of the light-emitting element ED, can be boosted while the potential difference (Data+Vth–Vini) between the two ends of the storage capacitor Cst is maintained.

[0109] The LED emits light when the boost voltage of the fourth node N4 is equal to or greater than the voltage value at which the driving current can flow through the LED (i.e., the state where it can emit light). The minimum voltage value at which the driving current can flow through the LED can be the voltage (EVSS+EVth) in the second driving voltage EVSS that corresponds to the value higher than the threshold voltage EVth of the LED. In this case, when the applied data voltage Data is a black signal, the boost voltage of the fourth node N4 does not exceed the threshold voltage EVth, so the LED does not emit light.

[0110] According to another embodiment of this disclosure, a seventh interval ⑦ for additionally applying the second scan signal SC2 may be included in the fifth interval ⑤.

[0111] When the seventh interval ⑦ begins, the second scan signal SC2 rises and has a high gate voltage, so that the first light emission control signal EM1 remains at a high gate voltage, and the first scan signal SC1 and the second light emission control signal EM2 remain at a low gate voltage.

[0112] During the seventh interval (⑦), since the first scan signal SC1 and the second light emission control signal EM2 remain at a low gate voltage, the first transistor T1, the third transistor T3, and the fourth transistor T4 are turned off. As the second scan signal SC2 becomes a high gate voltage, the second transistor T2 turns on, so the data voltage Data can be additionally applied to the third node N3 corresponding to the source node of the driving transistor DT through the second transistor T2. In this case, since the fifth transistor T5 is turned on, the data voltage Data is applied to the fourth node N4 through the first light emission signal EM1 at a high gate voltage.

[0113] At this point, unnecessarily increasing the applied data voltage may cause the voltage at the third node N3 of Data to decrease. For example... Figure 4As shown, when the data voltage Data is a black signal (0V), an additional black signal data voltage Data is applied in the seventh interval ⑦, thereby according to... Figure 3 The voltage of the third node N3 can be lower than the voltage of the third node N3 caused by pixel driving. In addition, since the voltage of the third node N3 decreases through the seventh interval ⑦, the boost voltage of the fourth node N4 may not reach the threshold voltage EVth of the light-emitting element ED.

[0114] According to another embodiment of this disclosure, such as Figure 5 As shown, in the dithering method, a low grayscale image can be achieved by combining sub-pixels SP arranged on adjacent horizontal lines instead of using only sub-pixels SP arranged on a single horizontal line. For example, in the dithering method, when representing 1 / 2 gray based on 2×2 pixels, the grayscale of individual pixels is not adjusted, and black data is applied to both sub-pixels of the 2×2 sub-pixel to represent 1 / 2 gray. For example, when representing 3 / 4 gray based on 2×2 pixels, 3 / 4 gray can be represented by applying black data to one of the 2×2 sub-pixels without adjusting the grayscale of individual pixels.

[0115] According to another embodiment of this disclosure, in the case of the dithering driving method, as the second transistor T2 is turned on in the seventh interval ⑦ by the second scan signal SC2, an additional data voltage Data is applied, which corresponds to the time point at which the black grayscale signal is applied to another horizontal line. Therefore, the black grayscale signal can be applied to the pixel driving circuit without separate additional lines or transistors.

[0116] According to another embodiment of this disclosure, a seventh interval ⑦ can be additionally prepared in the fifth interval ⑤ for supplying the data voltage Data to the source node of the driving transistor DT, so that the voltage of the third node N3, which increases due to the extension of the sampling period caused by the third interval ③, can be reduced. Therefore, even if the sampling period is extended, the undesirable emission of the light-emitting element ED can be prevented. Specifically, when the data voltage Data is a black signal that is easily identifiable as being emitted, the light-emitting element ED does not emit light, thereby achieving a clearer black image.

[0117] Reference Figure 6 A pixel driving circuit according to another embodiment of the present disclosure is described. Figure 6 The pixel driving circuit shown according to another embodiment of the present disclosure and Figure 2 The difference in the illustrated embodiment is that the pixel driving circuit also includes a transistor for applying the black grayscale signal. In the following sections, [the following will focus on]... Figure 2 The embodiments shown are described using different configurations. Figure 6 The pixel driving circuit shown is according to another embodiment of the present disclosure.

[0118] Figure 6 This is a circuit diagram of a pixel driving circuit and a light-emitting device according to another embodiment of the present disclosure.

[0119] refer to Figure 6 According to another embodiment of the present disclosure, the pixel driving circuit may further include a black data voltage V representing black grayscale applied to a third node N3. Black The sixth transistor T6 is located between the lines.

[0120] The sixth transistor T6 can be controlled by the second scan signal SC2 and can be connected between the line to which the black data voltage is applied and the third node N3. The sixth transistor T6 may include a gate, a drain (or a first source / drain), and a source (or a second source / drain). The gate (or gate node) of the sixth transistor T6 can be supplied with the second scan signal SC2_P, and the drain (or drain node) can be supplied with the black data voltage V. Black Furthermore, the source (or source node) can be connected to the third node N3.

[0121] According to another embodiment of this disclosure, the seventh interval ⑦ can be executed by the sixth transistor T6. In this case, the second scan signal SC2_P has the same waveform as in the seventh interval ⑦, and the second scan signal SC2_P maintains a low gate voltage in the remaining intervals other than the seventh interval ⑦.

[0122] Reference Figure 7 A pixel driving circuit according to another embodiment of the present disclosure is described. Figure 7 The pixel driving circuit shown according to another embodiment of the present disclosure and Figure 2 The difference in the illustrated embodiment is that the pixel driving circuit further includes a capacitor Cd located between the first scan signal line SC1 and the second scan signal line SC2. In the following sections, [the following will focus on]... Figure 2 The embodiments shown are described using different configurations. Figure 7 The pixel driving circuit shown is according to another embodiment of the present disclosure.

[0123] Figure 7 This is a circuit diagram of a pixel driving circuit and a light-emitting device according to another embodiment of the present disclosure.

[0124] refer to Figure 7 According to another embodiment of the present disclosure, the pixel driving circuit may further include a capacitor Cd between the line for applying the first scan signal SC1 and the line for applying the second scan signal SC2.

[0125] Capacitor Cd can be connected between the third node N3 and the gate node of the first transistor T1. During the operation of the seventh interval ⑦, capacitor Cd can additionally reduce the voltage of the third node N3 through the coupling effect.

[0126] The display device according to embodiments of the present disclosure can be described as follows.

[0127] A display device according to embodiments of the present disclosure may include: a light-emitting element; and a pixel driving circuit connected to the light-emitting element and configured to include a first node, a second node, a third node, and a fourth node. The pixel driving circuit may include: a driving transistor connected to the first node to the third node; a first transistor connected to a first scan signal line and connected between the first node and the second node; a second transistor connected to a second scan signal line and connected between the third node and a data line; a third transistor connected to the first scan signal line and connected between the first node and an initialization voltage line; a fourth transistor connected to a second light-emitting control line and connected between the second node and the first driving voltage line; a fifth transistor connected to the first light-emitting control line and connected between the third node and the fourth node; and a storage capacitor disposed between the first node and the fourth node. A second scan signal may be applied once or multiple times through the second scan signal line during a frame period.

[0128] In the display device according to an embodiment of the present disclosure, the time point at which the second scan signal can be applied includes a first time point at which the second scan signal is applied and a second time point at which the second scan signal is applied, and the data voltage at the second time point at which the second scan signal is applied can be a black data voltage.

[0129] In a display device according to an embodiment of the present disclosure, the data voltage at the first time point on which the second scan signal is applied can be the data voltage used to display the actual image.

[0130] In a display device according to an embodiment of the present disclosure, the first time point at which the second scan signal is applied may be earlier than the second time point at which the second scan signal is applied.

[0131] In a display device according to an embodiment of the present disclosure, the data voltage at a second time point where the second scan signal is applied may be equal to or lower than the data voltage at a first time point where the second scan signal is applied.

[0132] In the display device according to embodiments of the present disclosure, the pixel driving circuit can be driven in a first interval, a second interval, a third interval, a fourth interval, a fifth interval, and a sixth interval. A first scanning signal via a first scanning signal line can have a first voltage level in the first to third intervals and a second voltage level lower than the first voltage level in the fourth to sixth intervals. A second scanning signal via a second scanning signal line can have a first voltage level in the second interval. A first light emission control signal via a first light emission control line can have a first voltage level in the fifth and sixth intervals and a second voltage level in the first to fourth intervals. A second light emission control signal via a second light emission control line can have a first voltage level in the first and sixth intervals and a second voltage level in the second, third, fourth, and fifth intervals.

[0133] In a display device according to an embodiment of the present disclosure, the pixel driving circuit may further include a seventh interval that overlaps with any one of the first to sixth intervals.

[0134] In a display device according to an embodiment of the present disclosure, during the seventh interval, the second scan signal may have a first voltage level.

[0135] In a display device according to an embodiment of the present disclosure, the second scanning signal may have a first voltage level in the second interval and the seventh interval, and a second voltage level in the first interval, the third interval, the fourth interval and the sixth interval.

[0136] In a display device according to an embodiment of the present disclosure, the seventh interval may partially overlap with the fifth interval.

[0137] In a display device according to an embodiment of the present disclosure, a plurality of pixel driving circuits may be further included in each of the horizontal lines. The pixel driving circuit included in one of the horizontal lines may be subjected to a second scan signal once or multiple times during a frame, and the time point at which the second scan signal is additionally applied may correspond to the time point at which the black data voltage is applied to the pixel driving circuit included in another horizontal line.

[0138] In a display device according to an embodiment of the present disclosure, the pixel driving circuit may further include a sixth transistor disposed between the third node and the black data voltage.

[0139] In a display device according to an embodiment of the present disclosure, a sixth transistor may be connected to a second scan signal line.

[0140] In the display device according to embodiments of the present disclosure, a capacitor may also be formed between the first scan signal line and the third node.

[0141] In a display device according to an embodiment of the present disclosure, during a frame period, the time point at which an additional second scan signal is applied may overlap with the time period during which the first light emission control signal of the first light emission control line has a first voltage level, and may not overlap with the time period during which the second light emission control signal of the second light emission control line has a first voltage level.

[0142] In a display device according to an embodiment of the present disclosure, during a frame time period, the time point at which the second scan signal is additionally applied can be set between the time point at which the first light emission control signal via the first light emission control line changes to the first voltage level and the time point at which the second light emission control signal via the second light emission control line changes to the first voltage level.

[0143] In the display device including pixel driving circuit according to the present disclosure, the sampling period is sufficiently ensured, and the voltage of the source node of the driving transistor is reduced before the light emission period, thereby overcoming image quality defects such as blemishes, image retention and crosstalk, and improving black grayscale.

[0144] It will be apparent to those skilled in the art that various substitutions, modifications, and variations can be made within the scope of this disclosure without departing from its spirit and scope. Therefore, the scope of this disclosure is defined by the appended claims, and all variations or modifications derived from the meaning, scope, and equivalents of the claims should be understood to be included within the scope of this disclosure.

Claims

1. A display device comprising: a light emitting element; and a pixel drive circuit connected to the light emitting element and configured to include a first node, a second node, a third node, and a fourth node, wherein the pixel drive circuit includes: a drive transistor connected to the first node, the second node, and the third node; a first transistor connected to a first scan signal line and connected between the first node and the second node; a second transistor connected to a second scan signal line and connected between the third node and a data line; a third transistor connected to the first scan signal line and connected between the fourth node and an initialization voltage line; a fourth transistor connected to a second light emission control line and connected between the second node and a first drive voltage line; a fifth transistor connected to a first light emission control line and connected between the third node and the fourth node; and a storage capacitor provided between the first node and the fourth node, wherein a second scan signal is applied through the second scan signal line one or a plurality of times during a frame period, wherein, during the frame period, a point in time at which the second scan signal is additionally applied overlaps with a period in which a first light emission control signal has a first voltage level through the first light emission control line, and does not overlap with a period in which a second light emission control signal has the first voltage level through the second light emission control line.

2. The display device according to claim 1, wherein the point in time at which the second scan signal is applied includes a first point in time at which the second scan signal is applied and a second point in time at which the second scan signal is applied, and a data voltage at the second point in time at which the second scan signal is applied is a black data voltage.

3. The display device according to claim 2, wherein a data voltage at the first point in time at which the second scan signal is applied is a data voltage for displaying an actual image.

4. The display device according to claim 2, wherein the first point in time at which the second scan signal is applied is earlier than the second point in time at which the second scan signal is applied.

5. The display device according to claim 3, wherein the data voltage at the second point in time at which the second scan signal is applied is equal to or lower than the data voltage at the first point in time at which the second scan signal is applied.

6. The display device according to claim 1, wherein the pixel drive circuit is driven in a first interval, a second interval, a third interval, a fourth interval, a fifth interval, and a sixth interval, a first scan signal through the first scan signal line has a first voltage level in the first interval, the second interval, and the third interval, and has a second voltage level lower than the first voltage level in the fourth interval, the fifth interval, and the sixth interval, the second scan signal through the second scan signal line has the first voltage level in the second interval, the second scan signal through the second scan signal line has the first voltage level in the second interval, the first light emission control signal through the first light emission control line has the first voltage level in the fifth interval and the sixth interval, and has the second voltage level in the first interval, the second interval, the third interval, and the fourth interval, and the second light emission control signal through the second light emission control line has the first voltage level in the first interval and the sixth interval, and has the second voltage level in the second interval, the third interval, the fourth interval, and the fifth interval.

7. The display device of claim 6, wherein, the pixel driving circuit further includes a seventh interval overlapping any of the first interval, the second interval, the third interval, the fourth interval, the fifth interval, and the sixth interval.

8. The display device of claim 7, wherein, the second scan signal has the first voltage level during the seventh interval.

9. The display device of claim 8, wherein, the second scan signal has the first voltage level in the second interval and the seventh interval, and has the second voltage level in the first interval, the third interval, the fourth interval, and the sixth interval.

10. The display device of claim 9, wherein, the seventh interval partially overlaps the fifth interval.

11. The display device according to claim 1, further comprising a plurality of pixel driving circuits included in each of horizontal lines in a horizontal line group, wherein one of the horizontal lines includes the pixel driving circuits to which the second scan signal is applied one or more times during the one frame, and a timing at which the second scan signal is additionally applied corresponds to a timing at which a black data voltage is applied to the pixel driving circuits included in another of the horizontal lines.

12. The display device of claim 1, wherein, the pixel driving circuit further includes a sixth transistor provided between the third node and a black data voltage.

13. The display device of claim 12, wherein, the sixth transistor is connected to the second scan signal line.

14. The display device according to claim 1, further comprising a capacitor formed between the first scan signal line and the third node.

15. The display device of claim 1, wherein, during the one frame period, a timing at which the second scan signal is additionally applied is set between a timing at which the first light emission control signal through the first light emission control line becomes a first voltage level and a timing at which the second light emission control signal through the second light emission control line becomes the first voltage level.

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