Level shifter and display device including the same

Abstract

A display apparatus can include a timing controller, a level shifter including a signal input circuit that receives a first clock signal and a second clock signal, a driving mode conversion circuit that generates one or more mode signals for adjusting a driving mode based on the first clock signal and the second clock signal by itself, a signal output circuit that generates a plurality of scan clock signals based on the one or more mode signals, the first clock signal, and the second clock signal, a shift register configured to generate a scan signal based on the plurality of scan clock signals, and a display panel configured to display an image based on the scan signal. Furthermore, the level shifter is configured to sequentially output a pulse for each of the plurality of scan clock signals in response to a pulse width of the first clock signal being greater than a threshold value.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefit of priority to Korean Patent Application No. 10-2021-0194725, filed in Korea on December 31, 2021, the entire contents of which are expressly incorporated herein by reference. Technical Field

[0003] The present invention relates to a level shifter and a display device including the level shifter. Background Technology

[0004] With the development of information technology, the market for display devices, which serve as a connection medium between users and information, is growing. As a result, display devices such as light-emitting diode (LED) devices, quantum dot (QDD) devices, and liquid crystal display (LCD) devices are being used more and more.

[0005] The aforementioned display device includes a display panel containing sub-pixels, a driver that outputs drive signals for driving the display panel, and a power supply that generates power to provide to the display panel or the driver.

[0006] In the above-described display device, when a driving signal (e.g., a scan signal and a data signal) is provided to a sub-pixel formed in the display panel, the selected sub-pixel transmits light or emits light directly, thereby displaying an image.

[0007] However, as display devices become larger and have higher resolutions, and users expect smaller bezel areas, the number of input terminals and signal lines for various devices (such as level shifters) increases and takes up more space, which limits design freedom and increases manufacturing costs. Summary of the Invention

[0008] The purpose of this invention is to increase the design freedom in manufacturing display devices by reducing the number of input terminals and signal lines required for circuit configuration based on a level shifter, which can internally generate mode signals to automatically switch or adjust the driving mode of the level shifter.

[0009] One aspect of the present invention provides a display device, comprising: a timing controller configured to output a first clock signal and a second clock signal; a level shifter including: a signal input circuit configured to receive the first clock signal and the second clock signal from the timing controller; a drive mode conversion circuit configured to generate one or more mode signals for adjusting a drive mode of the level shifter based on the first clock signal and the second clock signal; a signal output circuit configured to generate a plurality of scan clock signals based on the one or more mode signals, the first clock signal, and the second clock signal; a shift register configured to generate scan signals based on the plurality of scan clock signals output from the level shifter; and a display panel configured to display an image based on the scan signals output from the shift register, wherein the level shifter is configured to sequentially output pulses for each of the plurality of scan clock signals in response to a pulse width of the first clock signal being greater than a threshold.

[0010] According to one aspect of the invention, one or more mode signals are generated not based on any other signal from an external input to the level shifter, but based on a first clock signal and a second clock signal.

[0011] According to another aspect of the invention, multiple scan clock signals are shifted and do not overlap with each other.

[0012] According to one aspect of the invention, the level shifter is configured to output two consecutive pulses for one of a plurality of scan clock signals in response to a pulse width of less than a threshold.

[0013] According to another aspect of the invention, the other scan clock signals among the plurality of scan clock signals that are different from the one scan clock signal among the plurality of scan clock signals do not include any pulses generated between the two consecutive pulses.

[0014] According to one aspect of the invention, a level shifter is configured to perform a muting operation on one of a plurality of scan clock signals in response to the overlap of a pulse of a first clock signal and a pulse of a second clock signal, such that when a pulse of the first clock signal overlaps with a pulse of the second clock signal, no pulse for that one of the plurality of scan clock signals is output.

[0015] According to another aspect of the invention, the level shifter is configured to respond to a pulse of a first clock signal that does not overlap with a pulse of a second clock signal, omitting a muting operation, and outputting a pulse of one of a plurality of scan clock signals that overlaps with both the pulse of the first clock signal and the pulse of the second clock signal.

[0016] According to one aspect of the invention, a level shifter is configured to output a pulse for one of a plurality of scan clock signals, wherein the rising edge of the pulse for the one scan clock signal is based on the rising edge of a first clock signal, and the falling edge of the pulse for the one scan clock signal is based on the rising edge of a second clock signal.

[0017] According to another aspect of the invention, the pulses of the plurality of scan clock signals do not overlap with each other.

[0018] According to one aspect of the invention, the drive mode conversion circuit includes a counter configured to measure the duration of a pulse of a first clock signal, outputting a first mode signal to a signal output circuit in response to the duration being less than a threshold, and the signal output circuit is configured to output two consecutive pulses for one of a plurality of scan clock signals based on the first clock signal and a second clock signal in response to receiving the first mode signal from the drive mode conversion circuit.

[0019] According to another aspect of the invention, the drive mode switching circuit includes an AND gate configured to receive a first clock signal and a second clock signal, and in response to simultaneously receiving a pulse of the first clock signal and a pulse of the second clock signal, output a second mode signal to a signal output circuit. The signal output circuit is configured to perform a mute operation on one of a plurality of scan clock signals in response to receiving the second mode signal from the drive mode switching circuit, such that when the AND gate simultaneously receives a pulse of the first clock signal and a pulse of the second clock signal, it does not output a pulse for that one of the plurality of scan clock signals.

[0020] According to one aspect of the invention, each of the plurality of scan clock signals has a pulse having a gate pulse modulation period at the falling edge of the pulse and including a falling slope, the gate pulse modulation period starting based on the rising edge of a second clock and ending based on the falling edge of the second clock.

[0021] According to another aspect of the invention, the pulse of each of the plurality of scan clock signals is synchronized with the rising edge of the first clock signal and the falling edge of the second clock signal.

[0022] Another aspect of the present invention provides a level shifter, comprising: internal circuitry configured to receive a first clock signal and a second clock signal; sequentially outputting pulses for each of a plurality of scan clock signals in response to a pulse width of the first clock signal being greater than a threshold; outputting two consecutive pulses for one of the plurality of scan clock signals in response to a pulse width of the first clock signal being less than a threshold; and performing a muting operation on the one of the plurality of scan clock signals in response to an overlap between the pulses of the first clock signal and the pulses of the second clock signal, such that when the pulses of the first clock signal overlap with the pulses of the second clock signal, no pulses for the one of the plurality of scan clock signals are output.

[0023] To achieve these and other advantages, and according to the purposes of the invention, as embodied and generally described herein, a display device includes: a timing controller; a level shifter including a drive mode conversion circuit and a signal output circuit, the drive mode conversion circuit being configured to generate a mode signal for switching drive modes based on a first clock signal and a second clock signal output from the timing controller, the signal output circuit being configured to generate and output a plurality of scan clock signals based on the first clock signal, the second clock signal, and the mode signal; a shift register being configured to generate scan signals based on the plurality of scan clock signals output from the level shifter; and a display panel being configured to display an image based on the scan signals output from the shift register, wherein the drive mode conversion circuit controls the generation of high periods of the plurality of scan clock signals based on the first clock signal or the second clock signal.

[0024] The level shifter can control clock shift based on a first clock signal, such that at least one high period or at least two high periods are included in at least one scan clock signal.

[0025] The level shifter can perform clock shifting based on the pulse width of the high period of the first clock signal and an internally determined threshold, such that a high period is included in at least one scan clock signal, or it can not perform clock shifting, such that at least two high periods are included in at least one scan clock signal.

[0026] The level shifter can count the time periods during which the high period of the first clock signal is held, and can perform clock shifting such that if the duration of the high period of the first clock signal is greater than a threshold, a high period is included in at least one scan clock signal, and can also not perform clock shifting such that if the duration of the high period of the first clock signal is less than a threshold, at least two high periods are included in at least one scan clock signal.

[0027] The level shifter can perform control such that, depending on whether the high periods of the first clock signal and the high periods of the second clock signal overlap, a high period of at least one of a plurality of scan clock signals is omitted and not included in at least one of the plurality of scan clock signals.

[0028] The level shifter can perform control such that if the high periods of the first clock signal and the high periods of the second clock overlap, a high period of at least one of the multiple scan clock signals is omitted and not included in at least one of the multiple scan clock signals.

[0029] The drive mode switching circuit includes: a counter configured to generate, based on the result of counting time periods that remain high in a first clock signal, a clock shift for controlling a clock shift such that a high period or at least two high periods are included in at least one scan clock signal; and a first mode signal of an AND gate configured to generate, based on the result of performing an AND operation on the first clock signal and the second clock signal, a second mode signal for controlling the omission of one high period from at least one of the plurality of scan clock signals and preventing the inclusion of that high period in at least one of the plurality of scan clock signals.

[0030] In another aspect of the invention, a level shifter includes: a signal input circuit configured to receive a first clock signal and a second clock signal from an external source; a drive mode conversion circuit configured to generate a mode signal for converting a drive mode based on the first clock signal and the second clock signal transmitted from the signal input circuit; and a signal output circuit configured to generate and output a plurality of scan clock signals based on the first clock signal and the second clock signal transmitted from the signal input circuit and the mode signal output from the drive mode conversion circuit, wherein the mode signal controls the generation of a high period in at least one of the plurality of scan clock signals.

[0031] The drive mode switching circuit may include a counter configured to generate a first mode signal for controlling clock shifting such that a high period or at least two high periods are included in at least one scan clock signal, based on the result of counting the time periods in the first clock signal that remain high.

[0032] The drive mode conversion circuit may include an AND gate configured to generate a second mode signal based on the result of performing an AND operation on a first clock signal and a second clock signal, for controlling the omission of a high period in at least one of a plurality of scan clock signals without including that high period in at least one of the plurality of scan clock signals.

[0033] Based on a level shifter capable of generating mode signals to automatically switch driving modes, this invention reduces the number of input terminals and signal lines required for circuit configuration. Furthermore, this invention reduces the number of input terminals and signal lines of the level shifter, thereby increasing design freedom in the manufacture of display devices. Attached Figure Description

[0034] The invention will be more fully understood from the following detailed description and the accompanying drawings, which are given by way of example only and therefore do not constitute a limitation on the invention.

[0035] Figure 1 This is a block diagram schematically illustrating a light-emitting display device according to an embodiment of the present invention. Figure 2 It is shown schematically. Figure 1 The diagram shows the configuration of sub-pixels according to an embodiment of the present invention.

[0036] Figure 3 and Figure 4 This is a diagram illustrating the configuration of an in-panel gate-type scan driver according to an embodiment of the present invention. Figure 5A and Figure 5B This is a diagram illustrating an example arrangement of an in-panel gate-type scan driver according to an embodiment of the present invention.

[0037] Figure 6 This is a circuit configuration diagram of a level shifter according to an embodiment of the present invention. Figure 7 This is a waveform diagram used to describe the input / output of a level shifter according to an embodiment of the present invention.

[0038] Figure 8 and Figure 9 This is a waveform diagram used to describe the first driving mode of a level shifter according to an embodiment of the present invention. Figure 10 This is a flowchart describing a first driving mode of a level shifter according to an embodiment of the present invention.

[0039] Figure 11 and Figure 12 This is a waveform diagram used to describe the second driving mode of a level shifter according to an embodiment of the present invention. Figure 13 This is a flowchart describing a second driving mode of a level shifter according to an embodiment of the present invention.

[0040] Figure 14 This is a circuit configuration diagram of a level shifter according to another embodiment of the present invention. Figure 15 and Figure 16 It is used to describe Figure 14 The diagram shows the operation of the drive mode switching unit.

[0041] Figure 17 and Figure 18 This is a diagram used to illustrate the advantages of a level shifter according to an embodiment of the present invention. Detailed Implementation

[0042] The display device according to embodiments of the present invention can be implemented as a television set, video player, personal computer (PC), home theater, automotive electronic device, smartphone, etc., but is not limited thereto. The display device according to embodiments of the present invention can be implemented as a light-emitting display (LED) device, a quantum dot display (QDD) device, a liquid crystal display (LCD) device, etc. However, for ease of description, a light-emitting display device based on direct light emission from inorganic or organic light-emitting diodes will be used as an example below.

[0043] Figure 1 This is a schematic block diagram illustrating a light-emitting display device. Figure 2 It is shown schematically. Figure 1 The diagram shows the configuration of the sub-pixels.

[0044] like Figure 1 and Figure 2 As shown, the light-emitting display device includes an image provider 110 (e.g., a host system), a timing controller 120, a scan driver 130 (e.g., a gate driver), a data driver 140, a display panel 150, a power supply 180, etc.

[0045] Image provider (group or host system) 110 can output various drive signals as well as image data signals provided externally or stored in internal memory. Image provider 110 can provide data signals and various drive signals to timing controller 120.

[0046] The timing controller 120 can output a gate timing control signal GDC for controlling the operating timing of the scan driver 130, a data timing control signal DDC for controlling the operating timing of the data driver 140, and various synchronization signals (vertical synchronization signal Vsync and horizontal synchronization signal Hsync). The timing controller 120 can provide the data signal DATA provided by the image provider 110 together with the data timing control signal DDC to the data driver 140. The timing controller 120 can be in the form of an integrated circuit (IC) and mounted on a printed circuit board, but is not limited thereto.

[0047] The scan driver 130 can output a scan signal (or scan voltage) in response to the gate timing control signal GDC provided by the timing controller 120. The scan driver 130 can provide scan signals to the sub-pixels included in the display panel 150 through gate lines GL1 to GLm. Here, m can be a positive number, such as an integer greater than 1. The scan driver 130 can be in the form of an IC or can be directly formed on the display panel 150 as an in-panel gate structure, but is not limited thereto.

[0048] The data driver 140 can sample and latch the data signal DATA in response to the data timing control signal DDC provided by the timing controller 120, convert the digital data signal into an analog data voltage based on the gamma reference voltage, and output the analog data voltage. The data driver 140 can provide data voltage to the sub-pixels included in the display panel 150 through data lines DL1 to DLn. Here, n can be a positive number, such as an integer greater than 1. The data driver 140 can be in the form of an IC and mounted on the display panel 150 or on a printed circuit board, but is not limited thereto.

[0049] Power supply 180 can generate a first voltage at a high level and a second voltage at a low level based on an externally supplied external input voltage, and output the first voltage and the second voltage through a first power line EVDD and a second power line EVSS, respectively. Power supply 180 can generate and output voltages for driving scan driver 130 (e.g., gate voltages including gate high voltage and gate low voltage) and voltages for driving data driver 140 (e.g., drain voltages including drain voltage and half-drain voltage), as well as the first voltage and the second voltage.

[0050] Display panel 150 can display an image in response to a drive signal including a scan signal and a data voltage, a first voltage, and a second voltage. The subpixels of display panel 150 emit light directly, for example, through an organic light-emitting diode (OLED). Display panel 150 can be manufactured based on a substrate having rigidity or flexibility, such as glass, silicon, polyimide, etc. Furthermore, the light-emitting subpixels can include red subpixels, green subpixels, and blue subpixels (e.g., RGB), or include red subpixels, green subpixels, blue subpixels, and white subpixels (e.g., RGBW).

[0051] For example, a sub-pixel SP can be connected to a first data line DL1, a first gate line GL1, a first power line EVDD, and a second power line EVSS, and can include pixel circuitry with switching transistors, driving transistors, capacitors, organic light-emitting diodes (OLEDs), etc. Since the sub-pixel SP used in a light-emitting display device emits light directly, the circuit configuration is complex. Furthermore, various compensation circuits exist to compensate for the degradation of the driving transistors used to provide the driving current required to drive the OLED to emit light, and to compensate for the degradation of the OLED itself. Therefore, the sub-pixel SP is simply shown in block form in the figure.

[0052] Meanwhile, in the above description, the timing controller 120, scan driver 130, data driver 140, etc., are described as separate components. However, depending on the implementation method of the light-emitting display device, one or more of the timing controller 120, scan driver 130, and data driver 140 can be integrated into a single IC.

[0053] Figure 3 and Figure 4 This is a diagram used to describe the configuration of the gate-type scan driver within the panel. Figure 5A and Figure 5B This is a diagram illustrating an example of the arrangement of gate-type scan drivers within a panel.

[0054] like Figure 3 As shown, the in-panel gate-type scan driver 130 may include a shift register 131 and a level shifter 135. The level shifter 135 can generate a drive clock signal Clks and a start signal Vst based on the signals and voltages output by the timing controller 120 and the power supply 180. The drive clock signal Clks can be generated in the form of J different phases (J is an integer greater than or equal to 2, such as 2-phase, 4-phase, or 8-phase).

[0055] The shift register 131 operates based on signals Clks and Vst output from the level shifter 135, and can output scan signals Scan[1] to Scan[m] to turn on or off transistors formed in the display panel (m is a positive integer greater than 1). The shift register 131 can be formed as a thin film on the display panel with an in-panel gate structure.

[0056] like Figure 3 and Figure 4 As shown, unlike shift register 131, level shifter 135 can be independently configured as an IC (e.g., see...). Figure 3 Alternatively, level shifter 135 can be included in power supply 180 (e.g., Figure 4 However, these are merely examples, and the invention is not limited thereto.

[0057] like Figure 5Aand Figure 5B As shown, in the in-panel gate-type scan driver, shift registers 131a and 131b that output scan signals can be located in the non-display area NA of the display panel 150. Shift registers 131a and 131b can be configured as follows: Figure 5A As shown, it can be set in the non-display areas NA on the left and right sides, or as... Figure 5B As shown, it is set in the non-display areas NA on the top and bottom sides. Although Figure 5A and Figure 5B The shift registers 131a and 131b are shown to be located in the non-display area NA, but the invention is not limited thereto.

[0058] Figure 6 This is a circuit configuration diagram of a level shifter according to a first embodiment of the present invention. Figure 7 This is a waveform diagram used to describe the input / output of a level shifter according to a first embodiment of the present invention.

[0059] like Figure 6 As shown, the level shifter 135 according to the first embodiment of the present invention may include a signal input unit (circuit) 132, a drive mode conversion unit (circuit) 133, a signal output unit (circuit) 134, etc.

[0060] The signal input unit 132 can be used to receive a first clock signal Gclk and a second clock signal Mclk from an external source (e.g., a timing controller) via a first input terminal IN1 and a second input terminal IN2, and transmit the received signals to the internal device (e.g., internal circuitry) of the level shifter 135.

[0061] The drive mode conversion unit 133 can be used to generate and output a first mode signal Csp and a second mode signal Mute for converting the drive mode of the level shifter 135 based on the first clock signal Gclk and the second clock signal Mclk output by the signal input unit 132.

[0062] The signal output unit 134 can generate a drive clock signal Clks, such as a scan clock signal, based on the first clock signal Gclk and the second clock signal Mclk output by the signal input unit 132 and the first mode signal Csp and the second mode signal Mute output by the drive mode conversion unit 133, and output the drive clock signal Clks through the first output terminal OUT1 to the Nth output terminal OUTn. Here, n is an integer greater than or equal to 3.

[0063] like Figure 6 and Figure 7As shown, the level shifter 135 according to the first embodiment of the present invention can generate and output a drive clock signal Clks including the first scan clock signal Scclk[1] to the i-th scan clock signal Scclk[i] based on the first clock signal Gclk and the second clock signal Mclk. Here, i is an integer greater than or equal to 3.

[0064] The first clock signal Gclk can be used to control the rising edge of the high period from the first scan clock signal Scclk[1] to the i-th scan clock signal Scclk[i], and the second clock signal Mclk can be used to control the falling edge of the high period from the first scan clock signal Scclk[1] to the i-th scan clock signal Scclk[i].

[0065] The first scan clock signal Scclk[1] to the i-th scan clock signal Scclk[i] can be generated sequentially such that their corresponding high periods do not overlap. The first scan clock signal Scclk[1] to the i-th scan clock signal Scclk[i] can include a gate pulse modulation (GPM) period for modulating the signal waveform after the high period.

[0066] Each of the first scan clock signal Scclk[1] to the i-th scan clock signal Scclk[i] may include a rising edge, a gate pulse modulation period, and a falling edge. The generation process of the rising edge, the gate pulse modulation period, and the falling edge will be described below based on the first scan clock signal Scclk[1].

[0067] The rising edge of the high period in the first scan clock signal Scclk[1] can occur in response to the rising edge CLK Rising of the high period H in the first clock signal Gclk (for example, the rising edge of the first scan clock signal Scclk[1] can be synchronized with the rising edge of the first clock signal Gclk, see Figure 7 The gate pulse modulation period in the first scan clock signal Scclk[1] can begin in response to the rising edge GPM Start of the high period H in the second clock signal Mclk (for example, the start of the falling edge of the first scan clock signal Scclk[1] can be synchronized with the rising edge of the second clock signal Mclk). In the first scan clock signal Scclk[1], the falling edge and end point of the high period of the gate pulse modulation period can occur in response to the falling edge CLK Falling of the high period in the second clock signal Mclk.

[0068] As described above, the level shifter 135 according to the first embodiment of the present invention can change the driving mode so that it can generate the first scan clock signal Scclk[1] to the i-th scan clock signal Scclk[i] in a variable manner, which will be discussed in more detail below.

[0069] Figure 8 and Figure 9 is a waveform diagram for describing the first driving mode of the level shifter according to the first embodiment of the present invention, Figure 10 is a flowchart for describing the first driving mode of the level shifter according to the first embodiment of the present invention. For example, in the first driving mode, based on whether the first mode signal Csp is generated, the level shifter 135 can provide a normal driving operation in which a clock shift is provided and a clock shift prevention operation for preventing the clock shift. In addition, when the pulse width WH of the high period of the first clock signal Gclk is less than the threshold TH (WH < TH), the driving mode conversion unit 133 can generate the first mode signal Csp and output the first mode signal Csp to the signal output unit 134.

[0070] As Figure 8 shown, the level shifter according to the first embodiment of the present invention can generate the high period of the first scan clock signal Scclk[1], and then can generate the high period of the second scan clock signal Scclk[2]. Then, the level shifter can generate the high period of the second scan clock signal Scclk[2], and then can generate the high period of the third scan clock signal Scclk[3]. For example, the level shifter can generate a pulse for the first scan clock signal Scclk[1], and then can generate a pulse for the second scan clock signal Scclk[2] that is shifted in time relative to the pulse of the first scan clock signal Scclk[1], and then can generate a pulse for the third scan clock signal Scclk[3] that is shifted in time relative to the pulse of the second scan clock signal Scclk[2]. As Figure 8 shown, the pulses of the first scan clock signal Scclk[1], the second scan clock signal Scclk[2], and the third scan clock signal Scclk[3] can be shifted in time so that they do not overlap each other.

[0071] In addition, as Figure 9 shown, the level shifter according to the first embodiment of the present invention can generate the high period of the first scan clock signal Scclk[1], and then can generate another high period of the first scan clock signal Scclk[1] (for example, two pulses for the first scan clock signal Scclk[1] can be generated closely and continuously before generating the pulse of the second scan clock signal Scclk[2]). Then, the level shifter can generate the high period of the second scan clock signal Scclk[2].

[0072] Referring to Figure 8 and Figure 9It can be seen that the level shifter according to the first embodiment of the present invention can output the first scan clock signals Scclk[1] to the i-th scan clock signal Scclk[i] including one or two high periods. For example, based on the pulse width of the first clock signal Gclk, the level shifter can sequentially generate pulses for each of the first scan clock signals Scclk[1] to the i-th scan clock signal Scclk[i], and one pulse is generated each time for each of the first scan clock signals Scclk[1] to the i-th scan clock signal Scclk[i] (e.g., Figure 8 ), or before generating a pulse for another one of the first scan clock signals Scclk[1] to the i-th scan clock signal Scclk[i], the level shifter can closely and continuously generate two pulses for one of the first scan clock signals Scclk[1] to the i-th scan clock signal Scclk[i] (e.g., Figure 9 ).

[0073] The level shifter according to the first embodiment of the present invention can perform clock shifting on the first scan clock signals Scclk[1] to the i-th scan clock signal Scclk[i] based on the pulse width WH of the high period of the first clock signal Gclk and a set threshold TH therein, or not perform clock shifting.

[0074] When clock shifting is performed, after the high-period pulse of another previous scan clock signal, a high-period pulse for the next scan clock signal is generated (e.g., see Figure 8 , the first scan clock signal Scclk[1] has a high-period pulse, and the second scan clock signal Scclk[2] has a high-period pulse). On the other hand, if clock shifting is not performed, the first scan clock signal can include at least two closely and continuously generated high periods because the high period is not passed to the next generated scan clock signal.

[0075] For this purpose, the level shifter can detect the pulse width WH of the high period of the first clock signal Gclk by counting or measuring the time period during which the high period H is maintained in the first clock signal Gclk. In addition, the level shifter can compare the detected pulse width WH of the high period of the first clock signal Gclk with the threshold TH. If the detected pulse width WH of the high period of the first clock signal Gclk is greater than the threshold TH (e.g., WH>TH), clock shifting can be performed so that one high period is included in the next scan clock signal, as shown in Figure 8 . However, if the detected pulse width WH of the high period of the first clock signal Gclk is less than the threshold TH (e.g., WH<TH), clock shifting is not performed so that in the current scan clock signal (e.g., see Figure 9The Scclk[1] in [ ] includes at least two high periods that are closely consecutive.

[0076] As Figure 10 shown, the level shifter according to the first embodiment of the present invention can generate and output a plurality of scan clock signals through the rising edge generation step (S110) to the falling edge generation step (S190). This will be described below.

[0077] The level shifter can generate the rising edge (Scclk rising edge) of the high period of the scan clock signal in response to the rising edge of the first clock signal Gclk (Gclk rising edge) (S110). The level shifter can detect the pulse width of the high period of the first clock signal Gclk (Gclk pulse width) to determine whether to perform clock shifting for the first scan clock signal Scclk[1] to the i-th scan clock signal Scclk[i] (S140). The step of detecting the pulse width of the high period of the first clock signal Gclk (Gclk pulse width) can be defined as the step of checking whether the level shifter is operating in the first driving mode (CSP Check).

[0078] The level shifter can compare the pulse width WH of the high period of the first clock signal Gclk with the threshold TH (S150). When the pulse width WH of the high period of the first clock signal Gclk is greater than the threshold TH (WH < TH = N), the level shifter can be normally driven and clock shifting for the first scan clock signal Scclk[1] to the i-th scan clock signal Scclk[i] can be provided. In this case, the level shifter can perform clock shifting (CLK shift) such that the scan clock signal includes one high period and then is sequentially generated in the next clock signal, as Figure 8 shown.

[0079] On the other hand, if the pulse width WH of the high period of the first clock signal Gclk is less than the threshold TH (WH < TH = Y), the level shifter can generate the first mode signal Csp to operate in the first driving mode. In this case, the level shifter can not perform clock shifting (No CLK Shift) such that the scan clock signal includes two closely consecutive high periods, as Figure 9 shown. Therefore, the level shifter can cancel or prevent clock shifting for the next clock signal and generate two consecutive pulses in the same scan clock signal (Clk Shift Cancel, Scclk Rising) (S160).

[0080] The level shifter can initiate the gate pulse modulation period (generating Scclk GPM) of the high-segment of the scan clock signal in response to the rising edge of the second clock signal Mclk (Mclk rising edge) (S170). The level shifter can maintain the gate pulse modulation period (Scclk GPM) of the scan clock signal in response to the pulse width of the high-segment of the second clock signal (Mclk pulse width) (S180). For example, the period for initiating gate pulse modulation of the high-segment of the scan clock signal can be set to be equal to or approximately equal to the pulse width of the second clock signal Mclk (e.g., the gate pulse modulation period can be synchronized with the rising and falling edges of the second clock signal Mclk).

[0081] The level shifter can respond to the falling edge of the second clock signal (Mclk falling edge) to end the high period of the scan clock signal and the gate pulse modulation period, and generate the low period of the scan clock signal (generating ScclkFalling) (S190).

[0082] Figure 11 and Figure 12 This is a waveform diagram used to describe the second driving mode of the level shifter according to the first embodiment of the present invention. Figure 13 This is a flowchart describing a second driving mode of a level shifter according to a first embodiment of the present invention. The second driving mode can provide a Mute off operation that generates normal pulses for a clock signal and a Mute on operation that does not generate pulses for a clock signal and the clock signal is "silenced".

[0083] like Figure 11 As shown, the level shifter according to the first embodiment of the present invention can generate a high period of a first scan clock signal Scclk[1], then generate a high period of a second scan clock signal Scclk[2], and then generate a high period of a third scan clock signal Scclk[3].

[0084] Furthermore, according to the first embodiment of the present invention, the level shifter can omit the high period, so that the high period is not included in the first scan clock signal Scclk[1], and then the high period of the second scan clock signal Scclk[2] can be generated, such as Figure 12 As shown (for example, a scan clock signal can be selected as "silent" or "still" and kept in a low state). Then, a level shifter can generate the high period of a third scan clock signal Scclk[3].

[0085] Reference Figure 11 and Figure 12It is understood that the level shifter according to the first embodiment of the present invention can output the first scan clock signal Scclk[1] to the i-th scan clock signal Scclk[i], but the generation of the high period is omitted in at least one of the first scan clock signal to the i-th scan clock signal (e.g., "silence" a scan clock signal).

[0086] The level shifter according to the first embodiment of the present invention can perform clock mute based on the high period H of the first clock signal Gclk and the high period of the second clock signal Mclk to omit the high period included in the first scan clock signal Scclk[1] to the i-th scan clock signal Scclk[i]. In other words, when both the first clock signal Gclk and the second clock signal Mclk are high, the function of the rising edge of the first clock signal Gclk is masked, and a clock signal pulse can be muted or prevented from being generated.

[0087] Therefore, the level shifter can detect the first clock signal Gclk and the second clock signal Mclk. Furthermore, the level shifter can determine whether the high-frequency period of the second clock signal Mclk overlaps with the high-frequency period of the first clock signal Gclk. If the high-frequency period H of the first clock signal Gclk does not overlap with the high-frequency period of the second clock signal Mclk, the clock shift can be performed normally, ensuring that a high-frequency period is included in the current scan clock signal, such as... Figure 11 As shown. However, if the high period H of the first clock signal Gclk overlaps with the high period of the second clock signal Mclk (e.g., the first clock signal Gclk and the second clock signal Mclk are both high), clock silencing can be performed, such that the current scan clock signal (e.g., see...) Figure 12 The high time period is not included in the Scclk[1] shown.

[0088] like Figure 13 As shown, the level shifter according to the first embodiment of the present invention can generate and output multiple scan clock signals through rising edge generation step S110 to falling edge generation step S190. This will be described below.

[0089] The level shifter can generate a rising edge of the high period of the scan clock signal (Scclk rising edge) in response to a rising edge of the first clock signal Gclk (Gclk rising edge) (S110). The level shifter can determine whether the high period of the second clock signal Mclk overlaps with the high period of the first clock signal Gclk to determine whether to perform clock silence (S120). The step of detecting whether the high period of the second clock signal Mclk appears when the first clock signal Gclk has a high period can be defined as the step of checking whether the level shifter is operating in the second drive mode (Mclk Check).

[0090] If the high period of the first clock signal Gclk does not overlap with the high period of the second clock signal Mclk (N: Mclk->L), the level shifter determines whether to perform clock shifting (S140). If the high period of the first clock signal Gclk and the high period of the second clock signal Mclk overlap (Y: Mclk->H), the level shifter can perform clock silence to cancel the rising edge of the scan clock signal so that the high period is not included in the current scan clock signal (e.g., Scclk[1]) (S130), as Figure 12 shown. For example, the level shifter can first determine whether a clock silence operation should be performed, and then the level shifter can determine whether to perform a normal clock shifting operation. Alternatively, these operations can be performed in parallel or in a different order. For example, Figure 13 The flowchart of Figure 10 is similar to the flowchart of

[0091] ]>The level shifter can detect the pulse width of the high period of the first clock signal Gclk (Gclk pulse width) to determine whether to perform clock shifting (S140). The step of detecting the pulse width of the high period of the first clock signal Gclk (Gclk pulse width) can be defined as the step of checking whether the level shifter is operating in the first drive mode (CSP Check).

[0092] The level shifter can compare the pulse width WH of the high period of the first clock signal Gclk with a threshold TH (S150). When the pulse width WH of the high period of the first clock signal Gclk is greater than the threshold TH (WH < TH = N), the level shifter can be normally driven. In this case, the level shifter can perform clock shifting so that a high period is included in the scan clock signal, as Figure 8 shown.

[0093] On the other hand, if the pulse width WH of the high period of the first clock signal Gclk is less than the threshold TH (WH < TH = Y), the level shifter can generate the first mode signal Csp not to perform the clock shift function in the first driving mode. In this case, the level shifter can not perform clock shift (No CLK Shift), such that two high periods are included in the scan clock signal, as Figure 9 shown. Therefore, the level shifter can cancel the clock shift and generate the rising edge of the scan clock signal (S160). For example, in the first driving mode, based on whether the first mode signal Csp is generated, the level shifter 135 can provide the normal driving operation with clock shift provided and the clock shift prevention operation to prevent clock shift. In addition, when the pulse width WH of the high period of the first clock signal Gclk is less than the threshold TH (WH < TH), the driving mode conversion unit 133 generates the first mode signal Csp and outputs the first mode signal Csp to the signal output unit 134. The level shifter can start the gate pulse modulation period (generate Scclk GPM) of the high period of the scan clock signal in response to the rising edge of the second clock signal (Mclk rising edge) (S170). The level shifter can maintain the gate pulse modulation period of the scan clock signal in response to the pulse width of the high period of the second clock signal (Mclk pulse width) (S180).

[0094] The level shifter can end the high period and the gate pulse modulation period of the scan clock signal in response to the falling edge of the second clock signal (Mclk falling edge) and generate the low period of the scan clock signal (S190).

[0095] Figure 14 is a circuit configuration diagram of the level shifter according to the second embodiment of the present invention, Figure 15 and Figure 16 is a diagram for describing Figure 14 the operation of the driving mode conversion unit shown.

[0096] As Figure 14 shown, the level shifter 135 according to the second embodiment of the present invention can include a signal input unit 132, a driving mode conversion unit 133, a signal output unit 134, etc. The level shifter 135 according to the second embodiment is different from the level shifter of the first embodiment in terms of the configuration and operation mode of the driving mode conversion unit 133, so the differences will be mainly described.

[0097] The drive mode conversion unit 133 may include a counter CNT and an AND gate to output a mode signal for converting or adjusting the drive mode of the level shifter. The counter CNT can be used to output a first mode signal Csp associated with a first drive mode of the level shifter 135. The AND gate can be used to output a second mode signal Mute associated with a second drive mode of the level shifter 135.

[0098] like Figure 14 and Figure 15 As shown, the counter CNT can count the time periods H in the first clock signal Gclk that remain high to detect the pulse width WH of the first clock signal Gclk. The counter CNT can then compare the detected pulse width WH of the first clock signal Gclk with a defined threshold TH.

[0099] If the pulse width WH of the first clock signal Gclk is greater than an internally determined threshold TH (e.g., 200 ns), the counter CNT can output a first mode off signal Csp_off Operation to perform a clock shift, such that a high period is included in the next scan clock signal (e.g., see...). Figure 8 ).

[0100] If the pulse width WH of the first clock signal Gclk is less than an internally determined threshold TH (e.g., 200 ns), the counter CNT can output a first mode enable signal Csp_on Operation that does not perform clock shifting, such that at least two high periods are included in the current scan clock signal (e.g., see...). Figure 9 ).

[0101] like Figure 14 and Figure 16 As shown, the AND gate can perform a logical AND operation on the first clock signal Gclk and the second clock signal Mclk to output a logic low signal L or a logic high signal H.

[0102] When the high period H of the first clock signal Gclk does not overlap with the high period of the second clock signal Mclk, the AND gate can output a logic low signal L as the second mode off signal CLK Mute Off (for example, one of the first clock signal Gclk and the second clock signal Mclk can be high and the other can be low).

[0103] However, when the high periods H of the first clock signal Gclk and the high periods of the second clock signal Mclk overlap, the AND gate can output a logic high signal H as a second mode enable signal CLK Mute on for performing clock silencing (e.g., both the first clock signal Gclk and the second clock signal Mclk are high at the same time).

[0104] Figure 17 and Figure 18 This is a diagram used to illustrate the advantages of a level shifter according to an embodiment of the present invention.

[0105] Figure 17 The level shifter 135 shown according to an embodiment of the present invention can selectively perform at least one of a clock shift operation and a clock silence operation based solely on a first clock signal Gclk and a second clock signal Mclk, as described in the first and second embodiments above.

[0106] On the other hand, according to Figure 18 The level shifter 135 of the comparative example shown can selectively perform at least one of clock shift and clock silencing only when an additional signal Csp is received through the third input terminal IN3.

[0107] Therefore, since the level shifter 135 according to an embodiment of the present invention can generate a mode signal capable of switching drive modes on its own (e.g., the mode signal can be generated internally within the level shifter without the need for additional input), the number of input terminals and signal lines for receiving additional signals from the timing controller can be reduced.

[0108] As described above, based on a level shifter capable of generating its own mode signal to automatically switch driving modes, this invention reduces the number of input terminals and signal lines required for circuit configuration. Furthermore, this invention reduces the number of input terminals and signal lines of the level shifter, thereby increasing design freedom in the manufacture of display devices (improving PCB layout efficiency or IC packaging efficiency).

[0109] As described above, the invention can obviously be modified in many ways. Such modifications should not be considered as departing from the spirit and scope of the invention, and it will be apparent to those skilled in the art that all such modifications are intended to be included within the scope of the following claims.

Claims

1. A display device, comprising: A timing controller configured to output a first clock signal and a second clock signal; A level shifter, the level shifter comprising: A signal input circuit configured to receive the first clock signal and the second clock signal from the timing controller; A drive mode conversion circuit, configured to generate one or more mode signals based on the first clock signal and the second clock signal for adjusting the drive mode of the level shifter; and A signal output circuit configured to generate a plurality of scan clock signals based on the one or more mode signals, the first clock signal, and the second clock signal; A shift register configured to generate a scan signal based on the plurality of scan clock signals output from the level shifter; and A display panel configured to display an image based on a scan signal output from the shift register. The level shifter is configured as follows: In response to the pulse width of the first clock signal being greater than a threshold, pulses for each of the plurality of scan clock signals are sequentially output. The level shifter is configured as follows: In response to the pulse width of the first clock signal being less than the threshold, two consecutive pulses are output for one of the plurality of scan clock signals.

2. The display device according to claim 1, wherein, The one or more mode signals are not generated based on any other signals input from the outside to the level shifter, but are generated based on the first clock signal and the second clock signal.

3. The display device according to claim 1, wherein, The multiple scan clock signals are shifted and do not overlap with each other.

4. The display device according to claim 1, wherein, The other scan clock signals among the plurality of scan clock signals, which are different from the one scan clock signal, do not include any pulses generated between the two consecutive pulses.

5. The display device according to claim 1, wherein, The level shifter is configured as follows: In response to the overlap of the pulse of the first clock signal and the pulse of the second clock signal, a muting operation is performed on one of the plurality of scan clock signals, such that when the pulse of the first clock signal overlaps with the pulse of the second clock signal, no pulse is output for the one of the plurality of scan clock signals.

6. The display device according to claim 5, wherein, The level shifter is configured as follows: In response to the pulse of the first clock signal not overlapping with the pulse of the second clock signal, the silence operation is omitted, and a pulse for one of the plurality of scan clock signals that overlaps with both the pulse of the first clock signal and the pulse of the second clock signal is output.

7. The display device according to claim 1, wherein, The level shifter is configured as follows: Output a pulse for one of the plurality of scan clock signals. Wherein, the rising edge of the pulse for one of the plurality of scan clock signals is based on the rising edge of the first clock signal. The falling edge of the pulse for one of the plurality of scan clock signals is based on the rising edge of the second clock signal.

8. The display device according to claim 1, wherein, The pulses of the multiple scan clock signals do not overlap with each other.

9. The display device according to claim 1, wherein, The drive mode switching circuit includes a counter, which is configured to: Measure the duration of the pulses of the first clock signal. In response to the time period being less than a threshold, a first mode signal is output to the signal output circuit. The signal output circuit is configured as follows: In response to receiving the first mode signal from the drive mode conversion circuit, two consecutive pulses are output for one of the plurality of scan clock signals based on the first clock signal and the second clock signal.

10. The display device according to claim 1, wherein, The drive mode conversion circuit includes an AND gate, which is configured to: Receive the first clock signal and the second clock signal. In response to simultaneously receiving pulses from the first clock signal and the second clock signal, a second mode signal is output to the signal output circuit. The signal output circuit is configured as follows: In response to receiving the second mode signal from the drive mode conversion circuit, a mute operation is performed on one of the plurality of scan clock signals, such that when the logic AND gate simultaneously receives the pulse of the first clock signal and the pulse of the second clock signal, no pulse for the one of the plurality of scan clock signals is output.

11. The display device according to claim 1, wherein, Each of the plurality of scan clock signals has a pulse with a gate pulse modulation period at the falling edge of the pulse and including a falling slope. The gate pulse modulation period begins based on the rising edge of the second clock. The gate pulse modulation period ends based on the falling edge of the second clock.

12. The display device according to claim 1, wherein, The pulse of each of the plurality of scan clock signals is synchronized with the rising edge of the first clock signal and the falling edge of the second clock signal.

13. A level shifter, comprising: Internal circuitry, the internal circuitry being configured as follows: Receive the first clock signal and the second clock signal. In response to the pulse width of the first clock signal being greater than a threshold, pulses for each of the multiple scan clock signals are sequentially output. In response to the pulse width of the first clock signal being less than a threshold, two consecutive pulses are output for one of the plurality of scan clock signals. In response to the overlap of the pulse of the first clock signal and the pulse of the second clock signal, a muting operation is performed on the one of the plurality of scan clock signals, such that when the pulse of the first clock signal overlaps with the pulse of the second clock signal, no pulse for the one of the plurality of scan clock signals is output.

14. The level shifter according to claim 13, wherein, The multiple scan clock signals are shifted and do not overlap with each other.

15. The level shifter of claim 13, wherein the other scan clock signals among the plurality of scan clock signals that are different from the one scan clock signal among the plurality of scan clock signals do not include any pulses generated between the two consecutive pulses.

16. The level shifter according to claim 13, wherein, The level shifter is configured as follows: In response to the pulse of the first clock signal not overlapping with the pulse of the second clock signal, the silence operation is omitted, and a pulse for one of the plurality of scan clock signals that overlaps with both the pulse of the first clock signal and the pulse of the second clock signal is output.

17. The level shifter according to claim 13, wherein, The level shifter is configured as follows: Output a pulse for one of the plurality of scan clock signals. Wherein, the rising edge of the pulse for one of the plurality of scan clock signals is based on the rising edge of the first clock signal. The falling edge of the pulse for one of the plurality of scan clock signals is based on the rising edge of the second clock signal.

18. The level shifter according to claim 13, wherein, The pulse of each of the plurality of scan clock signals is synchronized with the rising edge of the first clock signal and the falling edge of the second clock signal.

19. The level shifter according to claim 13, wherein, The pulses of the first clock signal do not overlap with the pulses of the second clock signal.

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