Pixel circuit and display panel

Abstract

This invention provides a pixel circuit and a display panel. The pixel circuit includes a power supply module, which provides a first power supply voltage to the power supply voltage terminal at least during the data writing phase, and provides a second power supply voltage to the power supply voltage terminal after the data writing phase, wherein the first power supply voltage is lower than the second power supply voltage. The technical solution provided by this invention ensures normal data voltage transmission to the gate of the driving transistor by providing a lower first power supply voltage during the data writing phase; and by providing a higher second power supply voltage after the data writing phase, the voltage at the gate of the driving transistor can be increased through the coupling effect of a first capacitor, thereby better turning off the driving transistor. This eliminates the need for peripheral circuits to provide a higher data voltage, avoiding excessive power consumption in the peripheral circuits.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more specifically, to a pixel circuit and a display panel. Background Technology

[0002] Existing display devices typically include peripheral circuitry in their bezel area and multiple pixel units in their display area. Each pixel unit includes a pixel circuit and a light-emitting element electrically connected to the pixel circuit. The pixel circuit is electrically connected to the peripheral circuitry in the bezel area. The peripheral circuitry provides the pixel circuit with reset voltage, data voltage, scan control signals, and light-emitting control signals to control the pixel circuit to provide driving current to the light-emitting element. Before generating the driving current, the existing pixel circuit requires a relatively large data voltage to better control the light-emitting element to reach a black state, resulting in increased power consumption in the peripheral circuitry. Summary of the Invention

[0003] In view of this, the present invention provides a pixel circuit and a display panel that effectively solves the existing technical problems. The pixel circuit can better turn off the driving transistors and does not require the peripheral circuit to provide a high data voltage, thus avoiding excessive power consumption of the peripheral circuit.

[0004] To achieve the above objectives, the technical solution provided by the present invention is as follows:

[0005] A pixel circuit, comprising:

[0006] A driving transistor, the driving transistor being used to generate a driving current;

[0007] The data writing module has a data voltage connected to its input terminal, an output terminal electrically connected to the first terminal of the driving transistor, and a data control signal connected to its control terminal.

[0008] A connection module, wherein the input terminal of the connection module is electrically connected to the second terminal of the driving transistor, the output terminal of the connection module is electrically connected to the gate of the driving transistor, and the control terminal of the connection module is connected to a connection control signal, wherein the data control signal and the connection control signal are enabled during the data writing phase;

[0009] A first capacitor, wherein the first plate of the first capacitor is electrically connected to the gate of the driving transistor, and the second plate of the first capacitor is electrically connected to the power supply voltage terminal.

[0010] A power supply module is configured to provide a first power supply voltage to the power supply voltage terminal at least during the data writing phase, and to provide a second power supply voltage to the power supply voltage terminal after the data writing phase, wherein the first power supply voltage is less than the second power supply voltage.

[0011] Accordingly, the present invention also provides a display panel, the display panel including the pixel circuit described above.

[0012] Compared with the prior art, the technical solution provided by the present invention has at least the following advantages:

[0013] The present invention provides a pixel circuit and a display panel. The pixel circuit includes a power supply module, which is used to provide a first power supply voltage to the power supply voltage terminal at least during the data writing phase, and to provide a second power supply voltage to the power supply voltage terminal after the data writing phase, wherein the first power supply voltage is less than the second power supply voltage.

[0014] As can be seen from the above, the technical solution provided by the present invention provides a lower first power supply voltage to the power supply voltage terminal during the data writing stage, which can ensure that the data voltage is transmitted normally to the gate of the driving transistor; and provides a higher second power supply voltage to the power supply voltage terminal after the data writing stage, which can increase the voltage at the gate of the driving transistor through the coupling effect of the first capacitor, so as to better turn off the driving transistor. Thus, there is no need for the peripheral circuit to provide a higher data voltage, avoiding excessive power consumption of the peripheral circuit. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0016] Figure 1 This is a schematic diagram of a pixel circuit provided in an embodiment of the present invention;

[0017] Figure 2 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention;

[0018] Figure 3 This is a schematic diagram of another pixel circuit provided in an embodiment of the present invention;

[0019] Figure 4 This is a schematic diagram of another pixel circuit provided in an embodiment of the present invention;

[0020] Figure 5 This is a schematic diagram of another pixel circuit provided in an embodiment of the present invention;

[0021] Figure 6This is a schematic diagram of another pixel circuit provided in an embodiment of the present invention;

[0022] Figure 7 This is a schematic diagram of another pixel circuit provided in an embodiment of the present invention;

[0023] Figure 8 This is a schematic diagram of another pixel circuit provided in an embodiment of the present invention;

[0024] Figure 9 This is a schematic diagram of another pixel circuit provided in an embodiment of the present invention;

[0025] Figure 10 A timing diagram provided for an embodiment of the present invention;

[0026] Figure 11 Another timing diagram provided for an embodiment of the present invention;

[0027] Figure 12 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention;

[0028] Figure 13 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention;

[0029] Figure 14 This is a schematic diagram of another display panel provided in an embodiment of the present invention. Detailed Implementation

[0030] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0031] As described in the background section, the pixel circuit is electrically connected to the peripheral circuitry in the bezel area. The peripheral circuitry provides the pixel circuit with reset voltage, data voltage, scan control signals, and light emission control signals to control the pixel circuit to provide driving current to the light-emitting element. In existing pixel circuits, before generating the driving current, a relatively large data voltage is required to better control the light-emitting element to reach a black state, resulting in increased power consumption in the peripheral circuitry.

[0032] Based on this, the present invention provides a pixel circuit and a display panel, which effectively solves the existing technical problems. The pixel circuit can better turn off the driving transistors and does not require the peripheral circuit to provide a high data voltage, thus avoiding excessive power consumption of the peripheral circuit.

[0033] To achieve the above objectives, the technical solutions provided by the embodiments of the present invention are as follows, in detail... Figures 1 to 14 The technical solutions provided in the embodiments of the present invention will be described in detail.

[0034] refer to Figure 1 The diagram shown is a schematic representation of a pixel circuit according to an embodiment of the present invention. The pixel circuit includes:

[0035] A driving transistor M0 is used to generate a driving current, which is transmitted to a light-emitting element (not shown), and the light-emitting element emits light in response to the driving current. The light-emitting element provided in this embodiment can be a light-emitting diode, and this invention does not impose specific limitations on it.

[0036] The data writing module 100 has a data voltage Vdata connected to its input terminal, an output terminal electrically connected to the first terminal of the driving transistor M0, and a data control signal Sd connected to its control terminal.

[0037] A connection module 200 is provided, wherein the input terminal of the connection module 200 is electrically connected to the second terminal of the driving transistor M0, the output terminal of the connection module 200 is electrically connected to the gate of the driving transistor M0, and the control terminal of the connection module 200 is connected to a connection control signal Sj. The data control signal Sd and the connection control signal Sj are enabled during the data writing phase.

[0038] The first capacitor C1 has its first plate electrically connected to the gate of the driving transistor M0, and its second plate electrically connected to the power supply voltage terminal Vpvdd.

[0039] A power supply module 300 is configured to provide a first power supply voltage Vg1 to the power supply voltage terminal Vpvdd at least during the data writing phase, and to provide a second power supply voltage Vg2 to the power supply voltage terminal Vpvdd after the data writing phase, wherein the first power supply voltage Vg1 is less than the second power supply voltage Vg2.

[0040] Understandably, the technical solution provided by the embodiments of the present invention provides a lower first power supply voltage to the power supply voltage terminal during the data writing stage, which can ensure that the data voltage is transmitted normally to the gate of the driving transistor; and provides a higher second power supply voltage to the power supply voltage terminal after the data writing stage, which can increase the voltage at the gate of the driving transistor through the coupling effect of the first capacitor, so as to better turn off the driving transistor. Thus, there is no need for the peripheral circuit to provide a higher data voltage, avoiding excessive power consumption of the peripheral circuit.

[0041] It should be noted that the driving transistor provided by this invention is a P-type transistor. Therefore, after the data writing stage, the voltage at the gate of the driving transistor is increased through the coupling effect of the first capacitor, thereby better turning off the driving transistor. This eliminates the need for peripheral circuits to provide a high data voltage, avoiding excessive power consumption in the peripheral circuits. Furthermore, the peripheral circuit provided by this invention includes a driving chip, and the data voltage can be provided by the driving chip. The display panel uses the pixel circuit provided in this embodiment of the invention, which can effectively reduce the power consumption of the driving chip.

[0042] In one embodiment of the present invention, the power supply voltage module provided by the present invention provides a first power supply voltage to the power supply voltage terminal at least during the data writing phase of the pixel circuit. Specifically, the power supply voltage module may start providing the first power supply voltage to the power supply voltage terminal before the data writing phase; or, the power supply voltage module may start providing the first power supply voltage to the power supply voltage terminal at the initial moment when the pixel circuit enters the data writing phase. Furthermore, the power supply voltage module provides a second power supply voltage to the power supply voltage terminal after the data writing phase, specifically, the power supply voltage module may provide the second power supply voltage to the power supply voltage terminal after the pixel circuit completes the data writing phase and before the pixel circuit enters the light emission control phase, so as to better achieve the purpose of controlling the drive transistor to turn off after the pixel circuit completes the data writing phase.

[0043] To enable the power supply voltage module to switch between outputting a first power supply voltage and a second power supply voltage to the power supply voltage terminal, the power supply voltage module provided in the embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. (Refer to...) Figure 2 The diagram shown is a structural schematic of another pixel circuit provided in an embodiment of the present invention. The power supply module 300 provided in this embodiment of the present invention includes a low-voltage submodule 310 and a high-voltage submodule 320.

[0044] The input terminal of the low-voltage submodule 310 is connected to the first power supply voltage Vg1, and the output terminal of the low-voltage submodule 310 is electrically connected to the power supply voltage terminal Vpvdd. The control terminal of the low-voltage submodule is connected to the low-voltage control signal Sgl. The input terminal of the high-voltage submodule 320 is connected to the second power supply voltage Vg2, and the output terminal of the high-voltage submodule 320 is electrically connected to the power supply voltage terminal Vpvdd. The control terminal of the high-voltage submodule 320 is connected to the high-voltage control signal Sgh.

[0045] Understandably, the power supply module provided in this embodiment of the invention has two sub-modules: a low-voltage sub-module and a high-voltage sub-module. The low-voltage sub-module provides a lower first power supply voltage to the power supply terminal through the enable control of a low-voltage control signal, and the high-voltage sub-module provides a higher second power supply voltage to the power supply terminal through the enable control of a high-voltage control signal. The low-voltage sub-module provided in this embodiment of the invention can be a synchronous control module, meaning the enable duration of the low-voltage control signal is synchronously the same as the output duration of the first power supply voltage; or, the low-voltage sub-module can be a trigger control module, meaning the enable of the low-voltage control signal is a trigger signal. After the low-voltage control signal enables the low-voltage sub-module to start outputting the first power supply voltage, it switches to non-enabled mode, while the low-voltage sub-module continues to output the first power supply voltage until the high-voltage control signal controls the high-voltage sub-module to output the second power supply voltage.

[0046] Similarly, the high-voltage submodule provided in this embodiment of the invention can be a synchronous control module, that is, the enable duration of the high-voltage control signal is synchronous with the output duration of the second power supply voltage; or, the high-voltage submodule can be a trigger control module, that is, the enable of the high-voltage control signal is a trigger signal, the high-voltage control signal enables the high-voltage submodule to start outputting the second power supply voltage and then switches to non-enabled, while the high-voltage submodule continues to output the second power supply voltage until the low-voltage control signal controls the low-voltage submodule to output the first power supply voltage.

[0047] refer to Figure 3 The diagram shows a schematic of another pixel circuit provided in an embodiment of the present invention. The low-voltage submodule 310 provided in this embodiment includes a low-voltage input circuit 311 and a low-voltage latch output circuit 312. The input terminal of the low-voltage input circuit 311 is connected to an enable voltage Vk, and the output terminal of the low-voltage input circuit 311 is electrically connected to the latch control terminal of the low-voltage latch output circuit 312. The control terminal of the low-voltage input circuit 311 is connected to the low-voltage control signal Sgl. The input terminal of the low-voltage latch output circuit 312 is connected to the first power supply voltage Vg1, and the output terminal of the low-voltage latch output circuit 312 is electrically connected to the power supply voltage terminal Vpvdd.

[0048] Furthermore, the high-voltage submodule 320 provided in this embodiment of the invention includes a high-voltage input circuit 321 and a high-voltage latch output circuit 322. The input terminal of the high-voltage input circuit 321 is connected to the turn-on voltage Vk, and the output terminal of the high-voltage input circuit 321 is electrically connected to the latch control terminal of the high-voltage latch output circuit 322. The control terminal of the high-voltage input circuit 321 is connected to the high-voltage control signal Sgh. The input terminal of the high-voltage latch output circuit 322 is connected to the second power supply voltage Vg2, and the output terminal of the high-voltage latch output circuit 322 is electrically connected to the power supply voltage terminal Vpvdd.

[0049] As can be understood, in the low-voltage submodule provided in this embodiment of the invention, the control terminal of the low-voltage input circuit receives a low-voltage control signal, and then, based on the enable of the low-voltage control signal, transmits the turn-on voltage to the latch control terminal of the low-voltage latch output circuit; the turn-on voltage is latched by the low-voltage latch output circuit, and the turn-on voltage controls the low-voltage latch output circuit to transmit the first power supply voltage to the power supply voltage terminal. Similarly, in the high-voltage submodule, the control terminal of the high-voltage input circuit receives a high-voltage control signal, and then, based on the enable of the high-voltage control signal, transmits the turn-on voltage to the latch control terminal of the high-voltage latch output circuit; the turn-on voltage is latched by the high-voltage latch output circuit, and the turn-on voltage controls the high-voltage latch output circuit to transmit the second power supply voltage to the power supply voltage terminal.

[0050] Furthermore, to avoid crosstalk between the first and second power supply voltages at the power supply voltage terminal, the power supply module provided in this embodiment of the invention can also be equipped with a shutdown circuit to turn off the high-voltage submodule when the low-voltage submodule outputs the first power supply voltage to the power supply voltage terminal, and to turn off the low-voltage submodule when the high-voltage submodule outputs the second power supply voltage to the power supply voltage terminal. See details. Figure 4 The diagram shown is a structural schematic of another pixel circuit provided in an embodiment of the present invention. The low-voltage submodule 310 provided in this embodiment of the present invention further includes a low-voltage shutdown circuit 313, and / or the high-voltage submodule 320 further includes a high-voltage shutdown circuit 323.

[0051] The control terminal of the low-voltage shutdown circuit 313 is electrically connected to the output terminal of the low-voltage input circuit 311. The input terminal of the low-voltage shutdown circuit 313 is connected to the shutdown voltage Vo. The output terminal of the low-voltage shutdown circuit 313 is electrically connected to the latch control terminal of the high-voltage latch output circuit 322. The control terminal of the high-voltage shutdown circuit 323 is connected to the high-voltage control signal Sgh. The input terminal of the high-voltage shutdown circuit 323 is connected to the shutdown voltage Vo. The output terminal of the high-voltage shutdown circuit 323 is electrically connected to the latch control terminal of the low-voltage latch output circuit 313.

[0052] Understandably, in the low-voltage submodule provided in this embodiment of the invention, the low-voltage input circuit transmits the turn-on voltage to both the latch control terminal of the low-voltage latch output circuit and the control terminal of the low-voltage turn-off circuit according to the enable signal of the low-voltage control signal. The turn-on voltage is latched by the low-voltage latch output circuit, and the turn-on voltage controls the low-voltage latch output circuit to transmit the first power supply voltage to the power supply voltage terminal. At the same time, the turn-on voltage controls the low-voltage turn-off circuit to transmit the turn-off voltage to the latch control terminal of the high-voltage latch output circuit. The high-voltage latch output circuit latches the turn-off voltage and is controlled to be in a turn-off state, preventing the high-voltage latch output circuit from transmitting the second power supply voltage to the power supply voltage terminal. Furthermore, in the high-voltage submodule, both the control terminal of the high-voltage input circuit and the control terminal of the high-voltage shutdown circuit are connected to the high-voltage control signal. Consequently, the high-voltage input circuit transmits the turn-on voltage to the latch control terminal of the high-voltage latch output circuit according to the enable of the high-voltage control signal. The turn-on voltage is latched by the high-voltage latch output circuit, and the turn-on voltage controls the high-voltage latch output circuit to transmit the second power supply voltage to the power supply voltage terminal. Similarly, the high-voltage shutdown circuit transmits the shutdown voltage to the latch control terminal of the low-voltage latch output circuit according to the enable of the high-voltage control signal. The low-voltage latch output circuit latches the shutdown voltage and is controlled to be in the shutdown state, preventing the low-voltage latch output circuit from transmitting the first power supply voltage to the power supply voltage terminal.

[0053] It should be noted that the control terminal of the low-voltage shutdown circuit provided in this embodiment of the invention is not limited to being electrically connected to the output terminal of the low-voltage input circuit. The control terminal of the low-voltage shutdown circuit can also be connected to a low-voltage control signal. The low-voltage shutdown circuit is turned on by the enable signal of the low-voltage control signal, so as to transmit the shutdown voltage to the latch control terminal of the high-voltage latch output circuit. Furthermore, the control terminal of the high-voltage shutdown circuit provided in this embodiment of the invention is not limited to being connected to a high-voltage control signal. The control terminal of the high-voltage shutdown circuit can also be electrically connected to the output terminal of the high-voltage input circuit. The high-voltage shutdown circuit responds to the control of the turn-on voltage output by the high-voltage input circuit and transmits the shutdown voltage to the latch control terminal of the low-voltage latch output circuit. This invention does not impose specific limitations on this aspect.

[0054] In one embodiment of the present invention, the input circuit, latched output circuit, and shutdown circuit of the low-voltage submodule and high-voltage submodule provided by the present invention can be composed of at least one of components such as transistors and capacitors. See details. Figure 5The diagram shows a schematic of another pixel circuit provided in an embodiment of the present invention. The low-voltage input circuit 311 provided in this embodiment includes a first transistor M1, and the low-voltage latch output circuit 312 includes a second transistor M2 and a second capacitor C2. The first terminal of the first transistor M1 is connected to the turn-on voltage Vk, and the second terminal of the first transistor M1 is electrically connected to the gate of the second transistor M2 and the first plate of the second capacitor C2. The gate of the first transistor M1 is connected to the low-voltage control signal Sgl. The first terminal of the second transistor M2 is connected to the first power supply voltage Vg1, and the second terminal of the second transistor M2 is electrically connected to the power supply voltage terminal Vpvdd. The second plate of the second capacitor C2 is electrically connected to the power supply voltage terminal Vpvdd. Alternatively, the second plate of the second capacitor provided in this embodiment can also be connected to a first reference voltage, as detailed in the following reference. Figure 6 In the pixel circuit shown, the second plate of the second capacitor C2 is connected to the first reference voltage Vr1, which can also achieve the latching of the voltage at the first plate of the second capacitor C2.

[0055] refer to Figure 5 As shown, the high-voltage input circuit 321 provided in this embodiment of the invention includes a fourth transistor M4, and the high-voltage latch output circuit 322 includes a fifth transistor M5 and a third capacitor C3. The first terminal of the fourth transistor M4 is connected to the turn-on voltage Vk, and the second terminal of the fourth transistor M4 is electrically connected to the gate of the fifth transistor M5 and the first plate of the third capacitor C3. The gate of the fourth transistor M4 is connected to the high-voltage control signal Sgh. The first terminal of the fifth transistor M5 is connected to the second power supply voltage Vg2, and the second terminal of the fifth transistor M5 is electrically connected to the power supply voltage terminal Vpvdd. The second plate of the third capacitor C3 is connected to the second reference voltage Vr2.

[0056] Continue to refer to Figure 5 As shown, the low-voltage shutdown circuit 313 provided in this embodiment of the invention includes a third transistor M3, and the high-voltage shutdown circuit 323 includes a sixth transistor M6.

[0057] The first terminal of the third transistor M3 is connected to the turn-off voltage Vo, and the second terminal of the third transistor M3 is electrically connected to the latch control terminal of the high-voltage latch output circuit 322, that is, the second terminal of the third transistor M3 is electrically connected to the first plate of the third capacitor C3 and the gate of the fifth transistor M5; the gate of the third transistor M3 is electrically connected to the output terminal of the low-voltage input circuit 311, that is, the gate of the third transistor M3 is electrically connected to the second terminal of the first transistor M1. The first terminal of the sixth transistor M6 is connected to the turn-off voltage Vo, and the second terminal of the sixth transistor M6 is electrically connected to the latch control terminal of the low-voltage latch output circuit 312, that is, the second terminal of the sixth transistor M6 is electrically connected to the first plate of the second capacitor C2 and the gate of the second transistor M2; the gate of the sixth transistor M6 is connected to the high-voltage control signal Sgh.

[0058] It should be noted that the gate of the third transistor provided in the embodiments of the present invention is not limited to being electrically connected to the output terminal of the low-voltage input circuit. The gate of the third transistor can also be selectively connected to a low-voltage control signal, that is, the gate of the third transistor is electrically connected to the output terminal of the low-voltage input circuit or connected to a low-voltage control signal. Similarly, the gate of the sixth transistor provided in the embodiments of the present invention is not limited to being connected to a high-voltage control signal. The gate of the sixth transistor can also be selectively connected to the output terminal of the high-voltage input circuit, that is, the gate of the sixth transistor is electrically connected to the output terminal of the high-voltage input circuit or connected to a high-voltage control signal. The present invention does not impose specific limitations on this.

[0059] Understandably, in the power supply module provided in this embodiment of the invention, a low-voltage control signal enables and controls the first transistor to turn on. The first transistor transmits the turn-on voltage to the first plate of the second capacitor for latching, and the turn-on voltage is simultaneously transmitted to the gate of the second transistor and the gate of the third transistor. The turn-on voltage controls the second transistor to turn on, so as to transmit the first power supply voltage to the power supply voltage terminal through the second transistor; and the turn-on voltage controls the third transistor to turn on, so as to transmit the turn-off voltage to the first plate of the third capacitor and the gate of the fifth transistor through the third transistor, so as to control the fifth transistor to turn off and prevent the fifth transistor from transmitting the second power supply voltage to the power supply voltage terminal.

[0060] Furthermore, the high-voltage control signal enables the fourth and sixth transistors to conduct. The fourth transistor transmits the turn-on voltage to the first plate of the third capacitor and the gate of the fifth transistor. The turn-on voltage controls the fifth transistor to conduct, so as to transmit the second power supply voltage to the power supply voltage terminal through the fifth transistor. The sixth transistor transmits the turn-off voltage to the first plate of the second capacitor, the gate of the second transistor, and the gate of the third transistor, so as to control the second and third transistors to turn off, preventing the third transistor from transmitting the turn-off voltage to the gate of the fifth transistor, and at the same time preventing the second transistor from transmitting the first power supply voltage to the power supply voltage terminal.

[0061] The working process of the pixel circuit provided in the embodiments of the present invention will be described in more detail below with reference to a specific circuit structure. The pixel circuit provided by the present invention further includes a reset module, an auxiliary reset module, and a light emission control module. See details below. Figure 7 The diagram shown is a structural schematic of another pixel circuit provided in an embodiment of the present invention. The pixel circuit further includes a reset module 400, an auxiliary reset module 500, and a light emission control module 600.

[0062] The input terminal of the reset module 400 is connected to the reset voltage Vref, the output terminal of the reset module 400 is electrically connected to the gate of the driving transistor M0, and the control terminal of the reset module 400 is connected to the reset control signal Sf.

[0063] The input terminal of the auxiliary reset module 500 is connected to the auxiliary reset voltage Vreff, the output terminal of the auxiliary reset module 500 is electrically connected to the anode of the light-emitting element 700, the cathode terminal of the light-emitting element 700 is electrically connected to the cathode voltage terminal Vpvee, and the control terminal of the auxiliary reset module 500 is connected to the auxiliary reset control signal Sff. The light-emitting control module 600 is electrically connected to both the first and second terminals of the driving transistor M0, and the control terminal of the light-emitting control module 600 is connected to the light-emitting control signal EMIT. In response to the enable of the light-emitting control signal EMIT, the light-emitting control module 600 transmits the driving current generated by the driving transistor M0 to the anode of the light-emitting element 700.

[0064] Further reference Figure 8 The diagram shows a schematic of another pixel circuit provided in an embodiment of the present invention. The data writing module 100 provided in this embodiment includes a data writing transistor Md, whose gate is connected to a data control signal Sd, whose first terminal is connected to a data voltage Vdata, and whose second terminal is electrically connected to the first terminal of a driving transistor M0. The connection module 200 includes a connection transistor Mj, whose first terminal is electrically connected to the second terminal of the driving transistor M0, whose second terminal is electrically connected to the gate of the driving transistor M0, and whose gate is connected to a connection control signal Sj.

[0065] The reset module 400 includes a reset transistor Mf, whose gate is connected to a reset control signal Sf, whose first terminal is connected to a reset voltage Vref, and whose second terminal is electrically connected to the gate of a driving transistor M0. The auxiliary reset module 500 includes an auxiliary reset transistor Mff, whose gate is connected to an auxiliary reset control signal Sff, whose first terminal is connected to an auxiliary reset voltage Vreff, and whose second terminal is electrically connected to the anode of the light-emitting element 700. The light-emitting control module 600 includes a first light-emitting control transistor Me1 and a second light-emitting control transistor Me2 with the same conduction type. One terminal of the first light-emitting control transistor Me1 is electrically connected to the power supply voltage terminal Vpvdd, and its second terminal is electrically connected to the first terminal of the driving transistor M0. The first terminal of the second light-emitting control transistor Me2 is also electrically connected to the first terminal of the driving transistor M0, and its second terminal is electrically connected to the anode of the light-emitting element 700. The gates of both the first and second light-emitting control transistors are connected to a light-emitting control signal EMIT.

[0066] It should be noted that the pixel circuit provided in the embodiments of the present invention is not limited to the transistor composition structure described above. In other embodiments of the present invention, the pixel circuit can also be other connection structures. Furthermore, the conduction type of the data writing transistor, connection transistor, reset transistor, auxiliary reset transistor, first light-emitting control transistor, second light-emitting control transistor, and the first to sixth transistors provided in the embodiments of the present invention can be N-type transistors or P-type transistors; the present invention does not impose specific limitations on this. Optionally, the conduction type of the data writing transistor, connection transistor, reset transistor, auxiliary reset transistor, first light-emitting control transistor, second light-emitting control transistor, and the first to sixth transistors provided in the embodiments of the present invention can all be the same to facilitate the fabrication of the pixel circuit.

[0067] In one embodiment of the present invention, some signals can be multiplexed to reduce the number of signal ports in the pixel circuit and optimize wiring. See details. Figure 9The diagram shows another pixel circuit provided in an embodiment of the present invention. The data control signal Sd and the connection control signal Sj provided by the present invention have the same enable phase. When the data writing transistor Md and the connection transistor Mj have the same conduction type, the data control signal Sd and the connection control signal Sj can be multiplexed as the same control signal. Similarly, the reset control signal Sf and the auxiliary reset control signal Sff have the same enable phase. When the reset transistor Mf and the auxiliary reset transistor Mff have the same conduction type, the reset control signal Sf and the auxiliary reset control signal Sff can be multiplexed as the same control signal; and the reset voltage Vref and the auxiliary reset voltage Vreff can be multiplexed as the same voltage. Furthermore, when the second transistor M2 and the fifth transistor M5 are P-type transistors, the turn-off voltage Vo is a high-level voltage, wherein the turn-off voltage Vo and the second reference voltage Vr2 can be multiplexed as the same voltage.

[0068] The following description uses an example where all transistors are P-type transistors to illustrate the operation of the pixel circuit provided in this embodiment of the invention. Figure 9 and Figure 10 As shown, Figure 10 A timing diagram provided in an embodiment of the present invention shows that the pixel circuit operation process includes a first voltage conversion stage T1, a reset stage T2, a data writing stage T3, a second voltage conversion stage T4, and a light emission control stage T5 performed sequentially, wherein:

[0069] During the first voltage conversion stage T1, the low-voltage control signal Sgl is enabled at a low level, controlling the first transistor M1 to turn on. The first transistor M1 transmits the low-level turn-on voltage Vk to the first plate of the second capacitor C2, the gate of the second transistor M2, and the gate of the third transistor M3. The second capacitor C2 latches the turn-on voltage Vk, and the second transistor M2 and the third transistor M3 are turned on according to the control of the turn-on voltage Vk. The second transistor M2 transmits the lower first power supply voltage Vg1 to the power supply voltage terminal Vpvdd; the third transistor M3 transmits the high-level turn-off voltage Vo to the first plate of the third capacitor C3 and the gate of the fifth transistor M5 to keep the fifth transistor M5 off.

[0070] During the reset phase T2, because the second capacitor C2 latches the turn-on voltage Vk and the third capacitor C3 latches the turn-off voltage Vo, the second transistor M2 and the third transistor M3 remain on while the fifth transistor M5 remains off. The power supply voltage Vpvdd remains at the lower first power supply voltage Vg1. The reset control signal Sf and the auxiliary reset control signal Sff are enabled at a low level, and the reset transistor Mf and the auxiliary reset transistor Mff are turned on. The reset transistor Mf transmits the reset voltage Vref to the gate of the driving transistor M0 for reset, and the auxiliary reset transistor Mff transmits the auxiliary reset voltage Vreff to the anode of the light-emitting element 700 for reset.

[0071] During the data writing phase T3, because the second capacitor C2 latches the turn-on voltage Vk and the third capacitor C3 latches the turn-off voltage Vo, the second transistor M2 and the third transistor M3 remain on while the fifth transistor M5 remains off. The power supply voltage Vpvdd remains at the lower first power supply voltage Vg1. The data control signal Sd and the connection control signal Sj are enabled at a low level, and the data writing transistor Md and the connection transistor Mj are turned on to transmit the data voltage Vdata to the gate of the driving transistor M0 through the data writing transistor Md, the driving transistor M0, and the connection transistor Mj.

[0072] During the second voltage conversion stage T4, the high-voltage control signal Sgh is enabled at a low level, controlling the fourth transistor M4 and the sixth transistor M6 to conduct. The fourth transistor M4 transmits the turn-on voltage Vk to the first plate of the third capacitor C3 and the gate of the fifth transistor M5. The fifth transistor M5 conducts, transmitting the higher second power supply voltage Vg2 to the power supply voltage terminal Vpvdd. The sixth transistor M6 transmits the turn-off voltage Vo to the first plate of the second capacitor C2 and the gate of the second transistor M2, thereby keeping the second transistor M2 off. As the voltage at the power supply voltage terminal Vpvdd increases, the voltage at the gate of the driving transistor M0 can be increased through the coupling effect of the first capacitor C1, thus better turning off the driving transistor M0.

[0073] During the light-emitting control phase T5, since the third capacitor C3 latches the turn-on voltage Vk and the second capacitor C2 latches the turn-off voltage Vo, the fifth transistor M5 remains on while the second transistor M2 and the third transistor M3 remain off. The power supply voltage Vpvdd remains at the higher second power supply voltage Vg2. When the light-emitting control signal EMIT is enabled at a low level, the first light-emitting control transistor Me1 and the second light-emitting control transistor Me2 are turned on to transfer the drive current generated by the drive transistor M0 to the light-emitting element 700. The light-emitting element 700 then emits light in response to the drive current.

[0074] like Figure 10As shown, the first voltage conversion stage T1 provided by the present invention can be located before the reset stage T2. Alternatively, the first voltage conversion stage and the reset stage provided in the embodiments of the present invention can be the same stage, that is, the enable stage of the low-voltage control signal, the enable stage of the reset control signal, and the enable stage of the auxiliary reset control signal are the same. In this case, the low-voltage control signal, the reset control signal, and the auxiliary reset control signal can be multiplexed into the same control signal; specifically as follows... Figure 11 The diagram shown is another timing diagram provided by an embodiment of the present invention. In this diagram, the low-voltage control signal Sgl, the reset control signal Sf, and the auxiliary reset control signal Sff are multiplexed into the same control signal. The first voltage conversion stage T1 and the reset stage T2 are the same stage. The present invention does not impose specific restrictions on this, as long as the voltage at the power supply voltage terminal Vpvdd is the lower first power supply voltage Vg1 during the data writing stage T3.

[0075] Accordingly, embodiments of the present invention also provide a display panel, the display panel including the pixel circuit provided in any of the above embodiments. Optionally, the display panel provided in the embodiments of the present invention includes: a first pixel row to an Nth pixel row, any pixel row including multiple pixel units, and the pixel unit including the pixel circuit, wherein all pixel circuits in the i-th pixel row reuse the same power supply module, N is an integer greater than or equal to 2, and i is a positive integer less than or equal to N.

[0076] It is understood that the display panel provided in this embodiment of the invention scans the first pixel row to the Nth pixel row line by line when displaying the image; that is, the pixel circuits located in the same pixel row are scanned and operated simultaneously. This embodiment of the invention reuses the same power supply module for the pixel circuits in the same pixel row, which can reduce the circuit structure of the display panel and simplify its circuit design.

[0077] refer to Figure 12 The diagram shows a schematic representation of a display panel according to an embodiment of the present invention. The display panel includes a first pixel row P1 to an Nth pixel row Pn. In any pixel row, the power supply modules (not shown) of the pixel circuits in the same row are multiplexed. The pixel circuits (not shown) include a reset module. The input terminal of the reset module is connected to a reset voltage, the output terminal of the reset module is electrically connected to the gate of the driving transistor, and the control terminal of the reset module is connected to a reset control signal. The power supply module includes a low-voltage submodule and a high-voltage submodule.

[0078] The i-th pixel row includes a reset control terminal Sf' for providing the reset control signal, a data control terminal Sd' for providing the data control signal, a low-voltage control terminal Sgl' for providing the low-voltage control signal, and a high-voltage control terminal Sgh' for providing the high-voltage control signal. The display panel includes a first virtual level scanning circuit SRx1 that outputs control signals in stages, first-level scanning circuits SR1 to Nth-level scanning circuits SRn, and a second virtual level scanning circuit SRx2. The output terminal of the i-th level scanning circuit is electrically connected to the data control terminal Sd' of the i-th pixel row, the reset control terminal Sf' of the (i+1)-th pixel row, and the low-voltage control terminal Sgl' of the (i+1)-th pixel row. The output terminal of the (i+1)-th level scanning circuit is also electrically connected to the high-voltage control terminal Sgh' of the i-th pixel row. The output terminal of the first virtual level scanning circuit SRx1 is electrically connected to the reset control terminal Sf' and the low-voltage control terminal Sd' of the first pixel row P1. The output terminal of the second virtual level scanning circuit SRx2 is electrically connected to the high-voltage control terminal Sgh' of the Nth pixel row Pn. Figure 12 Taking i as 1 as an example, the connection relationship between the i-th pixel row and the (i+1)-th pixel row is as follows: Figure 12 As shown in the first pixel row P1 and the second pixel row P2.

[0079] Understandably, in the display panel provided by the embodiments of the present invention, the first virtual level scanning circuit, the first level scanning circuit to the Nth level scanning circuit, and the second virtual level scanning circuit output enable control signals step by step to transmit them to the control terminals of the connected pixel rows. Taking the first pixel row as an example, after the first pixel row receives the enable signal output by the first virtual level scanning circuit, the reset control terminal is now an enabled reset control signal, and the low voltage control terminal is now an enabled low voltage control signal, so that the pixel circuit of the first pixel row performs the reset stage while performing the first voltage conversion stage of the pixel circuit, ensuring that the power supply voltage terminal of the pixel circuit is at a lower first power supply voltage during the data writing stage; then, the first pixel row receives the enable signal output by the first level scanning circuit, and the data control terminal is now an enabled data control signal, so that the pixel circuit performs the data writing stage; finally, the first pixel row receives the enable signal output by the second level scanning circuit, and the high voltage control terminal is now an enabled high voltage control signal, so that the pixel circuit performs the second voltage conversion stage, resulting in a higher second power supply voltage at the power supply voltage terminal, ensuring that the driving transistor of the pixel circuit can be better turned off. This process is repeated to complete the scanning of all pixel rows.

[0080] This invention Figure 12In the illustrated embodiment, the reset control terminal Sf' and the low-voltage control terminal Sgl' of the same pixel row are both connected to the output terminal of the same scanning circuit, making the first voltage conversion stage and the reset stage of the pixel circuit the same stage. Furthermore, in other embodiments of the present invention, the first voltage conversion stage of the pixel circuit provided by the present invention may also be located before the reset stage; see details below. Figure 13 The diagram shows a schematic representation of another display panel provided in an embodiment of the present invention. The display panel includes a first pixel row P1 to an Nth pixel row Pn. In any pixel row, the power supply modules (not shown) of the pixel circuits in the same row are multiplexed. The pixel circuits (not shown) include a reset module. The input terminal of the reset module is connected to a reset voltage, the output terminal of the reset module is electrically connected to the gate of the driving transistor, and the control terminal of the reset module is connected to a reset control signal. The power supply module includes a low-voltage submodule and a high-voltage submodule.

[0081] The i-th pixel row includes a reset control terminal Sf' for providing the reset control signal, a data control terminal Sd' for providing the data control signal, a low-voltage control terminal Sgl' for providing the low-voltage control signal, and a high-voltage control terminal Sgh' for providing the high-voltage control signal. The display panel includes a first virtual-level scanning circuit SRy1, a second virtual-level scanning circuit SRy2, and first-level scanning circuits SR1 to Nth-level scanning circuits SRn, each outputting control signals in stages. The output terminal of the i-th-level scanning circuit is electrically connected to the data control terminal Sd' of the i-th pixel row, the reset control terminal Sf' of the (i+1)-th pixel row, and the low-voltage control terminal Sgl' of the (i+2)-th pixel row. The output terminal of the (i+1)-th-level scanning circuit is electrically connected to the high-voltage control terminal Sgh' of the i-th pixel row. The output terminal of the first virtual-level scanning circuit SRy1 is electrically connected to the low-voltage control terminal Sgl' of the first pixel row P1. The output terminal of the second virtual-level scanning circuit SRy2 is electrically connected to the reset control terminal Sf' of the first pixel row P1 and the low-voltage control terminal Sgl' of the second pixel row P2. The output terminal of the third virtual-level scanning circuit SRy3 is electrically connected to the high-voltage control terminal Sgh' of the Nth pixel row Pn. Figure 13 Taking i as 1 as an example, the connection relationship between the i-th pixel row and the (i+1)-th pixel row is as follows: Figure 13 As shown in the first pixel row P1 and the second pixel row P2.

[0082] As can be understood, in the display panel provided in the embodiments of the present invention, the first virtual level scanning circuit, the second virtual level scanning circuit, the first level scanning circuit to the Nth level scanning circuit and the third virtual level scanning circuit output enable control signals step by step, so as to transmit them to the control terminal of the connected pixel row. Taking the first pixel row as an example, after the first pixel row receives the enable signal output from the first virtual level scanning circuit, the low-voltage control terminal is now an enabled low-voltage control signal, and the pixel circuit performs the first voltage conversion stage, ensuring that the power supply voltage terminal of the pixel circuit is at a lower first power supply voltage during the data writing stage. Then, the first pixel row receives the enable signal output from the second virtual level scanning circuit, and the reset control terminal is now an enabled reset control signal, enabling the pixel circuit of the first pixel row to perform the reset stage. Next, the first pixel row receives the enable signal output from the first level scanning circuit, and the data control terminal is now an enabled data control signal, enabling the pixel circuit to perform the data writing stage. Finally, the first pixel row receives the enable signal output from the second level scanning circuit, and the high-voltage control terminal is now an enabled high-voltage control signal, enabling the pixel circuit to perform the second voltage conversion stage, resulting in a higher second power supply voltage at the power supply voltage terminal, ensuring that the driving transistor of the pixel circuit can be better turned off. This process continues until all pixel rows are scanned.

[0083] refer to Figure 14 The diagram shown is a structural schematic of another display panel provided in an embodiment of the present invention, wherein the display panel 1000 provided in this embodiment of the present invention can be applied to a mobile terminal.

[0084] It should be noted that the display panel provided in the embodiments of the present invention can also be applied to laptops, tablets, computers, wearable devices, etc., and the present invention does not impose specific limitations on them.

[0085] This invention provides a pixel circuit and a display panel. The pixel circuit includes a power supply module, which is used to provide a first power supply voltage to the power supply voltage terminal at least during the data writing phase, and to provide a second power supply voltage to the power supply voltage terminal after the data writing phase, wherein the first power supply voltage is less than the second power supply voltage.

[0086] As can be seen from the above, the technical solution provided by the embodiments of the present invention provides a lower first power supply voltage to the power supply voltage terminal during the data writing stage, which can ensure that the data voltage is transmitted normally to the gate of the driving transistor; and provides a higher second power supply voltage to the power supply voltage terminal after the data writing stage, which can increase the voltage at the gate of the driving transistor through the coupling effect of the first capacitor, so as to better turn off the driving transistor. Thus, there is no need for the peripheral circuit to provide a higher data voltage, avoiding excessive power consumption of the peripheral circuit.

[0087] In the description of this invention, it should be understood that terms such as "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0088] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0089] In this invention, unless otherwise explicitly specified and limited, terms such as "installation," "connection," "linking," and "fixing" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection, an electrical connection, or a connection that allows communication between components; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise explicitly limited. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0090] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can mean that the first feature is in direct contact with the second feature, or that the first feature is in indirect contact with the second feature through an intermediate medium. Furthermore, "above," "over," and "on top" of the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "beneath" of the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0091] In this invention, the terms "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0092] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.

Claims

1. A pixel circuit, characterized by comprising: The application relates to a driving transistor for generating a driving current, a data writing module, a connection module, a first capacitor, and a power supply module. The driving transistor is a P-type transistor. The input end of the data writing module is connected with a data voltage, the output end of the data writing module is electrically connected with the first end of the driving transistor, and the control end of the data writing module is connected with a data control signal. The input end of the connection module is electrically connected with the second end of the driving transistor, the output end of the connection module is electrically connected with the gate of the driving transistor, the control end of the connection module is connected with a connection control signal, and the data control signal and the connection control signal are enabled in a data writing stage. The first end of the first capacitor is electrically connected with the gate of the driving transistor, and the second end of the first capacitor is electrically connected with a power voltage end. The power supply module is used for providing a first power voltage for the power voltage end at least in the data writing stage, and providing a second power voltage for the power voltage end after the data writing stage and before a light-emitting stage, wherein the first power voltage is smaller than the second power voltage. The power supply module comprises a low-voltage submodule and a high-voltage submodule.

2. The pixel circuit of claim 1, wherein, The input end of the low-voltage submodule is connected with the first power voltage, the output end of the low-voltage submodule is electrically connected with the power voltage end, and the control end of the low-voltage submodule is connected with a low-voltage control signal. The input end of the high-voltage submodule is connected with the second power voltage, the output end of the high-voltage submodule is electrically connected with the power voltage end, and the control end of the high-voltage submodule is connected with a high-voltage control signal. The low-voltage submodule comprises a low-voltage input circuit and a low-voltage latching output circuit.

3. The pixel circuit of claim 2, wherein, The input end of the low-voltage input circuit is connected with an opening voltage, the output end of the low-voltage input circuit is electrically connected with the latching control end of the low-voltage latching output circuit, and the control end of the low-voltage input circuit is connected with the low-voltage control signal. The input end of the low-voltage latching output circuit is connected with the first power voltage, and the output end of the low-voltage latching output circuit is electrically connected with the power voltage end. The low-voltage input circuit comprises a first transistor, and the low-voltage latching output circuit comprises a second transistor and a second capacitor.

4. The pixel circuit of claim 3, wherein, The first end of the first transistor is connected with the opening voltage, the second end of the first transistor is electrically connected with the gate of the second transistor and the first end plate of the second capacitor, and the gate of the first transistor is connected with the low-voltage control signal. The first end of the second transistor is connected with the first power voltage, the second end of the second transistor is electrically connected with the power voltage end, the second end plate of the second capacitor is electrically connected with the power voltage end, or the second end plate of the second capacitor is connected with a first reference voltage. The high-voltage submodule comprises a high-voltage input circuit and a high-voltage latching output circuit.

5. The pixel circuit of claim 3, wherein, The input end of the high-voltage input circuit is connected with the opening voltage, the output end of the high-voltage input circuit is electrically connected with the latching control end of the high-voltage latching output circuit, and the control end of the high-voltage input circuit is connected with the high-voltage control signal. ​ An input terminal of the high-voltage latch output circuit is connected to the second power supply voltage, and an output terminal of the high-voltage latch output circuit is electrically connected to the power supply voltage terminal.

6. The pixel circuit of claim 5, wherein, The high-voltage input circuit comprises a fourth transistor, and the high-voltage latch output circuit comprises a fifth transistor and a third capacitor. A first terminal of the fourth transistor is connected to the turn-on voltage, a second terminal of the fourth transistor is electrically connected to a gate of the fifth transistor and a first plate of the third capacitor, and a gate of the fourth transistor is connected to the high-voltage control signal. A first terminal of the fifth transistor is connected to the second power supply voltage, a second terminal of the fifth transistor is electrically connected to the power supply voltage terminal, and a second plate of the third capacitor is connected to a second reference voltage.

7. The pixel circuit of claim 5, wherein, The low-voltage sub-module further comprises a low-voltage turn-off circuit, and / or the high-voltage sub-module further comprises a high-voltage turn-off circuit. A control terminal of the low-voltage turn-off circuit is electrically connected to an output terminal of the low-voltage input circuit, or the control terminal of the low-voltage turn-off circuit is connected to the low-voltage control signal; an input terminal of the low-voltage turn-off circuit is connected to a turn-off voltage, and an output terminal of the low-voltage turn-off circuit is electrically connected to a latch control terminal of the high-voltage latch output circuit. A control terminal of the high-voltage turn-off circuit is electrically connected to an output terminal of the high-voltage input circuit, or the control terminal of the high-voltage turn-off circuit is connected to the high-voltage control signal; an input terminal of the high-voltage turn-off circuit is connected to the turn-off voltage, and an output terminal of the high-voltage turn-off circuit is electrically connected to the latch control terminal of the low-voltage latch output circuit.

8. The pixel circuit of claim 7, wherein, The low-voltage turn-off circuit comprises a third transistor, and the high-voltage turn-off circuit comprises a sixth transistor. A first terminal of the third transistor is connected to the turn-off voltage, a second terminal of the third transistor is electrically connected to the latch control terminal of the high-voltage latch output circuit, and a gate of the third transistor is electrically connected to the output terminal of the low-voltage input circuit, or the gate of the third transistor is connected to the low-voltage control signal. A first terminal of the sixth transistor is connected to the turn-off voltage, a second terminal of the sixth transistor is electrically connected to the latch control terminal of the low-voltage latch output circuit, and a gate of the sixth transistor is electrically connected to the output terminal of the high-voltage input circuit, or the gate of the sixth transistor is connected to the high-voltage control signal.

9. A display panel, characterized by, The display panel comprises the pixel circuit according to any one of claims 1-8.

10. The display panel of claim 9, wherein, The display panel comprises: first to Nth pixel rows, any one pixel row comprises a plurality of pixel units, and the pixel unit comprises the pixel circuit, wherein all pixel circuits of the ith pixel row share one power supply module, N is an integer greater than or equal to 2, and i is a positive integer less than or equal to N.

11. The display panel of claim 10, wherein, The pixel circuit comprises a reset module, an input terminal of the reset module is connected to a reset voltage, an output terminal of the reset module is electrically connected to a gate of the driving transistor, and a control terminal of the reset module is connected to a reset control signal. The power supply module comprises a low-voltage sub-module and a high-voltage sub-module. The i-th pixel row comprises a reset control end for providing the reset control signal, a data control end for providing the data control signal, a low-voltage control end for providing the low-voltage control signal, and a high-voltage control end for providing the high-voltage control signal; The display panel comprises a first virtual stage scanning circuit, a first stage scanning circuit to an N-th stage scanning circuit, and a second virtual stage scanning circuit, which output control signals in stages, wherein an output end of an i-th stage scanning circuit is electrically connected to a data control end of the i-th pixel row, a reset control end of an i+1-th pixel row, and a low-voltage control end of the i+1-th pixel row, and an output end of an i+1-th stage scanning circuit is electrically connected to a high-voltage control end of the i-th pixel row. An output end of the first virtual stage scanning circuit is electrically connected to a reset control end of the first pixel row and a low-voltage control end of the first pixel row, and an output end of the second virtual stage scanning circuit is electrically connected to a high-voltage control end of the N-th pixel row.

12. The display panel of claim 10, wherein, The pixel circuit comprises a reset module, an input end of the reset module is connected to a reset voltage, an output end of the reset module is electrically connected to a gate of the driving transistor, and a control end of the reset module is connected to a reset control signal. The power supply module comprises a low-voltage submodule and a high-voltage submodule. The i-th pixel row comprises a reset control end for providing the reset control signal, a data control end for providing the data control signal, a low-voltage control end for providing the low-voltage control signal, and a high-voltage control end for providing the high-voltage control signal; The display panel comprises a first virtual stage scanning circuit, a second virtual stage scanning circuit, a first stage scanning circuit to an N-th stage scanning circuit, and a third virtual stage scanning circuit, which output control signals in stages, wherein an output end of an i-th stage scanning circuit is electrically connected to a data control end of the i-th pixel row, a reset control end of an i+1-th pixel row, and a low-voltage control end of an i+2-th pixel row, and an output end of an i+1-th stage scanning circuit is electrically connected to a high-voltage control end of the i-th pixel row. An output end of the first virtual stage scanning circuit is electrically connected to a low-voltage control end of the first pixel row, an output end of the second virtual stage scanning circuit is electrically connected to a reset control end of the first pixel row and a low-voltage control end of a second pixel row, and an output end of the third virtual stage scanning circuit is electrically connected to a high-voltage control end of the N-th pixel row.

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