Display device including pixel drive circuit

Abstract

Disclosed is a display device including a light emitting element; and a pixel driving circuit connected to the light emitting element and configured to include a first node, a second node, a third node, and a fourth node, wherein the pixel driving circuit includes a driving transistor connected to the first node, the second node, and the third node, a plurality of switching transistors, a storage capacitor, and a plurality of signal lines and a plurality of voltage lines, wherein an initialization voltage applied through an initialization line among the plurality of signal lines and the plurality of voltage lines varies based on a data voltage.

Description

Technical Field

[0001] This disclosure relates to a display device including pixel driving circuitry. Background Technology

[0002] With the development of information technology, the market for display devices, which serve as the connection medium between users and information, has expanded. In addition to the transmission of text-based information between users, various forms of communication have been actively developed. Based on changes in information types, the performance of display devices for displaying information has also been improved. Therefore, display devices such as organic light-emitting diode (OLED) displays, micro LED displays, liquid crystal displays, and quantum dot displays have been widely used, and high-definition display devices for improving information clarity have been actively researched and developed.

[0003] The display device includes a display panel having multiple sub-pixels, a driving circuit for supplying signals to drive the display panel, and a power supply section for supplying power to the display panel. The driving circuit includes a gate driving circuit for supplying gate signals to the display panel and a data driving circuit for supplying data signals to the display panel.

[0004] For example, when gate signals and data signals are supplied to the sub-pixels of a display device, the display device can display an image by causing the light-emitting elements of the selected sub-pixels to emit light. The light-emitting elements can be implemented based on organic or inorganic materials.

[0005] Display devices display images based on light generated from light-emitting elements in sub-pixels, thus offering various advantages. However, to improve the image's graphic quality, it is necessary to increase the precision of the pixel driving circuitry used to control the light emission of sub-pixels. For example, the precision of the pixel driving circuitry can be improved by compensating for the threshold voltage of the driving transistors included in the pixel driving circuitry.

[0006] The above-described background information may be retained to allow inventors to deduce the present disclosure, or it may be technical information learned through practicing embodiments of the present disclosure. However, the above-described background information may not be prior art disclosed to the public prior to the application of this disclosure. Summary of the Invention

[0007] As display device resolution and power consumption increase, driving techniques have been developed to reduce power consumption. To reduce power consumption, pixels can be driven at a lower speed by reducing the frame rate during specific periods. For example, in mobile mode, power consumption can be reduced by performing normal driving at 60Hz or 120Hz in real-time mode and low-speed driving at 1Hz in standby mode.

[0008] To mitigate hysteresis in the driving transistors and improve initial frame response characteristics, the pixel driving circuit performs an on-bias stress (OBS) step, which biases the source and gate of the driving transistors to a predetermined data voltage, before sampling the threshold voltage of the driving transistors. While increasing the data voltage applied for the on-bias stress step can improve initial frame response characteristics, the light emission step may be affected by the data voltage applied to the driving transistors, potentially leading to increased black brightness.

[0009] To address the aforementioned problems, the inventors of this disclosure have confirmed that when an initialization step is performed before the conduction bias stress step, the data voltage required for the conduction bias stress operation can be sufficiently reduced, thereby overcoming the problem associated with increased black brightness. However, according to the conduction bias stress operation immediately following the initial step, a large threshold voltage variation ΔVth is generated in the gate-source voltage VGS of the driving transistor. To overcome flicker, it is important to reduce the deviation of the threshold voltage variation ΔVth through the subsequent conduction bias stress step. Therefore, the inventors of this disclosure have invented a pixel driving circuit and a display device including the pixel driving circuit, which can reduce the threshold voltage deviation independently of the gate-source voltage VGS of the driving transistor through the conduction bias stress operation, and can overcome flicker at low grayscale levels.

[0010] This disclosure was made in view of the above problems, and the object of this disclosure is to provide a display device including a pixel driving circuit that can reduce the deviation of the threshold voltage independently of the gate-source voltage VGS of the driving transistor by conducting bias stress operation, and overcome flickering at low gray level levels.

[0011] According to one aspect of this disclosure, the above and other objectives can be achieved by providing a display device comprising: a light-emitting element; and a pixel driving circuit connected to the light-emitting element and configured to include a first node, a second node, a third node, and a fourth node, wherein the pixel driving circuit includes: a driving transistor connected to the first node, the second node, and the third node; a first transistor connected to a first control signal line and connected to the first node and the third node; a second transistor connected to a second control signal line and connected between the second node and a data line; a third transistor connected to a light-emitting control signal and connected between the second node and a first driving voltage line; a fourth transistor connected to the light-emitting control signal and connected between the third node and the fourth node; a fifth transistor connected to a third control signal line and connected between the third node and a first initialization voltage line; a sixth transistor connected to the third control signal line and connected between the fourth node and the second initialization voltage line; and a storage capacitor disposed between the first driving voltage line and the first node, wherein the initialization voltage applied through the first initialization voltage line varies based on the data voltage applied through the data line (i.e., has different values).

[0012] In addition to the effects described above, those skilled in the art will clearly understand additional advantages and features of this disclosure through the above description. Attached Figure Description

[0013] The above and other objects, features, and other advantages of this disclosure can be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0014] Figure 1 This is a block diagram of a display device according to an embodiment of the present disclosure;

[0015] Figure 2 This is a circuit diagram of the pixel driving circuit and the light-emitting element of a display device according to an embodiment of the present disclosure;

[0016] Figure 3 This is a waveform diagram of the gate signal and the applied voltage of the pixel driving circuit of the display device according to an embodiment of the present disclosure;

[0017] Figures 4A to 4C This is a diagram illustrating the signal voltages of a pixel driving circuit according to an embodiment of the present disclosure;

[0018] Figure 5 This is a waveform diagram of the gate signal and the applied voltage of the pixel driving circuit according to an embodiment of the present disclosure;

[0019] Figure 6This is a waveform diagram of the gate signal and the applied voltage of the pixel driving circuit according to an embodiment of the present disclosure;

[0020] Figure 7 This is a waveform diagram of the gate signal of a pixel driving circuit according to an embodiment of the present disclosure;

[0021] Figure 8 This is a waveform diagram of the gate signal of a pixel driving circuit according to an embodiment of the present disclosure; and

[0022] Figure 9 This is a waveform diagram of the gate signal of a pixel driving circuit according to an embodiment of the present disclosure. Detailed Implementation

[0023] The advantages and features of this disclosure, as well as methods of implementing these advantages and features, will become clear from the following embodiments described with reference to the accompanying drawings. However, this disclosure may be implemented in various forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of this disclosure to those skilled in the art.

[0024] The shapes, dimensions, scales, angles, and quantities disclosed in the accompanying drawings used to describe embodiments of this disclosure are merely examples, and therefore this disclosure is not limited to the details shown. Throughout the specification, the same reference numerals refer to the same elements. In the following description, detailed descriptions of relevant known functions or configurations will be omitted where they are determined to unnecessarily obscure the essential points of this disclosure.

[0025] When using the terms "comprising," "having," and "including" as described in this specification, another component may be added unless the term "only" is used. Singular terms may include plural forms unless explicitly stated otherwise.

[0026] When interpreting a component, even if not explicitly described, the component is interpreted as including a normal error range.

[0027] When describing positional relationships, for example, when the positional relationship is described as "above", "over", "below", and "adjacent", one or more components may be arranged between two other components unless "close to" or "directly" is used.

[0028] When describing temporal relationships, such as when time sequence is described as “after,” “next,” and “before,” non-continuous cases may be included unless “just now” or “directly” is used.

[0029] It should be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements are not limited by these terms. These terms are used only to distinguish one element from another. For example, the term for a first element may be a second element, and similarly, the term for a second element may be a first element, without departing from the scope of this disclosure.

[0030] The term "at least one" should be understood to include any and all combinations of one or more of the related listed items. For example, "at least one of the first, second, and third items" means a combination of all items proposed from two or more of the first, second, and third items, as well as the first, second, or third item.

[0031] As will be fully appreciated by those skilled in the art, the features of the various embodiments of this disclosure may be joined or combined with each other in part or in whole, and may be technically interoperable with and driven by each other in various ways. Embodiments of this disclosure may be performed independently of each other, or may be performed together in an associated relationship.

[0032] In the following, preferred embodiments of the pixel driving circuit and the display device including the pixel driving circuit according to the present disclosure will be described in detail with reference to the accompanying drawings. Wherever possible, the same reference numerals will be used throughout the drawings to refer to the same or similar parts. Since the dimensions of each element shown in the drawings differ from the actual dimensions for ease of description, the present disclosure is not limited to the dimensions shown.

[0033] In this specification, the pixel driving circuit and gate driving circuit formed on the substrate of the display panel can be implemented as N-type transistors or P-type transistors. For example, the transistor can be implemented as a transistor having an N-type or P-type metal-oxide-semiconductor field-effect transistor (MOSFET) structure. A transistor is a three-electrode device including a gate, a source, and a drain. The source and drain of the transistor are not fixed, and the source and drain of the transistor can be changed according to the applied voltage. For example, one of the source or drain may be referred to as the first source / first drain, and the other may be referred to as the second source / second drain, but is not limited thereto.

[0034] The gate signal of a transistor used as a switching element can swing between a gate on-voltage and a gate off-voltage. The gate on-voltage is set to the voltage that turns the transistor on, and the gate off-voltage is set to the voltage that turns the transistor off. In the case of an N-type transistor, the gate on-voltage can be a gate high voltage VGH with a first voltage level, and the gate off-voltage can be a gate low voltage VGL with a second voltage level lower than the gate high voltage VGH. In the case of a P-type transistor, the gate on-voltage can be a gate low voltage VGL with a second voltage level, and the gate off-voltage can be a gate high voltage VGH with a first voltage level.

[0035] Figure 1 This is a block diagram of a display device according to an embodiment of the present disclosure.

[0036] Reference Figure 1 The display device 100 according to an embodiment of the present disclosure may include: a display panel 110, a plurality of data lines DL and a plurality of gate lines GL disposed in the display panel 110, and a plurality of pixels PX connected to the plurality of data lines DL and the plurality of gate lines GL disposed in the display panel 110; and a driving circuit for providing driving signals to the display panel 110.

[0037] Although a plurality of pixels PX are shown arranged in a matrix configuration and forming a pixel array, this disclosure is not limited thereto, and the pixels can be arranged in various configurations.

[0038] The driving circuit may include: a data driving circuit 120 for providing data signals to multiple data lines DL; a gate driving circuit GD for providing gate signals to multiple gate lines GL; and a controller 130 (or timing controller) for controlling the data driving circuit 120 and the gate driving circuit GD.

[0039] The display panel 110 may include: a display area DA for displaying images; and a non-display area NDA disposed around the periphery of the display area DA. The display area DA has multiple pixels PX, a data line DL for providing data signals to the multiple pixels PX, and a gate line GL for providing gate signals.

[0040] Multiple gate lines GL, located in the display area DA, can extend to the non-display area NDA and be electrically connected to the gate drive circuit GD. The gate lines GL electrically connect multiple pixels PX positioned in a first direction (or row direction) to the gate drive circuit GD. Furthermore, gate drive lines that need to generate various gate signals or drive multiple pixels PX can be located in the non-display area NDA. For example, the gate drive lines may include: one or more high-level gate voltage lines for supplying a high-level gate voltage to the gate drive circuit GD; one or more low-level gate voltage lines for supplying a low-level gate voltage to the gate drive circuit GD; multiple clock lines for supplying multiple clock signals to the gate drive circuit GD; and one or more start lines for supplying one or more start signals to the gate drive circuit GD.

[0041] Multiple data lines DL disposed in the display area DA can extend to the non-display area NDA and can be electrically connected to the data driving circuit 120. The data lines DL can electrically connect the data driving circuit 120 to multiple pixels PX disposed in a second direction (or column direction) intersecting the first direction. This can be implemented as a single wiring or by connecting multiple wirings through contact holes using link wires.

[0042] In the display panel 110, multiple data lines DL and multiple gate lines GL are arranged together with the pixel array. As described above, the multiple data lines DL and multiple gate lines GL can be arranged in rows or columns, respectively. For ease of description, it is assumed that the multiple data lines DL are arranged in columns and the multiple gate lines GL are arranged in rows.

[0043] The controller 130 (or timing controller) can start scanning the data signal according to the timing implemented in each frame, convert the input image data from the external input according to the data signal format used in the data driving circuit 120, output the converted image data, and control the data driving circuit 120 at the appropriate time according to the scan.

[0044] The controller 130 can receive timing signals, including vertical synchronization signals, horizontal synchronization signals, input data enable signals, clock signals, and input image data, from external sources. The controller 130, which receives timing signals, can generate and output control signals to control the data drive circuit 120 and the gate drive circuit GD.

[0045] For example, controller 130 can output various data control signals, including source start pulse, source sampling clock, and source output enable signal, to control data drive circuit 120. The source start pulse can control the data sampling start timing of one or more data signal generation circuits constituting data drive circuit 120. The source sampling clock is a clock signal used to control the data sampling timing in each data signal generation circuit. The source output enable signal can control the output timing of data drive circuit 120.

[0046] Furthermore, the controller 130 can output gate control signals, including a gate start pulse, a gate shift clock, and a gate output enable signal, to control the gate drive circuit GD. The gate start pulse controls the start timing of operation of one or more gate signal generation circuits constituting the gate drive circuit GD. The gate shift clock is a clock signal commonly input to one or more gate signal generation circuits, and it controls the shift timing of the scan signal. The gate output enable signal determines the timing information of one or more gate signal generation circuits.

[0047] The controller 130 may be a timing controller used in conventional display device technology or a control device including a timing controller to further perform other control functions.

[0048] The controller 130 may be implemented as a separate component from the data drive circuit 120, or it may be integrated with the data drive circuit 120 and implemented as an integrated circuit.

[0049] The data driving circuit 120 may include one or more data signal generation circuits. These data signal generation circuits may include shift registers, latch circuits, digital-to-analog converters, and output buffers. If necessary, the data signal generation circuits may further include an analog-to-digital converter.

[0050] The data signal generation circuit can be connected to the pads of the display panel 110 via tape-on-absence (TAB), chip-on-glass (COG), or chip-on-panel (COP) methods, or it can be directly mounted on or integrated with the display panel 110. Furthermore, multiple data signal generation circuits can be implemented using a chip-on-film (COF) method, mounting them on a source-circuit film connected to the display panel 110.

[0051] The gate drive circuit GD sequentially supplies gate signals to multiple gate lines GL, thereby driving multiple pixels PX connected to the multiple gate lines GL. The gate drive circuit GD may include shift registers, level shifters, etc.

[0052] The gate drive circuit GD can be connected to the pads of the display panel 110 via a tape-on-absence (TAB) method, a chip-on-glass (COG) method, or a chip-on-panel (COP) method, or it can be implemented using a gate-in-panel (GIP) method and can be directly disposed on the display panel 110. Furthermore, multiple gate signal generation circuits can be mounted on a gate circuit film connected to the display panel 110 and can be implemented using a chip-on-film (COF) method. The gate drive circuit GD can include multiple gate signal generation circuits, and these multiple gate signal generation lines can be implemented using the GIP method and can be disposed in the non-display area NDA of the display panel 110.

[0053] Under the control of controller 130, gate drive circuit GD can sequentially supply a gate signal with a gate high voltage VGH having a first voltage level for turning the transistor on or off, or a gate low voltage VGL having a second voltage level for turning the transistor on or off, to multiple gate lines GL. When a signal is provided to a specific gate line through gate drive circuit GD, data drive circuit 120 can convert image data received from controller 130 into an analog data signal and supply the analog data signal to multiple data lines DL.

[0054] The data driving circuit 120 can be disposed on one side of the display panel 110. For example, the data driving circuit 120 can be disposed on the upper, lower, left, or right side of the display panel 110. Furthermore, depending on the driving method, panel design method, etc., the data driving circuit 120 can be disposed on both sides of the display panel 110. For example, the data driving circuit 120 can be disposed on the upper and lower sides of the display panel 110, or on the left and right sides of the display panel 110.

[0055] The gate driving circuit GD can be disposed on one side of the display panel 110. For example, the gate driving circuit GD can be disposed on the upper, lower, left, or right side of the display panel 110. Furthermore, depending on the driving method, panel design method, etc., the gate driving circuit GD can be disposed on both sides of the display panel 110. For example, the gate driving circuit GD can be disposed on the upper and lower sides of the display panel 110, or on the left and right sides of the display panel 110. The gate driving circuit GD can be formed together with the thin-film transistor of the pixel PX in the left non-display area NDA and / or the right non-display area NDA of the substrate through the manufacturing process of the thin-film transistor of the pixel PX, and can operate according to a single-feed method to supply the gate signal to each of the multiple gate lines GL. Alternatively, the gate driving circuit GD can be formed in the left non-display area NDA and the right non-display area NDA of the substrate respectively, and can operate according to a dual-feed method to supply the gate signal to each of the multiple gate lines GL. Alternatively, the gate drive circuit GD can be formed in each of the left non-display area NDA and the right non-display area NDA of the substrate, and can operate alternately according to the dual-feed method to supply the gate signal to each of the multiple gate lines GL.

[0056] It is explained that multiple gate lines GL in the display panel 110 are arranged in a first direction (or row direction), and multiple data lines DL are arranged in a second direction (or column direction) that intersects the first direction. Therefore, it is assumed that the data driving circuit 120 is arranged on the upper side of the display panel 110, and the gate driving circuit GD is arranged on the left and right sides of the display panel 110.

[0057] The multiple gate lines GL disposed on the display panel 110 may include multiple first gate control lines, multiple second gate control lines, and multiple third gate control lines. The first gate control lines, second gate control lines, and third gate control lines are wirings that transmit different types of gate signals to the gates of different transistors. For example, the first gate control line may be a wiring for transmitting a first light emission control signal, the second gate control line may be a wiring for transmitting a second light emission control signal, and the third gate control line may be a wiring for transmitting a scan signal.

[0058] Therefore, the gate drive circuit GD may include a plurality of first light emission control drive circuits configured to output a first light emission control signal to a first gate control line of the gate line GLD, a plurality of second light emission control drive circuits configured to output a second light emission control signal to a second gate control line, and a plurality of scan drive circuits configured to output a scan signal to a third gate control line.

[0059] A time period during which gate signals, including a first light emission control signal, a second light emission control signal, a scan signal, and a data signal, are supplied to all pixels PX arranged along the second direction (or column direction) of the display area DA can be referred to as a frame period. A frame period can be divided into a scan period for scanning data in each of the gate lines GL connected to the pixel PX and writing the input image data to each pixel PX, and a light emission period after the scan period when the pixel PX is turned on according to the first and second light emission control signals. During the light emission period, the pixel PX can be repeatedly turned on and off. The scan period may include an initialization period, a sampling period, etc. The sampling period may include a programming period. During the scan period, nodes included in the pixel driving circuit are initialized, threshold voltage compensation of the driving transistors is performed, and data voltage is charged. During the light emission period, the light emission operation is performed. The scan period consists of only a few horizontal scan periods, and the light emission period occupies most of a frame period.

[0060] Figure 2 This is a circuit diagram of the pixel driving circuit and the light-emitting element of a display device according to an embodiment of the present disclosure.

[0061] Reference Figure 2 The pixel driving circuit according to embodiments of the present disclosure may include a light-emitting element (ED), a plurality of transistors, and a capacitor.

[0062] like Figure 2 As shown, the pixel driving circuit can be composed of a 7T1C, but is not limited to this. The transistors used in the pixel driving circuit can be P-type transistors, but are not limited to this. For example, the pixel driving circuit can be configured with N-type transistors or a combination of P-type and N-type transistors.

[0063] The pixel driving circuit may include a driving transistor DR for supplying driving current to the light-emitting element ED, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the storage capacitor C.

[0064] The light-emitting element (ED) may include a first electrode (anode or pixel electrode) and a second electrode (cathode or common electrode). The first electrode may correspond to or be connected to the fourth node N4. The second driving voltage EVSS (or common voltage) is a low-potential voltage that can be applied to the second electrode. For example, the ED may be positioned between the fourth node N4 and the line to which the second driving voltage EVSS is applied, and may be electrically connected thereto. For example, the ED may be an organic light-emitting diode (OLED), a light-emitting diode (LED), or a quantum dot light-emitting diode (QLED).

[0065] The driving transistor DR can be connected to a first node N1, a third node N3, and a second node N2, and can be controlled according to the voltage of the second node N2. The driving transistor DR may include a gate, a first source / drain, and a second source / drain. The gate (or gate node) of the driving transistor DR can be connected to the first node N1, the first source / drain can be connected to the second node N2, and the second source / drain can be connected to the third node N3. For example, a first driving voltage EVDD is a high-potential voltage that can be applied to the first source / drain of the driving transistor DR. The second source / drain of the driving transistor DR can be electrically connected to the first electrode (or anode) of the light-emitting element ED. The driving transistor DR can be a P-type thin-film transistor.

[0066] The first transistor T1 can be controlled by a first control signal SN and can be connected between the first node N1 and the third node N3. When the first control signal SN is applied to the first transistor T1, the first transistor T1 can electrically connect the first node N1 and the third node N3 to each other. The first transistor T1 can be an N-type thin-film transistor.

[0067] The second transistor T2 can be controlled by the second control signal SP1 and can be connected between the second node N2 and the line to which the data voltage Vdata is applied. When the second control signal SP1 is applied to the second transistor T2, the second transistor T2 can apply the data voltage Vdata to the second node N2. The second transistor T2 can be a P-type thin-film transistor.

[0068] The third transistor T3 can be controlled by the light emission control signal EM and can be connected between the line to which the first driving voltage EVDD is applied and the second node N2. When the light emission control signal EM is applied to the third transistor T3, the third transistor T3 can apply the first driving voltage EVDD to the second node N2. The third transistor T3 can be a P-type thin-film transistor.

[0069] The fourth transistor T4 can be controlled by the light emission control signal EM and can be connected between the third node N3 and the fourth node N4. When the light emission control signal EM is applied, the fourth transistor T4 can connect the third node N3 and the fourth node N4 to each other. The fourth transistor T4 can be a P-type thin-film transistor.

[0070] The fifth transistor T5 can be controlled by the third control signal SP2 and can be connected between the third node N3 and the line to which the initialization voltage D-Vini is applied. When the third control signal SP2 is applied to the fifth transistor T5, the fifth transistor T5 can apply the initialization voltage D-Vini to the third node N3. The fifth transistor T5 can be a P-type thin-film transistor.

[0071] The sixth transistor T6 can be controlled by the third control signal SP2 and can be connected between the fourth node N4 and the line where the anode reset voltage D-Var is applied. When the third control signal SP2 is applied to the sixth transistor T6, the sixth transistor T6 can apply the anode reset voltage D-Var to the fourth node N4. The sixth transistor T6 can be a P-type thin-film transistor.

[0072] The storage capacitor C can be connected between the second node N2 and the line to which the first drive voltage EVDD is applied. The storage capacitor C can store and hold the data voltage Vdata during one frame.

[0073] Figure 3 This is a waveform diagram of the gate signal and the applied voltage of the pixel driving circuit of a display device according to an embodiment of the present disclosure. Figures 4A to 4C This is a diagram illustrating the signal voltages of a pixel driving circuit according to an embodiment of the present disclosure.

[0074] Combination Figure 2 Reference Figure 3 The driving of the pixel driving circuit according to embodiments of the present disclosure may include an initialization period T1, a sampling period T2, and an emission period T3. Furthermore, at least one conduction bias stress period (hereinafter referred to as "OBS") may be included during any frame.

[0075] The gate signals input to the pixel driving circuit may include a first control signal SN, a second control signal SP1, a third control signal SP2, and a light emission control signal EM.

[0076] During the initialization period T1 and the sampling period T2, the first control signal SN can have a first voltage level. Since the first control signal SN applies a signal to the first transistor T1 corresponding to the N-type thin-film transistor, when the first control signal SN has the first voltage level, the first control signal SN can be the gate turn-on voltage.

[0077] During the sampling period T2, the second control signal SP1 can have a second voltage level lower than the first voltage level. Since the second control signal SP1 applies a signal to the second transistor T2 corresponding to the P-type thin-film transistor, when the voltage level has the second voltage level, the second control signal SP1 can be the gate turn-on voltage.

[0078] During the initialization period T1 and at least one OBS period, the third control signal SP2 may have a second voltage level. Since the third control signal SP2 applies a signal to the fifth transistor T5 and the sixth transistor T6 corresponding to the P-type thin-film transistor, the third control signal SP2 may be the gate turn-on voltage when the voltage level has the second voltage level.

[0079] During the light-emitting period T3, the light-emitting control signal EM can have a second voltage level. Since the light-emitting control signal EM applies a signal to the third transistor T3 and the fourth transistor T4 corresponding to the P-type thin-film transistor, when the voltage level has the second voltage level, the light-emitting control signal EM can be the gate turn-on voltage.

[0080] During the initialization period T1, the first control signal SN can change to a first voltage level, and the third control signal SP2 can change to a second voltage level. At this time, the second control signal SP1 and the light emission control signal EM can remain at the first voltage level. Therefore, the first transistor T1, controlled by the first control signal SN, can be turned on. The fifth transistor T5 and the sixth transistor T6, controlled by the third control signal SP2, can be turned on. The initialization voltage D-Vini can be applied to the first node N1 through the first transistor T1 and the fifth transistor T5, and the anode reset voltage D-Var can be applied to the fourth node N4 through the sixth transistor T6.

[0081] According to embodiments of this disclosure, the initialization voltage D-Vini applied during the initialization period T1 can be varied, i.e., set to a selected value each time and then supplied. The initialization voltage can be set using an image analysis algorithm for analyzing input image data. The initialization voltage is determined using the techniques described in detail herein, and then set to a value suitable for correcting the amount of light to be emitted. Therefore, this value can vary from one conduction moment to another for data pulses applied at different times (i.e., become different values).

[0082] For example, when the grayscale value of the image data is 450 nits, the initialization voltage can be set to -4.5V. When the grayscale value of the image data is 200 nits, the initialization voltage can be set to -4V. When the grayscale value of the image data is 20 nits, the initialization voltage can be set to -3.4V. When the grayscale value of the image data is 0.5 nits, the initialization voltage can be set to -1.5V. However, this specification is not limited to these specific values ​​and can be set according to the specifications of the display device.

[0083] According to embodiments of this disclosure, the initialization voltage applied to the initialization period T1 varies according to the grayscale level of the image data, thereby overcoming flicker when the screen is implemented with a low grayscale level. Specifically, when the OGS voltage for each brightness is used in the same manner, a deviation in the gate-source voltage VGS of the driving transistor DR occurs, which may cause flicker. To reduce the deviation of the gate-source voltage VGS of the driving transistor DR, the initialization voltage D-Vini can be higher for lower grayscale levels corresponding to the image data (data voltage). Flicker is sensitive to low grayscale levels. Therefore, by changing the initialization voltage D-Vini to a low grayscale level at different times, the deviation of the gate-source voltage VGS of the driving transistor DR can be reduced for each brightness, and flicker can be overcome.

[0084] For example, such as Figure 4A As shown, when the grayscale value of the image data is above 200 nits, the initialization voltage can be set to -4.5V, thereby increasing the gate-source voltage VGS of the driving transistor DR and thus overcoming the flickering phenomenon.

[0085] For example, such as Figure 4B As shown, when the grayscale value of the image data is 20 nits, the initialization voltage can be set to -3.5V, thereby increasing the gate-source voltage VGS of the driving transistor DR, thus overcoming the flickering phenomenon.

[0086] For example, such as Figure 4C As shown, when the gray level of the image data is 0.5 nit, the initial voltage can be set to -1.5V, thereby driving the gate-source voltage VGS of the transistor DR to increase, thus overcoming the flickering phenomenon.

[0087] According to embodiments of this disclosure, since the initialization voltage can be selected based on the gray levels of the image data, the device can be driven with the optimal threshold voltage Vth of the driving transistor DR for each gray level level of the image, independent of the gate-source voltage VGS of the driving transistor DR, thereby maintaining an appropriate gate-source voltage VGS that can overcome flicker. That is, the initialization voltage can have different values ​​and will therefore vary from one data driving moment to another.

[0088] After initialization period T1 is executed, the first OBS period OBS1 can then be executed. During OBS1, the third control signal SP2 can change to the second voltage level. Therefore, the fifth transistor T5, controlled by the third control signal SP2, can be turned on, so that the OBS voltage can be applied to the second node N2. The initialization voltage and OBS voltage applied to the source node of the fifth transistor T5 vary depending on the drive period selected.

[0089] When the image data is at a high grayscale level during the operation of the pixel driving circuit, the gate-source voltage VGS of the driving transistor DR may increase, and the threshold voltage Vth of the driving transistor DR may also increase. On the other hand, when the image data is at a low grayscale level, the threshold voltage Vth of the driving transistor DR can be set to a value that is relatively lower than that of the high grayscale level.

[0090] According to embodiments of this disclosure, the OBS period is executed after the initialization period T1. Therefore, when the image data is at a high grayscale level, applying a fixed initialization voltage during the initialization period T1 has little effect. However, when the image data is at a low grayscale level, a large gate-source voltage VGS of the driving transistor DR may have an adverse effect on the low grayscale level.

[0091] According to an embodiment of this disclosure, the pixel driving circuit changes the initialization voltage applied during the initialization period T1, which is executed before the OBS period, to a value set according to the gray level of the image data, and applies the changed value to overcome the flickering phenomenon at low gray level levels.

[0092] During the sampling period T2, the second control signal SP1 can be changed to a second voltage level, and the first control signal SN can be changed to a first voltage level. Therefore, the first transistor T1 and the second transistor T2, controlled by the first control signal SN and the second control signal SP1, can be turned on, so that the data voltage Vdata can be applied to the first node N1.

[0093] After sampling period T2, a second OBS period, OBS2, can be executed to mitigate the hysteresis of the driving transistor DR. During the second OBS period, OBS2, the third control signal SP2 can be changed to the second voltage level. Therefore, the fifth transistor T5 is turned on, allowing the OBS voltage to be applied to the second node N2.

[0094] Subsequently, during the light-emitting period T3, the light-emitting control signal EM can be changed to the second voltage level. Therefore, the third transistor T3 and the fourth transistor T4, controlled by the light-emitting control signal EM, can be turned on, and the drive current controlled by the drive transistor DR can be supplied to the light-emitting element ED, thereby emitting light.

[0095] Figure 5 This is a waveform diagram of the gate signal and the applied voltage of the pixel driving circuit according to an embodiment of the present disclosure.

[0096] Reference Figure 5After the sampling period T2 of the pixel driving circuit according to an embodiment of the present disclosure, when synchronization between the second OBS period OBS2 of the first frame F1 and the third OBS period OBS3 of the second frame F2 is not performed, a difference between the threshold voltage Vth of the driving transistor DR may occur at the beginning of the emission period T3.

[0097] Figure 6 This is a waveform diagram of the gate signal and the applied voltage of the pixel driving circuit according to an embodiment of the present disclosure. Figure 7 This is a waveform diagram of the gate signal of a pixel driving circuit according to an embodiment of the present disclosure. Figure 8 This is a waveform diagram of the gate signal of a pixel driving circuit according to an embodiment of the present disclosure. Figure 9 This is a waveform diagram of the gate signal of a pixel driving circuit according to an embodiment of the present disclosure.

[0098] Reference Figure 6 According to embodiments of the present disclosure, the pixel driving circuit can reduce the difference between the threshold voltage Vth of the driving transistor DR at the beginning of the light emission period T3 by synchronizing the second OBS period OBS2 of the first frame F1 and the third OBS period OBS3 of the second frame F2.

[0099] According to another embodiment of this disclosure, the OBS period of the pixel driving circuit can be set with reference to the threshold voltage Vth of the driving transistor DR.

[0100] The pixel driving circuit can perform synchronization between the second OBS period OBS2 of the first frame F1 and the third OBS period OBS3 of the second frame F2 in various ways. For example, as... Figure 7 As shown, the second OBS period OBS2 of the first frame F1 can be synchronized only with the time point of the third OBS period OBS3 of the second frame F2. For example, as Figure 8 As shown, the second OBS period OBS2 of the first frame F1 can be synchronized with the start point of the third OBS period OBS3 of the second frame F2, and the second OBS period OBS2 and the third OBS period OBS3 can be delayed by 4H. For example, as Figure 9 As shown, the start point of the second OBS period OBS2 in the first frame F1 is synchronized with the start point of the third OBS period OBS3 in the second frame F2, and the second OBS period OBS2 and the third OBS period OBS3 can be delayed by 8H. However, this disclosure is not necessarily limited to this. Considering the threshold voltage of the thin-film transistor DR, the second OBS period and the third OBS period can be changed in various ways. Therefore, according to the appropriate setting of the OBS timing, the deviation of the threshold voltage can be reduced independently of the gate-source voltage VGS of the driving transistor DR.

[0101] The display device according to embodiments of the present disclosure can be described as follows.

[0102] A display device according to embodiments of the present disclosure may include: a light-emitting element; and a pixel driving circuit connected to the light-emitting element and configured to include a first node, a second node, a third node, and a fourth node. The pixel driving circuit may include: a driving transistor connected to the first node, the second node, and the third node; a first transistor connected to a first control signal line and connected to the first node and the third node; a second transistor connected to a second control signal line and connected between the second node and a data line; a third transistor connected to a light-emitting control signal and connected between the second node and a first driving voltage line; a fourth transistor connected to the light-emitting control signal and connected between the third node and the fourth node; a fifth transistor connected to a third control signal line and connected between the third node and a first initialization voltage line; a sixth transistor connected to the third control signal line and connected between the fourth node and a second initialization voltage line; and a storage capacitor disposed between the first driving voltage line and the first node, wherein the initialization voltage applied through the first initialization voltage line may vary based on the data voltage applied through the data line, i.e., selected to different values.

[0103] In a display device according to an embodiment of the present disclosure, the data voltage may be a voltage generated based on an actual image.

[0104] In a display device according to an embodiment of the present disclosure, the data voltage may be a voltage set according to the grayscale level of the actual image.

[0105] In a display device according to an embodiment of the present disclosure, the initialization voltage may be increased as the data voltage becomes a low grayscale level.

[0106] In a display device according to an embodiment of the present disclosure, at least one of the first to sixth transistors and the driving transistor may be of a different type from the other transistors.

[0107] In a display device according to an embodiment of the present disclosure, the first transistor may be an N-type transistor.

[0108] In a display device according to an embodiment of the present disclosure, the second to sixth transistors and the driving transistor may be P-type transistors.

[0109] In a display device according to an embodiment of the present disclosure, the pixel driving circuit can be driven during an initialization period, a sampling period, and an emission period, wherein during the initialization period, the first control signal can have a first voltage level, and the third control signal can have a second voltage level lower than the first voltage level.

[0110] In a display device according to an embodiment of the present disclosure, during the initialization period, the initialization voltage may be applied to the first node.

[0111] In a display device according to an embodiment of the present disclosure, after the initialization period, a conduction bias stress period for applying the initialization voltage to the second node can be executed.

[0112] In a display device according to an embodiment of the present disclosure, the initialization voltage applied during the conduction bias stress period may vary based on image data analysis.

[0113] In a display device according to an embodiment of the present disclosure, the pixel driving circuit may include at least one conduction bias stress period in a frame time period.

[0114] In a display device according to an embodiment of the present disclosure, the conduction bias stress period may be performed after the sampling period.

[0115] In a display device according to an embodiment of the present disclosure, the at least one conduction bias stress period may include: a first conduction bias stress period executed after the initialization period; and a second conduction bias stress period executed after the sampling period.

[0116] In a display device according to an embodiment of the present disclosure, the execution time of the second conduction bias stress period is variable between the sampling period and the emission period.

[0117] In a display device according to an embodiment of the present disclosure, the second conduction bias stress period can be set based on the threshold voltage of the driving transistor.

[0118] In a display device according to an embodiment of the present disclosure, a third conduction bias stress period may also be included, which is executed in the next frame period adjacent to the first frame period.

[0119] In a display device according to an embodiment of the present disclosure, the third conduction bias stress period can be synchronized with the time point of the second conduction bias stress period in the previous frame.

[0120] In a display device according to an embodiment of the present disclosure, the third conduction bias stress period can be synchronized based on changes in the second conduction bias stress period.

[0121] The display device including pixel driving circuitry according to this disclosure can reduce the deviation of the threshold voltage by operating under conduction bias stress, regardless of the gate-source voltage VGS of the driving transistor. Furthermore, by using the optimal initialization voltage for each gray level level according to the image data and optimizing the operating time of the conduction bias stress, flickering at low gray level levels can be overcome.

[0122] It will be apparent to those skilled in the art that various substitutions, modifications, and variations can be made within the scope of this disclosure without departing from its spirit and scope. Therefore, the scope of this disclosure is defined by the following claims, and all variations or modifications derived from the meaning, scope, and equivalents of the claims should be interpreted as including within the scope of this disclosure.

Claims

1. A display device comprising: a light emitting element; and a pixel driving circuit connected to the light emitting element and configured to include a first node, a second node, a third node, and a fourth node, wherein the pixel driving circuit includes: a driving transistor connected to the first node, the second node, and the third node; a first transistor connected to a first control signal line and connected to the first node and the third node; a second transistor connected to a second control signal line and connected between the second node and a data line; a third transistor connected to a light emitting control signal line and connected between the second node and a first driving voltage line; a fourth transistor connected to the light emitting control signal line and connected between the third node and the fourth node; a fifth transistor connected to a third control signal line and connected between the third node and a first initialization voltage line; a sixth transistor connected to the third control signal line and connected between the fourth node and a second initialization voltage line; and a storage capacitor provided between the first driving voltage line and the first node, wherein a value of an initialization voltage applied through the first initialization voltage line varies based on a data voltage applied through the data line, wherein the pixel driving circuit is driven in an initialization period, a sampling period, and a light emitting period, and wherein, after the initialization period, at least one turn-on bias stress period for applying the initialization voltage to the second node is performed. The data voltage is a voltage generated based on an actual image.

2. The display device of claim 1, wherein, The data voltage is a voltage set according to a gray level of the actual image.

3. The display device of claim 2, wherein, The lower the gray level corresponding to the data voltage, the higher the initialization voltage.

4. The display device of claim 3, wherein, At least one of the first to sixth transistors and the driving transistor has a different type from the other transistors.

5. The display device of claim 1, wherein, The first transistor is an N-type transistor.

6. The display device of claim 5, wherein, The second to sixth transistors and the driving transistor are P-type transistors.

7. The display device of claim 5, wherein, In the initialization period, the first control signal has a first voltage level, and the third control signal has a second voltage level lower than the first voltage level.

8. The display device of claim 1, wherein, In the initialization period, the initialization voltage is applied to the first node.

9. The display device of claim 8, wherein, The initialization voltage applied in the at least one turn-on bias stress period is determined based on image data analysis.

10. The display device of claim 1, wherein, The pixel driving circuit includes the at least one turn-on bias stress period in one frame period.

11. The display device of claim 8, wherein, The at least one turn-on bias stress period is performed after the sampling period.

12. The display device of claim 11, wherein, The at least one turn-on bias stress period includes:

13. The display device of claim 11, wherein, a first turn-on bias stress period performed after the initialization period; and a second turn-on bias stress period performed after the sampling period. A timing point of performance of the second turn-on bias stress period is variable between the sampling period and the light emitting period.

14. The display device of claim 13, wherein, The second turn-on bias stress period is set based on a threshold voltage of the driving transistor.

15. The display device of claim 14, wherein, ​ 16. The display device of claim 13, further comprising a third on-bias stress period performed in a next frame period adjacent to the one frame period.

17. The display device of claim 16, wherein, The third on-bias stress period is synchronized in time with the second on-bias stress period of a previous frame.

18. The display device of claim 16, wherein, The third on-bias stress period is synchronized based on a change in the second on-bias stress period.

Images