A display panel and display device

Abstract

The application discloses a display panel and a display device. The display panel comprises a pixel circuit and a light emitting element; the pixel circuit comprises a driving module, a reset module and a compensation module; a first end of the driving module is coupled to the light emitting element, and is used for providing a driving current for the light emitting element; the driving module comprises a driving transistor; the reset module is connected between a reset signal end and a control end of the driving module, and is used for providing a reset signal for the driving module; the compensation module is connected between the control end and the first end of the driving module, and is used for compensating a threshold voltage of the driving transistor; a working process of the pixel circuit comprises a reset stage and a compensation stage; in the reset stage, the reset module is turned on; in the compensation stage, the compensation module is turned on; a part of a time period of the reset stage and a part of a time period of the compensation stage coincide. In the application, the reset signal is written into the three ends of the driving module, so that the ghosting problem during low-frequency display picture switching is improved, and the display effect is improved.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a display panel and a display device. Background Technology

[0002] In a display panel, the pixel circuit provides the driving current required for the light-emitting elements of the display panel and controls whether the light-emitting elements enter the light-emitting stage. It is an indispensable component in most self-emissive display panels.

[0003] In existing display panels, there is a serious ghosting problem when switching images at low frequencies, which affects the display effect. Summary of the Invention

[0004] The present invention provides a display panel and a display device to improve the display effect.

[0005] According to one aspect of the present invention, a display panel is provided, comprising:

[0006] Pixel circuits and light-emitting elements;

[0007] The pixel circuit includes a driving module, a reset module, and a compensation module;

[0008] The first end of the driving module is coupled to the light-emitting element and is used to provide driving current to the light-emitting element. The driving module includes a driving transistor.

[0009] The reset module is connected between the reset signal terminal and the control terminal of the drive module, and is used to provide a reset signal to the drive module;

[0010] The compensation module is connected between the control terminal of the drive module and the first terminal of the drive module, and is used to compensate the threshold voltage of the drive transistor;

[0011] The operation of the pixel circuit includes a reset phase and a compensation phase.

[0012] During the reset phase, the reset module is activated;

[0013] During the compensation phase, the compensation module is activated;

[0014] The time periods of the reset phase and the time periods of the compensation phase overlap.

[0015] According to another aspect of the present invention, a display device is provided, comprising a display panel as described above.

[0016] In this embodiment of the invention, the pixel circuit includes a driving module, a reset module, and a compensation module. The reset module is connected to the reset signal terminal and the control terminal of the driving module, and the compensation module is connected between the control terminal and the first terminal of the driving module. During the reset phase, the reset module is turned on; during the compensation phase, the compensation module is turned on. A portion of the reset phase time overlaps with a portion of the compensation phase time, so the reset signal is sequentially written to the gate, output terminal, and input terminal of the driving transistor. In this embodiment of the invention, the reset signal is written to all three terminals of the driving module, i.e., the same voltage is applied to all three terminals of the driving transistor. This reduces the bias voltage impact of different images on the driving transistor and refreshes the driving current of the driving transistor, thereby eliminating the bias voltage impact of the previous image on the driving transistor, improving the ghosting problem during low-frequency display image switching, and enhancing the display effect.

[0017] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a schematic diagram of a pixel circuit provided in an embodiment of the present invention;

[0020] Figure 2 This is a schematic diagram of another pixel circuit provided in an embodiment of the present invention;

[0021] Figure 3 This is a schematic diagram of a display panel provided in an embodiment of the present invention;

[0022] Figure 4 This is a schematic diagram of another pixel circuit provided in an embodiment of the present invention;

[0023] Figure 5 yes Figure 4 The timing diagram of the pixel circuit shown is shown.

[0024] Figure 6 yes Figure 4 Another timing diagram of the pixel circuit shown;

[0025] Figure 7 yes Figure 4 Another timing diagram of the pixel circuit shown;

[0026] Figure 8 yes Figure 4 Another timing diagram of the pixel circuit shown;

[0027] Figure 9 yes Figure 4 Another timing diagram of the pixel circuit shown;

[0028] Figure 10 yes Figure 4 Another timing diagram of the pixel circuit shown;

[0029] Figure 11 yes Figure 4 Another timing diagram of the pixel circuit shown;

[0030] Figure 12 yes Figure 4 Another timing diagram of the pixel circuit shown;

[0031] Figure 13 yes Figure 4 Another timing diagram of the pixel circuit shown;

[0032] Figure 14 yes Figure 4 Another timing diagram of the pixel circuit shown;

[0033] Figure 15 This is a schematic diagram of another pixel circuit provided in an embodiment of the present invention;

[0034] Figure 16 yes Figure 15 The timing diagram of the pixel circuit shown is shown.

[0035] Figure 17 yes Figure 15 Another timing diagram of the pixel circuit shown;

[0036] Figure 18 This is a schematic diagram of another pixel circuit provided in an embodiment of the present invention;

[0037] Figure 19 This is a schematic diagram of another display panel provided in an embodiment of the present invention;

[0038] Figure 20 This is a schematic diagram of another display panel provided in an embodiment of the present invention;

[0039] Figure 21 yes Figure 20 The timing diagram of the display panel is shown below;

[0040] Figure 22 This is a schematic diagram of another display panel provided in an embodiment of the present invention;

[0041] Figure 23 yes Figure 22 The timing diagram of the display panel is shown below;

[0042] Figure 24 This is a schematic diagram of another display panel provided in an embodiment of the present invention;

[0043] Figure 25 This is a schematic diagram of another display panel provided in an embodiment of the present invention;

[0044] Figure 26 yes Figure 25 The timing diagram of the display panel is shown below;

[0045] Figure 27 This is a schematic diagram of a display device provided in an embodiment of the present invention. Detailed Implementation

[0046] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0047] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0048] Figure 1 This is a schematic diagram of a pixel circuit provided in an embodiment of the present invention. For example... Figure 1As shown, the display panel includes: a pixel circuit 10 and a light-emitting element 20; the pixel circuit 10 includes a driving module 11, a reset module 12, and a compensation module 13; the first terminal N3 of the driving module 11 is coupled to the light-emitting element 20 and is used to provide driving current to the light-emitting element 20; the driving module 11 includes a driving transistor M0; the reset module 12 is connected between the reset signal terminal VREF and the control terminal N1 of the driving module 11 and is used to provide a reset signal to the driving module 11; the compensation module 13 is connected between the control terminal N1 of the driving module 11 and the first terminal N3 of the driving module 11 and is used to compensate for the threshold voltage of the driving transistor M0; the operation of the pixel circuit 10 includes a reset stage and a compensation stage; in the reset stage, the reset module 12 is turned on; in the compensation stage, the compensation module 13 is turned on; a portion of the time period of the reset stage and a portion of the time period of the compensation stage overlap. It should be noted that... Figure 1 The above embodiments only schematically illustrate the key structures and do not include all the structures in which the pixel circuit operates. Other circuit structures of the pixel circuit will be gradually shown in the following description of this embodiment.

[0049] In this embodiment, the pixel circuit 10 includes a driving module 11, which includes a control terminal N1, a first terminal N3, and a second terminal N2. The control terminal N1 of the driving module 11 is connected to the output terminal of the reset module 12. The first terminal N3 of the driving module 11 is coupled to the light-emitting element 20, and the second terminal N2 of the driving module 11 is coupled to the first power supply terminal PVDD. The driving module 11 includes a driving transistor M0. The gate of the driving transistor M0 is connected to the control terminal N1 of the driving module 11. When the driving transistor M0 is a P-type transistor, the input terminal (source) of the driving transistor M0 is connected to the second terminal N2 of the driving module 11, and the output terminal (drain) of the driving transistor M0 is connected to the first terminal N3 of the driving module 11. Here, N1 can also represent the gate of the driving transistor M0, N2 can also represent the input terminal of the driving transistor M0, and N3 can also represent the output terminal of the driving transistor M0. It can be understood that the source and drain of the transistor are not constant, but change with the driving state of the transistor. When the control terminal N1 of the driving module 11 receives a valid pulse signal, the driving transistor M0 is turned on, and the driving module 11 provides driving current to the light-emitting element 20. When the control terminal N1 of the driving module 11 receives an invalid pulse signal, the driving transistor M0 is turned off. Figure 1 As shown, if the drive transistor M0 is a P-type transistor, the effective pulse signal received by the control terminal N1 of the drive module 11 is a low voltage to turn on the drive transistor M0, and the invalid pulse signal received by the control terminal N1 of the drive module 11 is a high voltage to turn off the drive transistor M0.

[0050] In other embodiments, the driving transistor may be an N-type transistor, with its source electrically connected to the first terminal of the driving module and its drain electrically connected to the second terminal of the driving module. In this case, a valid pulse signal received by the control terminal of the driving module is a high voltage to turn on the driving transistor, and an invalid pulse signal received by the control terminal of the driving module is a low voltage to turn off the driving transistor. It is understood that the source and drain of the transistor are not constant but change with the transistor's driving state.

[0051] The pixel circuit 10 includes a reset module 12. The input terminal of the reset module 12 is connected to the reset signal terminal VREF, the control terminal of the reset module 12 is connected to the first scan terminal S1, and the output terminal of the reset module 12 is connected to the control terminal N1 of the drive module 11. The scan signal provided by the first scan terminal S1 is a pulse signal, which includes valid pulses and invalid pulses. If the scan signal provided by the first scan terminal S1 is a valid pulse, the transmission path between the input and output terminals of the reset module 12 is turned on, and the reset signal provided by the reset signal terminal VREF is transmitted to the gate N1 of the drive transistor M0 to control the on / off state of the drive transistor M0. It should be noted that, normally, the reset signal can control the drive transistor to turn on; therefore, the reset signal is transmitted to the gate N1 of the drive transistor M0 to control the drive transistor M0 to turn on. If the scan signal provided by the first scan terminal S1 is an invalid pulse, the transmission path between the input and output terminals of the reset module 12 is turned off. Therefore, the reset module 12 is used to transmit the reset signal provided by the reset signal terminal VREF to the gate N1 of the drive transistor M0 in response to the scan signal from the first scan terminal S1.

[0052] The pixel circuit 10 includes a compensation module 13, which is connected between the control terminal N1 and the first terminal N3 of the driving module 11. The control terminal of the compensation module 13 is connected to the second scanning terminal S2. The scanning signal provided by the second scanning terminal S2 is a pulse signal, which includes valid pulses and invalid pulses. If the scanning signal provided by the second scanning terminal S2 is a valid pulse, the transmission path between the control terminal N1 and the first terminal N3 of the driving module 11 is turned on, and the voltages of the control terminal N1 and the first terminal N3 of the driving module 11 can be adjusted, for example, to compensate the threshold voltage of the driving transistor M0. If the scanning signal provided by the second scanning terminal S2 is an invalid pulse, the transmission path between the control terminal N1 and the first terminal N3 of the driving module 11 is turned off. Therefore, the compensation module 13 is used to compensate the threshold voltage of the driving transistor M0 in response to the scanning signal of the second scanning terminal S2.

[0053] The operation of the pixel circuit 10 includes a reset phase and a compensation phase. During the reset phase, the scan signal provided by the first scan terminal S1 is a valid pulse, enabling the reset module 12. The reset signal provided by the reset signal terminal VREF is then transmitted by the reset module 12 to the gate N1 of the driving transistor M0, controlling the driving transistor M0 to turn on. This achieves the reset of the gate N1 of the driving transistor M0. During the compensation phase, the scan signal provided by the second scan terminal S2 is a valid pulse, enabling the compensation module 13. This allows signal transmission between the control terminal N1 and the first terminal N3 of the driving module 11.

[0054] In this embodiment, a portion of the reset phase and a portion of the compensation phase overlap. During this overlap, the scan signal provided by the first scan terminal S1 and the second scan terminal S2 are both valid pulses, activating the reset module 12 and the compensation module 13. The reset signal provided by the reset signal terminal VREF is then transmitted through the reset module 12 to the gate N1 of the driving transistor M0, activating the driving transistor M0. The reset signal is then transmitted through the compensation module 13 to the output N3 of the driving transistor M0, and finally to the input N2 of the driving transistor M0. The reset signal resets the gate N1 of the driving transistor M0, and also resets the input N2 and output N3 of the driving transistor M0 during the overlap phase. This applies the same voltage to all three terminals of the driving transistor M0, reducing the bias voltage effect of different images on the driving transistor M0 and refreshing the driving current of the driving transistor M0.

[0055] In this embodiment of the invention, the pixel circuit includes a driving module, a reset module, and a compensation module. The reset module is connected to the reset signal terminal and the control terminal of the driving module, and the compensation module is connected between the control terminal and the first terminal of the driving module. During the reset phase, the reset module is turned on; during the compensation phase, the compensation module is turned on. A portion of the reset phase time overlaps with a portion of the compensation phase time, so the reset signal is sequentially written to the gate, output terminal, and input terminal of the driving transistor. In this embodiment of the invention, the reset signal is written to all three terminals of the driving module, i.e., the same voltage is applied to all three terminals of the driving transistor. This reduces the bias voltage impact of different images on the driving transistor and refreshes the driving current of the driving transistor, thereby eliminating the bias voltage impact of the previous image on the driving transistor, improving the ghosting problem during low-frequency display image switching, and enhancing the display effect.

[0056] refer to Figure 1As shown, the optional reset module 12 includes a reset transistor M1, the gate of which is connected to the first scan terminal S1; the reset transistor M1 is a metal-oxide-semiconductor (MOD) transistor, and the driving transistor M0 is a low-temperature polysilicon (LTPS) transistor. The optional compensation module 13 includes a compensation transistor M2, the gate of which is connected to the second scan terminal S2; the compensation transistor M2 is a MOD transistor, and the driving transistor M0 is an LPS transistor. In other embodiments, the optional reset transistor is an LPS transistor, and the driving transistor is a MOD transistor; the optional compensation transistor is an LPS transistor, and the driving transistor is a MOD transistor.

[0057] In this embodiment, the reset module 12 includes a reset transistor M1. The input terminal of the reset transistor M1 is connected to the reset signal terminal VREF, and the output terminal of the reset transistor M1 is connected to the gate N1 of the driving transistor M0. The gate of the reset transistor M1 is connected to the first scan terminal S1. The reset transistor M1 is used to transmit a reset signal to the gate N1 of the driving transistor M0 in response to the scan signal of the first scan terminal S1. Optionally, the reset transistor M1 can be a metal-oxide transistor. Specifically, the metal-oxide transistor can be an indium gallium zinc oxide thin-film transistor (IGZO-TFT). IGZO-TFT is an N-type transistor, which has advantages such as high electron mobility, low leakage current, and small size. When the reset transistor M1 is an N-type transistor, the scan signal provided by the first scan terminal S1 is a high voltage, which can control the reset transistor M1 to conduct; the scan signal provided by the first scan terminal S1 is a low voltage, which can control the reset transistor M1 to be turned off. During the reset phase, the scan signal provided by the first scan terminal S1 is a high voltage, which turns on the reset transistor M1, and the reset signal turns on the driving transistor M0.

[0058] The compensation module 13 includes a compensation transistor M2. The first terminal of the compensation transistor M2 is connected to the gate N1 of the driving transistor M0, and the second terminal of the compensation transistor M2 is connected to the output terminal N3 of the driving transistor M0. The gate of the compensation transistor M2 is connected to the second scan terminal S2. The compensation transistor M2 is used to transmit a signal between the gate N1 and the output terminal N3 of the driving transistor M0 in response to the scan signal from the second scan terminal S2. Optionally, the compensation transistor M2 can be a metal-oxide-semiconductor (MOD) transistor; specifically, it can be an indium gallium zinc oxide (IGZO-TFT). When the compensation transistor M2 is an N-type transistor, a high voltage scan signal provided by the second scan terminal S2 can control the compensation transistor M2 to conduct; a low voltage scan signal provided by the second scan terminal S2 can control the compensation transistor M2 to be turned off. During the compensation phase, a high voltage scan signal provided by the second scan terminal S2 turns the compensation transistor M2 on.

[0059] The driving transistor M0 is a low-temperature polycrystalline silicon (LTPS) transistor, specifically a low-temperature polycrystalline silicon thin-film transistor (LTPS-TFT). LTPS-TFT is a P-type transistor, which has the advantage of high electron mobility, thus improving response speed. Based on this, the reset signal provided by the reset signal terminal VREF is a low voltage, which turns on the driving transistor M0. During the overlapping period of the reset and compensation phases, the scan signal provided by the first scan terminal S1 is a high voltage to turn on the reset transistor M1, and the scan signal provided by the second scan terminal S2 is a high voltage to turn on the compensation transistor M2. The reset signal provided by the reset signal terminal VREF is a low voltage to turn on the driving transistor M0. The reset signal is written to the gate N1, output terminal N3, and input terminal N2 of the driving transistor M0.

[0060] The pixel circuit 10 uses LTPS-TFT and IGZO-TFT, which can combine the advantages of both to achieve higher electron mobility, lower power consumption and higher stability.

[0061] In other embodiments, the reset transistor may be a low-temperature polysilicon transistor and the driving transistor may be a metal-oxide transistor; the compensation transistor may be a low-temperature polysilicon transistor and the driving transistor may be a metal-oxide transistor; if the driving transistor is a metal-oxide transistor, the reset signal provided at the reset signal terminal is a high voltage, and the reset signal turns on the driving transistor.

[0062] Figure 2 This is a schematic diagram of another pixel circuit provided in an embodiment of the present invention. Figure 2 As shown, the control terminal of the optional reset module 12 is connected to the first scanning terminal S1, and the control terminal of the compensation module 13 is connected to the second scanning terminal S2; the first scanning terminal S1 and the second scanning terminal S2 are coupled to the same scanning signal line. In this embodiment, using the same scanning signal line can simultaneously control the on / off state of the reset module 12 and the compensation module 13 in the pixel circuit 10, thus reducing the number of scanning signal lines in the pixel circuit 10 and the corresponding driving circuits in the non-display area, which is beneficial for the display panel to achieve narrow bezels and high resolution.

[0063] Figure 3 This is a schematic diagram of a display panel provided in an embodiment of the present invention. Figure 3As shown, the display panel includes a display area 21 and a non-display area 22 located around the display area 21. The display area 21 includes multiple pixel circuits 10 and multiple scan signal lines 23. Optionally, the multiple pixel circuits 10 can be arranged in an array, with one scan signal line 23 connecting to a row of pixel circuits 10, but the arrangement of the pixel circuits is not limited to this. The non-display area 22 includes a set of cascaded shift registers 24. The output of the shift registers 24 is connected to the scan signal lines 23, and the output of the shift registers 24 provides scan signals to the scan signal lines 23. Optionally, the display panel can perform row-by-row scanning, in which case the cascaded shift registers 24 sequentially provide valid pulses to the multiple scan signal lines 23 along the column direction. Optionally, the scan signal line 23 shown in the figure can be connected to the control terminal of the reset module 12 in the corresponding row of pixel circuits 10, i.e., the first scan terminal S1, and also connected to the control terminal of the compensation module 13 in the same row of pixel circuits 10, i.e., the second scan terminal S2. In this case, the scan signal line 23 simultaneously controls the on / off state of the reset module 12 and the compensation module 13 in the pixel circuits 10.

[0064] As described above, the reset module 12 includes a reset transistor M1, and the compensation module 13 includes a compensation transistor M2. Both the reset transistor M1 and the compensation transistor M2 can be IGZO-TFT. When the output of the shift register 23 provides a high voltage to the scan signal line 23, the reset transistor M1 and the compensation transistor M2 in the control pixel circuit 10 are simultaneously turned on. The time periods of the reset phase and the compensation phase completely overlap. The reset signal provided by the reset signal terminal VREF is written to the gate N1 of the driving transistor M0 through the reset transistor M1, then to the output N3 of the driving transistor M0 through the compensation transistor M2, and finally to the input N2 of the driving transistor M0, thus resetting the gate N1, output N3, and input N2 of the driving transistor M0. When the output of the shift register 23 provides a low voltage to the scan signal line 23, the reset transistor M1 and the compensation transistor M2 in the control pixel circuit 10 are simultaneously turned off. In other embodiments, both the reset transistor and the compensation transistor can be LTPS-TFT.

[0065] In pixel circuit 10, the first scan terminal S1 and the second scan terminal S2 are coupled to the same scan signal line 23. That is, the gate of reset transistor M1 and the gate of compensation transistor M2 are connected to the same scan signal line 23. This reduces the number of scan signal lines in pixel circuit 10, thereby reducing the layout size of pixel circuit 10 and improving the resolution of the display panel. In non-display area 22, a shift register 24 provides scan signals to the reset module 12 and compensation module 13 in pixel circuit 10 through a scan signal line 23. Therefore, at least one scan signal line is omitted in pixel circuit 10. Consequently, a set of driving circuits in non-display area 22 that is connected to the original scan signal line and used to provide scan signals to the scan signal line is also omitted. This reduces the bezel size of the display panel and achieves a narrow bezel for the display panel.

[0066] Figure 4 This is a schematic diagram of another pixel circuit provided in an embodiment of the present invention. Figure 4 As shown, the optional pixel circuit 10 also includes a first data writing module 14; the first data writing module 14 is connected between the data signal terminal VDATA and the second terminal N2 of the driving module 11, and the control terminal of the first data writing module 14 is connected to the third scanning terminal S3; the working process of the pixel circuit 10 includes a first data writing stage; in the first data writing stage, the first data writing module 14 is turned on.

[0067] In this embodiment, the pixel circuit 10 includes a first data writing module 14. The input terminal of the first data writing module 14 is connected to the data signal terminal VDATA, the control terminal of the first data writing module 14 is connected to the third scanning terminal S3, and the output terminal of the first data writing module 14 is connected to the second terminal N2 of the driving module 11. The scanning signal provided by the third scanning terminal S3 is a pulse signal, which includes valid pulses and invalid pulses. If the scanning signal provided by the third scanning terminal S3 is a valid pulse, the transmission path between the input and output terminals of the first data writing module 14 is turned on, and the data signal provided by the data signal terminal VDATA is transmitted to the input terminal N2 of the driving transistor M0 through the first data writing module 14. If the scanning signal provided by the third scanning terminal S3 is an invalid pulse, the transmission path between the input and output terminals of the first data writing module 14 is turned off. Therefore, the first data writing module 14 is used to transmit the data signal provided by the data signal terminal VDATA to the input terminal N2 of the driving transistor M0 in response to the scanning signal of the third scanning terminal S3.

[0068] Optional first data writing module 14 includes a first data writing transistor M3. The gate of the first data writing transistor M3 is connected to the third scan terminal S3, the input terminal of the first data writing transistor M3 is connected to the data signal terminal VDATA, and the output terminal of the first data writing transistor M3 is connected to the input terminal N2 of the driving transistor M0. Optionally, the first data writing transistor M3 can be a low-temperature polycrystalline silicon transistor (LTPS-TFT). When the first data writing transistor M3 is a P-type transistor, a low-voltage scan signal provided by the third scan terminal S3 can control the first data writing transistor M3 to conduct; a high-voltage scan signal provided by the third scan terminal S3 can control the first data writing transistor M3 to be cut off. During the first data writing stage, a low-voltage scan signal provided by the third scan terminal S3 turns on the first data writing transistor M3, and the data signal is written to the input terminal N2 of the driving transistor M0. In other embodiments, the first data writing transistor can be an alloy-oxide-semiconductor transistor (AMET).

[0069] refer to Figure 3 As shown, the display area 21 also includes multiple data signal lines 25. Each data signal line 25 is connected to the data signal terminal VDATA of a column of pixel circuits 10. The data signal line 25 provides data signals to each pixel circuit 10 in a column in a time-division manner. Therefore, the data signal received by the data signal terminal VDATA of a pixel circuit 10 is the data signal required by the pixel circuit 10 in this row or the data signal required by the pixel circuit in another row.

[0070] Taking the first row pixel circuit 10 as an example. If the data signal line 25 provides the data signal required by the first row pixel circuit 10, then the scan signal provided by the third scan terminal S3 of the first row pixel circuit 10 is a valid pulse to turn on the first data writing module 14 of the first row pixel circuit 10, and the data signal is written to the input terminal N2 of the driving transistor M0 of the first row pixel circuit 10. If the data signal line 25 provides the data signal required by other row pixel circuits, then the scan signal provided by the third scan terminal S3 of the first row pixel circuit 10 is an invalid pulse to turn off the first data writing module 14 of the first row pixel circuit 10, and the data signals of other row pixel circuits will not be written to the input terminal N2 of the driving transistor M0 of the first row pixel circuit 10.

[0071] Therefore, the first data writing stage of the pixel circuit 10 is the stage of writing the data signal of the pixel circuit 10 in this row. During the first data writing stage, the scanning signal provided by the third scanning terminal S3 is an effective pulse to turn on the first data writing module 14, and the data signal of the pixel circuit 10 in this row is written to the input terminal N2 of the driving transistor M0.

[0072] Optionally, the first data writing phase may occur after the reset phase, and a portion of the compensation phase may overlap with the first data writing phase. Optionally, the reset phase may begin earlier than the compensation phase. Figure 5 yes Figure 4 The timing diagram of the pixel circuit is shown. It should be noted that in this embodiment, only the timing of one row of pixel circuit 10 is described as an example. The first scan terminal S1 provides a scan signal to the control terminal of the reset module 12, the second scan terminal S2 provides a scan signal to the control terminal of the compensation module 13, and the third scan terminal S3 provides a scan signal to the control terminal of the first data writing module 14. The driving transistor M0 and the first data writing transistor M3 are both LTPS-TFT, and the reset transistor M1 and the compensation transistor M2 are both IGZO-TFT. The reset signal voltage provided by the reset signal terminal VREF is relatively low, for example, -7V; the data signal voltage provided by the data signal terminal VDATA is relatively high, for example, the data signal range is 0V to +5V.

[0073] refer to Figure 4 and Figure 5 As shown, the pixel circuit 10 includes a reset phase t11-t12, a compensation phase t12-t15, and a first data writing phase t14. The overlap time between the reset phase t11-t12 and the compensation phase t12-t15 is t12.

[0074] During the reset phase t11, the first scan terminal S1 provides a high voltage, turning on the reset transistor M1; the second scan terminal S2 provides a low voltage, turning off the compensation transistor M2; and the third scan terminal S3 provides a high voltage, turning off the first data writing transistor M3. The reset signal provided by the reset signal terminal VREF is then written to the gate N1 of the driving transistor M0 through the reset transistor M1, turning on the driving transistor M0. The reset of the gate N1 of the driving transistor M0 reduces the bias voltage effect of the previous frame, improving the ghosting problem.

[0075] During the reset phase t12, reset transistor M1 remains on; the second scan terminal S2 provides a high voltage, turning on compensation transistor M2; the first data write transistor M3 remains off; and the drive transistor M0 remains on. The reset signal is written to the gate N1 of drive transistor M0 through reset transistor M1, then to the output N3 of drive transistor M0 through compensation transistor M2, and finally to the input N2 of drive transistor M0. This achieves the reset of the three terminals of drive transistor M0: gate N1, input N2, and output N3. Applying the same voltage to the three terminals of drive transistor M0 eliminates the bias effects caused by other images.

[0076] During the compensation phase t13, the first scan terminal S1 provides a low voltage, causing the reset transistor M1 to be turned off; the compensation transistor M2 remains on; the first data writing transistor M3 remains off; and the drive transistor M0 remains on. This stabilizes the voltage across the three terminals of the drive transistor M0, further eliminating the bias effects caused by other images.

[0077] During the first data writing phase t14, the reset transistor M1 remains off; the compensation transistor M2 remains on; the third scan terminal S3 provides a low voltage, turning on the first data writing transistor M3; the drive transistor M0 remains on, and the data signal provided by the data signal terminal VDATA is written to the input terminal N2 of the drive transistor M0 through the first data writing transistor M3, then to the output terminal N3 of the drive transistor M0, and finally to the gate N1 of the drive transistor M0 through the compensation transistor M2. The potential of node N1 changes until the drive transistor M0 is turned off. The data signal required by the pixel circuit 10 of this row is written to the three terminals of the drive transistor M0.

[0078] During the compensation phase t15, the reset transistor M1 remains off; the compensation transistor M2 remains on; the first data writing transistor M3 is off; and the drive transistor M0 remains off. This stabilizes the voltage across the three terminals of the drive transistor M0, further eliminating the bias effects caused by other images.

[0079] In this embodiment, before the data signal of the pixel circuit 10 is written, the voltage of the three terminals of the driving transistor M0 is the same, which can eliminate the bias voltage effect of the previous image. Regardless of whether the previous image is black or white, the bias voltage effect caused by it can be avoided, thus improving the ghosting problem when switching low-frequency display images and enhancing the display effect.

[0080] The optional pixel circuit's operation includes a second data writing phase; the start time of the second data writing phase is later than or equal to the start time of the reset phase, and the end time of the second data writing phase is earlier than or equal to the start time of the compensation phase. Figure 6 yes Figure 4 Another timing diagram of the pixel circuit shown is... Figure 5 The difference lies in the fact that the operation of the pixel circuit 10 includes a second data writing stage t11a. The overlap time between the reset stage t11~t12 and the second data writing stage t11a is t11a, and the second data writing stage t11a does not overlap with the compensation stage t12~t15.

[0081] During the reset phase t11, reset transistor M1 is turned on, compensation transistor M2 is turned off, and the reset signal is written to the gate N1 of driving transistor M0 through reset transistor M1, turning driving transistor M0 on; the first data writing transistor M3 is turned on for a partial time period. During the second data writing phase t11a, the first data writing transistor M3 is turned on, and driving transistor M0 remains on. At this time, the data signal provided by the data signal terminal VDATA is the data signal of other row pixel circuits, and this data signal is sequentially written to the input terminal N2 and the output terminal N3 of driving transistor M0 through the first data writing transistor M3. When driving transistor M0 is a P-type transistor, the reset signal is a low voltage and the data signal is a high voltage, so driving transistor M0 is negatively biased, which can eliminate the positive bias effect of the previous frame and improve the ghosting problem.

[0082] In this embodiment, before writing the data signal for the current row, the driving transistor M0 is subjected to a negative bias voltage to eliminate the bias voltage effect of the previous image on the driving transistor M0.

[0083] The optional compensation phases include a first compensation phase and a second compensation phase with interval settings; a portion of the time period of the reset phase overlaps with a portion of the time period of the first compensation phase, and a portion of the time period of the second compensation phase overlaps with the first data writing phase. Figure 7 yes Figure 4 This is another timing diagram of the pixel circuit shown. (Reference) Figure 4 and Figure 7 As shown, the pixel circuit 10 includes a reset phase t21-t22, a compensation phase, and a first data writing phase t26. The compensation phase includes a first compensation phase t22-t23 and a second compensation phase t25, which are set at intervals. The overlap time between the reset phase t21-t22 and the first compensation phase t22-t23 is t22.

[0084] In this embodiment, during the reset phase t21, the reset transistor M1 is turned on, the compensation transistor M2 is turned off, the first data writing transistor M3 is turned off, and the driving transistor M0 is turned on; the reset signal is written to the gate N1 of the driving transistor M0 through the reset transistor M1.

[0085] During the reset phase t22, reset transistor M1 remains on, compensation transistor M2 is on, first data write transistor M3 remains off, and drive transistor M0 remains on. The reset signal is written to the gate N1, input terminal N2, and output terminal N3 of drive transistor M0. Applying the same voltage to all three terminals of drive transistor M0 eliminates the bias effects caused by other images.

[0086] During the first compensation phase t23, the reset transistor M1 is turned off, the compensation transistor M2 remains on, the first data writing transistor M3 remains off, and the driving transistor M0 remains on. In other embodiments, a portion of the reset phase may be multiplexed as the first compensation phase.

[0087] During the interval t24 between the first compensation stage t23 and the second compensation stage t25, the reset transistor M1 remains off, the compensation transistor M2 remains off, the first data write transistor M3 remains off, and the drive transistor M0 remains on.

[0088] During the second compensation phase t25, the reset transistor M1 remains off, the compensation transistor M2 is on, and the first data writing transistor M3 is on for a partial time period. During the first data writing phase t26, the first data writing transistor M3 is on, and the data signal of the pixel circuit 10 is written to the three terminals of the driving transistor M0, causing the driving transistor M0 to switch from the on state to the off state. In other embodiments, the second compensation phase may be multiplexed as the first data writing phase.

[0089] As described above, before the data signal of the pixel circuit 10 is written, a reset signal is written to the three terminals of the driving transistor M0, that is, the three terminals of the driving transistor M0 are applied with the same voltage, so the bias voltage effect of the previous image can be eliminated. Regardless of whether the previous image is black or white, the bias voltage effect caused by it can be avoided, improving the ghosting problem when switching low-frequency display images and enhancing the display effect.

[0090] The optional pixel circuit's operation includes a second data writing phase; the start time of the second data writing phase is later than or equal to the start time of the reset phase, and the end time of the second data writing phase is earlier than or equal to the start time of the compensation phase. Figure 8 yes Figure 4 The diagram shows another timing sequence of the pixel circuit, and... Figure 7The difference lies in the fact that the operation of the pixel circuit 10 includes a second data writing stage t21a. The overlap time between the reset stage t21~t22 and the second data writing stage t21a is t21a. The second data writing stage t21a does not overlap with the first compensation stage t22~t23, and the second data writing stage t21a does not overlap with the second compensation stage t25. If the start time of the second data writing stage is later than the start time of the reset stage, the time interval between the start time of the second data writing stage and the start time of the reset stage is set to be at least an even number of H, such as 2H, where 2H is the difference between the reset start time of adjacent row pixel circuits. For example, when the nth row pixel circuit performs the reset stage, the (n-2)th row pixel circuit performs the second data writing stage. This is beneficial for one scan driving unit to drive two rows of pixel circuits in a one-to-two manner, which can achieve a narrow bezel and high resolution of the display panel. However, it is not limited to this. For example, if the time interval between the start time of the second data writing stage and the start time of the reset stage is set to be at least an odd number of H, such as 1H, then when the nth row pixel circuit performs the reset stage, the (n-1)th row pixel circuit performs the second data writing stage.

[0091] During the reset phase t21, reset transistor M1 is turned on, compensation transistor M2 is turned off, and the reset signal is written to the gate N1 of driving transistor M0 through reset transistor M1, turning driving transistor M0 on; the first data writing transistor M3 is turned on for a partial time period. During the second data writing phase t21a, the first data writing transistor M3 is turned on, and driving transistor M0 remains on. At this time, the data signal provided by the data signal terminal VDATA is the data signal of other row pixel circuits, and this data signal is sequentially written to the input terminal N2 and the output terminal N3 of driving transistor M0 through the first data writing transistor M3. When driving transistor M0 is a P-type transistor, the reset signal is a low voltage and the data signal is a high voltage, so driving transistor M0 is negatively biased, which can eliminate the positive bias effect of the previous frame and improve the ghosting problem.

[0092] In this embodiment, before writing the data signal for the current row, the driving transistor M0 is subjected to a negative bias voltage to eliminate the bias voltage effect of the previous image on the driving transistor M0.

[0093] The optional reset phase also overlaps with a portion of the second compensation phase. Figure 9 yes Figure 4 This is another timing diagram of the pixel circuit shown. (Reference) Figure 4 and Figure 9As shown, the pixel circuit 10 includes a reset phase t31-t34, a compensation phase, and a first data writing phase t36. The compensation phase includes a first compensation phase t32 and a second compensation phase t34-t35, which are set at intervals. The overlap time between the reset phase t31-t34 and the first compensation phase t32 is t32, and the overlap time between the reset phase t31-t34 and the second compensation phase t34-t35 is t34.

[0094] In this embodiment, during the reset phase t31, the reset transistor M1 is turned on, the compensation transistor M2 is turned off, the first data writing transistor M3 is turned off, and the driving transistor M0 is turned on; the reset signal is written to the gate N1 of the driving transistor M0 through the reset transistor M1.

[0095] During the reset phase t32, reset transistor M1 remains on, compensation transistor M2 is on, first data write transistor M3 remains off, and drive transistor M0 remains on. The reset signal is written to the gate N1, input terminal N2, and output terminal N3 of drive transistor M0. Applying the same voltage to all three terminals of drive transistor M0 eliminates the bias effects caused by other images.

[0096] During the reset phase t33, the reset transistor M1 remains on, the compensation transistor M2 is off, the first data writing transistor M3 remains off, and the driving transistor M0 remains on; the reset signal is written to the gate N1 of the driving transistor M0 through the reset transistor M1.

[0097] During the reset phase t34, reset transistor M1 remains on, compensation transistor M2 is on, first data write transistor M3 remains off, and drive transistor M0 remains on. The reset signal is written to the gate N1, input terminal N2, and output terminal N3 of drive transistor M0. This achieves a secondary reset of the three terminals of drive transistor M0.

[0098] During the second compensation phase t35, the reset transistor M1 is turned off, the compensation transistor M2 remains on, and the first data writing transistor M3 is on for a partial time period. During the first data writing phase t36, the first data writing transistor M3 is on, and the data signal of the pixel circuit 10 is written to the three terminals of the driving transistor M0, causing the driving transistor M0 to switch from the on state to the off state.

[0099] As described above, before writing the data signal to the pixel circuit 10, the three terminals of the driving transistor M0 are reset twice, which can avoid the bias voltage effect caused by different display screens, improve the ghosting problem when switching low-frequency display screens, and enhance the display effect.

[0100] The optional pixel circuit's operation includes a second data writing phase; the start time of the second data writing phase is later than or equal to the start time of the reset phase, and the end time of the second data writing phase is earlier than or equal to the start time of the compensation phase. Figure 10 yes Figure 4 The diagram shows another timing sequence of the pixel circuit, and... Figure 9 The difference lies in that the operation of the pixel circuit 10 includes a second data writing stage t31a. The overlap time between the reset stage t31~t34 and the second data writing stage t31a is t31a. The second data writing stage t31a does not overlap with the first compensation stage t32, and the second data writing stage t31a does not overlap with the second compensation stages t34~t35.

[0101] During the reset phase t31, reset transistor M1 is turned on, compensation transistor M2 is turned off, and the reset signal is written to the gate N1 of driving transistor M0 through reset transistor M1, turning driving transistor M0 on; the first data writing transistor M3 is turned on for a partial time period. During the second data writing phase t31a, the first data writing transistor M3 is turned on, and driving transistor M0 remains on. At this time, the data signal provided by the data signal terminal VDATA is the data signal of other row pixel circuits, and this data signal is sequentially written to the input terminal N2 and the output terminal N3 of driving transistor M0 through the first data writing transistor M3. When driving transistor M0 is a P-type transistor, the reset signal is a low voltage and the data signal is a high voltage, so driving transistor M0 is negatively biased, which can eliminate the positive bias effect of the previous frame and improve the ghosting problem.

[0102] In this embodiment, the driving transistor M0 is reset twice before the current data signal is written to eliminate the bias effect of the previous image on the driving transistor M0.

[0103] The optional reset phase includes a first reset phase and a second reset phase with interval settings; a portion of the time period of the first reset phase overlaps with a portion of the time period of the compensation phase; a portion of the time period of the compensation phase is reused as the second reset phase. Figure 11 yes Figure 4 This is another timing diagram of the pixel circuit shown. (Reference) Figure 4 and Figure 11 As shown, the pixel circuit 10 includes a reset phase, compensation phases t42-t45, and a first data writing phase t46. The reset phase includes a first reset phase t41-t42 and a second reset phase t44, which are set at intervals. The overlap time between the first reset phase t41-t42 and the compensation phase t42-t45 is t42, and the overlap time between the second reset phase t44 and the compensation phase t42-t45 is t44.

[0104] In this embodiment, during the first reset phase t41, the reset transistor M1 is turned on, the compensation transistor M2 is turned off, the first data writing transistor M3 is turned off, and the driving transistor M0 is turned on; the reset signal is written to the gate N1 of the driving transistor M0 through the reset transistor M1.

[0105] During the first reset phase t42, reset transistor M1 remains on, compensation transistor M2 is on, first data write transistor M3 remains off, and drive transistor M0 remains on. The reset signal is written to the gate N1, input terminal N2, and output terminal N3 of drive transistor M0. Applying the same voltage to all three terminals of drive transistor M0 eliminates the bias effects caused by other images.

[0106] During the interval t43 between the first reset phase t42 and the second reset phase t44, the reset transistor M1 is turned off, the compensation transistor M2 remains on, the first data write transistor M3 remains off, and the drive transistor M0 remains on.

[0107] During the second reset phase t44, reset transistor M1 is turned on, compensation transistor M2 remains on, first data write transistor M3 remains off, and drive transistor M0 remains on. A reset signal is written to the gate N1, input terminal N2, and output terminal N3 of drive transistor M0. This achieves a secondary reset of the three terminals of drive transistor M0.

[0108] During the compensation phase t45, the reset transistor M1 is turned off, the compensation transistor M2 remains on, and the first data writing transistor M3 is on for a partial time period. During the first data writing phase t46, the first data writing transistor M3 is on, and the data signal of the pixel circuit 10 in this row is written to the three terminals of the driving transistor M0, at which point the driving transistor M0 switches from the on state to the off state.

[0109] As described above, before writing the data signal to the pixel circuit 10, the three terminals of the driving transistor M0 are reset twice, which can avoid the bias voltage effect caused by different display screens, improve the ghosting problem when switching low-frequency display screens, and enhance the display effect.

[0110] The optional pixel circuit operates by including a second data writing phase; the start time of the second data writing phase is later than or equal to the start time of the reset phase, and the end time of the second data writing phase is earlier than or equal to the start time of the compensation phase. The optional pixel circuit also operates by including a third data writing phase; the third data writing phase is located between the first and second reset phases, and a portion of the compensation phase time is multiplexed as the third data writing phase. Figure 12 yes Figure 4 The diagram shows another timing sequence of the pixel circuit, and... Figure 11The difference lies in the fact that the operation of the pixel circuit 10 includes a second data writing stage t41a, the overlap time between the first reset stage t41-t42 and the second data writing stage t41a is t41a, and the second data writing stage t41a does not overlap with the compensation stage t42-t45. The operation of the pixel circuit 10 includes a third data writing stage t43a, the overlap time between the compensation stage t42-t45 and the third data writing stage t43a is t43a.

[0111] During the first reset phase t41, reset transistor M1 is turned on, compensation transistor M2 is turned off, and the reset signal is written to the gate N1 of driving transistor M0 through reset transistor M1, turning driving transistor M0 on; first data writing transistor M3 is turned on for a partial time period. During the second data writing phase t41a, first data writing transistor M3 is turned on, and driving transistor M0 remains on. At this time, the data signal provided by the data signal terminal VDATA is the data signal of other row pixel circuits, and this data signal is sequentially written to the input terminal N2 and output terminal N3 of driving transistor M0 through first data writing transistor M3. When driving transistor M0 is a P-type transistor, the reset signal is a low voltage and the data signal is a high voltage, so driving transistor M0 is negatively biased, which can eliminate the positive bias effect of the previous frame and improve the ghosting problem.

[0112] During the third data writing phase t43a, reset transistor M1 is off, compensation transistor M2 is on, drive transistor M0 remains on, and first data writing transistor M3 is on. At this time, the data signal provided by the data signal terminal VDATA is the data signal of the current row pixel circuit 10. This data signal is then sequentially written to the input terminal N2, output terminal N3, and gate N1 of drive transistor M0 through the first data writing transistor M3 and compensation transistor M2, causing drive transistor M0 to switch from on to off. By applying a data signal writing operation for the current frame to drive transistor M0, the influence of the previous frame is further reduced. A positive bias voltage is applied to drive transistor M0 to eliminate the bias voltage effect of the previous frame on drive transistor M0.

[0113] In this embodiment, before writing the data signal for the current row, the driving transistor M0 is reset multiple times and written at least once to eliminate the bias effect of the previous screen on the driving transistor M0.

[0114] The optional reset phase includes a first reset phase and a second reset phase with interval settings; a portion of the time period of the first reset phase overlaps with a portion of the time period of the first compensation phase; a portion of the time period of the second reset phase overlaps with a portion of the time period of the first compensation phase. Figure 13 yes Figure 4 This is another timing diagram of the pixel circuit shown. (Reference) Figure 4 and Figure 13 As shown, the pixel circuit 10 includes a reset stage, a compensation stage, and a first data writing stage t58. The reset stage includes a first reset stage t51-t52 and a second reset stage t54-t55 spaced apart. The compensation stage includes a first compensation stage t52-t54 and a second compensation stage t57 spaced apart. The overlap time between the first reset stage t51-t52 and the first compensation stage t52-t54 is t52, and the overlap time between the second reset stage t54-t55 and the first compensation stage t52-t54 is t54.

[0115] In this embodiment, during the first reset phase t51, the reset transistor M1 is turned on, the compensation transistor M2 is turned off, the first data writing transistor M3 is turned off, and the driving transistor M0 is turned on; the reset signal is written to the gate N1 of the driving transistor M0 through the reset transistor M1.

[0116] During the first reset phase t52, reset transistor M1 remains on, compensation transistor M2 is on, first data write transistor M3 remains off, and drive transistor M0 remains on. The reset signal is written to the gate N1, input terminal N2, and output terminal N3 of drive transistor M0. Applying the same voltage to all three terminals of drive transistor M0 eliminates the bias effects caused by other images.

[0117] During the interval t53 between the first reset phase t52 and the second reset phase t54, the reset transistor M1 is turned off, the compensation transistor M2 remains on, the first data write transistor M3 remains off, and the drive transistor M0 remains on.

[0118] During the second reset phase t54, reset transistor M1 is turned on, compensation transistor M2 remains on, first data write transistor M3 remains off, and drive transistor M0 remains on. A reset signal is written to the gate N1, input terminal N2, and output terminal N3 of drive transistor M0. This achieves a secondary reset of the three terminals of drive transistor M0.

[0119] During the second reset phase t55, the reset transistor M1 remains on, the compensation transistor M2 is off, the first data write transistor M3 remains off, the drive transistor M0 remains on, and the reset signal is written to the gate N1 of the drive transistor M0.

[0120] During the interval t56 between the second reset phase t55 and the second compensation phase t57, the reset transistor M1 is turned off, the compensation transistor M2 remains turned off, the first data writing transistor M3 remains turned off, and the drive transistor M0 remains turned on.

[0121] During the second compensation phase t57, the reset transistor M1 remains off, the compensation transistor M2 is on, and the first data writing transistor M3 is on for a partial time period. During the first data writing phase t58, the first data writing transistor M3 is on, and the data signal of the pixel circuit 10 is written to the three terminals of the driving transistor M0, causing the driving transistor M0 to switch from the on state to the off state. In other embodiments, the second compensation phase may be multiplexed as the first data writing phase.

[0122] As described above, before writing the data signal to the pixel circuit 10, the three terminals of the driving transistor M0 are reset twice, which can avoid the bias voltage effect caused by different display screens, improve the ghosting problem when switching low-frequency display screens, and enhance the display effect.

[0123] The optional pixel circuit operates by including a second data writing phase; the start time of the second data writing phase is later than or equal to the start time of the reset phase, and the end time of the second data writing phase is earlier than or equal to the start time of the compensation phase. The optional pixel circuit also operates by including a third data writing phase; the third data writing phase is located between the first and second reset phases, and a portion of the compensation phase time is multiplexed as the third data writing phase. Figure 14 yes Figure 4 The diagram shows another timing sequence of the pixel circuit, and... Figure 13 The difference lies in that the operation of the pixel circuit 10 includes a second data writing stage t51a, the overlap time between the first reset stage t51-t52 and the second data writing stage t51a is t51a, and the second data writing stage t51a does not overlap with the first compensation stage t52-t54. The operation of the pixel circuit 10 includes a third data writing stage t53a, the overlap time between the first compensation stage t52-t54 and the third data writing stage t53a is t53a.

[0124] During the first reset phase t51, reset transistor M1 is turned on, compensation transistor M2 is turned off, and the reset signal is written to the gate N1 of driving transistor M0 through reset transistor M1, turning on driving transistor M0; the first data writing transistor M3 is turned on for a partial time period. During the second data writing phase t51a, the first data writing transistor M3 is turned on, and driving transistor M0 remains turned on. At this time, the data signal provided by the data signal terminal VDATA is the data signal of other row pixel circuits, and this data signal is sequentially written to the input terminal N2 and the output terminal N3 of driving transistor M0 through the first data writing transistor M3. When driving transistor M0 is a P-type transistor, the reset signal is a low voltage and the data signal is a high voltage, so driving transistor M0 is negatively biased, which can eliminate the positive bias effect of the previous frame and improve the ghosting problem.

[0125] During the third data writing stage t53a, reset transistor M1 is turned off, compensation transistor M2 is turned on, drive transistor M0 remains on, and first data writing transistor M3 is turned on. At this time, the data signal provided by the data signal terminal VDATA is the data signal of the current row pixel circuit 10. This data signal is then sequentially written to the input terminal N2, output terminal N3, and gate N1 of drive transistor M0 through the first data writing transistor M3 and compensation transistor M2, causing drive transistor M0 to switch from on to off. By applying a data signal writing operation for the current frame to drive transistor M0, the influence of the previous frame is further reduced. A positive bias voltage is applied to drive transistor M0 to eliminate the bias voltage influence of the previous frame on drive transistor M0.

[0126] In this embodiment, before writing the data signal for the current row, the driving transistor M0 is reset multiple times and written at least once to eliminate the bias effect of the previous screen on the driving transistor M0.

[0127] The optional pixel circuit also includes a second data writing module, which is connected between the first signal terminal and the second terminal of the driving module. The control terminal of the second data writing module is connected to the fourth scanning terminal; during the first data writing phase, the second data writing module is turned off. The optional first data writing module includes a first data writing transistor, the gate of which is connected to the third scanning terminal; the optional second data writing module includes a second data writing transistor, the gate of which is connected to the fourth scanning terminal. The optional reset signal terminal provides a low-voltage signal, and the first signal terminal provides a high-voltage signal.

[0128] Figure 15 This is a schematic diagram of another pixel circuit provided in an embodiment of the present invention. Figure 15 As shown, the pixel circuit 10 also includes a second data writing module 15. The input terminal of the second data writing module 15 is connected to the first signal terminal DV1, the control terminal of the second data writing module 15 is connected to the fourth scan terminal S4, and the output terminal of the second data writing module 15 is connected to the second terminal N2 of the driver module 11. During the first data writing stage, the data signal of the pixel circuit 10 in this row needs to be written to the driver transistor M0. Therefore, the third scan terminal S3 controls the first data writing module 14 to be turned on, and the fourth scan terminal S4 controls the second data writing module 15 to be turned off. Thus, the second data writing module 15 does not affect the normal writing of the data signal of the pixel circuit 10 in this row.

[0129] When the driving transistor M0 is a P-type transistor, applying a negative bias voltage to the driving transistor M0 before the first data writing stage can eliminate the influence of the positive bias voltage of the previous frame. Based on this, a low voltage signal can be provided at the reset signal terminal, and a high voltage signal can be provided at the first signal terminal DV1. The first data writing module 14 includes a first data writing transistor M3. The second data writing module 15 includes a second data writing transistor M4. The gate of the second data writing transistor M4 is connected to the fourth scan terminal S4, the input terminal of the second data writing transistor M4 is connected to the first signal terminal DV1, and the output terminal of the second data writing transistor M4 is connected to the second terminal N2 of the driving module 11. Optionally, both the first data writing transistor M3 and the second data writing transistor M4 can be low-temperature polycrystalline silicon transistors (LTPS-TFTs). In other embodiments, the second data writing transistor can also be an N-type transistor.

[0130] The outputs of the first data writing transistor M3 and the second data writing transistor M4 are both connected to the second terminal N2 of the driving module 11. The first signal terminal DV1 provides a high-voltage signal, and the data signal terminal VDATA provides the data signal of the current row pixel circuit 10 or the data signal of other row pixel circuits. The operating phases of the first data writing transistor M3 and the second data writing transistor M4 do not overlap, ensuring the normal writing of the data signal or the signal of the first signal terminal DV1. During the first data writing phase, the scan signal provided by the third scan terminal S3 is a low voltage, and the scan signal provided by the fourth scan terminal S4 is a high voltage, turning on the first data writing transistor M3 and turning off the second data writing transistor M4, so that the data signal is written to the input terminal N2 of the driving transistor M0.

[0131] The optional pixel circuit operates by including a second data writing phase; the start time of the second data writing phase is later than or equal to the start time of the reset phase, and the end time of the second data writing phase is earlier than or equal to the start time of the compensation phase. The optional pixel circuit also operates by including a third data writing phase; the third data writing phase is located between the first and second reset phases, and a portion of the compensation phase time is multiplexed as the third data writing phase.

[0132] In this embodiment, the operation of the pixel circuit 10 includes a second data writing stage and a third data writing stage. In either the second or third data writing stage, the second data writing transistor M4 is turned on, and the first data writing transistor M3 is turned off. The high-voltage signal provided by the first signal terminal DV1 is written to the input terminal N2 and the output terminal N3 of the driving transistor M0, thereby negatively biasing the driving transistor M0. In other embodiments, the operation of the pixel circuit may optionally include either a second data writing stage or a third data writing stage.

[0133] Figure 16 yes Figure 15 The timing diagram of the pixel circuit is shown. The first scan terminal S1 provides a scan signal to the control terminal of the reset module 12, the second scan terminal S2 provides a scan signal to the control terminal of the compensation module 13, the third scan terminal S3 provides a scan signal to the control terminal of the first data writing module 14, and the fourth scan terminal S4 provides a scan signal to the control terminal of the second data writing module 15. The driving transistor M0, the first data writing transistor M3, and the second data writing transistor M4 are all LTPS-TFT, while the reset transistor M1 and the compensation transistor M2 are both IGZO-TFT. The reset signal provided by the reset signal terminal VREF has a low voltage, for example, -7V. The data signal provided by the data signal terminal VDATA has a high voltage, for example, the data signal range is 0V to +5V. The first signal terminal DV1 provides a fixed high voltage signal, for example, +5V.

[0134] like Figure 16 As shown, the second data writing stage t41b overlaps with the first reset stages t41 to t42, and the third data writing stage t43b overlaps with the compensation stages t42 to t45.

[0135] During the second data writing phase t41b, reset transistor M1 is turned on, compensation transistor M2 is turned off, first data writing transistor M3 is turned off, second data writing transistor M4 is turned on, and driving transistor M0 is turned on. A reset signal is written to the gate N1 of driving transistor M0. The high voltage signal provided by the first signal terminal DV1 is sequentially written to the input terminal N2 and output terminal N3 of driving transistor M0 through the second data writing transistor M4. This applies a negative bias voltage to driving transistor M0, eliminating the positive bias voltage effect of the previous image and improving the ghosting problem.

[0136] In the third data writing stage t43b, reset transistor M1 is off, compensation transistor M2 is on, first data writing transistor M3 is off, second data writing transistor M4 is on, and driving transistor M0 is on. The high voltage signal provided by the first signal terminal DV1 is sequentially written to the input terminal N2, output terminal N3, and gate N1 of driving transistor M0 through the second data writing transistor M4, thus switching driving transistor M0 from on to off. By applying the same voltage to all three terminals of driving transistor M0 before writing the current row of data signals, the positive bias voltage effect of the previous frame can be eliminated, improving the ghosting problem.

[0137] Figure 17 yes Figure 15 Another timing diagram of the pixel circuit is shown. (As shown) Figure 17As shown, the second data writing stage t51b overlaps with the first reset stages t51 to t42, and the third data writing stage t53b overlaps with the first compensation stages t52 to t54.

[0138] During the second data writing phase t51b, reset transistor M1 is turned on, compensation transistor M2 is turned off, first data writing transistor M3 is turned off, second data writing transistor M4 is turned on, and driving transistor M0 is turned on. A low-voltage reset signal is written to the gate N1 of driving transistor M0, and a high-voltage signal provided by the first signal terminal DV1 is sequentially written to the input terminal N2 and output terminal N3 of driving transistor M0 through the second data writing transistor M4. This applies a negative bias voltage to driving transistor M0, which can eliminate the positive bias voltage effect of the previous frame and improve the ghosting problem.

[0139] In the third data writing stage t53b, reset transistor M1 is off, compensation transistor M2 is on, first data writing transistor M3 is off, second data writing transistor M4 is on, and drive transistor M0 is on. The high voltage signal provided by the first signal terminal DV1 is sequentially written to the input terminal N2, output terminal N3, and gate N1 of drive transistor M0 through the second data writing transistor M4, thus switching drive transistor M0 from on to off. By applying the same voltage to all three terminals of drive transistor M0 before writing the current row of data signals, the positive bias voltage effect of the previous frame can be eliminated, improving the ghosting problem.

[0140] In this embodiment, before writing the data signal of the pixel circuit 10, the three terminals of the driving transistor M0 are reset at least twice and written at least twice with high voltage. This can avoid the bias voltage effect caused by different display screens, improve the ghosting problem when switching low-frequency display screens, and enhance the display effect.

[0141] refer to Figure 4 and Figure 15 As shown, the optional pixel circuit 10 further includes a first light-emitting control module 16 and a second light-emitting control module 17. The first light-emitting control module 16 is connected between the first power supply terminal PVDD and the second terminal N2 of the driving module 11, and the control terminal of the first light-emitting control module 16 is connected to the first light-emitting control terminal E1. The second light-emitting control module 17 is connected between the first terminal N3 of the driving module 11 and the light-emitting element 20, and the control terminal of the second light-emitting control module 17 is connected to the second light-emitting control terminal E2. Optionally, the first light-emitting control module 16 includes a first light-emitting transistor M5, and the second light-emitting control module 17 includes a second light-emitting transistor M6. The first light-emitting control terminal E1 provides a first light-emitting control signal to control the on / off state of the first light-emitting transistor M5, and the second light-emitting control terminal E2 provides a second light-emitting control signal to control the on / off state of the second light-emitting transistor M6.

[0142] In this embodiment, both the first light-emitting transistor M5 and the second light-emitting transistor M6 can be low-temperature polysilicon transistors (LTPs). When the first light-emitting control signal provided by the first light-emitting control terminal E1 is low voltage, it controls the first light-emitting transistor M5 to conduct; when the first light-emitting control signal provided by the first light-emitting control terminal E1 is high voltage, it controls the first light-emitting transistor M5 to turn off. When the second light-emitting control signal provided by the second light-emitting control terminal E2 is low voltage, it controls the second light-emitting transistor M6 to conduct; when the second light-emitting control signal provided by the second light-emitting control terminal E2 is high voltage, it controls the second light-emitting transistor M6 to turn off. In other embodiments, both the first and second light-emitting transistors can also be metal-oxide transistors (MOTs).

[0143] The operation of the pixel circuit 10 includes a non-light-emitting stage and a light-emitting stage. The non-light-emitting stage includes a reset stage, a compensation stage, and a data writing stage. In the non-light-emitting stage, both the first light-emitting transistor M5 and the second light-emitting transistor M6 are turned off, and the pixel circuit 10 performs the reset stage, the compensation stage, and the data writing stage. In the light-emitting stage, both the first light-emitting transistor M5 and the second light-emitting transistor M6 are turned on, and the driving transistor M0 provides driving current to the light-emitting element 20.

[0144] Figure 18 This is a schematic diagram of another pixel circuit provided in an embodiment of the present invention. Figure 18 As shown, the first light-emitting control terminal E1 and the second light-emitting control terminal E2 of the optional pixel circuit 10 are coupled to the same light-emitting control line. When the light-emitting control line provides a low voltage, it controls the first light-emitting transistor M5 and the second light-emitting transistor M6 to conduct simultaneously; when the light-emitting control line provides a high voltage, it controls the first light-emitting transistor M5 and the second light-emitting transistor M6 to be turned off simultaneously.

[0145] refer to Figure 4 and Figure 15 As shown, the optional pixel circuit 10 also includes an initialization module 18; the initialization module 18 is connected between the initialization signal terminal DV2 and the light-emitting element 20, and the control terminal of the initialization module 18 is connected to the fifth scanning terminal S5. The optional initialization module 18 includes an initialization transistor M7, and the initialization signal terminal DV2 provides an initialization signal.

[0146] In this embodiment, the input terminal of the optional initialization module 18 is connected to the initialization signal terminal DV2, the control terminal of the initialization module 18 is connected to the fifth scanning terminal S5, and the output terminal of the initialization module 18 is connected to node N4. Node N4 is coupled to the first electrode of the light-emitting element 20, and the second electrode of the light-emitting element 20 is connected to the second power supply terminal PVEE; the first electrode of the optional light-emitting element 20 is the anode, and the second electrode of the light-emitting element 20 is the cathode. The scanning signal provided by the fifth scanning terminal S5 controls the initialization module 18 to be turned on or off. When the initialization module 18 is turned on, the initialization signal provided by the initialization signal terminal DV2 is written to the first electrode of the light-emitting element 20. Normally, the first power supply terminal PVDD is at a high voltage, the second power supply terminal PVEE is at a low voltage, and the initialization signal terminal DV2 is at a low voltage; however, it is not limited to this. When the structure of the pixel circuit changes, the signals provided by each power supply terminal or signal terminal may change accordingly.

[0147] Optionally, the initialization transistor M7 can be a low-temperature polysilicon transistor. When the scan signal provided by the fifth scan terminal S5 is a low voltage, the initialization transistor M7 is turned on; when the scan signal provided by the fifth scan terminal S5 is a high voltage, the initialization transistor M7 is turned off. In other embodiments, the initialization transistor can also be a metal-oxide-semiconductor transistor.

[0148] refer to Figure 18 As shown, the optional reset signal terminal VREF and the initialization signal terminal DV2 can be coupled to the same reference voltage line. The optional third scan terminal S3 and the fifth scan terminal S5 can be coupled to the same scan signal line.

[0149] The operation of the pixel circuit 10 includes a non-light-emitting stage and a light-emitting stage. The non-light-emitting stage also includes an initialization stage. In the initialization stage, the scanning signal provided by the fifth scanning terminal S5 controls the initialization transistor M7 to be turned on. Then the initialization signal is written to the first electrode of the light-emitting element 20 to reset the light-emitting element 20, which can reduce the bias voltage effect of the previous image on the driving transistor M0.

[0150] Optionally, the reset signal terminal VREF and the initialization signal terminal DV2 can be coupled to the same reference voltage line, which provides the same reference voltage to both. During the reset phase, the reference voltage is written to the gate N1 of the driving transistor M0, resetting the driving transistor M0. During the initialization phase, the reference voltage is written to the first electrode of the light-emitting element 20, resetting the light-emitting element 20. This eliminates the need for the original initialization signal line in the pixel circuit 10, reducing the layout size of the pixel circuit 10 and facilitating the implementation of a narrow bezel in the display panel.

[0151] During the non-light-emitting phase of the pixel circuit 10, the second light-emitting control module 17 is turned off. The non-light-emitting phase of the pixel circuit 10 includes an initialization phase and a data writing phase. In this embodiment, the first data writing transistor M3 and the initialization transistor M7 can be selected as low-temperature polysilicon transistors. Then, the third scanning terminal S3 and the fifth scanning terminal S5 can be coupled to the same scanning signal line, so that the initialization phase and the data writing phase coincide. In this way, the scanning signal line driving the initialization module 18 in the pixel circuit 10 can be omitted, thereby omitting the driving circuit of the initialization module 18 in the bezel of the display panel, which is beneficial for achieving a narrow bezel in the display panel.

[0152] The optional display panel includes: a display area and a non-display area surrounding the display area; the display area includes multiple rows of pixel circuits arranged along the column direction; the non-display area includes a first scan driving circuit, the first scan driving circuit including cascaded first scan driving units; the first-level first scan driving unit drives two adjacent rows of pixel circuits.

[0153] Figure 19 This is a schematic diagram of another display panel provided in an embodiment of the present invention. Figure 19 As shown, the display panel includes a display area 31 and a non-display area 32 surrounding the display area 31; the display area 31 includes multiple rows of pixel circuits 10 arranged along the column direction; the non-display area 32 includes a first scan driving circuit 33, and the first scan driving circuit 33 includes cascaded first scan driving units 34. Optionally, a first-level first scan driving unit 34 drives two adjacent rows of pixel circuits 10; however, in other embodiments, a first-level first scan driving unit can also drive one row of pixel circuits. It should be noted that the first-level first scan driving unit 34 drives two adjacent rows of pixel circuits 10. Specifically, the first-level first scan driving unit 34 provides scan signals to the same modules of each pixel circuit 10 in the two adjacent rows. For example, the first-level first scan driving unit 34 provides scan signals to the first scan terminal S1 of each pixel circuit 10 in the two adjacent rows.

[0154] In this embodiment, the first-level first scanning driving unit 34 drives two adjacent rows of pixel circuits 10. Compared with the first-level scanning driving unit driving one row of pixel circuits, the number of first scanning driving units 34 in the first scanning driving circuit 33 is reduced, which can reduce the bezel size of the display panel and achieve a narrow bezel of the display panel.

[0155] refer to Figure 19As shown, the optional display panel includes: a display area 31 and a non-display area 32 surrounding the display area 31; the display area 31 includes multiple rows of pixel circuits 10 arranged along the column direction; the non-display area 32 includes a second scan driving circuit 35, and the second scan driving circuit 35 includes cascaded second scan driving units 36; the first-level second scan driving unit 36 ​​is connected to the control terminal of the first data writing module of a row of pixel circuits 10. The control terminal of the first data writing module in the pixel circuit is the third scan terminal S3. Taking the first row of pixel circuits 10 as an example, it is connected to the first-level second scan driving unit 36a. If the first-level second scan driving unit 36a provides a valid scan signal, the first data writing module of each pixel circuit 10 in the first row is turned on, and the data signal received by the data signal terminal in the pixel circuit 10 is written into the driving transistor of the pixel circuit 10.

[0156] The output of the first scan drive unit of the i-th stage can be electrically connected to the control terminal of the reset module of the (2i-1)-th row pixel circuit and the 2i-th row pixel circuit, where i is a positive integer greater than or equal to 1. The control terminal of the reset module in the pixel circuit is the first scan terminal S1.

[0157] refer to Figure 19 As shown, the output terminal of the first-level first scan driving unit 34a is electrically connected to the first scan terminal S1 of each pixel circuit 10 in the first row pixel circuit, and the output terminal of the first-level first scan driving unit 34a is also electrically connected to the first scan terminal S1 of each pixel circuit 10 in the second row pixel circuit. Then, each pixel circuit 10 in the first row and the second row performs a reset operation synchronously.

[0158] The output terminal of the second-level first scan driving unit 34b is electrically connected to the first scan terminal S1 of each pixel circuit 10 in the third row pixel circuit, and the output terminal of the second-level first scan driving unit 34a is also electrically connected to the first scan terminal S1 of each pixel circuit 10 in the fourth row pixel circuit. Then, each pixel circuit 10 in the third and fourth rows performs a reset operation synchronously.

[0159] Similarly, the output of the first scanning drive unit of the i-th level is electrically connected to the control terminal of the reset module of the pixel circuit of the (2i-1)-th row and the pixel circuit of the 2i-th row, so that each pixel circuit 10 in the (2i-1)-th row and the 2i-th row will perform a reset operation synchronously.

[0160] When the scan signal output by the first scan driving unit 34 is a valid pulse (i.e., a valid scan signal), the reset module 12 of the corresponding two adjacent rows of pixel circuits 10 is turned on, and the reset signal is transmitted to the gate N1 of the driving transistor M0 of the pixel circuit 10. When the scan signal output by the first scan driving unit 34 is an invalid pulse (i.e., an invalid scan signal), the reset module 12 of the corresponding two adjacent rows of pixel circuits 10 is turned off. The first scan driving units 34 cascaded in the first scan driving circuit 33 sequentially output valid scan signals. When the reset transistor M1 is an N-type transistor, the valid scan signal output by the first scan driving unit 34 is a high voltage, and the invalid scan signal output by the first scan driving unit 34 is a low voltage.

[0161] The output of the first scan drive unit of the i-th stage can be electrically connected to the control terminal of the compensation module of the pixel circuit in rows (2i-9) and (2i-8), where i is a positive integer greater than or equal to 5. The control terminal of the compensation module in the pixel circuit is the second scan terminal.

[0162] Figure 20 This is a schematic diagram of another display panel provided in an embodiment of the present invention. For example... Figure 20 As shown, the display panel includes a first row pixel circuit P1, a second row pixel circuit P2, a third row pixel circuit P3, and so on. The first scan driving circuit includes cascaded first scan driving units, which are sequentially labeled SN1, SN2, SN3, SN4, SN5, SN6, and so on. The output terminal of the first-stage first scan driving unit SN1 is electrically connected to the first scan terminal S1 of each pixel circuit 10 in the first row pixel circuit P1 and the second row pixel circuit P2. The output terminal of the second-stage first scan driving unit SN2 is electrically connected to the first scan terminal S1 of each pixel circuit 10 in the third row pixel circuit P3 and the fourth row pixel circuit P4. The output terminal of the third-stage first scan driving unit SN3 is electrically connected to the first scan terminal S1 of each pixel circuit 10 in the fifth row pixel circuit P5 and the sixth row pixel circuit P6, and so on.

[0163] The second scan drive circuit includes cascaded second scan drive units, which are sequentially labeled SP1, SP2, SP3, SP4, SP5, SP6, and so on. When the third scan terminal S3 and the fifth scan terminal S5 are coupled to the same scan signal line, the output terminal of the first-stage second scan drive unit SP1 is electrically connected to the third scan terminal S3 and the fifth scan terminal S5 of each pixel circuit 10 in the first row pixel circuit P1; the output terminal of the second-stage second scan drive unit SP2 is electrically connected to the third scan terminal S3 and the fifth scan terminal S5 of each pixel circuit 10 in the second row pixel circuit P2; the output terminal of the third-stage second scan drive unit SP3 is electrically connected to the third scan terminal S3 and the fifth scan terminal S5 of each pixel circuit 10 in the third row pixel circuit P3, and so on.

[0164] In this embodiment, the first scan driving unit provides a scan signal to the control terminal of the reset module of the pixel circuit, and also provides a scan signal to the control terminal of the compensation module of the pixel circuit. Specifically, the output terminal of the 5th-level first scan driving unit SN5 is electrically connected to the second scan terminal S2 of each pixel circuit 10 in the 1st row pixel circuit P1 and the 2nd row pixel circuit P2; the output terminal of the 6th-level first scan driving unit SN6 is electrically connected to the second scan terminal S2 of each pixel circuit 10 in the 3rd row pixel circuit P3 and the 4th row pixel circuit P4; the output terminal of the 7th-level first scan driving unit SN7 is electrically connected to the second scan terminal S2 of each pixel circuit 10 in the 5th row pixel circuit P5 and the 6th row pixel circuit P6, and so on. Since the first scan driving unit adopts a one-to-four driving method, the area occupied by the scan driving circuit in the non-display area is reduced, which is beneficial for achieving a narrow bezel on the display panel.

[0165] Figure 20 The central display panel includes an independently configured light-emitting driving circuit, which comprises cascaded light-emitting driving units, sequentially labeled EM1, EM2, EM3, EM4, EM5, EM6, and so on. The output of the first-stage light-emitting driving unit EM1 is electrically connected to the first light-emitting control terminal E1 and the second light-emitting control terminal E2 of each pixel circuit 10 in the first row pixel circuit P1 and the second row pixel circuit P2. The output of the second-stage light-emitting driving unit EM2 is electrically connected to the first light-emitting control terminal E1 and the second light-emitting control terminal E2 of each pixel circuit 10 in the third row pixel circuit P3 and the fourth row pixel circuit P4. The output of the third-stage light-emitting driving unit EM3 is electrically connected to the first light-emitting control terminal E1 and the second light-emitting control terminal E2 of each pixel circuit 10 in the fifth row pixel circuit P5 and the sixth row pixel circuit P6, and so on. This one-to-two driving method reduces the area occupied by the light-emitting driving circuit in the non-display area, which is beneficial for achieving a narrow bezel on the display panel.

[0166] Figure 21 yes Figure 20 The timing diagram for the display panel is shown. (Reference) Figure 20 and Figure 21 As shown, taking the first row pixel circuit P1 as an example, the operation of pixel circuit 10 is described, wherein the structure of optional pixel circuit 10 is as follows. Figure 4 As shown.

[0167] During stages t1 to t8, the first-stage scanning drive unit SN1 provides a high voltage, turning on the reset transistor M1 of the pixel circuit 10. A reset signal is written to the gate N1 of the drive transistor M0, turning on the drive transistor M0. The fifth-stage first-stage scanning drive unit SN5 provides a low voltage, turning off the compensation transistor M2. During stage t3, the second-stage scanning drive unit SP1 provides a low voltage, turning on the first data writing transistor M3 and the initialization transistor M7 of the pixel circuit 10. A data signal is written to the input terminal N2 and the output terminal N3 of the drive transistor M0, and a reset signal is written to the first electrode N4 of the light-emitting element 20. Therefore, the gate N1 of the drive transistor M0 is at a low voltage, and the input terminal N2 and the output terminal N3 of the drive transistor M0 are at a high voltage, resulting in a negative bias for the drive transistor M0 and a reset for the light-emitting element 20.

[0168] During the t9-t10 stage, the reset transistor M1 of the pixel circuit 10 remains on, and the driving transistor M0 remains on. The first scan driving unit SN5 of the 5th stage provides a high voltage, which turns on the compensation transistor M2 of the pixel circuit 10, and a reset signal is written to the three terminals of the driving transistor M0. Thus, the same reset signal is written to the three terminals of the driving transistor M0, and the three terminals of the driving transistor M0 are reset once.

[0169] During stages t11 to t16, the first-stage scanning drive unit SN1 provides a low voltage, causing the reset transistor M1 of the pixel circuit 10 to turn off, while the compensation transistor M2 remains on. During stage t13, the second-stage scanning drive unit SP1 provides a low voltage, causing the first data writing transistor M3 and the initialization transistor M7 of the pixel circuit 10 to turn on. Data signals are written to the three terminals of the driving transistor M0 until the driving transistor M0 turns off, and a reset signal is written to the first electrode N4 of the light-emitting element 20. Thus, the same data signal is written to the three terminals of the driving transistor M0, performing one data writing operation on the driving transistor M0; and a second reset is performed on the light-emitting element 20.

[0170] During the t17–t22 phase, the reset transistor M1 of the pixel circuit 10 is turned on, and a reset signal is written to the gate N1 of the driving transistor M0, turning on the driving transistor M0. During the t17–t18 phase, the compensation transistor M2 of the pixel circuit 10 remains turned on, and a reset signal is written to the three terminals of the driving transistor M0. Therefore, the same reset signal is written to the three terminals of the driving transistor M0, performing a second reset on the three terminals of the driving transistor M0.

[0171] During stages t25 to t30, the reset transistor M1 of the pixel circuit 10 is turned off, and the compensation transistor M2 is turned on. During stage t27, the first-stage second scan drive unit SP1 provides a low voltage, causing the first data writing transistor M3 and the initialization transistor M7 of the pixel circuit 10 to turn on. The data signal of the pixel circuit 10 for this row is written to the three terminals of the drive transistor M0 until the drive transistor M0 is turned off, and the reset signal is written to the first electrode N4 of the light-emitting element 20. Thus, the same data signal is written to the three terminals of the drive transistor M0, performing a second data writing operation on the drive transistor M0; and the light-emitting element 20 is reset three times.

[0172] It can be understood that when the output of the nth-level light-emitting driving unit EMn provides an invalid light-emitting control signal, then each pixel circuit in the (2n-1)th row pixel circuit and the 2nth row pixel circuit is in a non-light-emitting stage, during which the pixel circuit performs a reset stage, a compensation stage, and a data writing stage. For example, during the t1 to t30 stage, if the output of the first-level light-emitting driving unit EM1 provides an invalid light-emitting control signal, then each pixel circuit in the first-row pixel circuit P1 and the second-row pixel circuit P2 is in a non-light-emitting stage, and each pixel circuit in the first-row pixel circuit P1 and the second-row pixel circuit P2 performs a reset stage, a compensation stage, and a data writing stage.

[0173] In this embodiment, the driving transistor is reset and data is written multiple times, and the light-emitting element is also reset multiple times. This eliminates the bias voltage effect of the previous image on the driving transistor and improves the ghosting problem. Each driving unit in the driving circuit adopts a one-to-many design, with one driving unit driving multiple rows of pixel circuits. This reduces the area occupied by the driving circuit in the non-display area, which is beneficial for achieving a narrow bezel on the display panel.

[0174] Figure 22 This is a schematic diagram of another display panel provided in an embodiment of the present invention. Figure 20 The difference is that, Figure 22The central display panel includes an independently configured compensation drive circuit, which comprises cascaded compensation drive units, sequentially labeled SN'1, SN'2, SN'3, SN'4, SN'5, SN'6, and so on. The output of the first-stage compensation drive unit SN'1 is electrically connected to the second scan terminal S2 of each pixel circuit 10 in the first row pixel circuit P1 and the second row pixel circuit P2. The output of the second-stage compensation drive unit SN'2 is electrically connected to the second scan terminal S2 of each pixel circuit 10 in the third row pixel circuit P3 and the fourth row pixel circuit P4. The output of the third-stage compensation drive unit SN'3 is electrically connected to the second scan terminal S2 of each pixel circuit 10 in the fifth row pixel circuit P5 and the sixth row pixel circuit P6, and so on.

[0175] Figure 23 yes Figure 22 The timing diagram for the display panel is shown. (Reference) Figure 22 and Figure 23 As shown, taking the first row pixel circuit P1 as an example, the operation of pixel circuit 10 is described, wherein the structure of optional pixel circuit 10 is as follows. Figure 4 As shown.

[0176] During stages t4 to t23, the output of the first-stage light-emitting driving unit EM1 provides an invalid light-emitting control signal. Therefore, each pixel circuit in the first-row pixel circuit P1 and the second-row pixel circuit P2 is in a non-light-emitting stage, and each pixel circuit in the first-row pixel circuit P1 and the second-row pixel circuit P2 performs a reset stage, a compensation stage, and a data writing stage. The specific details are as follows.

[0177] During stages t5 to t8, the first-stage scanning drive unit SN1 provides a high voltage, turning on the reset transistor M1 of the pixel circuit 10. A reset signal is written to the gate N1 of the drive transistor M0, turning on the drive transistor M0. The first-stage compensation drive unit SN'1 provides a low voltage, turning off the compensation transistor M2. During stage t7, the second-stage scanning drive unit SP1 provides a low voltage, turning on the first data writing transistor M3 and the initialization transistor M7 of the pixel circuit 10. A data signal is written to the input terminal N2 and the output terminal N3 of the drive transistor M0, and a reset signal is written to the first electrode N4 of the light-emitting element 20. Therefore, the gate N1 of the drive transistor M0 is at a low voltage, and the input terminal N2 and the output terminal N3 of the drive transistor M0 are at a high voltage, resulting in a negative bias for the drive transistor M0 and a reset for the light-emitting element 20.

[0178] During the t9-t10 stage, the reset transistor M1 of the pixel circuit 10 remains on, and the driving transistor M0 remains on. The first-stage compensation driving unit SN'1 provides a high voltage, which turns on the compensation transistor M2 of the pixel circuit 10, and a reset signal is written to the three terminals of the driving transistor M0. Thus, the same reset signal is written to the three terminals of the driving transistor M0, and the three terminals of the driving transistor M0 are reset once.

[0179] During stages t11 to t16, the first-stage scanning drive unit SN1 provides a low voltage, turning off the reset transistor M1 of the pixel circuit 10; the compensation transistor M2 remains on. During stage t13, the second-stage scanning drive unit SP1 provides a low voltage, turning on the first data writing transistor M3 and the initialization transistor M7 of the pixel circuit 10. Data signals are written to the three terminals of the driving transistor M0 until the driving transistor M0 turns off, and a reset signal is written to the first electrode N4 of the light-emitting element 20. Thus, the same data signal is written to the three terminals of the driving transistor M0, performing one data writing operation on the driving transistor M0; and a second reset is performed on the light-emitting element 20.

[0180] During the t17-t18 stage, the reset transistor M1 of the pixel circuit 10 is turned on, and a reset signal is written to the gate N1 of the driving transistor M0, turning on the driving transistor M0; the compensation transistor M2 of the pixel circuit 10 remains turned on, and a reset signal is written to the three terminals of the driving transistor M0. Thus, the same reset signal is written to the three terminals of the driving transistor M0, performing a second reset on the three terminals of the driving transistor M0.

[0181] During stages t19 to t22, the reset transistor M1 of the pixel circuit 10 is turned off, and the compensation transistor M2 is turned on. During stage t21, the first-stage second scan driving unit SP1 provides a low voltage, causing the first data writing transistor M3 and the initialization transistor M7 of the pixel circuit 10 to turn on. The data signal of the pixel circuit 10 for this row is written to the three terminals of the driving transistor M0 until the driving transistor M0 is turned off, and the reset signal is written to the first electrode N4 of the light-emitting element 20. Thus, the same data signal is written to the three terminals of the driving transistor M0, performing a second data writing operation on the driving transistor M0; and the light-emitting element 20 is reset three times.

[0182] In this embodiment, the driving transistor is reset and data is written multiple times, and the light-emitting element is also reset multiple times. This eliminates the bias voltage effect of the previous frame on the driving transistor and improves the ghosting problem. Each scanning driving unit in the first scanning driving circuit controls the reset module in the pixel circuit to be turned on or off; each compensation driving unit in the compensation driving circuit controls the compensation module in the pixel circuit to be turned on or off. This reduces the duration of the non-light-emitting phase of a row of pixel circuits, thereby reducing the refresh time per frame and increasing the refresh rate.

[0183] The optional display panel includes: a display area and a non-display area surrounding the display area; the display area includes multiple rows of pixel circuits arranged along the column direction; the non-display area includes a third scan driving circuit, the third scan driving circuit includes cascaded third scan driving units; the first-level third scan driving unit is connected to the control terminal of a second data writing module of at least one row of pixel circuits. Figure 24 This is a schematic diagram of another display panel provided in an embodiment of the present invention. For example... Figure 24 As shown, the display panel includes a display area 31 and a non-display area 32 surrounding the display area 31; the display area 31 includes multiple rows of pixel circuits 10 arranged along the column direction. Optional pixel circuits in the display panel include... Figure 18 As shown, the pixel circuit 10 includes a second data writing module 15, and the control terminal of the second data writing module 15 is connected to the fourth scanning terminal S4.

[0184] The non-display area 32 includes a first scan driving circuit 33, which includes cascaded first scan driving units 34. Optionally, the first scan driving unit 34 provides scan signals to the first scan terminals S1 of each pixel circuit 10 in two adjacent rows, controlling the reset module 12 in the pixel circuit 10 to turn on or off. The first scan driving unit 34 employs a 1-to-2 design, reducing the area occupied by the scan driving units in the non-display area 32 and achieving a narrow bezel on the display panel. Optionally, the first scan driving unit 34 also provides scan signals to the second scan terminals S2 of each pixel circuit 10 in two adjacent rows, controlling the compensation module 13 in the pixel circuit 10 to turn on or off, further reducing the area occupied by the scan driving units in the non-display area 32 and achieving a narrow bezel on the display panel.

[0185] The non-display area 32 includes a second scan driving circuit 35, which includes cascaded second scan driving units 36. Optionally, a first-level second scan driving unit 36 ​​provides a scan signal to the third scan terminal S3 of each pixel circuit 10 in a row, used to control the first data writing module 14 in the pixel circuit 10 to turn on or off. Optionally, the first-level second scan driving unit 36 ​​also provides a scan signal to the fifth scan terminal S5 of each pixel circuit 10 in a row, used to control the initialization module 18 in the pixel circuit 10 to turn on or off. This further reduces the area occupied by the scan driving units in the non-display area 32, achieving a narrow bezel on the display panel.

[0186] The non-display area 32 includes a third scan driving circuit 37, which includes cascaded third scan driving units 38. Optionally, a first-level third scan driving unit 38 provides scan signals to the fourth scan terminal S4 of each pixel circuit 10 in a row, used to control the second data writing module 15 in the pixel circuit 10 to turn on or off. In other embodiments, an optional first-level third scan driving unit can provide scan signals to the fourth scan terminal of each pixel circuit in two adjacent rows. The first-level third scan driving unit adopts a 1-to-2 design, which can reduce the area occupied by the scan driving units in the non-display area and achieve a narrow bezel on the display panel.

[0187] In this embodiment, at least one scan driving unit provides scan signals to two different scan terminals in the pixel circuit, which can reduce the area occupied by the scan driving unit in the non-display area and achieve a narrow bezel in the display panel. It also reduces the number of scan signal lines connected to the pixel circuit, decreasing the layout size of the pixel circuit and facilitating high resolution in the display panel.

[0188] But not limited to this. Refer to [reference] where required by the design. Figure 15 As shown, each scanning end of the pixel circuit 10 can be driven by different scanning signal lines. Therefore, the non-display area of ​​the display panel includes at least seven scanning drive circuits for driving the pixel circuit 10. Each scanning drive circuit includes cascaded scanning drive units. The cascaded scanning drive unit in the first scanning drive circuit provides a scanning signal to the first scanning end S1 of the pixel circuit 10 in the display area, controlling the on / off state of the reset module 12 of the pixel circuit 10. The cascaded scanning drive unit in the second scanning drive circuit provides a scanning signal to the second scanning end S2 of the pixel circuit 10 in the display area, controlling the on / off state of the compensation module 13 of the pixel circuit 10. The cascaded scanning drive unit in the third scanning drive circuit provides a scanning signal to the third scanning end S3 of the pixel circuit 10 in the display area, controlling the on / off state of the first data writing module 14 of the pixel circuit 10. The cascaded scanning drive unit in the fourth scanning drive circuit provides a scanning signal to the fourth scanning end S4 of the pixel circuit 10 in the display area, controlling the on / off state of the second data writing module 15 of the pixel circuit 10. The cascaded scanning drive unit in the fifth scanning drive circuit provides a scanning signal to the fifth scanning terminal S5 of the pixel circuit 10 in the display area, controlling the on / off state of the initialization module 18 of the pixel circuit 10. The cascaded scanning drive unit in the sixth scanning drive circuit provides a light emission control signal to the first light emission control terminal E1 of the pixel circuit 10 in the display area, controlling the on / off state of the first light emission control module 16 of the pixel circuit 10. The cascaded scanning drive unit in the seventh scanning drive circuit provides a light emission control signal to the second light emission control terminal E2 of the pixel circuit 10 in the display area, controlling the on / off state of the second light emission control module 17 of the pixel circuit 10.

[0189] Figure 25 This is a schematic diagram of another display panel provided in an embodiment of the present invention. For example... Figure 25 As shown, the display panel includes a first row pixel circuit P1, a second row pixel circuit P2, a third row pixel circuit P3, and so on. The first scan driving circuit includes cascaded first scan driving units, which are sequentially labeled SN1, SN2, SN3, SN4, SN5, SN6, and so on. The output terminal of the first-stage first scan driving unit SN1 is electrically connected to the first scan terminal S1 of each pixel circuit 10 in the first row pixel circuit P1 and the second row pixel circuit P2. The output terminal of the second-stage first scan driving unit SN2 is electrically connected to the first scan terminal S1 of each pixel circuit 10 in the third row pixel circuit P3 and the fourth row pixel circuit P4. The output terminal of the third-stage first scan driving unit SN3 is electrically connected to the first scan terminal S1 of each pixel circuit 10 in the fifth row pixel circuit P5 and the sixth row pixel circuit P6, and so on.

[0190] In this embodiment, the first scan driving unit provides a scan signal to the control terminal of the reset module of the pixel circuit, and also provides a scan signal to the control terminal of the compensation module of the pixel circuit. Specifically, the output terminal of the 5th-level first scan driving unit SN5 is electrically connected to the second scan terminal S2 of each pixel circuit 10 in the 1st row pixel circuit P1 and the 2nd row pixel circuit P2; the output terminal of the 6th-level first scan driving unit SN6 is electrically connected to the second scan terminal S2 of each pixel circuit 10 in the 3rd row pixel circuit P3 and the 4th row pixel circuit P4; the output terminal of the 7th-level first scan driving unit SN7 is electrically connected to the second scan terminal S2 of each pixel circuit 10 in the 5th row pixel circuit P5 and the 6th row pixel circuit P6, and so on.

[0191] The second scan drive circuit includes cascaded second scan drive units, which are sequentially labeled SP1, SP2, SP3, SP4, SP5, SP6, and so on. When the third scan terminal S3 and the fifth scan terminal S5 are coupled to the same scan signal line, the output terminal of the first-stage second scan drive unit SP1 is electrically connected to the third scan terminal S3 and the fifth scan terminal S5 of each pixel circuit 10 in the first row pixel circuit P1; the output terminal of the second-stage second scan drive unit SP2 is electrically connected to the third scan terminal S3 and the fifth scan terminal S5 of each pixel circuit 10 in the second row pixel circuit P2; the output terminal of the third-stage second scan drive unit SP3 is electrically connected to the third scan terminal S3 and the fifth scan terminal S5 of each pixel circuit 10 in the third row pixel circuit P3, and so on.

[0192] The third scan drive circuit includes cascaded third scan drive units, which are sequentially labeled SP.* 1. SP * 2. SP * 3. SP * 4. SP * 5. SP * 6. And so on. Level 1, Third Scan Drive Unit SP * The output terminal of 1 is electrically connected to the fourth scan terminal S4 of each pixel circuit 10 in the first row pixel circuit P1 and the second row pixel circuit P2, and the second-stage third scan drive unit SP. * The output terminal of 2 is electrically connected to the fourth scan terminal S4 of each pixel circuit 10 in the third row pixel circuit P3 and the fourth row pixel circuit P4, and the third scan drive unit SP of the third stage. * The output terminal of 3 is electrically connected to the fourth scanning terminal S4 of each pixel circuit 10 in the fifth row pixel circuit P5 and the sixth row pixel circuit P6, and so on.

[0193] Figure 26 yes Figure 25 The timing diagram for the display panel is shown. (Reference) Figure 25 and Figure 26 As shown, taking the first row pixel circuit P1 as an example, the operation of pixel circuit 10 is described, wherein the structure of optional pixel circuit 10 is as follows. Figure 18 As shown.

[0194] During stages t1 to t8, the first-stage first scan driving unit SN1 provides a high voltage, turning on the reset transistor M1 of the pixel circuit 10. A reset signal is written to the gate N1 of the driving transistor M0, turning on the driving transistor M0. The fifth-stage first scan driving unit SN5 provides a low voltage, turning off the compensation transistor M2. The first-stage second scan driving unit SP1 provides a high voltage, turning off the first data writing transistor M3 and the initialization transistor M7. During stage t3, the first-stage third scan driving unit SP... * A low voltage is provided to turn on the second data writing transistor M4, while the high voltage provided by the first signal terminal DV1 is written to the input terminal N2 and the output terminal N3 of the driving transistor M0. Therefore, the gate N1 of the driving transistor M0 is at a low voltage, and the input terminal N2 and the output terminal N3 of the driving transistor M0 are at a high voltage, thus applying a negative bias to the driving transistor M0.

[0195] During the t9-t10 stage, the reset transistor M1 remains on, and the drive transistor M0 remains on. The first scan drive unit SN5 of the 5th stage provides a high voltage, which turns on the compensation transistor M2, and a reset signal is written to the three terminals of the drive transistor M0. Thus, the same reset signal is written to the three terminals of the drive transistor M0, resetting the three terminals of the drive transistor M0 once.

[0196] During stages t11 to t16, the first scan drive unit SN1 of the first stage provides a low voltage, causing the reset transistor M1 to turn off and the compensation transistor M2 to remain on; the first data write transistor M3 and the initialization transistor M7 remain off. During stage t13, the third scan drive unit SP of the first stage... * A low voltage is provided to turn on the second data writing transistor M4, while the high voltage provided by the first signal terminal DV1 is written to all three terminals of the driving transistor M0 until the driving transistor M0 is turned off. Thus, the same data signal is written to all three terminals of the driving transistor M0, and a data write operation is performed on the driving transistor M0.

[0197] During the t17–t22 phase, reset transistor M1 is turned on, and a reset signal is written to the gate N1 of drive transistor M0, turning drive transistor M0 on. During the t17–t18 phase, compensation transistor M2 remains turned on, and a reset signal is written to the three terminals of drive transistor M0. Therefore, the same reset signal is written to the three terminals of drive transistor M0, performing a second reset on the three terminals of drive transistor M0.

[0198] During stages t25 to t30, reset transistor M1 is off, compensation transistor M2 is on, and second data writing transistor M4 is off. During stage t27, the first-stage second scan driving unit SP1 provides a low voltage, turning on the first data writing transistor M3 and initialization transistor M7. Data signals from the current row pixel circuit 10 are written to the three terminals of driving transistor M0 until driving transistor M0 is off, and a reset signal is written to the first electrode N4 of the light-emitting element 20. Thus, the same data signal is written to the three terminals of driving transistor M0, performing a second data writing operation on driving transistor M0; and resetting the light-emitting element 20 is also performed.

[0199] In this embodiment, multiple resets and data writes to the driving transistor can eliminate the bias voltage effect of the previous frame on the driving transistor and improve the ghosting problem.

[0200] Based on the same inventive concept, embodiments of the present invention also provide a display device, including the aforementioned display panel. The display panel may be an organic light-emitting display panel or a micro LED display panel, and is not limited thereto. Figure 27 This is a schematic diagram of a display device provided in an embodiment of the present invention, such as... Figure 27 As shown, this display device can be optionally applied to electronic devices 1 such as smartphones and tablets. It is understood that the above embodiments only provide a partial structure of the display panel and pixel circuitry; the display panel also includes other structures, which will not be described in detail here.

[0201] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A display panel, characterized by, The pixel circuit comprises a driving module, a reset module and a compensation module. A first end of the driving module is coupled to the light emitting element for providing a driving current for the light emitting element, and the driving module comprises a driving transistor. The reset module is connected between a reset signal terminal and a control terminal of the driving module for providing a reset signal for the driving module. The compensation module is connected between the control terminal of the driving module and the first end of the driving module for compensating a threshold voltage of the driving transistor. The working process of the pixel circuit comprises a reset phase and a compensation phase. In the reset phase, the reset module is turned on. In the compensation phase, the compensation module is turned on. Part of a time period of the reset phase overlaps with part of a time period of the compensation phase. The pixel circuit further comprises a first data writing module connected between a data signal terminal and a second end of the driving module, and a control terminal of the first data writing module is connected to a third scan terminal. The working process of the pixel circuit comprises a first data writing phase. In the first data writing phase, the first data writing module is turned on. The turning-on time of the reset phase is earlier than the turning-on time of the compensation phase. The working process of the pixel circuit comprises a second data writing phase. The turning-on time of the second data writing phase is later than or equal to the turning-on time of the reset phase, and the ending time of the second data writing phase is earlier than or equal to the turning-on time of the compensation phase. The reset module comprises a reset transistor, and a gate of the reset transistor is connected to a first scan terminal. The reset transistor is a metal oxide transistor, and the driving transistor is a low temperature poly-silicon transistor; or the reset transistor is a low temperature poly-silicon transistor, and the driving transistor is a metal oxide transistor.

2. The display panel of claim 1, wherein, The compensation module comprises a compensation transistor, and a gate of the compensation transistor is connected to a second scan terminal. The compensation transistor is a metal oxide transistor, and the driving transistor is a low temperature poly-silicon transistor; or the compensation transistor is a low temperature poly-silicon transistor, and the driving transistor is a metal oxide transistor.

3. The display panel of claim 1, wherein, A control terminal of the reset module is connected to the first scan terminal, and a control terminal of the compensation module is connected to the second scan terminal. The first scan terminal and the second scan terminal are coupled to the same scan signal line.

4. The display panel of claim 1, wherein, The first data writing phase is located after the reset phase, and part of a time period of the compensation phase overlaps with the first data writing phase. The compensation phase comprises a first compensation phase and a second compensation phase arranged at intervals.

5. The display panel of claim 1, wherein, Part of a time period of the reset phase overlaps with part of a time period of the first compensation phase, and part of a time period of the second compensation phase overlaps with the first data writing phase.

6. The display panel of claim 5, wherein, Part of a time period of the reset phase also overlaps with part of a time period of the second compensation phase. The reset phase comprises a first reset phase and a second reset phase arranged at intervals.

7. The display panel of claim 6, wherein, Part of a time period of the first reset phase overlaps with part of a time period of the compensation phase.

8. The display panel of claim 5, wherein, ​ ​ Part of the time period of the compensation stage is multiplexed as the second reset stage.

9. The display panel of claim 6, wherein, The reset stage comprises a first reset stage and a second reset stage arranged at intervals; Part of the time period of the first reset stage and part of the time period of the first compensation stage coincide; Part of the time period of the second reset stage and part of the time period of the first compensation stage coincide.

10. The display panel of claim 8, wherein, The working process of the pixel circuit comprises a third data writing stage; The third data writing stage is located between the first reset stage and the second reset stage, and part of the time period of the compensation stage is multiplexed as the third data writing stage.

11. The display panel of claim 1, wherein, The pixel circuit further comprises a second data writing module connected between the first signal end and the second end of the driving module, and the control end of the second data writing module is connected to the fourth scanning end. In the first data writing stage, the second data writing module is turned off.

12. The display panel of claim 11, wherein, The first data writing module comprises a first data writing transistor, and the gate of the first data writing transistor is connected to the third scanning end. The second data writing module comprises a second data writing transistor, and the gate of the second data writing transistor is connected to the fourth scanning end.

13. The display panel of claim 11, wherein, The reset signal end provides a low-voltage signal, and the first signal end provides a high-voltage signal.

14. The display panel of claim 1, wherein, The pixel circuit further comprises a first light-emitting control module and a second light-emitting control module. The first light-emitting control module is connected between the first power supply end and the second end of the driving module, and the control end of the first light-emitting control module is connected to the first light-emitting control end. The second light-emitting control module is connected between the first end of the driving module and the light-emitting element, and the control end of the second light-emitting control module is connected to the second light-emitting control end.

15. The display panel of claim 14, wherein, The first light-emitting control end and the second light-emitting control end are coupled to the same light-emitting control line.

16. The display panel of claim 1, wherein, The pixel circuit further comprises an initialization module. The initialization module is connected between the initialization signal end and the light-emitting element, and the control end of the initialization module is connected to the fifth scanning end.

17. The display panel of claim 16, wherein, The reset signal end and the initialization signal end are coupled to the same reference voltage line.

18. The display panel of claim 16, wherein, The third scanning end and the fifth scanning end are coupled to the same scanning signal line.

19. The display panel of claim 1, wherein, The display panel comprises a display area and a non-display area surrounding the display area. The display area comprises a plurality of rows of pixel circuits arranged in a column direction. The non-display area comprises a first scan driving circuit, and the first scan driving circuit comprises cascaded first scan driving units. The first scan driving unit at a first stage drives two adjacent rows of pixel circuits.

20. The display panel of claim 19, wherein, The output end of the first scan driving unit at the i-th stage is electrically connected to the control end of the reset module of the (2i-1)-th row of pixel circuits and the 2i-th row of pixel circuits, and i is a positive integer greater than or equal to 1.

21. The display panel of claim 19, wherein, The output end of the first scan driving unit at the i-th stage is electrically connected to the control end of the compensation module of the (2i-9)-th row of pixel circuits and the (2i-8)-th row of pixel circuits, and i is a positive integer greater than or equal to 5.

22. The display panel of claim 1, wherein, The display panel comprises a display area and a non-display area surrounding the display area. The display area includes a plurality of rows of the pixel circuits arranged along a column direction; The non-display area includes a second scan driving circuit, and the second scan driving circuit includes cascaded second scan driving units; A first one of the second scan driving units is connected to control ends of first data writing modules of a row of the pixel circuits.

23. The display panel of claim 11, wherein, The display panel includes a display area and a non-display area surrounding the display area; The display area includes a plurality of rows of the pixel circuits arranged along a column direction; The non-display area includes a third scan driving circuit, and the third scan driving circuit includes cascaded third scan driving units; A first one of the third scan driving units is connected to control ends of second data writing modules of at least one row of the pixel circuits.

24. A display device comprising: The display panel includes a display area and a non-display area surrounding the display area; The display area includes a plurality of rows of the pixel circuits arranged along a column direction; The non-display area includes a third scan driving circuit, and the third scan driving circuit includes cascaded third scan driving units; A first one of the third scan driving units is connected to control ends of second data writing modules of at least one row of the pixel circuits. The display panel includes a display area and a non-display area surrounding the display area; The display area includes a plurality of rows of the pixel circuits arranged along a column direction; The non-display area includes a third scan driving circuit, and the third scan driving circuit includes cascaded third scan driving units; A first one of the third scan driving units is connected to control ends of second data writing modules of at least one row of the pixel circuits. The display panel includes a display area and a non-display area surrounding the display area; The display area includes a plurality of rows of the pixel circuits arranged along a column direction; The non-display area includes a third scan driving circuit, and the third scan driving circuit includes cascaded third scan driving units; A first one of the third scan driving units is connected to control ends of second data writing modules of at least one row of

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