Display device

Abstract

According to one aspect of the present disclosure, a display device includes a display panel including a plurality of pixel units, each pixel unit including N pixels; a data driver configured to supply a data voltage to the N pixels via N data lines using sensing results of the N pixels via N reference voltage lines; and a gate driver configured to supply a gate signal to the N pixels via N gate lines, wherein each of the N pixels includes N sub-pixels each having a different color; wherein each of the N data lines is branched into N sub-data lines, wherein each of the N sub-data lines is connected to a sub-pixel having the same color, wherein each of the N gate lines is connected to all of the N pixels and to sub-pixels having different colors, N being a natural number of 1 or more.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2021-0194687, filed with the Korean Intellectual Property Office on December 31, 2021. Technical Field

[0003] This disclosure relates to a display device, and more specifically, to a display device capable of sensing light-emitting diodes. Background Technology

[0004] Display devices used for displays in computers, televisions, or mobile phones include organic light-emitting display (OLED) devices that are self-emissive devices and liquid crystal display (LCD) devices that require a separate light source.

[0005] Among various display devices, OLED devices include a display panel with multiple sub-pixels and a driver for driving the display panel. The driver includes a gate driver configured to supply gate signals to the display panel and a data driver configured to supply data voltages. When signals such as gate signals and data voltages are supplied to the sub-pixels of the OLED device, selected sub-pixels emit light to display an image.

[0006] Furthermore, the degree of variation in the characteristic values ​​between the circuit elements of a sub-pixel can vary depending on the degree of degradation of each circuit element. This difference in the degree of variation in the characteristic values ​​between circuit elements can lead to brightness deviations between sub-pixels. That is, brightness deviations between sub-pixels can cause problems such as reduced accuracy of sub-pixel brightness, and / or screen abnormalities. Summary of the Invention

[0007] One object of this disclosure is to provide a display device including a sensing transistor that senses characteristic values ​​of subpixels, or senses characteristic values ​​of subpixels more accurately and efficiently.

[0008] Another objective of this disclosure is to provide a display device with improved sensing speed.

[0009] Another objective of this disclosure is to provide a display device that suppresses unwanted or undesirable line patterns.

[0010] To achieve the above objectives, the display device of the present disclosure can reduce the sensing time of multiple sub-pixels.

[0011] The purpose of this disclosure is not limited to the above-mentioned purposes, and other purposes not mentioned above can be clearly understood by those skilled in the art through the following description.

[0012] According to an aspect of the disclosure, a display device includes a display panel in which a plurality of pixels including first, second, and third sub-pixels each having different colors are disposed; a data driver configured to supply a data voltage to the plurality of pixels via a plurality of data lines using sensing results of the plurality of pixels obtained via first, second, and third reference voltage lines; and a gate driver configured to supply a gate signal to the plurality of pixels via a plurality of gate lines, wherein the plurality of first sub-pixels are disposed in 9k-8th, 9k-5th, and 9k-2nd columns, wherein the plurality of second sub-pixels are disposed in 9k-7th, 9k-4th, and 9k-1st columns, wherein the plurality of third sub-pixels are disposed in 9k-6th, 9k-3rd, and 9kth columns, each of the plurality of data lines is branched into a plurality of sub-data lines and each of the plurality of sub-data lines is connected to a plurality of sub-pixels having the same color, the first reference voltage line is connected to the plurality of first sub-pixels disposed in the 9k-8th column, the plurality of second sub-pixels disposed in the 9k-7th column, and the plurality of third sub-pixels disposed in the 9k-6th column, the second reference voltage line is connected to the plurality of first sub-pixels disposed in the 9k-5th column, the plurality of second sub-pixels disposed in the 9k-4th column, and the plurality of third sub-pixels disposed in the 9k-3rd column, and the third reference voltage line is connected to the plurality of first sub-pixels disposed in the 9k-2nd column, the plurality of second sub-pixels disposed in the 9k-1st column, and the plurality of third sub-pixels disposed in the 9kth column, to improve a sensing speed of the sub-pixels.

[0013] According to another feature of the present application, for a row, any one of a plurality of first sub-pixels disposed in columns 16k-15, any one of a plurality of second sub-pixels disposed in columns 16k-14, any one of a plurality of third sub-pixels disposed in columns 16k-13, and any one of a plurality of fourth sub-pixels disposed in columns 16k-12 constitute a first pixel, any one of a plurality of first sub-pixels disposed in columns 16k-11, any one of a plurality of second sub-pixels disposed in columns 16k-10, any one of a plurality of third sub-pixels disposed in columns 16k-9, and any one of a plurality of fourth sub-pixels disposed in columns 16k-8 constitute a second pixel, any one of a plurality of first sub-pixels disposed in columns 16k-7, any one of a plurality of second sub-pixels disposed in columns 16k-6, any one of a plurality of third sub-pixels disposed in columns 16k-5, and any one of a plurality of fourth sub-pixels disposed in columns 16k-4 constitute a third pixel, and any one of a plurality of first sub-pixels disposed in columns 16k-3, any one of a plurality of second sub-pixels disposed in columns 16k-2, any one of a plurality of third sub-pixels disposed in columns 16k-1, and any one of a plurality of fourth sub-pixels disposed in columns 16k constitute a fourth pixel, in each of the first pixel, the second pixel, the third pixel, and the fourth pixel, the first sub-pixel, the second sub-pixel, the third sub-pixel, and the fourth sub-pixel are connected to different gate lines, the plurality of first sub-pixels included in the first pixel, the second pixel, the third pixel, and the fourth pixel are connected to gate lines different from each other, the plurality of second sub-pixels included in the first pixel, the second pixel, the third pixel, and the fourth pixel are connected to gate lines different from each other, the plurality of third sub-pixels included in the first pixel, the second pixel, the third pixel, and the fourth pixel are connected to gate lines different from each other, and the plurality of fourth sub-pixels included in the first pixel, the second pixel, the third pixel, and the fourth pixel are connected to gate lines different from each other.

[0014] According to still another feature of the present disclosure, a display apparatus includes a display panel in which a plurality of pixels including first, second, third, and fourth sub-pixels each having a different color are disposed; a data driver configured to supply a data voltage to the plurality of pixels via a plurality of data lines using sensing results of the plurality of pixels obtained via first, second, and third reference voltage lines; and a gate driver configured to supply a gate signal to the plurality of pixels via a plurality of gate lines, wherein the plurality of first sub-pixels are disposed in 12k-11, 12k-7, and 12k-3 columns, the plurality of second sub-pixels are disposed in 12k-10, 12k-6, and 12k-2 columns, the plurality of third sub-pixels are disposed in 12k-9, 12k-5, and 12k-1 columns, the plurality of fourth sub-pixels are disposed in 12k-8, 12k-4, and 12k columns, each of the plurality of data lines is branched into a plurality of sub-data lines, each of the plurality of sub-data lines is connected to a plurality of sub-pixels having the same color, the first reference voltage line is connected to the plurality of first sub-pixels disposed in the 12k-11 column, the plurality of second sub-pixels disposed in the 12k-10 column, the plurality of third sub-pixels disposed in the 12k-9 column, and the plurality of fourth sub-pixels disposed in the 12k-8 column, the second reference voltage line is connected to the plurality of first sub-pixels disposed in the 12k-7 column, the plurality of second sub-pixels disposed in the 12k-6 column, the plurality of third sub-pixels disposed in the 12k-5 column, and the plurality of fourth sub-pixels disposed in the 12k-4 column, and the third reference voltage line is connected to the plurality of first sub-pixels disposed in the 12k-3 column, the plurality of second sub-pixels disposed in the 12k-2 column, the plurality of third sub-pixels disposed in the 12k-1 column, and the plurality of fourth sub-pixels disposed in the 12k column, where k is a natural number of 1 or more.

[0015] Other matters to state example embodiments are described through the specific embodiments and the accompanying drawings.

[0016] According to the present disclosure, sub-pixels having different colors are sensed during one scan timing, thereby more precisely and / or more accurately compensating for a data voltage.

[0017] According to the present disclosure, a plurality of sub-pixels are sensed during one scan timing, thereby more quickly sensing all sub-pixels.

[0018] According to the present disclosure, an order in which a gate voltage is applied varies for each frame, thereby uniformly displaying an image.

[0019] Effects according to the present disclosure are not limited to what has been exemplified above, and include more various effects in the specification. BRIEF DESCRIPTION OF DRAWINGS

[0020] The above and other aspects, features, and other advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0021] Figure 1 is a schematic view of a display apparatus of one exemplary embodiment of the present disclosure;

[0022] Figure 2 is a circuit diagram of a sub-pixel of a display apparatus of one exemplary embodiment of the present disclosure;

[0023] Figure 3 is a block diagram for explaining an arrangement relationship of a sub-pixel of a display apparatus of one exemplary embodiment of the present disclosure;

[0024] Figure 4 is a diagram for explaining a sensing method of a display apparatus of one exemplary embodiment of the present disclosure;

[0025] Figure 5 is a block diagram for explaining an arrangement relationship of a sub-pixel of a display apparatus of another exemplary embodiment of the present disclosure;

[0026] Figure 6 is a diagram for explaining a sensing method of an even frame of a display apparatus of another exemplary embodiment of the present disclosure;

[0027] Figure 7A is a diagram for explaining a driving sequence of an odd frame of a display apparatus of another exemplary embodiment of the present disclosure;

[0028] Figure 7B is a diagram for explaining a driving sequence of an even frame of a display apparatus of another exemplary embodiment of the present disclosure;

[0029] Figure 8 is a diagram for explaining a charge rate of a data voltage of a display apparatus of another exemplary embodiment of the present disclosure;

[0030] Figure 9 is a block diagram for explaining an arrangement relationship of a sub-pixel of a display apparatus of still another exemplary embodiment (third exemplary embodiment) of the present disclosure;

[0031] Figure 10 is a diagram for explaining a sensing method of a display apparatus of still another exemplary embodiment (third exemplary embodiment) of the present disclosure;

[0032] Figure 11 is a block diagram for explaining an arrangement relationship of a sub-pixel of a display apparatus of yet another exemplary embodiment (fourth exemplary embodiment) of the present disclosure; and

[0033] Figure 12FIG. 1 is a diagram for explaining a sensing method of a display apparatus according to a first exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0034] The accompanying drawings, which are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this application, illustrate embodiments of the present disclosure and together with the description serve to explain the principles of the present disclosure. In the drawings: Figure 1 The advantages and features of the present disclosure and the methods of achieving the advantages and features will become apparent from the exemplary embodiments described below with reference to the accompanying drawings. However, the present disclosure is not limited to the exemplary embodiments disclosed herein and can be implemented in various forms. The exemplary embodiments are provided by way of example only, so that one of ordinary skill in the art can completely understand the disclosure and the scope of the present disclosure. Accordingly, the present disclosure is defined only by the scope of the claims.

[0035] The shapes, sizes, ratios, angles, numbers, and the like shown in the drawings for describing the exemplary embodiments of the present disclosure are merely examples and the present disclosure is not limited thereto. Throughout the specification, like reference numerals generally denote like elements. Furthermore, in the following description of the present disclosure, detailed explanations of known related technologies can be omitted to avoid unnecessarily obscuring the subject matter of the present disclosure. The terms such as "include," "have," and "comprise" used herein are generally intended to allow the addition of other components, unless the terms are used with the term "only." Unless otherwise explicitly stated, any singular reference can include a plurality.

[0036] Components are interpreted to include ordinary error ranges even if not explicitly stated.

[0037] When the arrangement relationship between two components is described using terms such as "upper," "above," "lower," and "adjacent," one or more components can be located between the two components, unless the terms are used with terms such as "immediately adjacent" or "directly."

[0038] When an element or layer is disposed "on" another element or layer, still another layer or element can be directly interposed thereon or therebetween.

[0039] Although the terms "first," "second," and the like are used to describe various components, the components are not limited by the terms. The terms are used only to distinguish one component from another component. Therefore, in the technical idea of the present disclosure, the first component mentioned below can be the second component.

[0040] Throughout the specification, like reference numerals generally denote like elements.

[0041] For ease of description, the sizes and thicknesses of the respective components shown in the drawings are shown, but the present disclosure is not limited to the sizes and thicknesses of the components shown.

[0042] Features of various embodiments of the present disclosure can be partially or wholly combined with or coupled to each other, and can be associated and operated in various technical ways, and these embodiments can be executed independently of or in association with each other.

[0043] A transistor used in a display device of the present disclosure can be implemented by one or more of an n-channel transistor (NMOS) and a p-channel transistor (PMOS). The transistor is implemented by an oxide semiconductor transistor having an oxide semiconductor as an active layer or an LTPS (low temperature polysilicon) transistor having LTPS as an active layer. The transistor can include at least a gate, a source, and a drain. The transistor can be implemented as a thin film transistor on a display panel. In the transistor, carriers flow from the source to the drain. In the case of an n-channel transistor (NMOS), since the carriers are electrons, in order to make the electrons flow from the source to the drain, the source voltage is lower than the drain voltage. The direction of current in the n-channel transistor NMOS is from the drain to the source, and the source can serve as an output terminal. In the case of a p-channel transistor (PMOS), since the carriers are holes, in order to make the holes flow from the source to the drain, the source voltage is higher than the drain voltage. In the p-channel transistor PMOS, the holes flow from the source to the drain, so that the current flows from the source to the drain, and the drain serves as an output terminal. Thus, the source and the drain can be switched depending on the applied voltage, so that it should be noted that the source and the drain of the transistor are not fixed. In the present disclosure, it is assumed that the transistor is an n-channel transistor NMOS, without being limited thereto. Alternatively, a p-channel transistor can be used, so that the circuit structure can be changed.

[0044] A gate signal of a transistor used as a switching element swings between a gate-on voltage and a gate-off voltage. The gate-on voltage is set to be higher than a threshold voltage Vth of the transistor, and the gate-off voltage is set to be lower than the threshold voltage Vth of the transistor. The transistor is turned on in response to the gate-on voltage, and turned off in response to the gate-off voltage. In the case of an NMOS, the gate-on voltage is a gate high voltage VGH, and the gate-off voltage is a gate low voltage VGL. In the case of a PMOS, the gate-on voltage is the gate low voltage VGL, and the gate-off voltage is the gate high voltage VGH.

[0045] Hereinafter, various exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0046] Figure 1 is a schematic view of a display device of one exemplary embodiment of the present disclosure. Referring to Figure 2 , the display device 100 includes a display panel 110, a gate driver 120, a data driver 130, and a timing controller 140.

[0047] The display panel 110 is a panel for displaying an image. The display panel 110 can include various circuits, wirings, and light emitting diodes disposed on a substrate. The display panel 110 is divided by a plurality of data lines DL and a plurality of gate lines GL crossing each other, and includes a plurality of pixels PX connected to the plurality of data lines DL and the plurality of gate lines GL. The display panel 110 includes a display area defined by the plurality of pixels PX and a non-display area formed with various signal lines or pads. The display panel 110 can be implemented by a display panel 110 used in various display devices such as an LED device, an OLED device, or an electrophoretic display device. Hereinafter, it is described that the display panel 110 is a panel used in an OLED device, but is not limited thereto.

[0048] The timing controller 140 receives timing signals such as a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, or a dot clock through a reception circuit such as an LVDS or TMDS interface connected to a host system. The timing controller 140 generates timing control signals to control the data driver 130 and the gate driver 120 based on the input timing signals.

[0049] The data driver 130 supplies a data voltage DATA to a plurality of sub-pixels SP. The data driver 130 can include a plurality of source driving integrated circuits (ICs). Digital video data and a source timing control signal from the timing controller 140 can be supplied to the plurality of source driving ICs. The plurality of source driving ICs convert the digital video data into a gamma voltage to generate the data voltage DATA in response to the source timing signal, and can supply the data voltage DATA through data lines DL of the display panel 110. The plurality of source driving ICs can be connected to the data lines DL of the display panel 110 through a chip on glass (COG) process or a tape automated bonding (TAB) process. In addition, the source driving ICs are formed on the display panel 110 or on a separate PCB substrate to be connected to the display panel 110.

[0050] The gate driver 120 supplies a gate signal to a plurality of sub-pixels SP. The gate driver 120 can include a level shifter and a shift register. The level shifter shifts a level of a clock signal input in a transistor-transistor-logic (TTL) level from the timing controller 140, and then supplies the shifted clock signal to the shift register. The shift register can be formed in a non-display area of the display panel 110 in a GIP manner, but is not limited thereto. The shift register is constituted by a plurality of stages that shift and output the gate signal in response to the clock signal and a driving signal. The plurality of stages included in the shift register sequentially output the gate signal through a plurality of output terminals.

[0051] The display panel 110 can include a plurality of sub-pixels SP. The plurality of sub-pixels SP can be sub-pixels for emitting light of different colors. For example, the plurality of sub-pixels SP can be red sub-pixels, green sub-pixels, and blue sub-pixels, but are not limited thereto, such that the plurality of sub-pixels SP can be red sub-pixels, green sub-pixels, blue sub-pixels, and white sub-pixels. The plurality of sub-pixels SP can constitute a pixel PX. That is, a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel can constitute one pixel PX, and the display panel 110 can include a plurality of pixels PX.

[0052] Hereinafter, a display device according to an exemplary embodiment of the present disclosure will be described in detail with reference to the accompanying drawings. Figure 2 A driving circuit for driving one sub-pixel SP will be described in more detail together.

[0053] Figure 2 is a circuit diagram of a sub-pixel of a display device according to an exemplary embodiment of the present disclosure. In Figure 2 , a circuit diagram of one sub-pixel SP of a plurality of sub-pixels SP of a display device 100 is illustrated.

[0054] Referring to Figure 2 , the sub-pixel SP can include a switching transistor SWT, a sensing transistor SET, a driving transistor DT, a storage capacitor SC, and a light emitting diode 150.

[0055] The light emitting diode 150 can include an anode, an organic layer, and a cathode. The organic layer can include various organic layers such as a hole injection layer, a hole transport layer, an organic light emitting layer, an electron transport layer, and an electron injection layer. The anode of the light emitting diode 150 can be connected to the output terminal of the driving transistor DT, and a low potential voltage VSS can be applied to the cathode. Although it is described in Figure 2 that the light emitting diode 150 is an organic light emitting diode 150, the present disclosure is not limited thereto, and an inorganic light emitting diode (i.e., an LED) can also be used as the light emitting diode 150.

[0056] Referring to Figure 2 , the switching transistor SWT is a transistor that transmits a data voltage DATA to a first node N1 corresponding to the gate of the driving transistor DT. The switching transistor SWT can include a drain connected to a data line DL, a gate connected to a gate line GL, and a source connected to the gate of the driving transistor DT. The switching transistor SWT is turned on by a scan signal SCAN applied from the gate line GL, thereby transmitting the data voltage DATA supplied from the data line DL to the first node N1 corresponding to the gate of the driving transistor DT.

[0057] Referring to Figure 2The drive transistor DT is a transistor configured to supply a drive current to the light emitting diode 150 to drive the light emitting diode 150. The drive transistor DT can include a gate corresponding to the first node N1, a source corresponding to the second node N2 and the output terminal, and a drain corresponding to the third node N3 and the input terminal. The gate of the drive transistor DT is connected to the switching transistor SWT, the drain is applied with the high potential voltage VDD via the high potential voltage line VDDL, and the source is connected to the anode of the light emitting diode 150.

[0058] Referring to Figure 2 The storage capacitor SC is a capacitor that holds a voltage corresponding to the data voltage DATA during one frame. One electrode of the storage capacitor SC is connected to the first node N1, and the other electrode is connected to the second node N2.

[0059] Meanwhile, in the case of the display apparatus 100, as the driving time of each sub-pixel SP increases, the circuit elements such as the drive transistor DT can deteriorate. Accordingly, the unique characteristic values of the circuit elements such as the drive transistor DT can change. Here, the unique characteristic values of the circuit elements can include the threshold voltage Vth of the drive transistor DT or the mobility a of the drive transistor DT. The change in the characteristic values of the circuit elements can cause a change in the brightness of the corresponding sub-pixel SP. Accordingly, the change in the characteristic values of the circuit elements can be used as the same concept as the change in the brightness of the sub-pixel SP.

[0060] Further, the degree of change in the characteristic values between the circuit elements of each sub-pixel SP can vary according to the degree of deterioration of each circuit element. Such a difference in the degree of change in the characteristic values between the circuit elements can cause a brightness deviation between the sub-pixels SP. Accordingly, the characteristic value deviation between the circuit elements can be used as the same concept as the brightness deviation between the sub-pixels SP. The change in the characteristic values of the circuit elements (i.e., the change in the brightness of the sub-pixel SP) and the characteristic value deviation between the circuit elements (i.e., the brightness deviation between the sub-pixels SP) can cause a problem such as a reduction in the accuracy of the brightness or the brightness "expression" of the sub-pixel SP, or can cause a screen abnormality.

[0061] Accordingly, the sub-pixel SP of the display apparatus 100 of the exemplary embodiment of the disclosure can provide a sensing function of sensing the characteristic values of the sub-pixel SP and a compensation function of compensating for the characteristic values of the sub-pixel SP using the sensing result.

[0062] Accordingly, as Figure 2 indicated, the sub-pixel SP can include a sensing transistor SET that effectively controls the voltage state of the source of the drive transistor DT, in addition to the switching transistor SWT, the drive transistor DT, the storage capacitor SC, and the light emitting diode 150.

[0063] Referring toFigure 2 The sensing transistor SET is connected between the source of the driving transistor DT and a reference voltage line RVL configured to supply a reference voltage Vref, and the gate is connected to a gate line GL. Accordingly, the sensing transistor SET is turned on by a sensing signal SENSE applied through the gate line GL to apply the reference voltage Vref supplied through the reference voltage line RVL to the source of the driving transistor DT. In addition, the sensing transistor SET can be used as one of the voltage sensing paths of the source of the driving transistor DT.

[0064] Referring to Figure 3 The switching transistor SWT and the sensing transistor SET of the sub-pixel SP can share one gate line GL. That is, the switching transistor SWT and the sensing transistor SET are connected to the same gate line GL to be applied with the same gate signal. However, for convenience of description, the voltage applied to the gate of the switching transistor SWT is referred to as a scan signal SCAN, and the voltage applied to the gate of the sensing transistor SET is referred to as a sensing signal SENSE. However, the scan signal SCAN and the sensing signal SENSE applied to one sub-pixel SP are the same signal transmitted from the same gate line GL. Accordingly, in Figure 3 , the scan signal SCAN and the sensing voltage SENSE are defined as the gate signals GATE1, GATE2, and GATE3 to be described.

[0065] However, the present disclosure is not limited thereto, such that only the switching transistor SWT is connected to the gate line GL, and the sensing transistor SET can be connected to a separate sensing line. Accordingly, the scan signal SCAN is applied to the switching transistor SWT through the gate line GL, and the sensing signal SENSE is applied to the sensing transistor SET through the sensing line.

[0066] Accordingly, the reference voltage Vref is applied to the source of the driving transistor DT via the sensing transistor SET. In addition, the voltage for sensing the threshold voltage Vth of the driving transistor DT or the mobility a of the driving transistor DT is detected through the reference voltage line RVL. Furthermore, the data driver 130 can compensate for the data voltage DATA according to a change in the threshold voltage Vth of the driving transistor DT or the mobility a of the driving transistor DT.

[0067] Hereinafter, the "arrangement relationship" (i.e., relative position setting) of a plurality of sub-pixels will be described with reference to Figure 3

[0068] Figure 3 is a block diagram for explaining the arrangement relationship of sub-pixels of a display apparatus of one exemplary embodiment of the present disclosure.

[0069] In Figure 3 ​For ease of description, only three pixels PX set in one row are shown, and in the display area, they are repeated. Figure 2 The arrangement of the three pixels PX is shown in the diagram. Furthermore, the transistors positioned between sub-pixels SP1, SP2, and SP3 and the gate lines refer to... Figure 3 The described sensing transistor SET.

[0070] Reference Figure 3 A pixel PX consists of three sub-pixels SP1, SP2, and SP3. For example, as shown... Figure 3 As shown, pixel PX may include a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3. Furthermore, the first sub-pixel P1 is a red sub-pixel, the second sub-pixel SP2 is a green sub-pixel, and the third sub-pixel SP3 is a blue sub-pixel. However, this disclosure is not limited to this; the multiple sub-pixels can be changed to various colors such as magenta, yellow, and cyan.

[0071] Multiple sub-pixels SP1, SP2, and SP3 of the same color can be placed in the same column. That is, multiple first sub-pixels SP1 are placed in the same column, multiple second sub-pixels SP2 are placed in the same column, and multiple third sub-pixels SP3 are placed in the same column.

[0072] More specifically, such as Figure 3 As shown, multiple first sub-pixels SP1 are located in columns 9k-8, 9k-5, and 9k-2. Multiple second sub-pixels SP2 are located in columns 9k-7, 9k-4, and 9k-1. Multiple third sub-pixels SP3 are located in columns 9k-6, 9k-3, and 9k. Here, k refers to a natural number greater than 1.

[0073] That is, for a row, the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 are repeated in sequence.

[0074] like Figure 3 As shown, for a row, the first sub-pixel SP1 set in column 9k-8, the second sub-pixel SP2 set in column 9k-7, and the third sub-pixel SP3 set in column 9k-6 constitute the first pixel PX1. The first sub-pixel SP1 set in column 9k-5, the second sub-pixel SP2 set in column 9k-4, and the third sub-pixel SP3 set in column 9k-3 constitute the second pixel PX2. The first sub-pixel SP1 set in column 9k-2, the second sub-pixel SP2 set in column 9k-1, and the third sub-pixel SP3 set in column 9k constitute the third pixel PX3.

[0075] Each of the plurality of data lines DL1, DL2, and DL3 can branch into a plurality of sub-data lines SDL1-1, SDL1-2, SDL1-3, SDL2-1, SDL2-2, SDL2-3, SDL3-1, SDL3-2, and SDL3-3. Specifically, the first data line DL1 branches into a plurality of first sub-data lines SDL1-1, SDL1-2, and SDL1-3, the second data line DL2 branches into a plurality of second sub-data lines SDL2-1, SDL2-2, and SDL2-3, and the third data line DL3 branches into a plurality of third sub-data lines SDL3-1, SDL3-2, and SDL3-3. As described above, the first sub-data lines SDL1-1, SDL1-2, and SDL1-3 can include a 1-1stsub-data line SDL1-1, a 1-2ndsub-data line SDL1-2, and a 1-3rdsub-data line SDL1-3. The second sub-data lines SDL2-1, SDL2-2, and SDL2-3 can include a 2-1stsub-data line SDL2-1, a 2-2ndsub-data line SDL2-2, and a 2-3rdsub-data line SDL2-3. The third sub-data lines SDL3-1, SDL3-2, and SDL3-3 can include a 3-1stsub-data line SDL3-1, a 3-2ndsub-data line SDL3-2, and a 3-3rdsub-data line SDL3-3.

[0076] The plurality of first sub-data lines SDL1-1, SDL1-2, and SDL1-3 are disposed adjacent to the plurality of first sub-pixels SP1 to be electrically connected to the plurality of first sub-pixels SP1.

[0077] Specifically, the 1-1stsub-data lines SDL1-1 are disposed on one side of the plurality of first sub-pixels SP1 disposed in the 9k-8thcolumn to be electrically connected to the plurality of first sub-pixels SP1 disposed in the 9k-8thcolumn. The plurality of 1-2ndsub-data lines SDL1-2 are disposed between the plurality of first sub-pixels SP1 disposed in the 9k-5thcolumn and the plurality of third sub-pixels SP3 disposed in the 9k-5thcolumn to be electrically connected to the plurality of first sub-pixels SP1 disposed in the 9k-5thcolumn. The plurality of 1-3rdsub-data lines SDL1-3 are disposed between the plurality of first sub-pixels SP1 disposed in the 9k-2ndcolumn and the plurality of third sub-pixels SP3 disposed in the 9k-2ndcolumn to be electrically connected to the plurality of first sub-pixels SP1 disposed in the 9k-2ndcolumn.

[0078] The plurality of second sub-data lines SDL2-1, SDL2-2, and SDL2-3 are disposed adjacent to the plurality of second sub-pixels SP2 to be electrically connected to the plurality of second sub-pixels SP2. The plurality of third sub-data lines SDL3-1, SDL3-2, and SDL3-3 are disposed adjacent to the plurality of third sub-pixels SP3 to be electrically connected to the plurality of third sub-pixels SP3.

[0079] Similar to the arrangement structure of the first sub data lines SDL1-1, SDL1-2 and SDL1-3, the arrangement structures of the plurality of second sub data lines SDL2-1, SDL2-2 and SDL2-3, the plurality of third sub data lines SDL3-1, SDL3-2 and SDL3-3 can be repeated.

[0080] The first data voltage DATA1 as a red data voltage can be applied to the first data line DL1, the second data voltage DATA2 as a green data voltage can be applied to the second data line DL2, and the third data voltage DATA3 as a blue data voltage can be applied to the third data line DL3.

[0081] Therefore, the first data voltage DATA1 as a red data voltage can be applied to the plurality of first sub data lines SDL1-1, SDL1-2 and SDL1-3, and the second data voltage DATA2 as a green data voltage can be applied to the plurality of second sub data lines SDL2-1, SDL2-2 and SDL2-3. In addition, the third data voltage DATA3 as a blue data voltage can be applied to the plurality of third sub data lines SDL3-1, SDL3-2 and SDL3-3.

[0082] The plurality of gate lines GL1 to GL3 can be respectively disposed at both sides of the plurality of sub-pixels SP1, SP2 and SP3.

[0083] Specifically, referring to Figure 3 , the first gate line GL1 is disposed at one side of the plurality of sub-pixels SP1, SP2 and SP3, and the second gate line GL2 and the third gate line GL3 can be disposed at the other side of the plurality of sub-pixels SP1, SP2 and SP3. Generally, the first gate line GL1 as the 3m-2 gate line is disposed at one side of the plurality of sub-pixels SP1, SP2 and SP3, and the second gate line GL2 as the 3m-1 gate line and the third gate line GL3 as the 3m gate line can be disposed at the other side of the plurality of sub-pixels SP1, SP2 and SP3. Here, m is a natural number of 1 or more.

[0084] Meanwhile, for each of the pixels PX1, PX2 and PX3, the first sub-pixel SP1, the second sub-pixel SP2 and the third sub-pixel SP3 can be connected to different gate lines GL1 to GL3 from each other.

[0085] In one row, the first sub-pixel SP1 of the plurality of pixels PX1, PX2, and PX3 is connected to a different gate line GL1 to GL3 from each other, the second sub-pixel SP2 of the plurality of pixels PX1, PX2, and PX3 is connected to a different gate line GL1 to GL3 from each other, and the third sub-pixel SP3 of the plurality of pixels PX1, PX2, and PX3 is connected to a different gate line GL1 to GL3 from each other.

[0086] For example, with reference to Figure 4 , the first gate line GL1 as the 3m-2 gate line is connected to the first sub-pixel SP1 as any one of the sub-pixels of the first pixel PX1. The first gate line GL1 as the 3m-2 gate line is connected to the second sub-pixel SP2 as one of the sub-pixels of the second pixel PX2, which is a sub-pixel having a different color from the first sub-pixel SP1 of the first pixel PX1 connected to the first gate line GL1. Further, the first gate line GL1 as the 3m-2 gate line is connected to the third sub-pixel SP3 as one of the sub-pixels of the third pixel PX3, which is a sub-pixel having a different color from the first sub-pixel SP1 of the first pixel PX1 connected to the first gate line GL1 and the second sub-pixel SP2 of the second pixel PX2 connected to the first gate line GL1.

[0087] The second gate line GL2 as the 3m-1 gate line is connected to the second sub-pixel SP2 as another one of the sub-pixels of the first pixel PX1. The second gate line GL2 as the 3m-1 gate line is connected to the third sub-pixel SP3 as one of the sub-pixels of the second pixel PX2, which is a sub-pixel having a different color from the second sub-pixel SP2 of the first pixel PX1 connected to the second gate line GL2. Further, the second gate line GL2 as the 3m-1 gate line is connected to the first sub-pixel SP1 as one of the sub-pixels of the third pixel PX3, which is a sub-pixel having a different color from the second sub-pixel SP2 of the first pixel PX1 connected to the second gate line GL2 and the third sub-pixel SP3 of the second pixel PX2 connected to the second gate line GL2.

[0088] The third gate line GL3 as the 3m gate line is connected to the third sub-pixel SP3 as yet another one of the sub-pixels of the first pixel PX1. The third gate line GL3 as the 3m gate line is connected to the first sub-pixel SP1 as one of the sub-pixels of the second pixel PX2, which is a sub-pixel having a different color from the third sub-pixel SP3 of the first pixel PX1 connected to the third gate line GL3. Further, the third gate line GL3 as the 3m gate line is connected to the second sub-pixel SP2 as one of the sub-pixels of the third pixel PX3, which is a sub-pixel having a different color from the third sub-pixel SP3 of the first pixel PX1 connected to the third gate line GL3 and the first sub-pixel SP1 of the second pixel PX2 connected to the third gate line GL3.

[0089] Each of the plurality of reference voltage lines RVL1, RVL2, and RVL3 can be disposed in one of the pixels PX1, PX2, and PX3.

[0090] That is, the first reference voltage line RVL1 is disposed within the first pixel PX1, the second reference voltage line RVL2 is disposed within the second pixel PX2, and the third reference voltage line RVL3 is disposed within the third pixel PX3.

[0091] Specifically, the first reference voltage line RVL1 is disposed between the plurality of second sub-pixels SP2 disposed in the 9k-7th column and the plurality of third sub-pixels SP3 disposed in the 9k-6th column. Accordingly, the plurality of first sub-pixels SP1 disposed in the 9k-8th column, the plurality of second sub-pixels SP2 disposed in the 9k-7th column, and the plurality of third sub-pixels SP3 disposed in the 9k-6th column can be connected to the first reference voltage line RVL1.

[0092] The second reference voltage line RVL2 is disposed between the plurality of second sub-pixels SP2 disposed in the 9k-4th column and the plurality of third sub-pixels SP3 disposed in the 9k-3rd column. Accordingly, the plurality of first sub-pixels SP1 disposed in the 9k-5th column, the plurality of second sub-pixels SP2 disposed in the 9k-4th column, and the plurality of third sub-pixels SP3 disposed in the 9k-3rd column can be connected to the second reference voltage line RVL2.

[0093] The third reference voltage line RVL3 is disposed between the plurality of second sub-pixels SP2 disposed in the 9k-1st column and the plurality of third sub-pixels SP3 disposed in the 9kth column. Accordingly, the plurality of first sub-pixels SP1 disposed in the 9k-2nd column, the plurality of second sub-pixels SP2 disposed in the 9k-1st column, and the plurality of third sub-pixels SP3 disposed in the 9k-3rd column can be connected to the third reference voltage line RVL3.

[0094] Hereinafter, a sensing method of a display apparatus according to an exemplary embodiment of the disclosure will be described with reference to the accompanying drawings. Figure 4 A sensing method of a display apparatus according to an exemplary embodiment of the disclosure will be described.

[0095] Figure 4 is a diagram for explaining a sensing method of a display apparatus according to an exemplary embodiment of the disclosure.

[0096] In Figure 2 , a sensing order of the plurality of sub-pixels SP1, SP2, and SP3 shown in Figure 4 is shown.

[0097] In Figure 3In the first scan period 1st SCAN, the first gate voltage GATE1 is the gate high voltage, so that the switch transistor SWT and the sensing transistor SET in the plurality of sub-pixels SP1, SP2, and SP3 connected to the first gate line GL1 are turned on. Further, the plurality of sub-pixels SP1, SP2, and SP3 connected to the first gate line GL1 are sensed by each of the plurality of reference voltage lines RVL1, RVL2, and RVL3.

[0098] The sub-pixels SP1, SP2, and SP3 shown in dotted lines refer to the sub-pixels SP1, SP2, and SP3 in which sensing is performed in the corresponding scan period, and the sub-pixels SP1, SP2, and SP3 having a black pattern refer to the sub-pixels SP1, SP2, and SP3 in which sensing is not performed in the corresponding scan period.

[0099] Referring to Figure 4 and Figure 5 In the first scan period 1st SCAN, the first gate voltage GATE1 is the gate high voltage, so that the switch transistor SWT and the sensing transistor SET in the plurality of sub-pixels SP1, SP2, and SP3 connected to the first gate line GL1 are turned on. Further, the plurality of sub-pixels SP1, SP2, and SP3 connected to the first gate line GL1 are sensed by each of the plurality of reference voltage lines RVL1, RVL2, and RVL3.

[0100] For example, in the first scan period 1st SCAN, the first sub-pixel SP1, which is any one of the sub-pixels of the first pixel PX1, is sensed by the first reference voltage line RVL1. The second sub-pixel SP2, which is a sub-pixel of the second pixel PX2 having a different color from the first sub-pixel SP1 of the first pixel PX1 connected to the first gate line GL1, is sensed by the second reference voltage line RVL2. The third sub-pixel SP3, which is a sub-pixel of the third pixel PX3 having a different color from the first sub-pixel SP1 of the first pixel PX1 connected to the first gate line GL1 and the second sub-pixel SP2 of the second pixel PX2 connected to the first gate line GL1, is sensed by the third reference voltage line RVL3.

[0101] In a subsequent second scan period 2nd SCAN, the second gate voltage GATE2 is the gate high voltage, thereby turning on the switching transistor SWT and the sensing transistor SET in the plurality of sub-pixels SP1, SP2, and SP3 connected to the second gate line GL2. In addition, the plurality of sub-pixels SP1, SP2, and SP3 connected to the second gate line GL2 are sensed by each of the plurality of reference voltage lines RVL1, RVL2, and RVL3.

[0102] For example, in the second scan period 2nd SCAN, the second sub-pixel SP2, which is another sub-pixel of the first pixel PX1, is sensed by the first reference voltage line RVL1. The third sub-pixel SP3, which is a sub-pixel having a different color from the second sub-pixel SP2 of the first pixel PX1 connected to the second gate line GL2, among the sub-pixels of the second pixel PX2, is sensed by the second reference voltage line RVL2. The first sub-pixel SP1, which is a sub-pixel having a different color from the second sub-pixel SP2 of the first pixel PX1 connected to the second gate line GL2 and the third sub-pixel SP3 of the second pixel PX2 connected to the second gate line GL2, among the sub-pixels of the third pixel PX3, is sensed by the third reference voltage line RVL3.

[0103] In a subsequent third scan period 3rd SCAN, the third gate voltage GATE3 is the gate high voltage, thereby turning on the switching transistor SWT and the sensing transistor SET in the plurality of sub-pixels SP1, SP2, and SP3 connected to the third gate line GL3. In addition, the plurality of sub-pixels SP1, SP2, and SP3 connected to the third gate line GL3 are sensed by each of the plurality of reference voltage lines RVL1, RVL2, and RVL3.

[0104] For example, in the third scan period 3rd SCAN, the third sub-pixel SP3, which is another sub-pixel of the first pixel PX1, is sensed by the first reference voltage line RVL1. The first sub-pixel SP1, which is a sub-pixel having a different color from the third sub-pixel SP3 of the first pixel PX1 connected to the third gate line GL3, among the sub-pixels of the second pixel PX2, is sensed by the second reference voltage line RVL2. The second sub-pixel SP2, which is a sub-pixel having a different color from the third sub-pixel SP3 of the first pixel PX1 connected to the third gate line GL3 and the first sub-pixel SP1 of the second pixel PX2 connected to the third gate line GL3, among the sub-pixels of the third pixel PX3, is sensed by the third reference voltage line RVL3.

[0105] As described above, during one of the plurality of scan periods, sub-pixels SP1, SP2, and SP3 having different colors from each other can be sensed.

[0106] In the display apparatus of the related art, only one of the plurality of sub-pixels disposed in the 9k-8th column to the 9kth column is sensed in one scan period, and thus nine scan periods are required to sense all of the plurality of sub-pixels disposed in the 9k-8th column to the 9kth column.

[0107] In contrast, in the display apparatus of one exemplary embodiment of the present disclosure, three of the plurality of sub-pixels SP1, SP2, and SP3 disposed in the 9k-8th column to the 9kth column are sensed in one scan period. Thus, only three scan periods are required to sense all of the plurality of sub-pixels SP1, SP2, and SP3 disposed in the 9k-8th column to the 9kth column. Thus, the display apparatus of one exemplary embodiment of the present disclosure can sense the plurality of sub-pixels more rapidly and more accurately.

[0108] Figure 5 is a block diagram for explaining an arrangement relationship of sub-pixels of the display apparatus of another exemplary embodiment of the present disclosure.

[0109] In Figure 5 , for convenience of description, only four pixels PX disposed in one row are illustrated, and the arrangement relationship of the four pixels PX illustrated in Figure 2 is repeated in the display area. Also, the transistors disposed between the sub-pixels SP1, SP2, SP3, and SP4 and the gate lines refer to the sensing transistors SET described with reference to Figure 5 .

[0110] With reference to Figure 5 , one pixel PX includes four sub-pixels SP1, SP2, SP3, and SP4. For example, as illustrated in Figure 5 , the pixel PX can include a first sub-pixel SP1, a second sub-pixel SP2, a third sub-pixel SP3, and a fourth sub-pixel SP4. Also, the first sub-pixel SP1 is a red sub-pixel, the second sub-pixel SP2 is a white sub-pixel, the third sub-pixel SP3 is a blue sub-pixel, and the fourth sub-pixel SP4 is a green sub-pixel. However, the present disclosure is not limited thereto, and the plurality of sub-pixels can be changed to various colors such as magenta, yellow, and cyan.

[0111] The plurality of sub-pixels SP1, SP2, SP3, and SP4 of the same color can be disposed in the same column. That is, the plurality of first sub-pixels SP1 is disposed in the same column, the plurality of second sub-pixels SP2 is disposed in the same column, the plurality of third sub-pixels SP3 is disposed in the same column, and the plurality of fourth sub-pixels SP4 is disposed in the same column.

[0112] More specifically, as illustrated in Figure 5As shown, multiple first sub-pixels SP1 are located in columns 16k-15, 16k-11, 16k-7, and 16k-3; multiple second sub-pixels SP2 are located in columns 16k-14, 16k-10, 16k-6, and 16k-2; multiple third sub-pixels SP3 are located in columns 16k-13, 16k-9, 16k-5, and 16k-1; and multiple fourth sub-pixels SP4 are located in columns 16k-12, 16k-8, 16k-4, and 16k. Here, k refers to a natural number greater than 1.

[0113] That is, for a row, the first sub-pixel SP1, the second sub-pixel SP2, the third sub-pixel SP3, and the fourth sub-pixel SP4 are repeated in sequence.

[0114] like Figure 5 As shown, for a row, the first sub-pixel SP1 set in columns 16k-15, the second sub-pixel SP2 set in columns 16k-14, the third sub-pixel SP3 set in columns 16k-13, and the fourth sub-pixel SP4 set in columns 16k-12 constitute the first pixel PX1. For a row, the first sub-pixel SP1 set in columns 16k-11, the second sub-pixel SP2 set in columns 16k-10, the third sub-pixel SP3 set in columns 16k-9, and the fourth sub-pixel SP4 set in columns 16k-8 constitute the second pixel PX2. For a row, the first sub-pixel SP1 set in columns 16k-7, the second sub-pixel SP2 set in columns 16k-6, the third sub-pixel SP3 set in columns 16k-5, and the fourth sub-pixel SP4 set in columns 16k-4 constitute the third pixel PX3. The first sub-pixel SP1 set in column 16k-3, the second sub-pixel SP2 set in column 16k-2, the third sub-pixel SP3 set in column 16k-1, and the fourth sub-pixel SP4 set in column 16k constitute the fourth pixel PX4.

[0115] Each of the plurality of data lines DL1, DL2, DL3, and DL4 can be branched into a plurality of sub-data lines SDL1-1, SDL1-2, SDL1-3, SDL1-4, SDL2-1, SDL2-2, SDL2-3, SDL2-4, SDL3-1, SDL3-2, SDL3-3, SDL3-4, SDL4-1, SDL4-2, SDL4-3, and SDL4-4. Specifically, the first data line DL1 can be branched into a plurality of first sub-data lines SDL1-1, SDL1-2, SDL1-3, and SDL1-4, and the second data line DL2 can be branched into a plurality of second sub-data lines SDL2-1, SDL2-2, SDL2-3, and SDL2-4. In addition, the third data line DL3 can be branched into a plurality of third sub-data lines SDL3-1, SDL3-2, SDL3-3, and SDL3-4, and the fourth data line DL4 can be branched into a plurality of fourth sub-data lines SDL4-1, SDL4-2, SDL4-3, and SDL4-4.

[0116] The first sub-data lines SDL1-1, SLD1-2, SDL1-3, and SDL1-4 can include a first-1 sub-data line SDL1-1, a first-2 sub-data line SDL1-2, a first-3 sub-data line SDL1-3, and a first-4 sub-data line SDL1-4. The second sub-data lines SDL2-1, SDL2-2, SDL2-3, and SDL2-4 can include a second-1 sub-data line SDL2-1, a second-2 sub-data line SDL2-2, a second-3 sub-data line SDL2-3, and a second-4 sub-data line SDL2-4. The third sub-data lines SDL3-1, SDL3-2, SDL3-3, and SDL3-4 can include a third-1 sub-data line SDL3-1, a third-2 sub-data line SLD3-2, a third-3 sub-data line SDL3-3, and a third-4 sub-data line SDL3-4. The fourth sub-data lines SDL4-1, SDL4-2, SDL4-3, and SDL3-4 can include a fourth-1 sub-data line SDL4-1, a fourth-2 sub-data line SDL4-2, a fourth-3 sub-data line SDL4-3, and a fourth-4 sub-data line SDL4-4.

[0117] The plurality of first sub-data lines SDL1-1, SDL1-2, SDL1-3, and SDL1-4 are disposed adjacent to the plurality of first sub-pixels SP1 to be connected to the plurality of first sub-pixels SP1.

[0118] The plurality of second sub-data lines SDL2-1, SDL2-2, SDL2-3, and SDL2-4 are disposed adjacent to the plurality of second sub-pixels SP2 to be connected to the plurality of second sub-pixels SP2.

[0119] A plurality of third sub data lines SDL3-1, SDL3-2, SDL3-3, and SDL3-4 are disposed adjacent to the plurality of third sub pixels SP3 to be connected to the plurality of third sub pixels SP3.

[0120] A plurality of fourth sub data lines SDL4-1, SDL4-2, SDL4-3, and SDL4-4 are disposed adjacent to the plurality of fourth sub pixels SP4 to be connected to the plurality of fourth sub pixels SP4.

[0121] Similar to the arrangement structure of the plurality of first sub data lines SDL1-1, SDL1-2, SDL1-3, and SDL1-4, the arrangement structure of the plurality of second sub data lines SDL2-1, SDL2-2, SDL2-3, and SDL2-4, the plurality of third sub data lines SDL3-1, SDL3-2, SDL1-3, and SDL3-4, and the plurality of fourth sub data lines SDL4-1, SDL4-2, SDL4-3, and SDL4-4 can be repeated.

[0122] A first data voltage DATA1 as a red color data voltage can be applied to the first data line DL1, and a second data voltage DATA2 as a white color data voltage can be applied to the second data line DL2. In addition, a third data voltage DATA3 as a blue color data voltage can be applied to the third data line DL3, and a fourth data voltage DATA4 as a green color data voltage can be applied to the fourth data line DL4.

[0123] Therefore, a first data voltage DATA1 as a red color data voltage can be applied to the plurality of first sub data lines SDL1-1, SDL1-2, SDL1-3, and SDL1-4, and a second data voltage DATA2 as a white color data voltage can be applied to the plurality of second sub data lines SDL2-1, SDL2-2, SDL2-3, and SDL2-4. In addition, a third data voltage DATA3 as a blue color data voltage can be applied to the plurality of third sub data lines SDL3-1, SDL3-2, DL3-3, and SDL3-4, and a fourth data voltage DATA4 as a green color data voltage can be applied to the plurality of fourth sub data lines SDL4-1, SDL4-2, SDL4-3, and SDL4-4.

[0124] The plurality of gate lines GL1 to GL4 can be disposed at both sides of the plurality of sub pixels SP1, SP2, SP3, and SP4, respectively.

[0125] In detail, referring to Figure 5The first gate line GL1 and the second gate line GL2 are provided on one side of the plurality of sub-pixels SP1, SP2, SP3, and SP4, and the third gate line GL3 and the fourth gate line GL4 can be provided on the other side of the plurality of sub-pixels SP1, SP2, SP3, and SP4. Generally, the first gate line GL1 as the 4m-3 gate line and the second gate line GL2 as the 4m-2 gate line are provided on one side of the plurality of sub-pixels SP1, SP2, SP3, and SP4. The third gate line GL3 as the 4m-1 gate line and the fourth gate line GL4 as the 4m gate line can be provided on the other side of the plurality of sub-pixels SP1, SP2, SP3, and SP4. Here, m is a natural number of 1 or more.

[0126] Meanwhile, in each of the pixels PX1, PX2, PX3, and PX4, the first sub-pixel SP1, the second sub-pixel SP2, the third sub-pixel SP3, and the fourth sub-pixel SP4 can be connected to different gate lines GL1 to GL4 from each other.

[0127] In one row, the first sub-pixels SP1 of the plurality of pixels PX1, PX2, PX3, and PX4 are connected to different gate lines GL1 to GL4, and the second sub-pixels SP2 of the plurality of pixels PX1, PX2, PX3, and PX4 are connected to different gate lines GL1 to GL4. The third sub-pixels SP3 of the plurality of pixels PX1, PX2, PX3, and PX4 are connected to different gate lines GL1 to GL4, and the fourth sub-pixels SP4 of the plurality of pixels PX1, PX2, PX3, and PX4 are connected to different gate lines GL1 to GL4.

[0128] For example, with reference to Figure 6 The first gate line GL1 as the 4m-3 gate line is connected to the first sub-pixel SP1 of any one of the sub-pixels of the first pixel PX1, and is connected to the third sub-pixel SP3 of the sub-pixels of the second pixel PX2 as a sub-pixel having a different color from the first sub-pixel SP1 of the first pixel PX1 connected to the first gate line GL1. The first gate line GL1 as the 4m-3 gate line is connected to the second sub-pixel SP2 of the sub-pixels of the third pixel PX3 as a sub-pixel having a different color from the first sub-pixel SP1 of the first pixel PX1 connected to the first gate line GL1 and the third sub-pixel SP3 of the second pixel PX2 connected to the first gate line GL1. Further, the first gate line GL1 as the 4m-3 gate line is connected to the fourth sub-pixel SP4 of the sub-pixels of the fourth pixel PX4 as a sub-pixel having a different color from the first sub-pixel SP1 of the first pixel PX1 connected to the first gate line GL1, the third sub-pixel SP3 of the second pixel PX2 connected to the first gate line GL1, and the second sub-pixel SP2 of the third pixel PX3 connected to the first gate line GL1.

[0129] The second gate line GL2, serving as the 4m-2 gate line, connects to the second sub-pixel SP2, which is another sub-pixel of the first pixel PX1, and to the fourth sub-pixel SP4, which is a sub-pixel of a different color than the second sub-pixel SP2 of the first pixel PX1 connected to the second gate line GL2. The second gate line GL2, serving as the 4m-2 gate line, connects to the first sub-pixel SP1, which is a sub-pixel of a different color than both the second sub-pixel SP2 and the fourth sub-pixel SP4 of the second pixel PX2 connected to the second gate line GL2. Furthermore, the second gate line GL2, serving as the 4m-2 gate line, connects to the third sub-pixel SP3, which is a sub-pixel of a different color than the second sub-pixel SP2 of the first pixel PX1 connected to the second gate line GL2, the fourth sub-pixel SP4 of the second pixel PX2 connected to the second gate line GL2, and the first sub-pixel SP1 of the third pixel PX3 connected to the second gate line GL2.

[0130] The third gate line GL3, serving as the 4m-1 gate line, connects to the third sub-pixel SP3, which is another sub-pixel of the first pixel PX1, and to the second sub-pixel SP2, which is a sub-pixel of a different color than the third sub-pixel SP3 of the first pixel PX1 connected to the third gate line GL3. The third gate line GL3, serving as the 4m-1 gate line, also connects to the fourth sub-pixel SP4, which is a sub-pixel of a different color than both the third sub-pixel SP3 of the first pixel PX1 connected to the third gate line GL3 and the second sub-pixel SP2 of the second pixel PX2 connected to the third gate line GL3. Furthermore, the third gate line GL3, serving as the 4m-1 gate line, connects to the first sub-pixel SP1, which is a sub-pixel of a different color than the third sub-pixel SP3 of the first pixel PX1 connected to the third gate line GL3, the second sub-pixel SP2 of the second pixel PX2 connected to the third gate line GL3, and the fourth sub-pixel SP4 of the third pixel PX3 connected to the third gate line GL3.

[0131] The fourth gate line GL4 as the 4mth gate line is connected to the fourth sub-pixel SP4 which is the remaining one sub-pixel of the first pixel PX1, and is connected to the first sub-pixel SP1 which is a sub-pixel having a different color from the fourth sub-pixel SP4 of the first pixel PX1 connected to the fourth gate line GL4, among the sub-pixels of the second pixel PX2. The fourth gate line GL4 as the 4mth gate line is connected to the third sub-pixel SP3 which is a sub-pixel having a different color from the fourth sub-pixel SP4 of the first pixel PX1 connected to the fourth gate line GL4 and the first sub-pixel SP1 of the second pixel PX2 connected to the fourth gate line GL4, among the sub-pixels of the third pixel PX3. Further, the fourth gate line GL4 as the 4mth gate line is connected to the second sub-pixel SP2 which is a sub-pixel having a different color from the fourth sub-pixel SP4 of the first pixel PX1 connected to the fourth gate line GL4, the second sub-pixel SP2 of the second pixel PX2 connected to the fourth gate line GL4, and the third sub-pixel SP3 of the third pixel PX3 connected to the fourth gate line GL4, among the sub-pixels of the fourth pixel PX4.

[0132] Each of the plurality of reference voltage lines RVL1, RVL2, RVL3, and RVL4 can be provided in one of the pixels PX1, PX2, PX3, and PX4.

[0133] That is, the first reference voltage line RVL1 is provided within the first pixel PX1, the second reference voltage line RVL2 is provided within the second pixel PX2, the third reference voltage line RVL3 is provided within the third pixel PX3, and the fourth reference voltage line RVL4 is provided within the fourth pixel PX4.

[0134] Specifically, the first reference voltage line RVL1 is provided between the plurality of second sub-pixels SP2 provided in the 16k-14th column and the plurality of third sub-pixels SP3 provided in the 16k-13th column. Accordingly, the plurality of first sub-pixels SP1 provided in the 16k-15th column, the plurality of second sub-pixels SP2 provided in the 16k-14th column, the plurality of third sub-pixels SP3 provided in the 16k-13th column, and the plurality of fourth sub-pixels SP4 provided in the 16k-12th column can be connected to the first reference voltage line RVL1.

[0135] The second reference voltage line RVL2 is provided between the plurality of second sub-pixels SP2 provided in the 16k-10th column and the plurality of third sub-pixels SP3 provided in the 16k-9th column. Accordingly, the plurality of first sub-pixels SP1 provided in the 16k-11th column, the plurality of second sub-pixels SP2 provided in the 16k-10th column, the plurality of third sub-pixels SP3 provided in the 16k-9th column, and the plurality of fourth sub-pixels SP4 provided in the 16k-8th column can be connected to the second reference voltage line RVL2.

[0136] The third reference voltage line RVL3 is disposed between the plurality of second sub-pixels SP2 disposed in the 16k-6th column and the plurality of third sub-pixels SP3 disposed in the 16k-5th column. Accordingly, the plurality of first sub-pixels SP1 disposed in the 16k-7th column, the plurality of second sub-pixels SP2 disposed in the 16k-6th column, the plurality of third sub-pixels SP3 disposed in the 16k-5th column, and the plurality of fourth sub-pixels SP4 disposed in the 16k-4th column can be connected to the third reference voltage line RVL3.

[0137] The fourth reference voltage line RVL4 is disposed between the plurality of second sub-pixels SP2 disposed in the 16k-2nd column and the plurality of third sub-pixels SP3 disposed in the 16k-1st column. Accordingly, the plurality of first sub-pixels SP1 disposed in the 16k-3rd column, the plurality of second sub-pixels SP2 disposed in the 16k-2nd column, the plurality of third sub-pixels SP3 disposed in the 16k-1st column, and the plurality of fourth sub-pixels SP4 disposed in the 16kth column can be connected to the fourth reference voltage line RVL4.

[0138] Hereinafter, a sensing method of a display apparatus of an exemplary embodiment of the disclosure will be described with reference to the accompanying drawings. Figure 6 A sensing method of a display apparatus of an exemplary embodiment of the disclosure will be described.

[0139] Figure 6 is a view for explaining a sensing method of a display apparatus of another exemplary embodiment of the disclosure.

[0140] In Figure 5 , the state of the plurality of sub-pixels disposed in one row in each of a first scan period 1st SCAN in which a gate high voltage is applied to a first gate line GL1 which is a 4m-3rd gate line, a second scan period 2nd SCAN in which a gate high voltage is applied to a second gate line GL2 on a 4m-2nd gate line, a third scan period 3rd SCAN in which a gate high voltage is applied to a third gate line GL3 on a 4m-1st gate line, and a fourth scan period in which a gate high voltage is applied to a fourth gate line GL4 on a 4mth gate line is shown.

[0141] The sub-pixels SP1, SP2, SP3, and SP4 shown in dotted lines refer to sub-pixels SP1, SP2, SP3, and SP4 in which sensing is performed in the corresponding scan period, and the sub-pixels SP1, SP2, SP3, and SP4 having a black pattern refer to sub-pixels SP1, SP2, SP3, and SP4 in which sensing is not performed in the corresponding scan period.

[0142] Referring to Figure 6 and Figure 7AIn the first scan period 1st SCAN, the first gate voltage GATE1 is a gate high voltage, so that the switching transistor SWT and the sensing transistor SET in the plurality of sub-pixels SP1, SP2, SP3, and SP4 connected to the first gate line GL1 are turned on. Further, the plurality of sub-pixels SP1, SP2, SP3, and SP4 connected to the first gate line GL1 are sensed by each of the plurality of reference voltage lines RVL1, RVL2, RVL3, and RVL4.

[0143] For example, in the first scan period 1st SCAN, the first sub-pixel SP1 as any one of the sub-pixels of the first pixel PX1 is sensed by the first reference voltage line RVL1. The third sub-pixel SP3 as a sub-pixel having a different color from the first sub-pixel SP1 of the first pixel PX1 connected to the first gate line GL1 among the sub-pixels of the second pixel PX2 is sensed by the second reference voltage line RVL2. The second sub-pixel SP2 as a sub-pixel having a different color from the first sub-pixel SP1 of the first pixel PX1 connected to the first gate line GL1 and the third sub-pixel SP3 of the second pixel PX2 connected to the first gate line GL1 among the sub-pixels of the third pixel PX3 is sensed by the third reference voltage line RVL3. The fourth sub-pixel SP4 as a sub-pixel having a different color from the first sub-pixel SP1 of the first pixel PX1 connected to the first gate line GL1, the third sub-pixel SP3 of the second pixel PX2 connected to the first gate line GL1, and the second sub-pixel SP2 of the third pixel PX3 connected to the first gate line GL1 among the sub-pixels of the fourth pixel PX4 is sensed by the fourth reference voltage line RVL4.

[0144] In the subsequent second scan period 2nd SCAN, the second gate voltage GATE2 is a gate high voltage, so that the switching transistor SWT and the sensing transistor SET in the plurality of sub-pixels SP1, SP2, SP3, and SP4 connected to the second gate line GL2 are turned on. Further, the plurality of sub-pixels SP1, SP2, SP3, and SP4 connected to the second gate line GL2 are sensed by each of the plurality of reference voltage lines RVL1, RVL2, RVL3, and PVL4.

[0145] For example, in the second scan period 2nd SCAN, a second sub-pixel SP2, which is another sub-pixel of the first pixel PX1, is sensed by the first reference voltage line RVL1. A fourth sub-pixel SP4, which is a sub-pixel having a different color from the second sub-pixel SP2 of the first pixel PX1 connected to the second gate line GL2, among the sub-pixels of the second pixel PX2, is sensed by the second reference voltage line RVL2. A first sub-pixel SP1, which is a sub-pixel having a different color from the second sub-pixel SP2 of the first pixel PX1 connected to the second gate line GL2 and the fourth sub-pixel SP4 of the second pixel PX2 connected to the second gate line GL2, among the sub-pixels of the third pixel PX3, is sensed by the third reference voltage line RVL3. A third sub-pixel SP3, which is a sub-pixel having a different color from the second sub-pixel SP2 of the first pixel PX1 connected to the second gate line GL2, the fourth sub-pixel SP4 of the second pixel PX2 connected to the second gate line GL2, and the first sub-pixel SP1 of the third pixel PX3 connected to the second gate line GL2, among the sub-pixels of the fourth pixel PX4, is sensed by the fourth reference voltage line RVL4.

[0146] In a subsequent third scan period 3rd SCAN, the third gate voltage GATE3 is the gate high voltage, so that the switching transistor SWT and the sensing transistor SET in the plurality of sub-pixels SP1, SP2, SP3, and SP4 connected to the third gate line GL3 are turned on. In addition, the plurality of sub-pixels SP1, SP2, SP3, and SP4 connected to the third gate line GL3 are sensed by each of the plurality of reference voltage lines RVL1, RVL2, RVL3, and RVL4.

[0147] For example, in the third scan period 3rd SCAN, a third sub-pixel SP3, which is yet another sub-pixel of the first pixel PX1, is sensed by the first reference voltage line RVL1. A second sub-pixel SP2, which is a sub-pixel having a different color from the third sub-pixel SP3 of the first pixel PX1 connected to the third gate line GL3, among the sub-pixels of the second pixel PX2, is sensed by the second reference voltage line RVL2. A fourth sub-pixel SP4, which is a sub-pixel having a different color from the third sub-pixel SP3 of the first pixel PX1 connected to the third gate line GL3 and the second sub-pixel SP2 of the second pixel PX2 connected to the third gate line GL3, among the sub-pixels of the third pixel PX3, is sensed by the third reference voltage line RVL3. A first sub-pixel SP1, which is a sub-pixel having a different color from the third sub-pixel SP3 of the first pixel PX1 connected to the third gate line GL3, the second sub-pixel SP2 of the second pixel PX2 connected to the third gate line GL3, and the fourth sub-pixel SP4 of the third pixel PX3 connected to the third gate line GL3, among the sub-pixels of the fourth pixel PX4, is sensed by the fourth reference voltage line RVL4.

[0148] In a subsequent fourth scan period 4th SCAN, the fourth gate voltage GATE4 is the gate high voltage, so that the switch transistors SWT and the sensing transistors SET in the plurality of sub-pixels SP1, SP2, SP3, and SP4 connected to the fourth gate line GL4 are turned on. In addition, the plurality of sub-pixels SP1, SP2, SP3, and SP4 connected to the fourth gate line GL4 are sensed by each of the plurality of reference voltage lines RVL1, RVL2, RVL3, and RVL4.

[0149] For example, in the fourth scan period 4th SCAN, the fourth sub-pixel SP4, which is the remaining one sub-pixel of the first pixel PX1, is sensed by the first reference voltage line RVL1. The first sub-pixel SP1, which is a sub-pixel having a different color from the fourth sub-pixel SP4 of the first pixel PX1 connected to the fourth gate line GL4, among the sub-pixels of the second pixel PX2, is sensed by the second reference voltage line RVL2. The third sub-pixel SP3, which is a sub-pixel having a different color from the fourth sub-pixel SP4 of the first pixel PX1 connected to the fourth gate line GL4 and the first sub-pixel SP1 of the second pixel PX2 connected to the fourth gate line GL4, among the sub-pixels of the third pixel PX3, is sensed by the third reference voltage line RVL3. The second sub-pixel SP2, which is a sub-pixel having a different color from the fourth sub-pixel SP4 of the first pixel PX1 connected to the fourth gate line GL4, the first sub-pixel SP1 of the second pixel PX2 connected to the fourth gate line GL4, and the third sub-pixel SP3 of the third pixel PX3 connected to the fourth gate line GL4, among the sub-pixels of the fourth pixel PX4, is sensed by the fourth reference voltage line RVL4.

[0150] As described above, during one of the plurality of scan periods, the sub-pixels SP1, SP2, SP3, and SP4 having different colors from each other can be sensed.

[0151] In the related art display apparatus, in one scan period, only one sub-pixel among the plurality of sub-pixels disposed in the 16k-15th column to the 16kth column is sensed, so that 16 scan periods are required to sense all of the plurality of sub-pixels disposed in the 16k-15th column to the 16kth column.

[0152] On the other hand, in the display apparatus of another exemplary embodiment of the present disclosure, four sub-pixels among the plurality of sub-pixels SP1, SP2, SP3, and SP4 disposed in the 16k-15th column to the 16kth column are sensed in one scan period. Accordingly, only four scan periods are required to sense all of the plurality of sub-pixels SP1, SP2, SP3, and SP4 disposed in the 16k-15th column to the 16kth column. Accordingly, the display apparatus of another exemplary embodiment of the present disclosure can sense the plurality of sub-pixels more rapidly and more accurately.

[0153] Hereinafter, a driving method of the display apparatus of exemplary embodiments of the present disclosure will be described with reference to Figure 7B , Figure 8 and Figure 7A .

[0154] Figure 7B is a diagram for explaining a driving sequence of an odd frame of the display apparatus of another exemplary embodiment of the present disclosure.

[0155] Figure 8 is a diagram for explaining a driving sequence of an even frame of the display apparatus of another exemplary embodiment of the present disclosure.

[0156] Figure 7A is a diagram for explaining a data voltage charging rate of the display apparatus of another exemplary embodiment of the present disclosure.

[0157] Although, for convenience of description, the data lines, the reference voltage lines, and the high potential voltage lines are not shown in Figure 7B and Figure 5 , the arrangement relationship of the data lines, the reference voltage lines, and the high potential voltage lines is the same as described in Figure 7A .

[0158] As described above, in the display apparatus of another exemplary embodiment of the present disclosure, the data voltage charging rate of the data lines is increased, and the data voltage charging rate of the data lines is decreased in the odd frame and the even frame. Accordingly, the display apparatus of another exemplary embodiment of the present disclosure can display an image with less flicker and more accurately. Figure 7B and Figure 8As illustrated, an example in which a plurality of first sub-pixels SP1 disposed in the 16k-15th column, a plurality of second sub-pixels SP2 disposed in the 16k-14th column, a plurality of third sub-pixels SP3 disposed in the 16k-13th column, and a plurality of fourth sub-pixels SP4 disposed in the 14k-12th column emit light, a plurality of first sub-pixels SP1 disposed in the 16k-11th column, a plurality of second sub-pixels SP2 disposed in the 16k-10th column, a plurality of third sub-pixels SP3 disposed in the 16k-9th column, and a plurality of fourth sub-pixels SP4 disposed in the 16k-8th column do not emit light, a plurality of first sub-pixels SP1 disposed in the 16k-7th column, a plurality of second sub-pixels SP2 disposed in the 16k-6th column, a plurality of third sub-pixels SP3 disposed in the 16k-5th column, and a plurality of fourth sub-pixels SP4 disposed in the 16k-4th column emit light, and a plurality of first sub-pixels SP1 disposed in the 16k-3rd column, a plurality of second sub-pixels SP2 disposed in the 16k-2nd column, a plurality of third sub-pixels SP1 disposed in the 16k-1st column, and a plurality of fourth sub-pixels SP4 disposed in the 16kth column do not emit light will be described.

[0159] Hereinafter, the data fill rate of the plurality of first sub-pixels SP1 will be described in detail, and the data fill rate of the plurality of second sub-pixels SP2, the data fill rate of the plurality of third sub-pixels SP3, and the data fill rate of the plurality of fourth sub-pixels SP4 will be described in the same principle as the data fill rate of the plurality of first sub-pixels SP1.

[0160] As illustrated, Figure 7A When the vertical stripe pattern is displayed, the fill rate of the first data voltage DATA1 can increase during the first and second horizontal periods (1) and (2), and the fill rate of the first data voltage DATA1 can decrease during the third and fourth horizontal periods (3) and (4). The fill rate waveform of the first data voltage DATA1 can be repeated.

[0161] The turn-on order of the plurality of gate lines GL1, GL2, GL3, and GL4 in the odd frame can be different from the turn-on order of the plurality of gate lines GL1, GL2, GL3, and GL4 in the even frame.

[0162] Specifically, referring to Figure 7B In the odd frame, the first gate line GL1, the second gate line GL2, the third gate line GL3, and the fourth gate line GL4 are sequentially turned on. Referring to Figure 7A In the even frame, the second gate line GL2, the first gate line GL1, the fourth gate line GL4, and the third gate line CL3 are sequentially turned on.

[0163] Simultaneously, the conduction sequence of multiple gate lines GL1, GL2, GL3, and GL4 in odd-numbered frames can be switched to the conduction sequence of multiple gate lines GL1, GL2, GL3, and GL4 in even-numbered frames.

[0164] For example, refer to Figure 7B During odd-numbered frames, in the first horizontal time period (1), the first gate voltage GATE1 is applied to the first gate line GL1 at an on level to charge the first sub-pixel SP1 set in columns 16k-15 with a data voltage.

[0165] During odd-numbered frames, in the second horizontal time period (2), the second gate voltage GATE2 is applied to the second gate line GL2 at an on level to charge the first sub-pixel SP1 set in column 16k-7 with a data voltage.

[0166] During odd-numbered frames, in the third level period (3), the third gate voltage GATE3 is applied to the third gate line GL3 at an on level to discharge the data voltage of the first sub-pixel SP1 set in column 16k-3.

[0167] During odd-numbered frames, in the fourth level period (4), the fourth gate voltage GATE4 is applied to the fourth gate line GL4 at an on level to discharge the data voltage of the first sub-pixel SP1 set in column 16k-11.

[0168] Reference Figure 8 During even-numbered frames, in the first horizontal time period (1), the second gate voltage GATE2 is applied to the second gate line GL2 at an on level to charge the first sub-pixel SP1 set in column 16k-7 with a data voltage.

[0169] During even-numbered frames, in the second horizontal time period (2), the first gate voltage GATE1 is applied to the first gate line GL1 at an on level to charge the first sub-pixel SP1 set in columns 16k-15 with a data voltage.

[0170] During even frames, in the third level period (3), the fourth gate voltage GATE4 is applied to the fourth gate line GL4 at an on level to discharge the data voltage of the first sub-pixel SP1 set in column 16k-11.

[0171] During even frames, in the fourth level period (4), the third gate voltage GATE3 is applied to the third gate line GL3 at the on level to discharge the data voltage of the first sub-pixel SP1 set in column 16k-3.

[0172] As mentioned above, when implementing vertical stripe patterns, please refer to the following text for further details. Figure 9Data charge rates of the plurality of sub-pixels SP1 are described.

[0173] During the odd frame, in a first horizontal period (1) in which a data voltage is started to be charged, the data charge rate of the first sub-pixel SP1 disposed in the 16k-15th column can be 70% (weak charging).

[0174] During the odd frame, in a second horizontal period (2) in which the data voltage is ended to be charged, the charge rate of the first sub-pixel SP1 disposed in the 16k-7th column can be 100% (strong charging, i.e., the amount and rate of full charging).

[0175] During the odd frame, in a third horizontal period (3) and a fourth horizontal period (4) in which the data voltage is discharged, the charge rate of the first sub-pixel SP1 disposed in the 16k-3rd column and the first sub-pixel SP1 disposed in the 16k-11th column can be 0%.

[0176] During the even frame, in a first horizontal period (1) in which a data voltage is started to be charged, the data charge rate of the first sub-pixel SP1 disposed in the 16k-7th column can be 70% (weak charging).

[0177] During the even frame, in a second horizontal period (2) in which the data voltage is ended to be charged, the charge rate of the first sub-pixel SP1 disposed in the 16k-15th column can be 100% (strong charging).

[0178] During the even frame, in a third horizontal period (3) and a fourth horizontal period (4) in which the data voltage is discharged, the charge rate of the first sub-pixel SP1 disposed in the 16k-11th column and the first sub-pixel SP1 disposed in the 16k-3rd column can be 0%.

[0179] In summary, the data charge rate of the first sub-pixel SP1 disposed in the 16k-15th column is 100% (strong charging) during the odd frame and about 70% (weak charging) during the even frame. Thus, the average of the data charge rate of the first sub-pixel SP1 disposed in the 16k-15th column can be 85%, i.e., 80-90%.

[0180] In summary, the data charge rate of the first sub-pixel SP1 disposed in the 16k-7th column is 100% (strong charging) during the even frame and 70% (weak charging) during the odd frame. Thus, the average of the data charge rate of the first sub-pixel SP1 disposed in the 16k-7th column can also be 85%.

[0181] Accordingly, the display apparatus of another exemplary embodiment of the disclosure sets different gate-on sequences for each frame to set the average of the data charge rates of the sub-pixels emitting light from the vertical stripe pattern to be the same.

[0182] Accordingly, in the display apparatus of another exemplary embodiment of the disclosure, line defects do not occur even in a specific pattern, and a pattern can be more precisely implemented. Accordingly, the image quality of the display apparatus of another exemplary embodiment of the disclosure can be improved.

[0183] Hereinafter, a display apparatus of yet another exemplary embodiment (a third exemplary embodiment) of the disclosure will be described in detail with reference to the accompanying drawings. Figure 10 Figure 9 A display apparatus of yet another exemplary embodiment (a third exemplary embodiment) of the disclosure will be described in detail.

[0184] Figure 9 is a block diagram for explaining an arrangement relationship of sub-pixels of the display apparatus of yet another exemplary embodiment (a third exemplary embodiment) of the disclosure.

[0185] In Figure 9 , for convenience of description, only three pixels PX disposed in one row are illustrated, and in a display area, the arrangement relationship of the three pixels PX illustrated in Figure 2 is repeated. Further, a transistor disposed between the sub-pixels SP1, SP2, SP3, and SP4 and a gate line refers to a sensing transistor SET described with reference to Figure 9

[0186] With reference to Figure 9 , one pixel PX includes four sub-pixels SP1, SP2, SP3, and SP4. For example, as illustrated in Figure 9 , the pixel PX can include a first sub-pixel SP1, a second sub-pixel SP2, a third sub-pixel SP3, and a fourth sub-pixel SP4. Further, the first sub-pixel P1 is a red sub-pixel, the second sub-pixel SP2 is a white sub-pixel, the third sub-pixel SP3 is a blue sub-pixel, and the fourth sub-pixel SP4 is a green sub-pixel. However, the disclosure is not limited thereto, and the plurality of sub-pixels can be changed to various colors such as magenta, yellow, and cyan.

[0187] A plurality of sub-pixels SP1, SP2, SP3, and SP4 of the same color can be disposed in the same column. That is, a plurality of first sub-pixels SP1 are disposed in the same column, a plurality of second sub-pixels SP2 are disposed in the same column, a plurality of third sub-pixels SP3 are disposed in the same column, and a plurality of fourth sub-pixels SP4 are disposed in the same column.

[0188] More specifically, as Figure 9 ​​As shown, multiple first sub-pixels SP1 are located in columns 12k-11, 12k-7, and 12k-3; multiple second sub-pixels SP2 are located in columns 12k-10, 12k-6, and 12k-2; multiple third sub-pixels SP3 are located in columns 12k-9, 12k-5, and 12k-1; and multiple fourth sub-pixels SP4 are located in columns 12k-8, 12k-4, and 12k. Here, k refers to a natural number greater than 1.

[0189] That is, for a row, the first sub-pixel SP1, the second sub-pixel SP2, the third sub-pixel SP3, and the fourth sub-pixel SP4 are repeated in sequence.

[0190] like Figure 9 As shown, for a row, the first sub-pixel SP1 set in column 12k-11, the second sub-pixel SP2 set in column 12k-10, the third sub-pixel SP3 set in column 12k-9, and the fourth sub-pixel SP4 set in column 12k-8 constitute the first pixel PX1. For a row, the first sub-pixel SP1 set in column 12k-7, the second sub-pixel SP2 set in column 12k-6, the third sub-pixel SP3 set in column 12k-5, and the fourth sub-pixel SP4 set in column 12k-4 constitute the second pixel PX2. For a row, the first sub-pixel SP1 set in column 12k-3, the second sub-pixel SP2 set in column 12k-2, the third sub-pixel SP3 set in column 12k-1, and the fourth sub-pixel SP4 set in column 12k constitute the third pixel PX3.

[0191] Each of the multiple data lines DL1, DL2, DL3, and DL4 can branch into multiple sub-data lines SDL1-1, SDL1-2, SDL1-3, SDL2-1, SDL2-2, SDL2-3, SDL3-1, SDL3-2, SDL3-3, SDL4-1, SDL4-2, and SDL4-3. Specifically, the first data line DL1 branches into multiple first sub-data lines SDL1-1, SDL1-2, and SDL1-3; the second data line DL2 branches into multiple second sub-data lines SDL2-1, SDL2-2, and SDL2-3; furthermore, the third data line DL3 branches into multiple third sub-data lines SDL3-1, SDL3-2, and SDL3-3; and the fourth data line DL4 branches into multiple fourth sub-data lines SDL4-1, SDL4-2, and SDL4-3.

[0192] The first sub data lines SDL1-1, SDL1-2, and SDL1-3 can include a 1-1stsub data line SDL1-1, a 1-2ndsub data line SDL1-2, and a 1-3rdsub data line SDL1-3, and the second sub data lines SDL2-1, SDL2-2, and SDL2-3 can include a 2-1stsub data line SDL2-1, a 2-2ndsub data line SDL2-2, and a 2-3rdsub data line SDL2-3. The third sub data lines SDL3-1, SDL3-2, and SDL3-3 can include a 3-1stsub data line SDL3-1, a 3-2ndsub data line SDL3-2, and a 3-3rdsub data line SDL3-3, and the fourth sub data lines SDL4-1, SDL4-2, and SDL4-3 can include a 4-1stsub data line SDL4-1, a 4-2ndsub data line SDL4-2, and a 4-3rdsub data line SDL4-3.

[0193] The plurality of first sub data lines SDL1-1, SDL1-2, and SDL1-3 are disposed adjacent to the plurality of first sub pixels SP1 to be connected to the plurality of first sub pixels SP1.

[0194] Specifically, the plurality of 1-1stsub data lines SDL1-1 are disposed at one side of the plurality of first sub pixels SP1 disposed in the 12k-11thcolumn to be electrically connected to the plurality of first sub pixels SP1 disposed in the 12k-11thcolumn. The plurality of 1-2ndsub data lines SDL1-2 are disposed between the plurality of first sub pixels SP1 disposed in the 12k-7thcolumn and the plurality of fourth sub pixels SP4 disposed in the 12k-8thcolumn to be electrically connected to the plurality of first sub pixels SP1 disposed in the 12k-7thcolumn. The plurality of 1-3rdsub data lines SDL1-3 are disposed between the plurality of first sub pixels SP1 disposed in the 12k-3rdcolumn and the plurality of fourth sub pixels SP4 disposed in the 12k-4thcolumn to be electrically connected to the plurality of first sub pixels SP1 disposed in the 12k-3rdcolumn.

[0195] The plurality of second sub data lines SDL2-1, SDL2-2, and SDL2-3 are disposed adjacent to the plurality of second sub pixels SP2 to be connected to the plurality of second sub pixels SP2.

[0196] The plurality of third sub data lines SDL3-1, SDL3-2, and SDL3-3 are disposed adjacent to the plurality of third sub pixels SP3 to be connected to the plurality of third sub pixels SP3.

[0197] The plurality of fourth sub data lines SDL4-1, SDL4-2, and SDL4-3 are disposed adjacent to the plurality of fourth sub pixels SP4 to be connected to the plurality of fourth sub pixels SP4.

[0198] The arrangement structure of the plurality of second sub data lines SDL2-1, SDL2-2, and SDL2-3, the plurality of third sub data lines SDL3-1, SDL3-2, and SDL3-3, and the plurality of fourth sub data lines SDL4-1, SDL4-2, and SDL4-3 can be repeated similarly to the arrangement structure of the first sub data lines SDL1-1, SDL1-2, and SDL1-3.

[0199] A first data voltage DATA1 as a red color data voltage can be applied to the first data line DL1, and a second data voltage DATA2 as a white color data voltage can be applied to the second data line DL2. Further, a third data voltage DATA3 as a blue color data voltage can be applied to the third data line DL3, and a fourth data voltage DATA4 as a green color data voltage can be applied to the fourth data line DL4.

[0200] Therefore, a first data voltage DATA1 as a red color data voltage can be applied to the plurality of first sub data lines SDL1-1, SDL1-2, and SDL1-3, and a second data voltage DATA2 as a white color data voltage can be applied to the plurality of second sub data lines SDL2-1, SDL2-2, and SDL2-3. Further, a third data voltage DATA3 as a blue color data voltage can be applied to the plurality of third sub data lines SDL3-1, SDL3-2, and SDL3-3, and a fourth data voltage DATA4 as a green color data voltage can be applied to the plurality of fourth sub data lines SDL4-1, SDL4-2, and SDL4-3.

[0201] The plurality of gate lines GL1 to GL3 can be respectively disposed at both sides of the plurality of sub pixels SP1, SP2, SP3, and SP4.

[0202] In detail, referring to Figure 10 , the first gate line GL1 is disposed at one side of the plurality of sub pixels SP1, SP2, SP3, and SP4, and the second gate line GL2 and the third gate line GL3 can be disposed at the other side of the plurality of sub pixels SP1, SP2, SP3, and SP4. In general, the first gate line GL1 as the 3m-2 gate line is disposed at one side of the plurality of sub pixels SP1, SP2, SP3, and SP4, and the second gate line GL2 as the 3m-1 gate line and the third gate line GL3 as the 3m gate line can be disposed at the other side of the plurality of sub pixels SP1, SP2, SP3, and SP4. Here, m is a natural number of 1 or more.

[0203] Any one of the plurality of gate lines GL1 to GL3 is connected to the first sub-pixel SP1 of the first pixel PX1, the second sub-pixel SP2 of the first pixel PX1, the third sub-pixel SP3 of the third pixel PX3, and the fourth sub-pixel SP4 of the third pixel PX3. Another of the plurality of gate lines GL1 to GL3 is connected to the third sub-pixel SP3 of the first pixel PX1, the fourth sub-pixel SP4 of the first pixel PX1, the first sub-pixel SP1 of the second pixel PX2, and the second sub-pixel SP2 of the second pixel PX2. The remaining one of the plurality of gate lines GL1 to GL3 is connected to the third sub-pixel SP3 of the second pixel PX1, the fourth sub-pixel SP4 of the second pixel PX2, the first sub-pixel SP1 of the second pixel PX2, and the second sub-pixel SP2 of the second pixel PX2.

[0204] For example, the first gate line GL1 as the 3m-2 gate line can be connected to the first sub-pixel SP1 of the first pixel PX1, the second sub-pixel SP2 of the first pixel PX1, the third sub-pixel SP3 of the third pixel PX3, and the fourth sub-pixel SP4 of the third pixel PX3.

[0205] The second gate line GL2 as the 3m-1 gate line can be connected to the first sub-pixel SP1 of the first pixel PX1, the second sub-pixel SP2 of the first pixel PX1, the third sub-pixel SP3 of the third pixel PX3, and the fourth sub-pixel SP4 of the third pixel PX3.

[0206] The third gate line GL3 as the 3m gate line can be connected to the third sub-pixel SP3 of the second pixel PX2, the fourth sub-pixel SP4 of the second pixel PX1, the first sub-pixel SP1 of the second pixel PX2, and the second sub-pixel SP2 of the second pixel PX2.

[0207] However, the plurality of gate lines GL1 to GL3 and the plurality of sub-pixels SP1, SP2, SP3, and SP4 are not limited to the above-described example, but can vary in various ways.

[0208] The plurality of reference voltage lines RVL1, RVL2, and RVL3 can each be provided in one of the pixels PX1, PX2, and PX3.

[0209] That is, the first reference voltage line RVL1 is provided within the first pixel PX1, the second reference voltage line RVL2 is provided within the second pixel PX2, and the third reference voltage line RVL3 is provided within the third pixel PX3.

[0210] Specifically, the first reference voltage line RVL1 is disposed between the plurality of second sub-pixels SP2 disposed in the 12k-10th column and the plurality of third sub-pixels SP3 disposed in the 12k-9th column. Accordingly, the plurality of first sub-pixels SP1 disposed in the 12k-11th column, the plurality of second sub-pixels SP2 disposed in the 12k-10th column, the plurality of third sub-pixels SP3 disposed in the 12k-9th column, and the plurality of fourth sub-pixels SP4 disposed in the 12k-8th column can be connected to the first reference voltage line RVL1.

[0211] The second reference voltage line RVL1 is disposed between the plurality of second sub-pixels SP2 disposed in the 12k-6th column and the plurality of third sub-pixels SP3 disposed in the 12k-5th column. Accordingly, the plurality of first sub-pixels SP1 disposed in the 12k-7th column, the plurality of second sub-pixels SP2 disposed in the 12k-6th column, the plurality of third sub-pixels SP3 disposed in the 12k-5th column, and the plurality of fourth sub-pixels SP4 disposed in the 12k-4th column can be connected to the second reference voltage line RVL2.

[0212] The third reference voltage line RVL3 is disposed between the plurality of second sub-pixels SP2 disposed in the 12k-2nd column and the plurality of third sub-pixels SP3 disposed in the 12k-1st column. Accordingly, the plurality of first sub-pixels SP1 disposed in the 12k-3rd column, the plurality of second sub-pixels SP2 disposed in the 12k-2nd column, the plurality of third sub-pixels SP3 disposed in the 12k-1st column, and the plurality of fourth sub-pixels SP4 disposed in the 12kth column can be connected to the third reference voltage line RVL3.

[0213] Hereinafter, a sensing method of a display apparatus of yet another exemplary embodiment (a third exemplary embodiment) of the present disclosure will be described with reference to Figure 10 a sensing method of a display apparatus of yet another exemplary embodiment (a third exemplary embodiment) of the present disclosure.

[0214] Figure 10 is a diagram for explaining a sensing method of a display apparatus of yet another exemplary embodiment (a third exemplary embodiment) of the present disclosure.

[0215] In Figure 9 , the state of the plurality of sub-pixels disposed in one row in each of a first scan period 1st SCAN and a fourth scan period 4th SCAN in which a gate high voltage is applied to the first gate line GL1, a second scan period 2nd SCAN and a fifth scan period 5th SCAN in which a gate high voltage is applied to the second gate line GL2, and a third scan period 3rd SCAN and a sixth scan period 6th SCAN in which a gate high voltage is applied to the third gate line GL3 is shown.

[0216] The sub-pixels SP1, SP2, SP3, and SP4 shown in dotted lines refer to sub-pixels SP1, SP2, SP3, and SP4 that perform sensing in the corresponding scan period, while the sub-pixels SP1, SP2, SP3, and SP4 having a black pattern refer to sub-pixels SP1, SP2, SP3, and SP4 that do not perform sensing in the corresponding scan period.

[0217] Referring to Figure 10 and Figure 11 In the first scan period 1st SCAN, the first gate voltage GATE1 is a gate high voltage, such that the switching transistor SWT and the sensing transistor SET in the plurality of sub-pixels SP1, SP2, SP3, and SP4 connected to the first gate line GL1 are turned on. Further, certain sub-pixels among the plurality of sub-pixels SP1, SP2, SP3, and SP4 connected to the first gate line GL1 are sensed by each of the plurality of reference voltage lines RVL1, RVL2, and RVL3.

[0218] For example, in the first scan period 1st SCAN, the first sub-pixel SP1 of the first pixel PX1 is sensed by the first reference voltage line RVL1, and the third sub-pixel SP3 of the third pixel PX3 is sensed by the third reference voltage line RVL3.

[0219] In the subsequent second scan period 2nd SCAN, the second gate voltage GATE2 is a gate high voltage, such that the switching transistor SWT and the sensing transistor SET in the plurality of sub-pixels SP1, SP2, SP3, and SP4 connected to the second gate line GL2 are turned on. Further, certain sub-pixels among the plurality of sub-pixels SP1, SP2, SP3, and SP4 connected to the second gate line GL2 are sensed by each of the plurality of reference voltage lines RVL1, RVL2, and RVL3.

[0220] For example, in the second scan period 2nd SCAN, the third sub-pixel SP3 of the first pixel PX1 is sensed by the first reference voltage line RVL1, and the first sub-pixel SP1 of the second pixel PX2 is sensed by the second reference voltage line RVL2.

[0221] In the subsequent third scan period 3rd SCAN, the third gate voltage GATE3 is a gate high voltage, such that the switching transistor SWT and the sensing transistor SET in the plurality of sub-pixels SP1, SP2, SP3, and SP4 connected to the third gate line GL3 are turned on. Further, certain sub-pixels among the plurality of sub-pixels SP1, SP2, SP3, and SP4 connected to the third gate line GL3 are sensed by each of the plurality of reference voltage lines RVL1, RVL2, and RVL3.

[0222] For example, in the third scan period 3rd SCAN, the third sub-pixel SP3 of the second pixel PX2 is sensed by the second reference voltage line RVL2, and the first sub-pixel SP1 of the third pixel PX3 is sensed by the third reference voltage line RVL3.

[0223] In the subsequent fourth scan period 4th SCAN, the first gate voltage GATE1 is the gate high voltage, so that the switch transistor SWT and the sensing transistor SET in the plurality of sub-pixels SP1, SP2, SP3 and SP4 connected to the second gate line GL2 are turned on. In addition, certain sub-pixels in the plurality of sub-pixels SP1, SP2, SP3 and SP4 connected to the first gate line GL1 are sensed by each of the plurality of reference voltage lines RVL1, RVL2 and RVL3.

[0224] For example, in the fourth scan period 4th SCAN, the second sub-pixel SP2 of the first pixel PX1 is sensed by the first reference voltage line RVL1, and the fourth sub-pixel SP4 of the third pixel PX3 is sensed by the third reference voltage line RVL3.

[0225] In the subsequent fifth scan period 5th SCAN, the second gate voltage GATE2 is the gate high voltage, so that the switch transistor SWT and the sensing transistor SET in the plurality of sub-pixels SP1, SP2, SP3 and SP4 connected to the second gate line GL2 are turned on. In addition, certain sub-pixels in the plurality of sub-pixels SP1, SP2, SP3 and SP4 connected to the second gate line GL2 are sensed by each of the plurality of reference voltage lines RVL1, RVL2 and RVL3.

[0226] For example, in the fifth scan period 5th SCAN, the fourth sub-pixel SP4 of the first pixel PX1 is sensed by the first reference voltage line RVL1, and the second sub-pixel SP2 of the second pixel PX2 is sensed by the second reference voltage line RVL2.

[0227] In the subsequent sixth scan period 6th SCAN, the third gate voltage GATE3 is the gate high voltage, so that the switch transistor SWT and the sensing transistor SET in the plurality of sub-pixels SP1, SP2, SP3 and SP4 connected to the third gate line GL3 are turned on. In addition, certain sub-pixels in the plurality of sub-pixels SP1, SP2, SP3 and SP4 connected to the third gate line GL3 are sensed by each of the plurality of reference voltage lines RVL1, RVL2 and RVL3.

[0228] For example, in the sixth scan period 6th SCAN, the fourth sub-pixel SP4 of the second pixel PX2 is sensed by the second reference voltage line RVL2, and the second sub-pixel SP2 of the third pixel PX3 is sensed by the third reference voltage line RVL3.

[0229] As described above, during one of the plurality of scan periods, sub-pixels SP1, SP2, SP3, and SP4 having different colors from each other can be sensed.

[0230] Further, in the display apparatus of the related art, in one scan period, only one of the plurality of sub-pixels disposed in the 12k-11th column to the 12kth column is sensed, and thus 12 scan periods are required to sense all of the plurality of sub-pixels disposed in the 12k-11th column to the 12kth column.

[0231] On the contrary, in the display apparatus of yet another exemplary embodiment (third exemplary embodiment) of the present disclosure, in one scan period, two of the plurality of sub-pixels SP1, SP2, SP3, and SP4 disposed in the 12k-11th column to the 12kth column are sensed. Thus, only six scan periods are required to sense all of the plurality of sub-pixels SP1, SP2, SP3, and SP4 disposed in the 12k-11th column to the 12kth column. Thus, the display apparatus of yet another exemplary embodiment (third exemplary embodiment) of the present disclosure can more rapidly and accurately sense the plurality of sub-pixels.

[0232] Hereinafter, a display apparatus of still another exemplary embodiment (fourth exemplary embodiment) of the present disclosure will be described. The only difference between the display apparatus of still another exemplary embodiment (fourth exemplary embodiment) of the present disclosure and the display apparatus of another exemplary embodiment (third exemplary embodiment) of the present disclosure is a connection relationship of the plurality of gate lines GL1 to GL3 with the plurality of sub-pixels SP1, SP2, SP3, and SP4, and thus a description thereof will be mainly made. Thus, a repeated description of the display apparatus of still another exemplary embodiment (fourth exemplary embodiment) of the present disclosure and the display apparatus of yet another exemplary embodiment (third exemplary embodiment) of the present disclosure will be omitted.

[0233] Figure 11 is a block diagram for explaining an arrangement relationship of sub-pixels of the display apparatus of still another exemplary embodiment (fourth exemplary embodiment) of the present disclosure.

[0234] Referring to Figure 12 , any one of the plurality of gate lines GL1 to GL3 is connected to the first sub-pixel SP1 of the first pixel PX1, the second sub-pixel SP2 of the second pixel PX2, the third sub-pixel SP3 in the second pixel PX2, and the fourth sub-pixel SP4 of the third pixel PX3.

[0235] Another one of the plurality of gate lines GL1 to GL3 is connected to the fourth sub-pixel SP4 of the first pixel PX1, the first sub-pixel SP1 of the second pixel PX2, the second sub-pixel SP2 of the third pixel PX3, and the third sub-pixel SP3 of the third pixel PX3.

[0236] The remaining one of the plurality of gate lines GL1 to GL3 is connected to the second sub-pixel SP2 of the first pixel PX1, the third sub-pixel SP3 of the first pixel PX1, the fourth sub-pixel SP4 of the second pixel PX2, and the first sub-pixel SP1 of the third pixel PX3.

[0237] For example, the first gate line GL1 which is the 3m-2 gate line can be connected to the first sub-pixel SP1 of the first pixel PX1, the second sub-pixel SP2 of the second pixel PX2, the third sub-pixel SP3 of the second pixel PX2, and the fourth sub-pixel SP4 of the third pixel PX3.

[0238] The second gate line GL2 which is the 3m-1 gate line can be connected to the fourth sub-pixel SP4 of the first pixel PX1, the first sub-pixel SP1 of the second pixel PX2, the second sub-pixel SP2 of the third pixel PX3, and the third sub-pixel SP3 of the third pixel PX3.

[0239] The third gate line GL3 which is the 3m gate line can be connected to the second sub-pixel SP2 of the first pixel PX1, the third sub-pixel SP3 of the first pixel PX1, the fourth sub-pixel SP4 of the second pixel PX2, and the first sub-pixel SP1 of the third pixel PX3.

[0240] However, the plurality of gate lines GL1 to GL3 and the plurality of sub-pixels SP1, SP2, SP3, and SP4 are not limited to the above-described example, and thus can vary in various ways.

[0241] Hereinafter, a display device according to an exemplary embodiment of the present disclosure will be described with reference to the accompanying drawings. Figure 12 A sensing method of a display device according to still another exemplary embodiment (a fourth exemplary embodiment) of the present disclosure will be described.

[0242] Figure 12 is a diagram for explaining a sensing method of a display device according to still another exemplary embodiment (a fourth exemplary embodiment) of the present disclosure.

[0243] In Figure 11In the first scan period 1st SCAN, the first gate voltage GATE1 is the gate high voltage, so that the switching transistor SWT and the sensing transistor SET in the plurality of sub-pixels SP1, SP2, SP3, and SP4 connected to the first gate line GL1 are turned on. Further, some of the plurality of sub-pixels SP1, SP2, SP3, and SP4 connected to the first gate line GL1 are sensed by each of the plurality of reference voltage lines RVL1, RVL2, and RVL3.

[0244] The sub-pixels SP1, SP2, SP3, and SP4 shown in dashed lines refer to the sub-pixels SP1, SP2, SP3, and SP4 in which sensing is performed in the corresponding scan period, and the sub-pixels SP1, SP2, SP3, and SP4 having a black pattern refer to the sub-pixels SP1, SP2, SP3, and SP4 in which sensing is not performed in the corresponding scan period.

[0245] Referring to Figure 12 and ​ In the first scan period 1st SCAN, the first gate voltage GATE1 is the gate high voltage, so that the switching transistor SWT and the sensing transistor SET in the plurality of sub-pixels SP1, SP2, SP3, and SP4 connected to the first gate line GL1 are turned on. Further, some of the plurality of sub-pixels SP1, SP2, SP3, and SP4 connected to the first gate line GL1 are sensed by each of the plurality of reference voltage lines RVL1, RVL2, and RVL3.

[0246] For example, in the first scan period 1st SCAN, the first sub-pixel SP1 of the first pixel PX1 is sensed by the first reference voltage line RVL1, the second sub-pixel SP2 of the second pixel PX2 is sensed by the second reference voltage line RVL2, and the third sub-pixel SP3 of the third pixel PX3 is sensed by the third reference voltage line RVL3.

[0247] In the subsequent second scan period 2nd SCAN, the first gate voltage GATE1 is the gate high voltage, so that the switching transistor SWT and the sensing transistor SET in the plurality of sub-pixels SP1, SP2, SP3, and SP4 connected to the second gate line GL2 are turned on. Further, some of the plurality of sub-pixels SP1, SP2, SP3, and SP4 connected to the first gate line GL1 are sensed by each of the plurality of reference voltage lines RVL1, RVL2, and RVL3.

[0248] For example, in the second scan period 2nd SCAN, the second sub-pixel SP2 of the second pixel PX2 is sensed by the second reference voltage line RVL2.

[0249] In a subsequent third scan period 3rd SCAN, the second gate voltage GATE2 is a gate high voltage, causing the switch transistor SWT and the sense transistor SET in the plurality of sub-pixels SP1, SP2, SP3, and SP4 connected to the second gate line GL2 to turn on. In addition, certain ones of the plurality of sub-pixels SP1, SP2, SP3, and SP4 connected to the second gate line GL2 are sensed by each of the plurality of reference voltage lines RVL1, RVL2, and RVL3.

[0250] For example, in the third scan period 3rd SCAN, the fourth sub-pixel SP4 of the first pixel PX1 is sensed by the first reference voltage line RVL1, the first sub-pixel SP1 of the second pixel PX2 is sensed by the second reference voltage line RVL2, and the second sub-pixel SP2 of the third pixel PX3 is sensed by the third reference voltage line RVL3.

[0251] In a subsequent fourth scan period 4th SCAN, the second gate voltage GATE2 is a gate high voltage, causing the switch transistor SWT and the sense transistor SET in the plurality of sub-pixels SP1, SP2, SP3, and SP4 connected to the second gate line GL2 to turn on. In addition, certain ones of the plurality of sub-pixels SP1, SP2, SP3, and SP4 connected to the second gate line GL2 are sensed by each of the plurality of reference voltage lines RVL1, RVL2, and RVL3.

[0252] For example, in the fourth scan period 4th SCAN, the third sub-pixel SP3 of the third pixel PX3 is sensed by the third reference voltage line RVL3.

[0253] In a subsequent fifth scan period 5th SCAN, the third gate voltage GATE3 is a gate high voltage, causing the switch transistor SWT and the sense transistor SET in the plurality of sub-pixels SP1, SP2, SP3, and SP4 connected to the third gate line GL3 to turn on. In addition, certain ones of the plurality of sub-pixels SP1, SP2, SP3, and SP4 connected to the third gate line GL3 are sensed by each of the plurality of reference voltage lines RVL1, RVL2, and RVL3.

[0254] For example, in the fifth scan period 5th SCAN, the second sub-pixel SP2 of the first pixel PX1 is sensed by the first reference voltage line RVL1, the fourth sub-pixel SP4 of the second pixel PX2 is sensed by the second reference voltage line RVL2, and the first sub-pixel SP1 of the third pixel PX3 is sensed by the third reference voltage line RVL3.

[0255] In a subsequent sixth scan period 6th SCAN, the third gate voltage GATE3 is the gate high voltage, such that the switching transistor SWT and the sensing transistor SET in the plurality of sub-pixels SP1, SP2, SP3, and SP4 connected to the third gate line GL3 are turned on. In addition, some of the plurality of sub-pixels SP1, SP2, SP3, and SP4 connected to the third gate line GL3 are sensed by each of the plurality of reference voltage lines RVL1, RVL2, and RVL3.

[0256] For example, in the sixth scan period 6th SCAN, the third sub-pixel SP3 of the first pixel PX1 is sensed by the first reference voltage line RVL1.

[0257] As described above, during one of the plurality of scan periods, the sub-pixels SP1, SP2, SP3, and SP4 having different colors from each other can be sensed.

[0258] In addition, in the display apparatus of the related art, in one scan period, only one of the plurality of sub-pixels provided in the 12k-11th column to the 12kth column is sensed, and thus 12 sensing periods are required to sense all of the plurality of sub-pixels provided in the 12k-11th column to the 12kth column.

[0259] In contrast, in the display apparatus of still another exemplary embodiment (fourth exemplary embodiment) of the disclosure, in one scan period, three or one of the plurality of sub-pixels SP1, SP2, SP3, and SP4 provided in the 12k-11th column to the 12kth column is sensed. Thus, only six scan periods are required to sense all of the plurality of sub-pixels SP1, SP2, SP3, and SP4 provided in the 12k-11th column to the 12kth column. Thus, the display apparatus of still another exemplary embodiment (fourth exemplary embodiment) of the disclosure can sense the plurality of sub-pixels more rapidly and more accurately.

[0260] The exemplary embodiments of the disclosure can also be described as follows:

[0261] In one aspect of the disclosure, a display apparatus includes a display panel in which a plurality of pixels including first, second, and third sub-pixels each having different colors are disposed, a data driver configured to supply data voltages to the plurality of pixels through a plurality of data lines using sensing results of the plurality of pixels obtained via first, second, and third reference voltage lines, and a gate driver configured to supply gate signals to the plurality of pixels via a plurality of gate lines, wherein the plurality of first sub-pixels are disposed in 9k-8th, 9k-5th, and 9k-2nd columns, wherein the plurality of second sub-pixels are disposed in 9k-7th, 9k-4th, and 9k-1st columns, wherein the plurality of third sub-pixels are disposed in 9k-6th, 9k-3rd, and 9kth columns, each of the plurality of data lines is branched into a plurality of sub-data lines and each of the plurality of sub-data lines is connected to a plurality of sub-pixels having the same color, the first reference voltage line is connected to the plurality of first sub-pixels disposed in the 9k-8th column, the plurality of second sub-pixels disposed in the 9k-7th column, and the plurality of third sub-pixels disposed in the 9k-6th column, the second reference voltage line is connected to the plurality of first sub-pixels disposed in the 9k-5th column, the plurality of second sub-pixels disposed in the 9k-4th column, and the plurality of third sub-pixels disposed in the 9k-3rd column, and the third reference voltage line is connected to the plurality of first sub-pixels disposed in the 9k-2nd column, the plurality of second sub-pixels disposed in the 9k-1st column, and the plurality of third sub-pixels disposed in the 9kth column, to improve a sensing speed of the sub-pixels.

[0262] For one row, any one of the plurality of first sub-pixels disposed in the 9k-8th column, any one of the plurality of second sub-pixels disposed in the 9k-7th column, and any one of the plurality of third sub-pixels disposed in the 9k-6th column can constitute a first pixel, any one of the plurality of first sub-pixels disposed in the 9k-5th column, any one of the plurality of second sub-pixels disposed in the 9k-4th column, and any one of the plurality of third sub-pixels disposed in the 9k-3rd column can constitute a second pixel, and any one of the plurality of first sub-pixels disposed in the 9k-2nd column, any one of the plurality of second sub-pixels disposed in the 9k-1st column, and any one of the plurality of third sub-pixels disposed in the 9kth column constitute a third pixel.

[0263] In each of the first, second, and third pixels, the first, second, and third sub-pixels can be connected to different gate lines from each other.

[0264] The first, second, and third sub-pixels included in the first, second, and third pixels can be connected to different gate lines from each other, the second sub-pixels included in the first, second, and third pixels can be connected to different gate lines from each other, and the third sub-pixels included in the first, second, and third pixels can be connected to different gate lines from each other.

[0265] The 3m-2 gate line can be connected to any one of the sub-pixels of the first pixel, a sub-pixel of the second pixel having a different color from the sub-pixel of the first pixel connected to the 3m-2 gate line, and a sub-pixel of the third pixel having a different color from the sub-pixel of the first pixel connected to the 3m-2 gate line and the sub-pixel of the second pixel connected to the 3m-2 gate line (m is a natural number of 1 or more).

[0266] The 3m-1 gate line is connected to another one of the sub-pixels of the first pixel, a sub-pixel of the second pixel having a different color from the sub-pixel of the first pixel connected to the 3m-1 gate line, and a sub-pixel of the third pixel having a different color from the sub-pixel of the first pixel connected to the 3m-1 gate line and the sub-pixel of the second pixel connected to the 3m-1 gate line.

[0267] The 3m gate line can be connected to still another one of the sub-pixels of the first pixel, a sub-pixel of the second pixel having a different color from the sub-pixel of the first pixel connected to the 3m gate line, and a sub-pixel of the third pixel having a different color from the sub-pixel of the first pixel connected to the 3m gate line and the sub-pixel of the second pixel connected to the 3m gate line.

[0268] In the first scan period, a gate high voltage can be applied to the 3m-2 gate line, in the second scan period, a gate high voltage can be applied to the 3m-1 gate line, and in the third scan period, a gate high voltage can be applied to the 3m gate line.

[0269] In the first scan period, any one of the sub-pixels of the first pixel can be sensed by the first reference voltage line, a sub-pixel of the second pixel having a different color from the sub-pixel of the first pixel connected to the 3m-2 gate line can be sensed by the second reference voltage line, and a sub-pixel of the third pixel having a different color from the sub-pixel of the first pixel connected to the 3m-2 gate line and the sub-pixel of the second pixel connected to the 3m-2 gate line can be sensed by the third reference voltage line.

[0270] In the second scan period, another one of the sub-pixels of the first pixel can be sensed by the first reference voltage line, one of the sub-pixels of the second pixel that has a different color from the sub-pixel of the first pixel connected to the 3m-1th gate line can be sensed by the second reference voltage line, and one of the sub-pixels of the third pixel that has a different color from the sub-pixel of the first pixel connected to the 3m-1th gate line and the sub-pixel of the second pixel connected to the 3m-1th gate line can be sensed by the third reference voltage line.

[0271] In the third scan period, still another one of the sub-pixels of the first pixel can be sensed by the first reference voltage line, one of the sub-pixels of the second pixel that has a different color from the sub-pixel of the first pixel connected to the 3mth gate line can be sensed by the second reference voltage line, and one of the sub-pixels of the third pixel that has a different color from the sub-pixel of the first pixel connected to the 3mth gate line and the sub-pixel of the second pixel connected to the 3m-1th gate line can be sensed by the third reference voltage line.

[0272] The first reference voltage line can be disposed inside the first pixel, the second reference voltage line can be disposed inside the second pixel, and the third reference voltage line can be disposed inside the third pixel.

[0273] Each of the first sub-pixel, the second sub-pixel, and the third sub-pixel can include a switching transistor, a driving transistor, a storage capacitor, a sensing transistor, and a light emitting diode, and the sensing transistor outputs a voltage for sensing a threshold voltage and mobility of the driving transistor to the first reference voltage line, the second reference voltage line, and the third reference voltage line.

[0274] According to another feature of the present application, for a row, any one of a plurality of first sub-pixels disposed in columns 16k-15, any one of a plurality of second sub-pixels disposed in columns 16k-14, any one of a plurality of third sub-pixels disposed in columns 16k-13, and any one of a plurality of fourth sub-pixels disposed in columns 16k-12 constitute a first pixel, any one of a plurality of first sub-pixels disposed in columns 16k-11, any one of a plurality of second sub-pixels disposed in columns 16k-10, any one of a plurality of third sub-pixels disposed in columns 16k-9, and any one of a plurality of fourth sub-pixels disposed in columns 16k-8 constitute a second pixel, any one of a plurality of first sub-pixels disposed in columns 16k-7, any one of a plurality of second sub-pixels disposed in columns 16k-6, any one of a plurality of third sub-pixels disposed in columns 16k-5, and any one of a plurality of fourth sub-pixels disposed in columns 16k-4 constitute a third pixel, and any one of a plurality of first sub-pixels disposed in columns 16k-3, any one of a plurality of second sub-pixels disposed in columns 16k-2, any one of a plurality of third sub-pixels disposed in columns 16k-1, and any one of a plurality of fourth sub-pixels disposed in columns 16k constitute a fourth pixel, in each of the first pixel, the second pixel, the third pixel, and the fourth pixel, the first sub-pixel, the second sub-pixel, the third sub-pixel, and the fourth sub-pixel are connected to different gate lines, the plurality of first sub-pixels included in the first pixel, the second pixel, the third pixel, and the fourth pixel are connected to gate lines different from each other, the plurality of second sub-pixels included in the first pixel, the second pixel, the third pixel, and the fourth pixel are connected to gate lines different from each other, the plurality of third sub-pixels included in the first pixel, the second pixel, the third pixel, and the fourth pixel are connected to gate lines different from each other, and the plurality of fourth sub-pixels included in the first pixel, the second pixel, the third pixel, and the fourth pixel are connected to gate lines different from each other.

[0275] In the first pixel, the second pixel, the third pixel, and the fourth pixel, the first sub-pixel, the second sub-pixel, the third sub-pixel, and the fourth sub-pixel can be connected to different gate lines, including the plurality of first sub-pixels in the first pixel, the second pixel, the third pixel, and the fourth pixel can be connected to different gate lines from each other, including the plurality of second sub-pixels in the first pixel, the second pixel, the third pixel, and the fourth pixel can be connected to different gate lines from each other, including the plurality of third sub-pixels in the first pixel, the second pixel, the third pixel, and the fourth pixel can be connected to different gate lines from each other, and including the plurality of fourth sub-pixels in the first pixel, the second pixel, the third pixel, and the fourth pixel can be connected to different gate lines from each other.

[0276] In the first pixel, the second pixel, the third pixel, and the fourth pixel, the first sub-pixel, the second sub-pixel, the third sub-pixel, and the fourth sub-pixel can be connected to different gate lines, including the plurality of first sub-pixels in the first pixel, the second pixel, the third pixel, and the fourth pixel can be connected to different gate lines from each other, including the plurality of second sub-pixels in the first pixel, the second pixel, the third pixel, and the fourth pixel can be connected to different gate lines from each other, including the plurality of third sub-pixels in the first pixel, the second pixel, the third pixel, and the fourth pixel can be connected to different gate lines from each other, and including the plurality of fourth sub-pixels in the first pixel, the second pixel, the third pixel, and the fourth pixel can be connected to different gate lines from each other.

[0277] The 4m-3 gate line is connected to any one of the sub-pixels of the first pixel, the sub-pixel of the second pixel having a different color from the sub-pixel of the first pixel connected to the 4m-3 gate line, the sub-pixel of the third pixel having a different color from the sub-pixel of the first pixel connected to the 4m-3 gate line and the sub-pixel of the second pixel connected to the 4m-3 gate line, and the sub-pixel of the fourth pixel having a different color from the sub-pixel of the first pixel connected to the 4m-3 gate line, the second pixel connected to the 4m-3 gate line, and the third pixel connected to the 4m-3 gate line (m is a natural number of 1 or more).

[0278] The 4m-2 gate line can be connected to another one of the sub-pixels of the first pixel, a sub-pixel of the second pixel having a different color from the sub-pixel of the first pixel connected to the 4m-2 gate line, a sub-pixel of the third pixel having different colors from the sub-pixel of the first pixel connected to the 4m-2 gate line and the sub-pixel of the second pixel connected to the 4m-2 gate line, and a sub-pixel of the fourth pixel having different colors from the sub-pixel of the first pixel connected to the 4m-2 gate line, the sub-pixel of the second pixel connected to the 4m-2 gate line, and the sub-pixel of the third pixel connected to the 4m-2 gate line.

[0279] The 4m-1 gate line can be connected to still another one of the sub-pixels of the first pixel, a sub-pixel of the second pixel having a different color from the sub-pixel of the first pixel connected to the 4m-1 gate line, a sub-pixel of the third pixel having different colors from the sub-pixel of the first pixel connected to the 4m-1 gate line and the sub-pixel of the second pixel connected to the 4m-1 gate line, and a sub-pixel of the fourth pixel having different colors from the sub-pixel of the first pixel connected to the 4m-1 gate line, the sub-pixel of the second pixel connected to the 4m-1 gate line, and the sub-pixel of the third pixel connected to the 4m-1 gate line.

[0280] The 4m gate line can be connected to a remaining one of the sub-pixels of the first pixel, a sub-pixel of the second pixel having a different color from the sub-pixel of the first pixel connected to the 4m gate line, a sub-pixel of the third pixel having different colors from the sub-pixel of the first pixel connected to the 4m gate line and the sub-pixel of the second pixel connected to the 4m gate line, and a sub-pixel of the fourth pixel having different colors from the sub-pixel of the first pixel connected to the 4m gate line, the sub-pixel of the second pixel connected to the 4m gate line, and the sub-pixel of the third pixel connected to the 4m gate line.

[0281] During the first scan period, a gate high voltage can be applied to the 4m-3 gate line, during the second scan period, a gate high voltage can be applied to the 4m-2 gate line, during the third scan period, a gate high voltage can be applied to the 4m-1 gate line, and during the fourth scan period, a gate high voltage can be applied to the 4m gate line.

[0282] In the first scan period, any one of the sub-pixels of the first pixel can be sensed by the first reference voltage line, the sub-pixel of the second pixel having a different color from the sub-pixel of the first pixel connected to the 4m-3 gate line can be sensed by the second reference voltage line, the sub-pixel of the third pixel having a different color from the sub-pixel of the first pixel connected to the 4m-3 gate line and the sub-pixel of the second pixel connected to the 4m-3 gate line can be sensed by the third reference voltage line, and the sub-pixel of the third pixel having a different color from the sub-pixel of the first pixel connected to the 4m-3 gate line, the sub-pixel of the second pixel connected to the 4m-3 gate line, and the sub-pixel of the third pixel connected to the 4m-3 gate line can be sensed by the fourth reference voltage line.

[0283] In the second scan period, another one of the sub-pixels of the first pixel can be sensed by the first reference voltage line, the sub-pixel of the second pixel having a different color from the sub-pixel of the first pixel connected to the 4m-2 gate line can be sensed by the second reference voltage line, the sub-pixel of the third pixel having a different color from the sub-pixel of the first pixel connected to the 4m-2 gate line and the sub-pixel of the second pixel connected to the 4m-2 gate line can be sensed by the third reference voltage line, and the sub-pixel of the third pixel having a different color from the sub-pixel of the first pixel connected to the 4m-2 gate line, the sub-pixel of the second pixel connected to the 4m-2 gate line, and the sub-pixel of the third pixel connected to the 4m-2 gate line can be sensed by the fourth reference voltage line.

[0284] In the third scan period, still another one of the sub-pixels of the first pixel can be sensed by the first reference voltage line, the sub-pixel of the second pixel having a different color from the sub-pixel of the first pixel connected to the 4m-1 gate line can be sensed by the second reference voltage line, the sub-pixel of the third pixel having a different color from the sub-pixel of the first pixel connected to the 4m-1 gate line and the sub-pixel of the second pixel connected to the 4m-1 gate line can be sensed by the third reference voltage line, and the sub-pixel of the third pixel having a different color from the sub-pixel of the first pixel connected to the 4m-1 gate line, the sub-pixel of the second pixel connected to the 4m-1 gate line, and the sub-pixel of the third pixel connected to the 4m-1 gate line can be sensed by the fourth reference voltage line.

[0285] In the fourth scan period, the remaining one of the sub-pixels of the first pixel can be sensed by the first reference voltage line, the sub-pixel of the second pixel having a different color from the sub-pixel of the first pixel connected to the 4mth gate line can be sensed by the second reference voltage line, the sub-pixel of the third pixel having a different color from the sub-pixel of the first pixel connected to the 4mth gate line and the sub-pixel of the second pixel connected to the 4mth gate line can be sensed by the third reference voltage line, and the sub-pixel of the third pixel having a different color from the sub-pixel of the first pixel connected to the 4mth gate line, the sub-pixel of the second pixel connected to the 4mth gate line, and the sub-pixel of the third pixel connected to the 4mth gate line can be sensed by the fourth reference voltage line.

[0286] The first reference voltage line can be disposed inside the first pixel, the second reference voltage line can be disposed inside the second pixel, the third reference voltage line can be disposed inside the third pixel, and the fourth reference voltage line can be disposed inside the fourth pixel.

[0287] Each of the first sub-pixel, the second sub-pixel, the third sub-pixel, and the fourth sub-pixel can include a switching transistor, a driving transistor, a storage capacitor, a sensing transistor, and a light emitting diode, and the sensing transistor outputs a voltage for sensing a threshold voltage and mobility of the driving transistor to the first reference voltage line, the second reference voltage line, the third reference voltage line, and the fourth reference voltage line.

[0288] Yet another feature of the present disclosure, a display device includes a display panel in which a plurality of pixels including first, second, third, and fourth sub-pixels each having different colors are disposed, a data driver configured to supply data voltages to the plurality of pixels via a plurality of data lines using sensing results of the plurality of pixels obtained via first, second, and third reference voltage lines, and a gate driver configured to supply gate signals to the plurality of pixels via a plurality of gate lines, wherein the plurality of first sub-pixels are disposed in 12k-11th, 12k-7th, and 12k-3rd columns, the plurality of second sub-pixels are disposed in 12k-10th, 12k-6th, and 12k-2nd columns, the plurality of third sub-pixels are disposed in 12k-9th, 12k-5th, and 12k-1st columns, the plurality of fourth sub-pixels are disposed in 12k-8th, 12k-4th, and 12kth columns, each of the plurality of data lines is branched into a plurality of sub-data lines, each of the plurality of sub-data lines is connected to a plurality of sub-pixels having the same color, the first reference voltage line is connected to the plurality of first sub-pixels disposed in the 12k-11th column, the plurality of second sub-pixels disposed in the 12k-10th column, the plurality of third sub-pixels disposed in the 12k-9th column, and the plurality of fourth sub-pixels disposed in the 12k-8th column, the second reference voltage line is connected to the plurality of first sub-pixels disposed in the 12k-7th column, the plurality of second sub-pixels disposed in the 12k-6th column, the plurality of third sub-pixels disposed in the 12k-5th column, and the plurality of fourth sub-pixels disposed in the 12k-4th column, and the third reference voltage line is connected to the plurality of first sub-pixels disposed in the 12k-3rd column, the plurality of second sub-pixels disposed in the 12k-2nd column, the plurality of third sub-pixels disposed in the 12k-1st column, and the plurality of fourth sub-pixels disposed in the 12kth column (k is a natural number of 1 or more).

[0289] For a row, any one of the plurality of first sub-pixels set in the 12k-11th column, any one of the plurality of second sub-pixels set in the 12k-10th column, any one of the plurality of third sub-pixels set in the 12k-9th column, and any one of the plurality of fourth sub-pixels set in the 12k-8th column can constitute a first pixel, any one of the plurality of first sub-pixels set in the 12k-7th column, any one of the plurality of second sub-pixels set in the 12k-6th column, any one of the plurality of third sub-pixels set in the 12k-5th column, and any one of the plurality of fourth sub-pixels set in the 12k-4th column can constitute a second pixel, any one of the plurality of first sub-pixels set in the 12k-3rd column, any one of the plurality of second sub-pixels set in the 12k-2nd column, any one of the plurality of third sub-pixels set in the 12k-1st column, and any one of the plurality of fourth sub-pixels set in the 12k can constitute a third pixel.

[0290] Any one of the plurality of gate lines can be connected to the first sub-pixel of the first pixel, the second sub-pixel of the first pixel, the third sub-pixel of the third pixel, and the fourth sub-pixel of the third pixel, another one of the plurality of gate lines can be connected to the third sub-pixel of the first pixel, the fourth sub-pixel of the second pixel, the first sub-pixel of the second pixel, and the second sub-pixel of the second pixel, and

[0291] The remaining one of the plurality of gate lines can be connected to the third sub-pixel of the second pixel, the fourth sub-pixel of the second pixel, the first sub-pixel of the second pixel, and the second sub-pixel of the second pixel.

[0292] Any one of the plurality of gate lines can be connected to the first sub-pixel of the first pixel, the second sub-pixel of the second pixel, the third sub-pixel of the second pixel, and the fourth sub-pixel of the third pixel, another one of the plurality of gate lines can be connected to the fourth sub-pixel of the first pixel, the first sub-pixel of the second pixel, the second sub-pixel of the third pixel, and the third sub-pixel of the third pixel, and the remaining one of the plurality of gate lines can be connected to the second sub-pixel of the first pixel, the third sub-pixel of the first pixel, the fourth sub-pixel of the second pixel, and the first sub-pixel of the third pixel.

[0293] The first reference voltage line can be disposed inside the first pixel, the second reference voltage line can be disposed inside the second pixel, and the third reference voltage line can be disposed inside the third pixel.

[0294] Each of the first, second, and third sub-pixels can include a switching transistor, a driving transistor, a storage capacitor, a sensing transistor, and a light emitting diode, and the sensing transistor outputs a voltage for sensing a threshold voltage and mobility of the driving transistor to the first, second, and third reference voltage lines.

[0295] Further examples are listed in the following numbered clauses:

[0296] 1. A display apparatus comprising:

[0297] a display panel in which a plurality of pixels including first, second, and third sub-pixels each having different colors are disposed;

[0298] a data driver configured to supply data voltages to the plurality of pixels through a plurality of data lines using sensing results of the plurality of pixels obtained via first, second, and third reference voltage lines; and

[0299] a gate driver configured to supply gate signals to the plurality of pixels via a plurality of gate lines, wherein the plurality of first sub-pixels are disposed in 9k-8th, 9k-5th, and 9k-2nd columns,

[0300] the plurality of second sub-pixels are disposed in 9k-7th, 9k-4th, and 9k-1st columns,

[0301] the plurality of third sub-pixels are disposed in 9k-6th, 9k-3rd, and 9kth columns,

[0302] each of the plurality of data lines is branched into a plurality of sub-data lines,

[0303] each of the plurality of sub-data lines is connected to a plurality of sub-pixels having the same color,

[0304] the first reference voltage line is connected to the plurality of first sub-pixels disposed in the 9k-8th column, the plurality of second sub-pixels disposed in the 9k-7th column, and the plurality of third sub-pixels disposed in the 9k-6th column,

[0305] the second reference voltage line is connected to the plurality of first sub-pixels disposed in the 9k-5th column, the plurality of second sub-pixels disposed in the 9k-4th column, and the plurality of third sub-pixels disposed in the 9k-3rd column, and

[0306] the third reference voltage line is connected to the plurality of first sub-pixels disposed in the 9k-2nd column, the plurality of second sub-pixels disposed in the 9k-1st column, and the plurality of third sub-pixels disposed in the 9kth column (k is a natural number of 1 or more).

[0307] 2. The display device according to item 1,

[0308] wherein, for one row, any one of the plurality of first sub-pixels provided in the 9k-8thcolumn, any one of the plurality of second sub-pixels provided in the 9k-7thcolumn, and any one of the plurality of third sub-pixels provided in the 9k-6thcolumn constitute a first pixel,

[0309] any one of the plurality of first sub-pixels provided in the 9k-5thcolumn, any one of the plurality of second sub-pixels provided in the 9k-4thcolumn, and any one of the plurality of third sub-pixels provided in the 9k-3rdcolumn constitute a second pixel,

[0310] any one of the plurality of first sub-pixels provided in the 9k-2ndcolumn, any one of the plurality of second sub-pixels provided in the 9k-1stcolumn, and any one of the plurality of third sub-pixels provided in the 9kthcolumn constitute a third pixel,

[0311] In the first pixel, the second pixel, and the third pixel, the first sub-pixel, the second sub-pixel, and the third sub-pixel are connected to different gate lines from each other.

[0312] The plurality of first sub-pixels included in the first pixel, the second pixel, and the third pixel can be connected to different gate lines from each other,

[0313] The plurality of second sub-pixels included in the first pixel, the second pixel, and the third pixel are connected to different gate lines from each other,

[0314] The plurality of third sub-pixels included in the first pixel, the second pixel, and the third pixel are connected to different gate lines from each other.

[0315] 3. The display device according to item 1 or 2,

[0316] wherein the 3m-2ndgate line can be connected to any one of the sub-pixels of the first pixel, any one of the sub-pixels of the second pixel having a different color from the sub-pixel of the first pixel connected to the 3m-2ndgate line, and any one of the sub-pixels of the third pixel having a different color from the sub-pixel of the first pixel connected to the 3m-2ndgate line and the sub-pixel of the second pixel connected to the 3m-2ndgate line (m is a natural number of 1 or more).

[0317] 4. The display device according to item 3,

[0318] wherein the 3m-1 gate line is connected to another one of the sub-pixels of the first pixel, to a sub-pixel of the sub-pixels of the second pixel having a different color from the sub-pixel of the first pixel connected to the 3m-1 gate line, and to a sub-pixel of the sub-pixels of the third pixel having different colors from the sub-pixel of the first pixel connected to the 3m-1 gate line and the sub-pixel of the second pixel connected to the 3m-1 gate line.

[0319] 5. The display device according to item 4,

[0320] wherein the 3m gate line is connected to yet another one of the sub-pixels of the first pixel, to a sub-pixel of the sub-pixels of the second pixel having a different color from the sub-pixel of the first pixel connected to the 3m gate line, and to a sub-pixel of the sub-pixels of the third pixel having different colors from the sub-pixel of the first pixel connected to the 3m gate line and the sub-pixel of the second pixel connected to the 3m gate line.

[0321] 6. The display device according to item 5,

[0322] wherein in the first scan period, a gate high voltage is applied to the 3m-2 gate line,

[0323] in the second scan period, a gate high voltage is applied to the 3m-1 gate line, and

[0324] in the third scan period, a gate high voltage is applied to the 3m gate line.

[0325] 7. The display device according to item 5 or 6,

[0326] wherein in the first scan period, any one of the sub-pixels of the first pixel is sensed by the first reference voltage line,

[0327] a sub-pixel of the sub-pixels of the second pixel having a different color from the sub-pixel of the first pixel connected to the 3m-2 gate line is sensed by the second reference voltage line, and

[0328] a sub-pixel of the sub-pixels of the third pixel having different colors from the sub-pixel of the first pixel connected to the 3m-2 gate line and the sub-pixel of the second pixel connected to the 3m-2 gate line is sensed by the third reference voltage line.

[0329] 8. The display device according to any one of items 5 to 7,

[0330] wherein in the second scan period, another one of the sub-pixels of the first pixel is sensed by the first reference voltage line,

[0331] a sub-pixel of the second pixel connected to the first pixel of the 3m-1th gate line has a different color, and

[0332] a sub-pixel of the third pixel connected to the first pixel of the 3m-1th gate line and a sub-pixel of the second pixel connected to the 3m-1th gate line have different colors.

[0333] 9. The display apparatus according to item 8,

[0334] wherein, in the third scan period, another sub-pixel of the sub-pixels of the first pixel is sensed by the first reference voltage line,

[0335] a sub-pixel of the second pixel connected to the first pixel of the 3mth gate line has a different color, and

[0336] a sub-pixel of the third pixel connected to the first pixel of the 3mth gate line and a sub-pixel of the second pixel connected to the 3mth gate line have different colors.

[0337] 10. The display apparatus according to item 2,

[0338] wherein the first reference voltage line is disposed inside the first pixel, the second reference voltage line is disposed inside the second pixel, and the third reference voltage line is disposed inside the third pixel.

[0339] 11. The display apparatus according to any one of the preceding items,

[0340] wherein each of the first sub-pixel, the second sub-pixel, and the third sub-pixel includes:

[0341] a switching transistor, a driving transistor, a storage capacitor, a sensing transistor, and a light emitting diode, and the sensing transistor outputs a voltage for sensing a threshold voltage and mobility of the driving transistor to the first reference voltage line, the second reference voltage line, and the third reference voltage line.

[0342] 12. A display apparatus comprising:

[0343] a display panel in which a plurality of pixels including first sub-pixels, second sub-pixels, and third sub-pixels each having different colors are disposed;

[0344] a data driver configured to supply a data voltage to the plurality of pixels via a plurality of data lines using sensing results of the plurality of pixels obtained via a first reference voltage line, a second reference voltage line, a third reference voltage line, and a fourth reference voltage line; and

[0345] a gate driver configured to supply a gate signal to a plurality of pixels via a plurality of gate lines,

[0346] wherein a plurality of first sub-pixels are disposed in the 16k-15th column, the 16k-11th column, the 16k-7th column, and the 16k-3rd column,

[0347] a plurality of second sub-pixels are disposed in the 16k-14th column, the 16k-10th column, the 16k-6th column, and the 16k-2nd column,

[0348] a plurality of third sub-pixels are disposed in the 16k-13th column, the 16k-9th column, the 16k-5th column, and the 16k-1st column,

[0349] a plurality of fourth sub-pixels are disposed in the 16k-12th column, the 16k-8th column, the 16k-4th column, and the 16kth column,

[0350] each of the plurality of data lines is branched into a plurality of sub-data lines,

[0351] each of the plurality of sub-data lines is connected to a plurality of sub-pixels having the same color,

[0352] the first reference voltage line is connected to the plurality of first sub-pixels disposed in the 16k-15th column, the plurality of second sub-pixels disposed in the 16k-14th column, the plurality of third sub-pixels disposed in the 16k-13th column, and the plurality of fourth sub-pixels disposed in the 16k-12th column,

[0353] the second reference voltage line is connected to the plurality of first sub-pixels disposed in the 16k-11th column, the plurality of second sub-pixels disposed in the 16k-10th column, the plurality of third sub-pixels disposed in the 16k-9th column, and the plurality of fourth sub-pixels disposed in the 16k-8th column,

[0354] the third reference voltage line is connected to the plurality of first sub-pixels disposed in the 16k-7th column, the plurality of second sub-pixels disposed in the 16k-6th column, the plurality of third sub-pixels disposed in the 16k-5th column, and the plurality of fourth sub-pixels disposed in the 16k-4th column, and

[0355] the fourth reference voltage line is connected to the plurality of first sub-pixels disposed in the 16k-6th column, the plurality of second sub-pixels disposed in the 16k-2nd column, the plurality of third sub-pixels disposed in the 16k-1st column, and the plurality of fourth sub-pixels disposed in the 16kth column (k is a natural number of 1 or more).

[0356] 13. The display device according to item 12,

[0357] wherein, for a row, any one of a plurality of first sub-pixels disposed in the 16k-15th column, any one of a plurality of second sub-pixels disposed in the 16k-14th column, any one of a plurality of third sub-pixels disposed in the 16k-13th column, and any one of a plurality of fourth sub-pixels disposed in the 16k-12th column constitute a first pixel,

[0358] any one of a plurality of first sub-pixels disposed in the 16k-11th column, any one of a plurality of second sub-pixels disposed in the 16k-10th column, any one of a plurality of third sub-pixels disposed in the 16k-9th column, and any one of a plurality of fourth sub-pixels disposed in the 16k-8th column constitute a second pixel,

[0359] any one of a plurality of first sub-pixels disposed in the 16k-7th column, any one of a plurality of second sub-pixels disposed in the 16k-6th column, any one of a plurality of third sub-pixels disposed in the 16k-5th column, and any one of a plurality of fourth sub-pixels disposed in the 16k-4th column constitute a third pixel, and

[0360] any one of a plurality of first sub-pixels disposed in the 16k-3rd column, any one of a plurality of second sub-pixels disposed in the 16k-2nd column, any one of a plurality of third sub-pixels disposed in the 16k-1st column, and any one of a plurality of fourth sub-pixels disposed in the 16kth column constitute a fourth pixel,

[0361] In each of the first pixel, the second pixel, the third pixel, and the fourth pixel, the first sub-pixel, the second sub-pixel, the third sub-pixel, and the fourth sub-pixel are connected to different gate lines from each other,

[0362] The plurality of first sub-pixels included in the first pixel, the second pixel, the third pixel, and the fourth pixel are connected to different gate lines from each other,

[0363] The plurality of second sub-pixels included in the first pixel, the second pixel, the third pixel, and the fourth pixel are connected to different gate lines from each other,

[0364] The plurality of third sub-pixels included in the first pixel, the second pixel, the third pixel, and the fourth pixel are connected to different gate lines from each other, and

[0365] The plurality of fourth sub-pixels included in the first pixel, the second pixel, the third pixel, and the fourth pixel are connected to different gate lines from each other.

[0366] 14. The display device according to item 12 or 13,

[0367] wherein the 4m-3rd gate line is connected to any one of the sub-pixels of the first pixel, the sub-pixels of the second pixel which have different colors from the sub-pixels of the first pixel connected to the 4m-3rd gate line, the sub-pixels of the third pixel which have different colors from the sub-pixels of the first pixel connected to the 4m-3rd gate line and the sub-pixels of the second pixel connected to the 4m-3rd gate line, and the sub-pixels of the fourth pixel which have different colors from the sub-pixels of the first pixel connected to the 4m-3rd gate line, the sub-pixels of the second pixel connected to the 4m-3rd gate line, and the sub-pixels of the third pixel connected to the 4m-3rd gate line (m is a natural number of 1 or more).

[0368] 15. The display device according to item 14,

[0369] wherein the 4m-2nd gate line is connected to another one of the sub-pixels of the first pixel, the sub-pixels of the second pixel which have different colors from the sub-pixels of the first pixel connected to the 4m-2nd gate line, the sub-pixels of the third pixel which have different colors from the sub-pixels of the first pixel connected to the 4m-2nd gate line and the sub-pixels of the second pixel connected to the 4m-2nd gate line, and the sub-pixels of the fourth pixel which have different colors from the sub-pixels of the first pixel connected to the 4m-2nd gate line, the sub-pixels of the second pixel connected to the 4m-2nd gate line, and the sub-pixels of the third pixel connected to the 4m-2nd gate line.

[0370] 16. The display device according to item 15,

[0371] wherein the 4m-1st gate line is connected to still another one of the sub-pixels of the first pixel, the sub-pixels of the second pixel which have different colors from the sub-pixels of the first pixel connected to the 4m-1st gate line, the sub-pixels of the third pixel which have different colors from the sub-pixels of the first pixel connected to the 4m-1st gate line and the sub-pixels of the second pixel connected to the 4m-1st gate line, and the sub-pixels of the fourth pixel which have different colors from the sub-pixels of the first pixel connected to the 4m-1st gate line, the sub-pixels of the second pixel connected to the 4m-1st gate line, and the sub-pixels of the third pixel connected to the 4m-1st gate line.

[0372] 17. The display device according to item 16,

[0373] wherein the 4mth gate line is connected to a remaining one of the sub-pixels of the first pixel, a sub-pixel of the second pixel having a different color from the sub-pixel of the first pixel connected to the 4mth gate line, a sub-pixel of the third pixel having a different color from the sub-pixel of the first pixel connected to the 4mth gate line and the sub-pixel of the second pixel connected to the 4mth gate line, and a sub-pixel of the fourth pixel having a different color from the sub-pixel of the first pixel connected to the 4mth gate line, the sub-pixel of the second pixel connected to the 4mth gate line, and the sub-pixel of the third pixel connected to the 4mth gate line.

[0374] 18. The display device according to claim 17,

[0375] wherein during the first scan period, a gate high voltage is applied to the 4m-3rd gate line,

[0376] during the second scan period, a gate high voltage is applied to the 4m-2nd gate line,

[0377] during the third scan period, a gate high voltage is applied to the 4m-1st gate line, and

[0378] during the fourth scan period, a gate high voltage is applied to the 4mth gate line.

[0379] 19. The display device according to claim 18, wherein in the first scan period,

[0380] any one of the sub-pixels of the first pixel is sensed by the first reference voltage line,

[0381] the sub-pixel of the second pixel having a different color from the sub-pixel of the first pixel connected to the 4m-3rd gate line is sensed by the second reference voltage line,

[0382] the sub-pixel of the third pixel having a different color from the sub-pixel of the first pixel connected to the 4m-3rd gate line and the sub-pixel of the second pixel connected to the 4m-3rd gate line is sensed by the third reference voltage line, and

[0383] the sub-pixel of the third pixel having a different color from the sub-pixel of the first pixel connected to the 4m-3rd gate line, the sub-pixel of the second pixel connected to the 4m-3rd gate line, and the sub-pixel of the third pixel connected to the 4m-3rd gate line is sensed by the fourth reference voltage line.

[0384] 20. The display device according to claim 18 or 19,

[0385] wherein in the second scan period,

[0386] another one of the sub-pixels of the first pixel is sensed by the first reference voltage line,

[0387] a sub-pixel of the second pixel having a different color from the sub-pixel of the first pixel connected to the 4m-2 gate line is sensed by the second reference voltage line,

[0388] a sub-pixel of the third pixel having a different color from the sub-pixel of the first pixel connected to the 4m-2 gate line and the sub-pixel of the second pixel connected to the 4m-2 gate line is sensed by the third reference voltage line, and

[0389] a sub-pixel of the third pixel having a different color from the sub-pixel of the first pixel connected to the 4m-2 gate line, the sub-pixel of the second pixel connected to the 4m-2 gate line, and the sub-pixel of the third pixel connected to the 4m-2 gate line is sensed by the fourth reference voltage line.

[0390] 21. The display device according to any one of items 18 to 20,

[0391] wherein in the third scan period,

[0392] another one of the sub-pixels of the first pixel is sensed by the first reference voltage line,

[0393] a sub-pixel of the second pixel having a different color from the sub-pixel of the first pixel connected to the 4m-1 gate line is sensed by the second reference voltage line,

[0394] a sub-pixel of the third pixel having a different color from the sub-pixel of the first pixel connected to the 4m-1 gate line and the sub-pixel of the second pixel connected to the 4m-1 gate line is sensed by the third reference voltage line, and

[0395] a sub-pixel of the third pixel having a different color from the sub-pixel of the first pixel connected to the 4m-1 gate line, the sub-pixel of the second pixel connected to the 4m-1 gate line, and the sub-pixel of the third pixel connected to the 4m-1 gate line is sensed by the fourth reference voltage line.

[0396] 22. The display device according to item 21,

[0397] wherein in the fourth scan period,

[0398] the remaining one of the sub-pixels of the first pixel is sensed by the first reference voltage line,

[0399] a sub-pixel of the second pixel having a different color from the sub-pixel of the first pixel connected to the 4m gate line is sensed by the second reference voltage line,

[0400] the third sub-pixel of the third pixel is sensed by the fourth reference voltage line.

[0401] the third sub-pixel of the third pixel is sensed by the fourth reference voltage line.

[0402] 23. The display apparatus according to any one of items 13 to 22,

[0403] wherein the first reference voltage line is disposed inside the first pixel,

[0404] the second reference voltage line is disposed inside the second pixel,

[0405] the third reference voltage line is disposed inside the third pixel, and

[0406] the fourth reference voltage line is disposed inside the fourth pixel.

[0407] 24. The display apparatus according to item 12, wherein each of the first sub-pixel, the second sub-pixel, the third sub-pixel, and the fourth sub-pixel includes:

[0408] a switching transistor, a driving transistor, a storage capacitor, a sensing transistor, and a light emitting diode, and the sensing transistor outputs a voltage for sensing a threshold voltage and mobility of the driving transistor to the first reference voltage line, the second reference voltage line, the third reference voltage line, and the fourth reference voltage line.

[0409] 25. A display apparatus comprising:

[0410] a display panel in which a plurality of pixels including first sub-pixels, second sub-pixels, and third sub-pixels each having different colors are disposed;

[0411] a data driver configured to supply a data voltage to the plurality of pixels via a plurality of data lines using sensing results of the plurality of pixels obtained via first reference voltage lines, second reference voltage lines, and third reference voltage lines; and

[0412] a gate driver configured to supply a gate signal to the plurality of pixels via a plurality of gate lines,

[0413] wherein the plurality of first sub-pixels are disposed in 12k-11th, 12k-7th, and 12k-3rd columns,

[0414] The plurality of second sub-pixels are arranged in the 12k-10th column, the 12k-6th column, and the 12k-2nd column,

[0415] The plurality of third sub-pixels are arranged in the 12k-9th column, the 12k-5th column, and the 12k-1st column, and

[0416] The plurality of fourth sub-pixels are arranged in the 12k-8th column, the 12k-4th column, and the 12th column,

[0417] Each of the plurality of data lines is branched into a plurality of sub-data lines,

[0418] Each of the plurality of sub-data lines is connected to a plurality of sub-pixels having the same color,

[0419] The first reference voltage line is connected to the plurality of first sub-pixels arranged in the 12k-11th column, the plurality of second sub-pixels arranged in the 12k-10th column, the plurality of third sub-pixels arranged in the 12k-9th column, and the plurality of fourth sub-pixels arranged in the 12k-8th column,

[0420] The second reference voltage line is connected to the plurality of first sub-pixels arranged in the 12k-7th column, the plurality of second sub-pixels arranged in the 12k-6th column, the plurality of third sub-pixels arranged in the 12k-5th column, and the plurality of fourth sub-pixels arranged in the 12k-4th column, and

[0421] The third reference voltage line is connected to the plurality of first sub-pixels arranged in the 12k-3rd column, the plurality of second sub-pixels arranged in the 12k-2nd column, the plurality of third sub-pixels arranged in the 12k-1st column, and the plurality of fourth sub-pixels arranged in the 12th column (k is a natural number of 1 or more).

[0422] 26. The display device according to item 25,

[0423] wherein, for one row,

[0424] any one of the plurality of first sub-pixels arranged in the 12k-11th column, any one of the plurality of second sub-pixels arranged in the 12k-10th column, any one of the plurality of third sub-pixels arranged in the 12k-9th column, and any one of the plurality of fourth sub-pixels arranged in the 12k-8th column constitute a first pixel,

[0425] any one of the plurality of first sub-pixels arranged in the 12k-7th column, any one of the plurality of second sub-pixels arranged in the 12k-6th column, any one of the plurality of third sub-pixels arranged in the 12k-5th column, and any one of the plurality of fourth sub-pixels arranged in the 12k-4th column constitute a second pixel,

[0426] Any one of the plurality of first sub-pixels arranged in the 12k-3column, any one of the plurality of second sub-pixels arranged in the 12k-2column, any one of the plurality of third sub-pixels arranged in the 12k-1column, and any one of the plurality of fourth sub-pixels arranged in the 12kcolumn constitute a third pixel.

[0427] 27. The display device according to claim 26,

[0428] wherein any one of the plurality of gate lines is connected to the first sub-pixel of the first pixel, the second sub-pixel of the first pixel, the third sub-pixel of the third pixel, and the fourth sub-pixel of the third pixel,

[0429] another one of the plurality of gate lines is connected to the third sub-pixel of the first pixel, the fourth sub-pixel of the first pixel, the first sub-pixel of the second pixel, and the second sub-pixel of the second pixel, and

[0430] the remaining one of the plurality of gate lines is connected to the third sub-pixel of the second pixel, the fourth sub-pixel of the second pixel, the first sub-pixel of the second pixel, and the second sub-pixel of the second pixel.

[0431] 28. The display device according to claim 26 or 27,

[0432] wherein any one of the plurality of gate lines is connected to the first sub-pixel of the first pixel, the second sub-pixel of the second pixel, the third sub-pixel of the second pixel, and the fourth sub-pixel of the third pixel,

[0433] another one of the plurality of gate lines is connected to the fourth sub-pixel of the first pixel, the first sub-pixel of the second pixel, the second sub-pixel of the third pixel, and the third sub-pixel of the third pixel, and

[0434] the remaining one of the plurality of gate lines is connected to the second sub-pixel of the first pixel, the third sub-pixel of the first pixel, the fourth sub-pixel of the second pixel, and the first sub-pixel of the third pixel.

[0435] 29. The display device according to any one of claims 25 to 28,

[0436] wherein the first reference voltage line is disposed inside the first pixel, the second reference voltage line is disposed inside the second pixel, and the third reference voltage line is disposed inside the third pixel.

[0437] 30. The display device according to any one of claims 25 to 29,

[0438] wherein each of the first sub-pixel, the second sub-pixel, and the third sub-pixel includes:

[0439] A switching transistor, a driving transistor, a storage capacitor, a sensing transistor, and a light emitting diode, and the sensing transistor outputs a voltage for sensing a threshold voltage and a mobility of the driving transistor to a first reference voltage line, a second reference voltage line, and a third reference voltage line.

[0440] 31. A display apparatus comprising:

[0441] a display panel including a plurality of pixel units each including N pixels;

[0442] a data driver configured to supply data voltages to the N pixels via N data lines using sensing results of the N pixels via N reference voltage lines; and

[0443] a gate driver configured to supply gate signals to the N pixels via N gate lines,

[0444] wherein each of the N pixels includes N sub-pixels each having a different color;

[0445] wherein each of the N data lines is branched into N sub-data lines,

[0446] wherein each of the N sub-data lines is connected to sub-pixels having the same color,

[0447] wherein each of the N gate lines is connected to all of the N pixels and to sub-pixels having different colors (N is a natural number of 1 or more).

[0448] 32. A display apparatus comprising:

[0449] a display panel in which a plurality of pixels including first, second, and third sub-pixels each having a different color are disposed;

[0450] a data driver configured to supply data voltages to the N pixels via N data lines using sensing results of the N pixels via N reference voltage lines; and

[0451] a gate driver configured to supply gate signals to the N pixels via N gate lines,

[0452] wherein each of the plurality of data lines is branched into a plurality of sub-data lines,

[0453] wherein each of the plurality of sub-data lines is connected to a plurality of sub-pixels having the same color,

[0454] wherein each of the plurality of gate lines is connected to four sub-pixels arranged in a row in order.

[0455] 33. A display apparatus comprising:

[0456] a display panel in which a plurality of pixels of a first sub-pixel, a second sub-pixel, a third sub-pixel, and a fourth sub-pixel, which are sequentially arranged in a row and each have a different color, are provided;

[0457] a data driver configured to supply a data voltage to the plurality of pixels via a plurality of data lines using sensing results of the plurality of pixels obtained via a first reference voltage line, a second reference voltage line, and a third reference voltage line; and

[0458] a gate driver configured to supply a gate signal to the plurality of pixels via a plurality of gate lines,

[0459] wherein each of the plurality of data lines is branched into a plurality of sub-data lines,

[0460] wherein each of the plurality of sub-data lines is connected to a plurality of sub-pixels having the same color,

[0461] wherein the first sub-pixel of one of the plurality of pixels and the fourth sub-pixel of an adjacent pixel of the plurality of pixels are connected to the same gate line, and

[0462] wherein the second sub-pixel and the third sub-pixel of one of the plurality of pixels are connected to the same gate line.

[0463] Although exemplary embodiments of the disclosure have been described in detail with reference to the accompanying drawings, the disclosure is not limited thereto and can be implemented in various different forms without departing from the technical concept of the disclosure. Therefore, the exemplary embodiments of the disclosure are provided only for illustrative purposes and are not intended to limit the technical concept of the disclosure. The scope of the technical concept of the disclosure is not limited thereto. Therefore, it should be understood that the above-described exemplary embodiments are illustrative in all aspects and do not limit the disclosure. The scope of protection of the disclosure should be interpreted based on the following claims, and all technical concepts within the equivalent scope thereof should be interpreted as falling within the scope of the disclosure.

Claims

1. A display apparatus comprising: a display panel including a plurality of pixel units each including N pixels; a data driver configured to supply data voltages to the N pixels via N data lines using sensing results of the N pixels via N reference voltage lines; and a gate driver configured to supply gate signals to the N pixels via N gate lines, wherein each of the N pixels includes N sub-pixels each having a different color, wherein each of the N data lines is branched into N sub-data lines, wherein each of the N sub-data lines is connected to sub-pixels having the same color, wherein each of the N gate lines is connected to all of the N pixels and to sub-pixels having different colors, N being a natural number greater than 1. for one row, each of the pixel units includes three pixels, and each of the three pixels includes first, second, and third sub-pixels each having a different color; 2. The display device of claim 1, wherein, wherein the N reference voltage lines include first, second, and third reference voltage lines; and wherein each of the N reference voltage lines is connected to the first, second, and third sub-pixels in each pixel. 3.The display apparatus of claim 2, the pixel units include first, second, and third pixels, and each pixel includes the first, second, and third sub-pixels disposed in a row in order, wherein in each of the first, second, and third pixels, the first, second, and third sub-pixels are connected to different gate lines from each other, a plurality of first sub-pixels included in the first, second, and third pixels are connected to different gate lines from each other, a plurality of second sub-pixels included in the first, second, and third pixels are connected to different gate lines from each other, and a plurality of third sub-pixels included in the first, second, and third pixels are connected to different gate lines from each other. 4.The display apparatus of claim 3, the N gate lines include first, second, and third gate lines; and wherein wherein the first gate line is connected to any one of the sub-pixels of the first pixel, the first gate line is connected to a sub-pixel of the second pixel having a different color from the sub-pixel of the first pixel connected to the first gate line, and the first gate line is connected to a sub-pixel of the third pixel having a different color from the sub-pixel of the first pixel connected to the first gate line and the sub-pixel of the second pixel connected to the first gate line; and wherein the second gate line is connected to another one of the sub-pixels of the first pixel, ​ the second gate line is connected to sub-pixels of the second pixel that have different colors from the sub-pixels of the first pixel connected to the second gate line, and the second gate line is connected to sub-pixels of the third pixel that have different colors from the sub-pixels of the first pixel connected to the second gate line and the sub-pixels of the second pixel connected to the second gate line; and wherein the third gate line is connected to a further one of the sub-pixels of the first pixel, the third gate line is connected to sub-pixels of the second pixel that have different colors from the sub-pixels of the first pixel connected to the third gate line, and the third gate line is connected to sub-pixels of the third pixel that have different colors from the sub-pixels of the first pixel connected to the third gate line and the sub-pixels of the second pixel connected to the third gate line.

5. The display device of claim 2, wherein, For a row, each of the pixel units includes four pixels, and each of the four pixels includes a first sub-pixel, a second sub-pixel, a third sub-pixel, and a fourth sub-pixel, each sub-pixel having a different color; wherein the N reference voltage lines include a first reference voltage line, a second reference voltage line, a third reference voltage line, and a fourth reference voltage line; wherein each of the N reference voltage lines is connected to the first sub-pixel, the second sub-pixel, the third sub-pixel, and the fourth sub-pixel in each pixel.

6. The display device of claim 5, wherein the pixel units include a first pixel, a second pixel, a third pixel, and a fourth pixel, and each pixel includes the first sub-pixel, the second sub-pixel, the third sub-pixel, and the fourth sub-pixel arranged in order in a row, in each of the first pixel, the second pixel, the third pixel, and the fourth pixel, the first sub-pixel, the second sub-pixel, the third sub-pixel, and the fourth sub-pixel are connected to different gate lines from each other, a plurality of first sub-pixels included in the first pixel, the second pixel, the third pixel, and the fourth pixel are connected to different gate lines from each other, a plurality of second sub-pixels included in the first pixel, the second pixel, the third pixel, and the fourth pixel are connected to different gate lines from each other, a plurality of third sub-pixels included in the first pixel, the second pixel, the third pixel, and the fourth pixel are connected to different gate lines from each other, and a plurality of fourth sub-pixels included in the first pixel, the second pixel, the third pixel, and the fourth pixel are connected to different gate lines from each other.

7. The display device of claim 6, wherein the N gate lines include a first gate line, a second gate line, a third gate line, and a fourth gate line; and wherein the first gate line is connected to one of the sub-pixels of the first pixel, a sub-pixel of the second pixel having a different color than the one of the sub-pixels of the first pixel connected to the first gate line, a sub-pixel of the third pixel having a different color than the one of the sub-pixels of the first pixel connected to the first gate line and the sub-pixel of the second pixel connected to the first gate line, and a sub-pixel of the fourth pixel having a different color than the one of the sub-pixels of the first pixel connected to the first gate line, the sub-pixel of the second pixel connected to the first gate line, and the sub-pixel of the third pixel connected to the first gate line; and wherein the second gate line is connected to another one of the sub-pixels of the first pixel, a sub-pixel of the second pixel having a different color than the another one of the sub-pixels of the first pixel connected to the second gate line, a sub-pixel of the third pixel having a different color than the another one of the sub-pixels of the first pixel connected to the second gate line and the sub-pixel of the second pixel connected to the second gate line, and a sub-pixel of the fourth pixel having a different color than the another one of the sub-pixels of the first pixel connected to the second gate line, the sub-pixel of the second pixel connected to the second gate line, and the sub-pixel of the third pixel connected to the second gate line; and wherein the third gate line is connected to yet another one of the sub-pixels of the first pixel, a sub-pixel of the second pixel having a different color than the yet another one of the sub-pixels of the first pixel connected to the third gate line, a sub-pixel of the third pixel having a different color than the yet another one of the sub-pixels of the first pixel connected to the third gate line and the sub-pixel of the second pixel connected to the third gate line, and a sub-pixel of the fourth pixel having a different color than the yet another one of the sub-pixels of the first pixel connected to the third gate line, the sub-pixel of the second pixel connected to the third gate line, and the sub-pixel of the third pixel connected to the third gate line; and wherein the fourth gate line is connected to a remaining one of the sub-pixels of the first pixel, a sub-pixel of the second pixel having a different color than the remaining one of the sub-pixels of the first pixel connected to the fourth gate line, a sub-pixel of the third pixel having a different color than the remaining one of the sub-pixels of the first pixel connected to the fourth gate line and the sub-pixel of the second pixel connected to the fourth gate line, and a sub-pixel of the fourth pixel having a different color than the remaining one of the sub-pixels of the first pixel connected to the fourth gate line, the sub-pixel of the second pixel connected to the fourth gate line, and the sub-pixel of the third pixel connected to the fourth gate line.

8. The display device of any of claims 1-7, wherein each of the sub-pixels comprises: a switching transistor, a driving transistor, a storage capacitor, a sensing transistor, and a light emitting diode, and the sensing transistor outputs a voltage for sensing a threshold voltage and mobility of the driving transistor to the N reference voltage lines.

9. A sensing method of the display apparatus of claim 4, wherein, in a first scan period, a gate high voltage is applied to the first gate line, in a second scan period, a gate high voltage is applied to the second gate line, and in a third scan period, a gate high voltage is applied to the third gate line.

10. The sensing method of claim 9, wherein, in the first scan period, any one of the sub-pixels of the first pixel connected to the first gate line is sensed by the first reference voltage line, a sub-pixel of the second pixel having a different color from the sub-pixel of the first pixel connected to the first gate line is sensed by the second reference voltage line, and a sub-pixel of the third pixel having a different color from the sub-pixel of the first pixel connected to the first gate line and the sub-pixel of the second pixel connected to the first gate line is sensed by the third reference voltage line; wherein, in the second scan period, another one of the sub-pixels of the first pixel connected to the second gate line is sensed by the first reference voltage line, a sub-pixel of the second pixel having a different color from the sub-pixel of the first pixel connected to the second gate line is sensed by the second reference voltage line, and a sub-pixel of the third pixel having a different color from the sub-pixel of the first pixel connected to the second gate line and the sub-pixel of the second pixel connected to the second gate line is sensed by the third reference voltage line; wherein, in the third scan period, yet another one of the sub-pixels of the first pixel connected to the third gate line is sensed by the first reference voltage line, a sub-pixel of the second pixel having a different color from the sub-pixel of the first pixel connected to the third gate line is sensed by the second reference voltage line, and a sub-pixel of the third pixel having a different color from the sub-pixel of the first pixel connected to the third gate line and the sub-pixel of the second pixel connected to the third gate line is sensed by the third reference voltage line.

11. The sensing method of claim 9 or 10, wherein each of the sub-pixels includes: a switching transistor, a driving transistor, a storage capacitor, a sensing transistor, and a light emitting diode, and the sensing transistor outputs a voltage for sensing a threshold voltage and mobility of the driving transistor to the N reference voltage lines.

12. A sensing method of the display apparatus of claim 7, wherein in a first scan period, a gate high voltage is applied to the first gate line, in a second scan period, a gate high voltage is applied to the second gate line, in a third scan period, a gate high voltage is applied to the third gate line, and in a fourth scan period, a gate high voltage is applied to the fourth gate line.

13. The sensing method of claim 12, wherein, in the first scan period, any one of the sub-pixels of the first pixel connected to the first gate line is sensed by the first reference voltage line, a sub-pixel of the second pixel having a different color from the sub-pixel of the first pixel connected to the first gate line is sensed by the second reference voltage line, a sub-pixel of the third pixel having a different color from the sub-pixel of the first pixel connected to the first gate line and the sub-pixel of the second pixel connected to the first gate line is sensed by the third reference voltage line, and a sub-pixel of the fourth pixel having a different color from the sub-pixel of the first pixel connected to the first gate line, the sub-pixel of the second pixel connected to the first gate line, and the sub-pixel of the third pixel connected to the first gate line is sensed by the fourth reference voltage line; wherein, in the second scan period, another one of the sub-pixels of the first pixel connected to the second gate line is sensed by the first reference voltage line, a sub-pixel of the second pixel having a different color from the sub-pixel of the first pixel connected to the second gate line is sensed by the second reference voltage line, a sub-pixel of the third pixel having a different color from the sub-pixel of the first pixel connected to the second gate line and the sub-pixel of the second pixel connected to the second gate line is sensed by the third reference voltage line, and a sub-pixel of the fourth pixel having a different color from the sub-pixel of the first pixel connected to the second gate line, the sub-pixel of the second pixel connected to the second gate line, and the sub-pixel of the third pixel connected to the second gate line is sensed by the fourth reference voltage line; wherein, in the third scan period, yet another one of the sub-pixels of the first pixel connected to the third gate line is sensed by the first reference voltage line, a sub-pixel of the second pixel having a different color from the sub-pixel of the first pixel connected to the third gate line is sensed by the second reference voltage line, a sub-pixel of the third pixel having a different color from the sub-pixel of the first pixel connected to the third gate line and the sub-pixel of the second pixel connected to the third gate line is sensed by the third reference voltage line, and a sub-pixel of the fourth pixel having a different color from the sub-pixel of the first pixel connected to the third gate line, the sub-pixel of the second pixel connected to the third gate line, and the sub-pixel of the third pixel connected to the third gate line is sensed by the fourth reference voltage line; wherein, in the fourth scan period, the remaining one of the sub-pixels of the first pixel connected to the fourth gate line is sensed by the first reference voltage line, sensing, by the second reference voltage line, sub-pixels of the second pixel that have different colors from sub-pixels of the first pixel connected to the fourth gate line, sensing, by the third reference voltage line, sub-pixels of the third pixel that have different colors from sub-pixels of the first pixel connected to the fourth gate line and sub-pixels of the second pixel connected to the fourth gate line, and sensing, by the fourth reference voltage line, sub-pixels of the fourth pixel that have different colors from sub-pixels of the first pixel connected to the fourth gate line, sub-pixels of the second pixel connected to the fourth gate line, and sub-pixels of the third pixel connected to the fourth gate line.

14. The sensing method of claim 12 or 13, wherein each of the sub-pixels includes: a switching transistor, a driving transistor, a storage capacitor, a sensing transistor, and a light emitting diode, and the sensing transistor outputs a voltage for sensing a threshold voltage and mobility of the driving transistor to the N reference voltage lines.

15. A display apparatus comprising: a display panel in which each pixel unit of a plurality of pixel units includes N-1 pixels; a data driver configured to supply data voltages to the N-1 pixels via N data lines using sensing results of the N-1 pixels via N-1 reference voltage lines; and a gate driver configured to supply gate signals to the N-1 pixels via N-1 gate lines, wherein each of the N-1 pixels includes N sub-pixels each having a different color; wherein each of the N data lines is branched into N-1 sub-data lines, wherein each of the N-1 sub-data lines is connected to sub-pixels having the same color in a pixel unit, wherein the pixel unit includes a first pixel, a second pixel, and a third pixel, and each pixel includes a first sub-pixel, a second sub-pixel, a third sub-pixel, and a fourth sub-pixel arranged in order in a row, wherein the first sub-pixel and the second sub-pixel of one pixel of the pixel unit arranged in order in a row and the third sub-pixel and the fourth sub-pixel of an adjacent pixel of the pixel unit are connected to the same gate line.

16. The display apparatus of claim 15, wherein, a first sub-pixel of one pixel of the plurality of pixels and a fourth sub-pixel of an adjacent pixel of the plurality of pixels are connected to the same gate line, and wherein a second sub-pixel and a third sub-pixel of one pixel of the plurality of pixels are connected to the same gate line.

17. The display apparatus of any one of claims 15-16, wherein, each of the sub-pixels includes: a switching transistor, a driving transistor, a storage capacitor, a sensing transistor, and a light emitting diode, and the sensing transistor outputs a voltage for sensing a threshold voltage and mobility of the driving transistor to the N-1 reference voltage lines.

Images