A mixed carrier device for suppressing turn-off noise

Abstract

The present invention discloses a mixed carrier device for suppressing turn-off noise, comprising a working area, an NMOS region (303), a PMOS region (304), a thyristor region (302), and a capacitor region. The NMOS region (303) surrounds the PMOS region (304), the PMOS region (304) surrounds the thyristor region (302), the NMOS region (303) and the thyristor region (302) are both hexagonally distributed, and the gate of the NMOS region (303) and the gate of the thyristor region (302) are connected to form a capacitor region. The present invention solves the problem of noise current generated by existing thyristors during turn-off.

Description

Technical Field

[0001] The present invention relates to the technical field of power semiconductors, and in particular to a mixed carrier device capable of suppressing turn-off noise. Background Art

[0002] An MCT, a type of Bi-MOS device, combines the high input impedance, low drive power, and fast switching of a MOSFET with the high voltage, high current, and low on-state voltage drop of a thyristor. An MCT is comprised of tens of thousands of MCT elements, each consisting of a PNPN thyristor, a MOSFET that controls the thyristor's turn-on, and a MOSFET that controls the thyristor's turn-off. MCTs offer high voltage, high current, high current density, and low on-state voltage drop. Their on-state voltage drop is only about one-third that of a GTR, and their continuous current density per unit area of ​​silicon is the highest among all devices. Furthermore, MCTs can withstand extremely high di / dt and du / dt, simplifying their protection circuitry. They also offer faster switching times than GTRs and minimize switching losses.

[0003] However, during the shutdown process of the current MCT, due to the rapid change of the collector current in a short period of time, the device generates noise current during the shutdown process. This noise current not only causes serious noise interference during shutdown, but also causes permanent damage to the device. Summary of the Invention

[0004] In view of the above-mentioned deficiencies in the prior art, the present invention provides a mixed carrier device for suppressing turn-off noise, which solves the problem of noise current generated during the turn-off process of the conventional MCT.

[0005] In order to achieve the above-mentioned object of the invention, the technical solution adopted by the present invention is: a mixed carrier device for suppressing turn-off noise, the device including a working area, an NMOS region, a PMOS region, a thyristor region and a capacitor region, the NMOS region surrounds the PMOS region, the PMOS region surrounds the thyristor region, the NMOS region and the thyristor region are both distributed in a hexagonal shape, and the gate of the NMOS region and the gate of the thyristor region are connected to form a capacitor region.

[0006] The beneficial effects of the above scheme are: due to the presence of the thyristor and the depletion-mode PMOS, the on-state voltage drop is small, thereby improving the turn-off speed and reducing the turn-off loss; at the same time, the first capacitor area is used to effectively reduce the instantaneous voltage generated during turn-off, thereby achieving the purpose of reducing the noise current generated during turn-off, and solving the problem of noise current generated during the turn-off process of the existing MCT.

[0007] Furthermore, the NMOS region includes a first electrode heavily doped region, a second electrode base region, a sixth doped region, a third doped region, a fourth doped region, a fifth doped region, a first insulating region and a first control gate, wherein the first control gate is located inside the first insulating region and is distributed in a hexagonal shape, the first electrode heavily doped region surrounds the first insulating region and is distributed in a hexagonal shape, the sixth doped region is located below the second electrode base region, the third doped region is located below the sixth doped region, the fourth doped region is located below the third doped region, the fifth doped region is located below the fourth doped region, and the fifth doped region includes the first electrode.

[0008] The beneficial effect of the above further solution is that when a positive voltage is applied to the first control gate, the heavily doped region of the fourth electrode will inject electrons downward, thereby turning on the device quickly. Moreover, the hexagonal shape of the NMOS region increases the area of ​​the NMOS region, thereby further improving the turn-on speed.

[0009] Further, the PMOS region includes a third electrode base region, a seventh doping region, an eighth doping region, a third doping region, a fourth doping region and a fifth doping region, the seventh doping region is placed below the third electrode base region, the eighth doping region is placed below the seventh doping region, the third doping region is placed below the eighth doping region, the fourth doping region is placed below the third doping region, the fifth doping region is placed below the fourth doping region, and the fifth doping region includes a first electrode.

[0010] The beneficial effect of the above further solution is that when the switch is turned off, the excess carriers can enter the PMOS channel faster, so that the excess carriers flow away faster, thereby improving the turn-off speed and reducing the turn-off loss.

[0011] Furthermore, the thyristor region includes a first control gate, a second electrode heavily doped region, a second insulating region, a first electrode base region, a first doped region, a second doped region, a third doped region, a fourth doped region and a fifth doped region, the second insulating region surrounds the second electrode heavily doped region, the second electrode heavily doped region is distributed in a hexagonal shape, the first control gate is placed inside the second insulating region, the first doped region is placed below the first electrode base region, the second doped region is placed below the first doped region, the third doped region is placed below the second doped region, the fourth doped region is placed below the third doped region, the fifth doped region is placed below the fourth doped region, and the fifth doped region includes the first electrode.

[0012] The beneficial effect of the above further solution is that by providing a thyristor region, the thyristor region is surrounded by the PMOS region to enable rapid flow of residual carriers during the turn-off period.

[0013] Furthermore, the capacitor region is a first capacitor region, the first capacitor region includes a second insulating region and a first control gate, the first control gate is placed inside the second insulating region, and the first capacitor region passes through the PMOS region and is evenly distributed inside the PMOS region.

[0014] The beneficial effect of the above further scheme is that when the device is turned off, the collector current changes sharply, and the instantaneous electromotive force generated affects the turn-off current of the device when it is turned off, and the first capacitor area suppresses the charge change of the emitter by releasing the charge, so that the current will not oscillate during the turn-off process, and the noise current at the time of turn-off is suppressed by suppressing the instantaneous electromotive force at the time of turn-off.

[0015] Furthermore, the capacitor region is a second capacitor region, which includes a gate section extending from the NMOS gate, the gate section extending from the NMOS gate is connected to the NMOS region and wrapped by an oxide layer, and there is a gate section extending from the NMOS gate on each of the six sides of the NMOS region.

[0016] The beneficial effect of the above further scheme is: the above technical scheme provides a second implementation scheme of the capacitor structure, and a gate section extending from the NMOS gate is set on each side of the hexagonal NMOS gate area. The capacitor thus formed can release a large amount of charge stored in the capacitor area when the device is turned off, thereby achieving the purpose of suppressing charge changes.

[0017] Furthermore, the capacitor region is a third capacitor region, and the third capacitor region includes a first electrode region and a third insulating region. The third insulating region wraps the first electrode region in a hexagonal distribution and extends into the PMOS region.

[0018] The beneficial effect of the above further solution is that: the above technical solution provides a third implementation solution of the capacitor structure, and by setting the capacitor, the charge stored therein can be released to prevent the charge from changing. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 A partial dense map of the cells of a mixed-carrier device that suppresses turn-off noise.

[0020] Wherein: 001, the first single cell of the device; 002, the second single cell of the device; 003, the dense tiling of the device cells; 010, the device along AA; dotted line cross-section; 020, the device along BB; dotted line cross-section; 030, the device along CC; dotted line cross-section; 100, the first electrode; 101, the fifth doping region; 102, the fourth doping region; 103, the third doping region; 104, the eighth doping region; 105, the second doping region; 106, the first doping region; 107, the first electrode base region; 108, the sixth doping region; 109, the second electrode base region ; 120, the third electrode base region; 121, the seventh doped region; 201, the first electrode heavily doped region; 202, the first insulating region; 203, the first control gate; 204, the second electrode heavily doped region; 207, the second insulating region; 301, the first capacitor region; 302, the thyristor region; 303, the NMOS region; 304, the PMOS region; 401, a gate extending from the NMOS gate; 501, the second capacitor region; 601, the third capacitor region; 610, the first electrode region; 611, the third insulating region.

[0021] Figure 2 A single cell diagram of the device.

[0022] Figure 3 A cross-sectional view of the device cell.

[0023] Figure 4 This is a dense tiling of device cells for the second implementation method.

[0024] Figure 5 This is a single cell diagram of the device for the second implementation method.

[0025] Figure 6 This is a cross-sectional view of the device cell for the second implementation method.

[0026] Figure 7 This is a dense tiling of device cells for the third implementation method.

[0027] Figure 8 This is a single cell diagram of the device for the third implementation method.

[0028] Figure 9 This is a cross-sectional view of the device cell for the third implementation method. DETAILED DESCRIPTION

[0029] The present invention will be further described below with reference to the accompanying drawings and specific embodiments.

[0030] like Figure 1As shown, a mixed carrier device for suppressing turn-off noise includes a working area, an NMOS region 303, a PMOS region 304, a thyristor region 302, and a capacitor region. The NMOS region 303 surrounds the PMOS region 304, and the PMOS region 304 surrounds the thyristor region 302. The NMOS region 303 and the thyristor region 302 are both hexagonally distributed. The gate of the NMOS region 303 and the gate of the thyristor region 302 are connected to form a capacitor region. The gate includes an NMOS control gate and a thyristor control gate.

[0031] like Figure 2 and Figure 3 As shown, the NMOS region 303 includes a first electrode heavily doped region 201, a second electrode base region 109, a sixth doped region 108, a third doped region 103, a fourth doped region 102, a fifth doped region 101, a first insulating region 202 and a first control gate 203, wherein the first control gate 203 is placed inside the first insulating region 202 and is distributed in a hexagonal shape, the first electrode heavily doped region 201 surrounds the first insulating region 202 and is distributed in a hexagonal shape, the sixth doped region 108 is placed below the second electrode base region 109, the third doped region 103 is placed below the sixth doped region 108, the fourth doped region 102 is placed below the third doped region 103, the fifth doped region 101 is placed below the fourth doped region 102, and the fifth doped region 101 includes the first electrode 100.

[0032] like Figure 3 As shown, the PMOS region 304 includes a third electrode base region 120, a seventh doping region 121, an eighth doping region 104, a third doping region 103, a fourth doping region 102 and a fifth doping region 101, wherein the seventh doping region 121 is placed below the third electrode base region 120, the eighth doping region 104 is placed below the seventh doping region 121, the third doping region 103 is placed below the eighth doping region 104, the fourth doping region 102 is placed below the third doping region 103, the fifth doping region 101 is placed below the fourth doping region 102, and the fifth doping region 101 includes a first electrode 100.

[0033] like Figure 3As shown, the thyristor region 302 includes a first control gate 203, a second electrode heavily doped region 204, a second insulating region 207, a first electrode base region 107, a first doped region 106, a second doped region 105, a third doped region 103, a fourth doped region 102 and a fifth doped region 101, the second insulating region 207 surrounds the second electrode heavily doped region 204, the second electrode heavily doped region 204 is distributed in a hexagonal shape, the first control gate 203 is placed inside the second insulating region 207, the first doped region 106 is placed below the first electrode base region 107, the second doped region 105 is placed below the first doped region 106, the third doped region 103 is placed below the second doped region 105, the fourth doped region 102 is placed below the third doped region 103, the fifth doped region 101 is placed below the fourth doped region 102, and the fifth doped region 101 includes the first electrode 100.

[0034] like Figure 3 As shown, the capacitor region is a first capacitor region 301, which includes a second insulating region 207 and a first control gate 203, wherein the first control gate 203 is placed inside the second insulating region 207, and the first capacitor region 301 passes through the PMOS region 304 and is evenly distributed inside the PMOS region 304.

[0035] In one embodiment of the present invention, the presence of the PMOS region allows excess carriers to quickly flow away from the device during shutdown, thereby reducing switching losses. During the shutdown period, the collector current fluctuates dramatically, and the di / dt flowing through the parasitic capacitance / inductance / resistance within the device generates a transient electromotive force. This transient electromotive force affects the device's turn-off current during shutdown. A capacitor positioned between the gate and emitter releases stored charge to suppress the charge change at the emitter, preventing current oscillation during the shutdown process. This suppresses the transient electromotive force generated during shutdown and, consequently, noise current during the shutdown period. Multiple capacitor regions within the PMOS region connect the thyristor gate and the NMOS gate, further suppressing the generation of noise current during the shutdown process. Furthermore, the cell shape, internal gate region, emitter region, and insulation region are all hexagonally distributed, which increases cell density. The capacitor regions within the PMOS region are evenly distributed within the PMOS region, further ensuring more uniform current distribution and preventing excessive current density on one side that could damage the device. In addition, the depth of the capacitor region connecting the thyristor gate and the NMOS gate, which is configured in the PMOS region, is consistent with the trench depth of the thyristor gate and the NMOS gate, so it can be formed simultaneously with the thyristor gate and the NMOS gate in the process, with minimal modification steps in the traditional process.

[0036] The capacitor region is a second capacitor region 501, which includes a gate segment 401 extending from the NMOS gate. The gate segment 401 extending from the NMOS gate is connected to the NMOS region 303 and is wrapped by an oxide layer. There is a gate segment 401 extending from the NMOS gate on each of the six sides of the NMOS region 303.

[0037] In one embodiment of the present invention, Figure 4 、 Figure 5 、 Figure 6 As shown, a second implementation of a capacitor structure is provided, wherein the second capacitor region 501 is a capacitor region configured between the gate and the emitter, configured as a gate section 401 extending from the NMOS gate, which is connected to the NMOS gate and wrapped by an oxide layer. Each side of the hexagonal NMOS gate region has a gate section 401 extending from the NMOS gate, and is configured as a capacitor connected between the gate and the emitter. The capacitor can also significantly release the charge stored in the capacitor region during the shutdown period, thereby suppressing the charge change during the shutdown period, thereby suppressing the potential between the gate and the emitter, and thus suppressing the generation of noise current during the shutdown period.

[0038] The capacitor region is a third capacitor region 601 . The third capacitor region 601 includes a first electrode region 610 and a third insulating region 611 . The third insulating region 611 wraps the first electrode region 610 in a hexagonal distribution and extends into the PMOS region 304 .

[0039] In one embodiment of the present invention, Figure 7 、 Figure 8 、 Figure 9 As shown, a third implementation of a capacitor structure is provided, wherein the third capacitor region 601 is configured as a capacitor region for suppressing shutdown noise, which is composed of a first electrode region 610 and a third insulating region 611. The third insulating region 611 wraps the first electrode region 610 to be configured as a capacitor for suppressing shutdown noise, and is symmetrically distributed in a hexagonal shape. The third capacitor region 601 is distributed in a hexagonal shape and extends into the PMOS region 304. When a shutdown operation is performed, the instantaneous change in potential generates an induced electromotive force, thereby generating a noise current. The capacitor releases the charge stored therein to prevent the charge change during the shutdown period, thereby suppressing the generation of noise current during shutdown.

[0040] The present invention utilizes a thyristor and depletion-mode PMOS transistor to minimize the on-state voltage drop during turn-on. This allows for rapid removal of excess carriers within the device during turn-off, improving turn-off speed and reducing turn-off losses. Furthermore, within the depletion-mode PMOS region, the NMOS gate is connected to the thyristor gate, configured as a capacitor connected between the gate and emitter to effectively reduce the transient voltage generated during turn-off, thereby reducing noise current generated during turn-off.

[0041] Those skilled in the art will appreciate that the embodiments described herein are intended to help readers understand the principles of the present invention, and it should be understood that the scope of protection of the present invention is not limited to such specific descriptions and embodiments. Those skilled in the art can make various other specific variations and combinations based on the technical teachings disclosed in the present invention without departing from the essence of the present invention, and such variations and combinations are still within the scope of protection of the invention.

Claims

1. A mixed carrier device for suppressing turn-off noise, characterized in that: The device comprises a working area, an NMOS region (303), a PMOS region (304), a thyristor region (302), and a capacitor region; the NMOS region (303) surrounds the PMOS region (304), the PMOS region (304) surrounds the thyristor region (302), the NMOS region (303) and the thyristor region (302) are both distributed in a hexagonal shape, and the gate of the NMOS region (303) and the gate of the thyristor region (302) are connected to form a capacitor region; The PMOS region (304) comprises a third electrode base region (120), a seventh doping region (121), an eighth doping region (104), a third doping region (103), a fourth doping region (102) and a fifth doping region (101); the seventh doping region (121) is disposed below the third electrode base region (120); the eighth doping region (104) is disposed below the seventh doping region (121); the third doping region (103) is disposed below the eighth doping region (104); the fourth doping region (102) is disposed below the third doping region (103); the fifth doping region (101) is disposed below the fourth doping region (102); and the fifth doping region (101) comprises a first electrode (100) therein; The thyristor region (302) includes a first control gate (203), a second electrode heavily doped region (204), a second insulating region (207), a first electrode base region (107), a first doped region (106), a second doped region (105), a third doped region (103), a fourth doped region (102) and a fifth doped region (101), wherein the second insulating region (207) surrounds the second electrode heavily doped region (204), and the second electrode heavily doped region (204) is distributed in a hexagonal shape, the first control gate (203) is placed inside the second insulating region (207), the first doped region (106) is placed below the first electrode base region (107), the second doped region (105) is placed below the first doped region (106), and the third doped region (103) is placed below the second doped region (105).

2. The mixed carrier device for suppressing turn-off noise according to claim 1, characterized in that: The NMOS region (303) comprises a first electrode heavily doped region (201), a second electrode base region (109), a sixth doped region (108), a third doped region (103), a fourth doped region (102), a fifth doped region (101), a first insulating region (202) and a first control gate (203), wherein the first control gate (203) is disposed inside the first insulating region (202) and is distributed in a hexagonal shape, the first electrode heavily doped region (201) surrounds the first insulating region (202) and is distributed in a hexagonal shape, the sixth doped region (108) is disposed below the second electrode base region (109), and the third doped region (103) is disposed below the sixth doped region (108).

3. The mixed carrier device for suppressing turn-off noise according to claim 1, characterized in that: The capacitor region is a first capacitor region (301), the first capacitor region (301) comprises a second insulating region (207) and a first control gate (203), the first control gate (203) is placed inside the second insulating region (207), and the first capacitor region (301) passes through the PMOS region (304) and is evenly distributed inside the PMOS region (304).

4. The mixed carrier device for suppressing turn-off noise according to claim 1, characterized in that: The capacitor region is a second capacitor region (501), and the second capacitor region (501) includes a gate segment (401) extending from an NMOS gate. The gate segment (401) extending from the NMOS gate is connected to the NMOS region (303) and is wrapped by an oxide layer. Each of the six sides of the NMOS region (303) has a gate segment (401) extending from the NMOS gate.

5. The mixed carrier device for suppressing turn-off noise according to claim 1, characterized in that: The capacitor region is a third capacitor region (601), and the third capacitor region (601) comprises a first electrode region (610) and a third insulating region (611). The third insulating region (611) wraps the first electrode region (610) in a hexagonal distribution and extends into the PMOS region (304).

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