High-speed, high-capacity, aggregated queuing switch system

Abstract

The application provides a high-speed and large-capacity aggregated cross-node output joint queuing switch system, which is composed of an input processing module, a large-capacity crossbar processing unit and an output queue management. The input processing module adopts a pipeline structure, can ensure that data can be transmitted every clock, can aggregate more ports, and can reduce the cache occupation of the large-capacity crossbar processing unit and the number of output queues. The cross nodes in the large-capacity crossbar processing unit adopt a FIFO form, which can improve the cache utilization rate; the number threshold is set when the cross nodes are arbitrated, which can reduce the cache while providing better Qos for high priority. In addition, the large-capacity crossbar processing unit and the output queue management are isolated by the cache, so that the large-capacity crossbar processing unit and the output queue management have higher processing efficiency, and the output queue management can greatly reduce the number of queues.

Description

Technical Field

[0001] This invention belongs to the field of packet switching architecture technology, specifically relating to a high-speed, high-capacity aggregated cross-connect node output joint queuing switching system. Background Technology

[0002] Current switching structures can be categorized according to queuing strategies into Input Queued (IQ), Output Queued (OQ), Combined Input and Output Queued (CIOQ), and Combined Input and Crosspoint Queued (CICQ).

[0003] Input queuing (IQ) involves setting up buffers at the input ports before the Crossbar switching network. Input data packets are first stored in the buffers, and then dequeued using a specific queue scheduling algorithm before being transmitted through the Crossbar structure to the output ports. Since the output rate of each output channel connected to the Crossbar switching network is limited, and there are no queuing buffers at the output ports or Crossbar nodes, data packets can only be dequeued when the output ports are idle. Therefore, for a single channel in the Crossbar network, the channel transmission rate only needs to be the same as the output port's output rate. In this case, the speedup ratio (the ratio of the internal rate of the switching structure to the port rate) is 1, and there are no high requirements for the internal rate of the switching structure and the buffer write / read rate, resulting in good scalability. Input queuing structures with only a single First-In-First-Out (FIFO) queue in the input buffer can suffer from Head of Line (HOL) blocking. This can severely reduce switching capacity when the number of ports is large; for example, in the Bernoulli service where all output ports are evenly distributed, this structure only achieves 58.6% throughput. To address this issue, Virtual Output Queues (VOQ) technology can be used to set up queues at the input buffer according to output ports, distinguishing data packets destined for different destinations. However, because multiple queues need to be differentiated, similar to a shared buffer structure, a certain amount of buffer space must be allocated to each queue to ensure fairness. If the number of ports increases, leading to a greater number of queues, the buffer resource requirements at each input port will also increase.

[0004] The output queuing structure (OQ) sets up a queuing buffer at the output port. The input data packets are first switched through the Crossbar switching network to the corresponding output port and then enter the buffer for queuing. Since no queuing buffer is set at the input and inside the Crossbar network, when all N input ports simultaneously input packets destined for the same output port, to ensure no packet loss at this time, the receiving bandwidth at the output queuing needs to reach at least N times the line speed of the input port (the input port speeds are the same), that is, the acceleration ratio needs to reach N. It can be seen that essentially this structure is still shared cache, except that the single-channel shared cache is split into multiple channels and distributed shared cache switching, so it naturally inherits the disadvantages of shared cache.

[0005] The combined input-output queuing structure (CIOQ) is a compromise between input queuing and output queuing. Caches are set at both the input port and the output port, and the Crossbar switching network is set to have a certain acceleration ratio s. The setting of the input port cache can solve the problem of the N-fold acceleration ratio of the output queuing structure, making 1 < s < N; while the high acceleration ratio of the switching network can aggregate multiple input ports and solve the problem of the large demand for cache resources by the VOQ mechanism of the input queuing structure. It is found that for the combined input-output queuing structure, a throughput rate of 100% can be achieved when the acceleration ratio is 2. However, the scheduling algorithm on this structure needs to handle the queues of both input and output queuing simultaneously, with high complexity and being not conducive to FPGA implementation.

[0006] The combined input cross-node queuing structure (CICQ) is a combination of input queuing (IQ) and cross-node queued with cache (CQ). The main difference from input queuing is that a certain number of caches for queuing are set at the cross nodes. This method effectively isolates the input end and the output end. Especially in the further developed combined input cross-node output queuing structure, the cache at the cross node isolates the queue scheduling of the input and output, enabling different scheduling algorithms to be used for the input and output respectively, reducing the complexity of a single algorithm, and the distributed structure is also very suitable for joint implementation using multiple FPGA chips. As the number of ports increases, the dependence on cache resources under this structure also becomes higher and higher. The caches at the input queuing and cross nodes both have an O(N 2 ) relationship with the port number N.

[0007] Through the above analysis, the problems and defects existing in the prior art are as follows:

[0008] (1) Existing switching architecture technologies that are easy to implement on FPGA, such as input queuing structure (IQ), input cross node joint queuing structure (CICQ) and output queuing structure (OQ), all have an increasing dependence on cache resources as the number of ports, port speed and port bit width increase.

[0009] (2) The input-output joint queuing structure (CIOQ) can solve the problem of high cache resource requirements of the input queuing structure VOQ mechanism, but the scheduling algorithm on this structure has to process the input and output queues at the same time, which is highly complex and not conducive to FPGA implementation.

[0010] (3) Existing switching architecture technologies that are easy to implement on FPGA, such as output queuing (OQ), require that the receiving bandwidth at the output queuing point be at least N times the line speed of the input port in order to ensure that no packet loss occurs when all N input ports simultaneously input packets destined for the same output port. In other words, the speedup ratio needs to reach N.

[0011] (4) Existing switching architecture technologies that are easy to implement with FPGA are only suitable for low speed, small bit width and small switching capacity, and are not very practical for high speed and large capacity switching. Summary of the Invention

[0012] To address the aforementioned problems in the existing technology, this invention provides a high-speed, high-capacity aggregated cross-connect node output joint queuing switching system. The technical problem to be solved by this invention is achieved through the following technical solution:

[0013] This invention provides a high-speed, high-capacity aggregated cross-connect node output joint queuing switching system, comprising: an input processing module, a high-capacity switching processing unit, and an output processing module;

[0014] The input module is used to aggregate and poll all input Ethernet frame data, and search and learn frame information that matches the Ethernet frame data, thereby writing the Ethernet frame data into the corresponding cross node in the high-capacity switching processing unit.

[0015] The high-capacity switching processing unit is used to arbitrate and schedule the written Ethernet frame data according to priority in order to generate enqueue requests.

[0016] The output processing module is used to determine whether to enqueue or discard the scheduled Ethernet frame data based on the enqueue request, and to dequeue when its own queue has Ethernet frame data.

[0017] This invention provides a high-speed, high-capacity aggregated cross-node output joint queuing switching system, consisting of input processing, cross-nodes in the high-capacity switching unit (Crossbar), and output queue management. The input processing module employs a pipelined architecture, ensuring data transmission every clock cycle, aggregating more ports, and reducing the Crossbar buffer footprint and the number of output queues. The cross-nodes in the high-capacity switching unit use a FIFO (Fixed-For-Flight) configuration, improving buffer utilization. Setting a threshold for cross-node arbitration reduces buffer usage while providing better QoS for high-priority nodes. Furthermore, this invention uses buffer isolation between the high-capacity switching unit and output queue management, resulting in higher processing efficiency. The use of output queue management significantly reduces the number of queues.

[0018] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0019] Figure 1 This is a structural diagram of the high-speed, high-capacity aggregated cross-connect node output joint queuing switching system provided in an embodiment of the present invention;

[0020] Figure 2 This is a flowchart of multi-path group aggregation and polling provided in an embodiment of the present invention;

[0021] Figure 3 This is a diagram of the 4-stage pipeline structure of the learning lookup table module in the input processing provided in this embodiment of the invention;

[0022] Figure 4 This is a flowchart of the 4-level pipeline for the learning lookup table module in input processing provided in this embodiment of the invention;

[0023] Figure 5 This is a diagram of the three-stage pipeline structure of the frame shifting module in the input processing provided in this embodiment of the invention;

[0024] Figure 6 This is a flowchart of the three-stage pipeline of the frame shifting module in the input processing provided in this embodiment of the invention;

[0025] Figure 7 This is a structural diagram of the cross node in the high-capacity switching processing unit Crossbar provided in this embodiment of the invention;

[0026] Figure 8 This is an outstanding flowchart of the management of cross nodes and output queues in the high-capacity switching processing unit Crossbar provided in this embodiment of the invention. Detailed Implementation

[0027] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0028] like Figure 1 As shown, the present invention provides a high-speed, high-capacity aggregated cross-connect node output joint queuing switching system, comprising: an input processing module, a high-capacity switching processing unit, and an output processing module;

[0029] The input module is used to aggregate and poll all input Ethernet frame data, and search and learn frame information that matches the Ethernet frame data, thereby writing the Ethernet frame data into the corresponding cross node in the high-capacity switching processing unit.

[0030] It's worth noting that aggregation refers to combining multiple ports into a single bus, which can reduce the buffer resources occupied by high-capacity switching processing units (Crossbar nodes) and improve bus utilization. Aggregated ports use the LocalLink format. When a port has packets, it will raise the send_data_flag signal in advance, indicating that the port has packets that need to enter input processing. When the output bus is idle, only one send_data_flag signal is high; in this case, the output bus occupancy is allocated to that port's packets. When the output bus is busy, the bus occupancy remains unchanged. When the bus is idle, multiple send_data_flag signals are high; the LocalLink ready signal is raised to indicate which port the output bus is assigned to. For fairness, a round-robin (RR) polling method is used.

[0031] The high-capacity switching processing unit is used to arbitrate and schedule the written Ethernet frame data according to priority in order to generate enqueue requests.

[0032] The output processing module is used to determine whether to enqueue or discard the scheduled Ethernet frame data based on the enqueue request, and to dequeue when its own queue has Ethernet frame data.

[0033] refer to Figure 1 The input processing module of this invention includes an input polling module, a frame extraction module, a learning and searching module, and a frame shifting module; the output processing module includes a pre-queueing module and an output queue management module.

[0034] The input polling module is used to receive Ethernet frame data through multiple parallel high-speed ports. Each Ethernet frame data represents a packet. The multiple parallel packets are aggregated and polled to form a serial packet, which is then stored in the RAM of the frame shifting module.

[0035] refer to Figure 2 , Figure 2This invention illustrates the details of high-speed ports, packets, Ethernet frame data, and aggregated polling. Figure 2 As can be seen, multiple packets eventually form a single serial packet. The polled packets are stored in the RAM of the frame shifting module. The RAM is divided into 9 segments, each holding the longest frame. When the destination port number is found, the packet enters the corresponding node of the high-capacity switching processing unit Crossbar according to the destination port number.

[0036] The frame extraction module is used to extract the source MAC, destination MAC, and source port number of the packets for the learning and searching module to learn and search.

[0037] The learning and lookup module is used to search and learn based on the source MAC, destination MAC, and source port number using a four-level pipeline method, so as to find the matching frame information from the lookup table and the learning table.

[0038] The frame information includes the destination port, packet priority, frame length, and frame type.

[0039] The frame shifting module is used to read the corresponding packet from its own RAM and write the packet into the cross node of the high-capacity switching processing unit according to the frame information.

[0040] The high-capacity switching processing unit is used to arbitrate the packets written to its own cross node according to priority, thereby determining whether to store them in its own unicast buffer FIFO or multicast buffer FIFO.

[0041] The pre-queue module is used to cache packets after cross-node column arbitration, isolate the high-capacity switching processing unit and output queue management, and move packets onto the bus;

[0042] The output queue management module is used to read packets from the bus using a shared buffer and cache them, and to perform at least one of the following operations on the packets: logical enqueue, physical enqueue, logical dequeue, and physical dequeue.

[0043] The aggregated joint cross node and output queuing exchange architecture significantly reduces the number of queues and caches in queue management compared to input queue management, thus reducing the reliance on caches.

[0044] The input processing module adopts a pipelined and outstanding architecture, which is better suited to high-speed and high-capacity requirements, ensuring data transmission every clock cycle during bus migration and allowing for higher port aggregation. High aggregation reduces the number of buses; the number of cross-connect nodes is the square of the number of buses, meaning reducing the number of buses reduces the number of cross-connect nodes and lowers buffer usage.

[0045] Setting thresholds within the cross nodes of the high-capacity switching processing unit (Crossbar) ensures high-priority QoS. Column arbitration employs a multi-level column arbitration approach to avoid wiring congestion. In output processing, a pre-queue module isolates the output queue management and cross nodes of the high-capacity switching processing unit (Crossbar), making the queue management and cross nodes of the high-capacity switching processing unit (Crossbar) stand out, reducing scheduling complexity and improving scheduling efficiency.

[0046] like Figure 3 As shown, this embodiment of the invention provides a schematic diagram of a four-stage pipeline learning and search process under high-speed, high-capacity conditions. Figure 4 As shown, the left diagram is the flowchart for the four-level pipeline, and the right diagram is the flowchart for the four-level pipeline. The four-level pipeline consists of four stages: the first stage is hashing, the second stage is table lookup, the third stage is result processing, and the fourth stage is write-back.

[0047] The search steps in the learning and search module, which utilize a four-level pipeline approach, include:

[0048] The pipeline starts working when a valid source MAC address is received;

[0049] The first stage of the pipeline is used to perform hash operations on the source MAC and the destination MAC;

[0050] The second stage of the pipeline is used to read the lookup table based on the hash result of the source MAC;

[0051] The third stage of the pipeline is used to process the results read from the lookup table. The processing includes: comparing the source MAC address in the lookup table result with the destination MAC address. If they are the same, the destination port is the source port number in the lookup table result. If they are different, the packet is broadcast to each port.

[0052] The fourth stage of the pipeline is used to take the source MAC address as the query address and write the source MAC address, source port number, and current time as data into the lookup table according to the query address.

[0053] The learning and search module uses a four-level pipeline approach for learning, including the following steps:

[0054] The pipeline starts working when a valid MAC address is received;

[0055] The first stage of the pipeline is used to perform hash operations on the source MAC and the destination MAC;

[0056] The second stage of the pipeline is used to read the learning table using the hash result of the source MAC;

[0057] The third stage of the pipeline is used to process the results read from the lookup table. The processing includes: comparing the source port number in the result read from the learning table with the current source port number. If they are different and conflict detection is enabled, then learning fails, the conflict port and source MAC are recorded, and the pipeline result is recorded. If they are different but conflict detection is not enabled, then the process proceeds to the fourth stage of the pipeline.

[0058] The fourth stage of the pipeline is used to use the source MAC address as the query address as the address of the learning table, and to write the source MAC address, source port number, and current time into the learning table according to the query address.

[0059] The four-level pipeline for table lookups has two bypasses: adjacent-level bypass and skip-level bypass. Adjacent-level bypass occurs when the lookup address is the same as the address of the previous lookup, in which case the result processed by the previous lookup is treated as the result of the current lookup. Skip-level bypass occurs when the write-back address of the parent-parent lookup is the same as the address of the current lookup, in which case the content written back by the parent-parent lookup is treated as the result of the current lookup.

[0060] like Figure 5 As shown, this embodiment of the invention provides a schematic diagram of a three-stage pipeline frame transfer module under high-speed and high-capacity conditions. Figure 6 As shown, the frame shifting module of the present invention adopts a three-stage pipeline, and the specific steps are as follows:

[0061] When packets are extracted and searched for frame information, the packets polled by the polling module first enter the frame shifting module for buffering. The buffer is a 4KB RAM divided into 10 segments. Each segment's availability is indicated by a single bit, so a 10-bit `ram_seg_valid` signal is maintained. When a segment corresponding to a bit is available, the corresponding bit is set to 1; otherwise, it is set to 0. When a segment's data is moved by one clock cycle, the corresponding `ram_seg_valid` bit is set to 1. The first 1 in `ram_seg_valid` is then searched for, indicating the first segment where data can be stored. This search is combinational logic, similar to binary search, allowing the system to determine which segment the data should be stored in upon receipt. When the destination MAC address is found, the source port number, output port number, multicast flag, frame priority, segment containing the data frame, frame length, and frame type are written into the frame information FIFO. When the FIFO is not empty and the shifting bus is idle, a frame tag is created based on the frame information FIFO data: destination port, frame priority, frame length, and frame type. Simultaneously, data frames are read based on frame length and segment number, and frame tags are added to the corresponding frame header. While a frame is being transmitted, data is read one clock group tag before the frame shift ends. The purpose is to ensure that each clock can transmit data at high-speed port line speeds, improving bandwidth utilization. If a frame is stored in a single RAM, for example, 256 bits wide and supporting a length of 1522 bytes, one RAM would require four 36Kbit memory locations. If each RAM is independent, 90.8% of resources are wasted. Therefore, the storage RAM needs to be combined into one RAM, and the address segmented. A 256-bit wide, 512-bit deep RAM can support 10 longest frames, meaning it can be divided into 10 segments, resulting in a 7.11% resource waste. Therefore, segmenting the RAM in this way improves resource utilization.

[0062] When the destination port number is received from the learning lookup module, the destination port number, source port number, multicast flag, priority, storage segment number, frame length, and frame type are used as frame information; the frame information FIFO adopts the First-word-Fall-Through format.

[0063] Store the frame information into its own frame information FIFO;

[0064] When the frame information FIFO is not empty, the starting address and frame length of the packet storage are calculated based on the frame length in the frame information FIFO and the corresponding segment of the packet RAM. At the same time, the frame information FIFO is read to obtain the frame information of the next packet.

[0065] The packet is obtained by reading its own RAM based on the starting address and frame length of the packet.

[0066] Set tags for the read groups;

[0067] The tags include: destination port number, priority, frame length, and frame type;

[0068] Assign the groups carrying the tag to the corresponding cross nodes.

[0069] This invention combines tags and data, places the tag at the beginning of the frame, and then moves them together onto the bus. The tag information is used by the high-capacity switching processing unit (Crossbar column arbitration) to generate enqueue frame information and request enqueueing based on the tag information.

[0070] The input processing system employs a pipelined and outstanding architecture, making it better suited for high-speed, high-capacity requirements. This pipelined and outstanding architecture ensures data transmission every clock cycle on the bus, allowing for higher port aggregation. High aggregation reduces the number of buses; since the number of cross-connect nodes is the square of the number of buses, reducing the number of buses reduces the number of cross-connect nodes, thus lowering buffer usage.

[0071] like Figure 7 This invention provides a schematic diagram of a cross-node in a high-capacity switching processing unit (Crossbar) under high-speed and high-capacity conditions. The corresponding column arbitration is multi-level column arbitration, which makes cabling resources more evenly distributed and alleviates cabling congestion under high-speed and large-bit-width conditions. The cross-node has unicast and multicast buffer FIFOs, each buffer FIFO being 16KB. The high-capacity switching processing unit includes multiple rows and columns, with each column containing a column arbitration module. The intersection of rows and columns forms the cross-node.

[0072] To reduce reliance on cache under high-speed, high-capacity conditions, cross-connect nodes do not differentiate between priorities. However, to provide better QoS, a threshold is set at the cross-connect node. When the cross-connect node's capacity exceeds this threshold, only high-priority data is allowed to enter the cross-connect node, while low-priority data is dropped. Below the threshold, both high-priority and low-priority data can enter the cross-connect node, thus providing better QoS for high-priority data. When there is data in the corresponding column node of the high-capacity switching unit (Crossbar), column arbitration is performed on the corresponding column of the high-capacity switching unit (Crossbar) using RR scheduling. Under high-speed, high-capacity, and wide-bit-width conditions, a multi-level arbitration method is used to reduce placement and routing congestion, distributing placement and routing resources more evenly.

[0073] Each intersection node is used for:

[0074] Upon receiving a packet, determine whether it is a unicast or multicast packet. If it is a unicast packet, check whether the amount of data stored in the unicast buffer FIFO exceeds the set threshold. If it exceeds the threshold, store the high-priority packets according to the priority of the tags. If it does not exceed the set threshold, both high-priority and low-priority packets are allowed to enter the unicast buffer FIFO.

[0075] If the packet is multicast, it is directly stored in the multicast FIFO; when the packet enters the buffer FIFO, the remaining data volume of the multicast buffer FIFO is maintained according to the frame length; when there is data in the multicast buffer FIFO, a request is sent to the column arbitration module, which indicates that the cross node has data that needs to be forwarded.

[0076] The column arbitration module is used to perform round-robin scheduling based on the requests issued by the corresponding column intersection nodes. At the same time, it generates an enqueue request based on the tag of the group and sends the enqueue request to the output queue management; and sends the untagged groups to the pre-enqueue module cache.

[0077] This invention sets a threshold in the unicast buffer FIFO, which can guarantee the QoS of high-priority groups under high speed, large capacity and low cache. At the same time, the column arbitration is multi-level column arbitration, which can make the cabling resources more even and reduce cabling congestion under high speed and large bit width.

[0078] like Figure 8 As shown in the diagram, this embodiment of the invention provides a process schematic of a pre-queueing module under high-speed, high-capacity conditions. The column arbitration scheduling method and enqueue scheduling method of the high-capacity switching processing unit Crossbar can be isolated through the pre-queueing module. The enqueueing, moving, and discarding operations of groups are performed in this module, without affecting the execution process of column arbitration and enqueue scheduling in the high-capacity switching processing unit Crossbar, thus reducing scheduling complexity and improving scheduling efficiency. The specific steps to make the high-capacity switching processing unit Crossbar and output queue management outstanding under high-speed, high-capacity conditions through the pre-queueing module are as follows:

[0079] When a packet after column arbitration is received, the packet is written into its own data buffer FIFO, and the frame length of the packet is written into its own frame length FIFO.

[0080] The frame length is used to make an offset when reading data buffers or discarding packets;

[0081] When the enqueue ready signal is received, the data buffer FIFO is read according to the frame length. When the corresponding group is read, the frame length FIFO is read to obtain the frame length information of the next group. The frame length FIFO adopts the First-word-Fall-Through method, which can save the time of reading the FIFO. The read group is then moved to the bus.

[0082] When an enqueue failure signal is received, the data buffer will be offset according to the frame length, and the corresponding group will be discarded.

[0083] The pre-queueing module is used to isolate column arbitration and enqueue scheduling. This allows column arbitration and enqueue scheduling to be outstanding, and the enqueueing result will not affect the processing bandwidth of column arbitration, resulting in higher efficiency in group processing.

[0084] The queue management in this invention uses a shared buffer delimiter (BD) for enqueueing. Enqueueing is divided into logical enqueueing and physical enqueueing. Logical enqueueing refers to reading relevant queue information based on the enqueue frame information, and then using this queue information and thresholds to determine whether to enqueue: whether the number of used node BDs plus the current BD consumption exceeds the maximum node threshold; whether the number of used BDs plus the current BD consumption exceeds the queue's maximum threshold; if the number of used node BDs exceeds the node's minimum threshold, whether the shared buffer overflows; if the number of used node BDs is less than the node's minimum threshold, whether the shared buffer overflows. If enqueueing is allowed based on the above determinations, the corresponding number of BDs is requested; otherwise, enqueueing is rejected. Physical enqueueing refers to writing the corresponding group into the corresponding buffer based on the requested BD information.

[0085] Dequeue management uses a shared business logic block (BD) approach. Dequeueing is divided into logical dequeueing and physical dequeueing. Logical dequeueing refers to obtaining relevant queue information based on the queue number and generating a dequeue schedule. Physical dequeueing refers to obtaining the storage address corresponding to the data packet based on the dequeue schedule information, retrieving the data from the storage address, and outputting it onto the bus.

[0086] The present invention enables the system to be applied by performing the following steps on the system:

[0087] S101, the input polling module aggregates multiple ports and performs RR fair polling;

[0088] S102, the frame extraction module extracts the source MAC, destination MAC, and source port number of the packet;

[0089] S103, The learning and searching module adopts a pipeline approach for learning and searching;

[0090] S104, the frame shifting module reads data according to the frame length segment number, groups tags, and shifts the data to the corresponding cross node according to the destination port number;

[0091] S105, the column arbitration module performs RR scheduling based on the cache status of the corresponding column cross node, and generates an enqueue request based on the group tag header of the scheduled group;

[0092] S106, the scheduled group enters the pre-queueing module, waits for the enqueueing result, if it can be enqueued, it is physically enqueued, otherwise it is discarded;

[0093] S107 performs logical dequeueing and physical dequeueing when there is data in the queue.

[0094] The above describes the details of the high-speed, high-capacity aggregated cross-node output joint queuing switching system provided by this invention. In the system of this invention, packet forwarding is based on the aggregated cross-node output joint queuing switching architecture to interact with devices in the switching network. This invention is generally divided into three parts: input processing, cross-nodes in the high-capacity switching processing unit (Crossbar), and output queue management. To meet the speed requirements of high-speed port aggregation, the input processing adopts a pipelined approach: the learning and lookup module is a four-stage pipeline, consisting of hashing, table lookup, result processing, and write-back. The data transfer module is a three-stage pipeline, consisting of obtaining frame information, grouping tags and reading data from RAM, and transferring data to the bus. The learning and lookup module and the data transfer module are outstanding. This design of the input processing module ensures that data can be transmitted every clock cycle, allows for the aggregation of more ports, and reduces the buffer usage of the high-capacity switching processing unit (Crossbar) and the number of output queues.

[0095] Another objective of this invention is to reduce buffering while ensuring high-priority QoS for packets under high-speed, high-capacity conditions. Through multi-level column arbitration, cabling resources are more evenly distributed, alleviating cabling congestion under high-speed, large-bit-width conditions. A threshold is set in the high-capacity switching processing unit (Crossbar). When the Crossbar node buffer exceeds this threshold, only high-priority packets are allowed to enter the Crossbar buffer, while low-priority packets are dropped. When the buffer is below the threshold, both high-priority and low-priority packets can enter the Crossbar, thus ensuring high-priority QoS.

[0096] Another objective of this invention is to transform input queue management into output queue management, which can significantly reduce the number of queues: Let the number of buses be B, the priority be F, and the number of queue output ports be N, then the total number of queues Q = B × F × N. Taking six buses, with two ports aggregated on each bus as an example, the number of queues managed by the input queue is 6 × 8 × 12, and the number of queues managed by the output queue is 6 × 8 × 2, reducing the number of queues by a factor of 5. Furthermore, the high-capacity switching processing unit Crossbar and the output queue management are isolated by a buffer, resulting in outstanding high-efficiency grouping.

[0097] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0098] Although this application has been described herein in conjunction with various embodiments, those skilled in the art will understand and implement other variations of the disclosed embodiments by reviewing the accompanying drawings, the disclosure, and the appended claims in carrying out the claimed application. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality.

[0099] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A high-speed, high-capacity aggregated cross-connect node output joint queuing switching system, characterized in that, include: Input processing module, high-capacity switching processing unit, and output processing module; The input module is used to aggregate and poll all input Ethernet frame data, and search and learn frame information that matches the Ethernet frame data, thereby writing the Ethernet frame data into the corresponding cross node in the high-capacity switching processing unit. The high-capacity switching processing unit is used to arbitrate and schedule the written Ethernet frame data according to priority in order to generate enqueue requests. The output processing module is used to determine whether to enqueue or discard the scheduled Ethernet frame data based on the enqueue request, and to dequeue when its own queue has Ethernet frame data. The input processing module includes an input polling module, a frame extraction module, a learning and searching module, and a frame shifting module; the output processing module includes a pre-queueing module and an output queue management module. The input polling module is used to receive Ethernet frame data through multiple parallel high-speed ports. Each Ethernet frame data represents a packet. The multiple parallel packets are aggregated and polled to form a serial packet, which is then stored in the RAM of the frame shifting module. The frame extraction module is used to extract the source MAC, destination MAC, and source port number of the packets for the learning and searching module to learn and search. The learning and lookup module is used to search and learn based on the source MAC, destination MAC, and source port number using a four-level pipeline method, so as to find the matching frame information from the lookup table and the learning table. The frame information includes the destination port, packet priority, frame length, and frame type. The frame shifting module is used to read the corresponding packet from its own RAM and write the packet into the cross node of the high-capacity switching processing unit according to the frame information. The high-capacity switching processing unit is used to arbitrate the packets written to its own cross node according to priority, thereby determining whether to store them in its own unicast buffer FIFO or multicast buffer FIFO. The pre-queue module is used to cache packets after cross-node column arbitration, isolate the high-capacity switching processing unit and output queue management, and move packets onto the bus; The output queue management module is used to read packets from the bus using a shared buffer and cache them, and to perform at least one of the following operations on the packets: logical enqueue, physical enqueue, logical dequeue, and physical dequeue.

2. The high-speed, high-capacity aggregated cross-connect node output joint queuing switching system according to claim 1, characterized in that, The search steps in the learning and search module, which utilize a four-level pipeline approach, include: The pipeline starts working when a valid source MAC address is received; The first stage of the pipeline is used to perform hash operations on the source MAC and the destination MAC; The second stage of the pipeline is used to read the lookup table based on the hash result of the source MAC; The third stage of the pipeline is used to process the results read from the lookup table. The processing includes: comparing the source MAC address in the lookup table result with the destination MAC address. If they are the same, the destination port is the source port number in the lookup table result. If they are different, the packet is broadcast to each port. The fourth stage of the pipeline is used to take the source MAC address as the query address and write the source MAC address, source port number, and current time as data into the lookup table according to the query address.

3. The high-speed, high-capacity aggregated cross-connect node output joint queuing switching system according to claim 1, characterized in that, The learning and search module uses a four-level pipeline approach for learning, including the following steps: The pipeline starts working when a valid MAC address is received; The first stage of the pipeline is used to perform hash operations on the source MAC and the destination MAC; The second stage of the pipeline is used to read the learning table using the hash result of the source MAC; The third stage of the pipeline is used to process the results read from the lookup table. The processing includes: comparing the source port number in the result read from the learning table with the current source port number. If they are different and conflict detection is enabled, then learning fails, the conflict port and source MAC are recorded, and the pipeline result is recorded. If they are different but conflict detection is not enabled, then the process proceeds to the fourth stage of the pipeline. The fourth stage of the pipeline is used to use the source MAC address as the query address as the address of the learning table, and to write the source MAC address, source port number, and current time into the learning table according to the query address.

4. The high-speed, high-capacity aggregated cross-connect node output joint queuing switching system according to claim 1, characterized in that, The frame shifting module is specifically used for: When the destination port number is received from the learning lookup module, the destination port number, source port number, multicast flag, priority, storage segment number, frame length, and frame type are used as frame information. Store the frame information into its own frame information FIFO; When the frame information FIFO is not empty, the starting address and frame length of the packet storage are calculated based on the frame length in the frame information FIFO and the corresponding segment of the packet RAM. At the same time, the frame information FIFO is read to obtain the frame information of the next packet. The packet is obtained by reading its own RAM based on the starting address and frame length of the packet. Set tags for the read groups; The tags include: destination port number, priority, frame length, and frame type; Assign the groups carrying the tag to the corresponding cross nodes.

5. The high-speed, high-capacity aggregated cross-connect node output joint queuing switching system according to claim 1, characterized in that, The high-capacity switching processing unit consists of multiple rows and columns, with each column containing a column arbitration module, and the intersection of rows and columns forming an intersection node; Each intersection node is used for: Upon receiving a packet, determine whether it is a unicast or multicast packet. If it is a unicast packet, check whether the amount of data stored in the unicast buffer FIFO exceeds the set threshold. If it exceeds the threshold, store the high-priority packets according to the priority of the tags. If it does not exceed the set threshold, both high-priority and low-priority packets are allowed to enter the unicast buffer FIFO. If the packet is multicast, it is directly stored in the multicast FIFO; when the packet enters the buffer FIFO, the remaining data volume of the multicast buffer FIFO is maintained according to the frame length; when there is data in the multicast buffer FIFO, a request is sent to the column arbitration module, which indicates that the cross node has data that needs to be forwarded. The column arbitration module is used to perform round-robin scheduling based on the requests issued by the corresponding column intersection nodes. At the same time, it generates an enqueue request based on the tag of the group and sends the enqueue request to the output queue management; and sends the untagged groups to the pre-enqueue module cache.

6. The high-speed, high-capacity aggregated cross-connect node output joint queuing switching system according to claim 1, characterized in that, The pre-queue module is specifically used for: When a packet after column arbitration is received, the packet is written into its own data buffer FIFO, and the frame length of the packet is written into its own frame length FIFO. The frame length is used to make an offset when reading data buffers or discarding packets; When the enqueue ready signal is received, the data buffer FIFO is read according to the frame length. When the corresponding group is read, the frame length FIFO is read to obtain the frame length information of the next group. The read group is then moved onto the bus. When an enqueue failure signal is received, the data buffer will be offset according to the frame length, and the corresponding group will be discarded.

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