Address allocation method, multi-device system, and storage medium

Abstract

The application relates to the new energy field and provides an address allocation method, a multi-device system and a storage medium. When an address allocation request is received through a first parallel port, the address allocation function of other parallel ports except the first parallel port is disabled, an address allocation instruction is sent to the first parallel port, and when an address configuration completion instruction is received through the first parallel port, the address allocation function of other parallel ports except the first parallel port is enabled. The above method can sequentially allocate addresses for slave devices, thereby improving the accuracy of address allocation.

Description

Technical Field

[0001] This application relates to the field of new energy technology, specifically to an address allocation method, a multi-device system, and a storage medium. Background Technology

[0002] In a master-slave architecture, such as a multi-device system for energy storage devices (e.g., battery packs), the master device uses the same communication bus to communicate with multiple slave devices. When the master device in a multi-device system detects a slave device connecting, it assigns an address to the connected slave device. However, when multiple slave devices connect to the master device simultaneously, the master device may be unable to accurately assign addresses to the multiple connected slave devices. Summary of the Invention

[0003] This application provides an address allocation method, a multi-device system, and a storage medium to solve the technical problem of how to accurately and orderly allocate addresses to slave devices.

[0004] A first aspect of this application provides an address allocation method applied to a master device in a multi-device system. The master device is connected to a slave device via a parallel port; the slave device is connected to the master device or other slave devices via a parallel port. The method includes: disabling the address allocation function of parallel ports other than the first parallel port when an address allocation request is received through a first parallel port; the first parallel port being any parallel port of the master device; sending an address allocation instruction to the first parallel port; the address allocation instruction being used to allocate an address to the slave device that sent the address allocation request; and enabling the address allocation function of parallel ports other than the first parallel port when an address configuration completion instruction is received through the first parallel port.

[0005] In this embodiment of the application, when an address allocation request is received on the first parallel port, the address allocation function of other parallel ports besides the first parallel port is disabled. This prevents the address allocated by the master device to the slave device that sent the address allocation request from being received by other slave devices, improves the orderliness of address allocation, and thus improves the accuracy of address allocation.

[0006] A second aspect of this application provides an address allocation device, comprising a master device operating in a multi-device system, the master device being connected to slave devices via parallel ports; the slave devices being connected to the master device or other slave devices via parallel ports; the method comprising: a disabling unit, configured to disable the address allocation function of parallel ports other than the first parallel port when an address allocation request is received through a first parallel port; the first parallel port being any parallel port of the master device; a sending unit, configured to send an address allocation instruction to the first parallel port; the address allocation instruction being used to allocate an address to the slave device that sent the address allocation request; and a control unit, configured to enable the address allocation function of parallel ports other than the first parallel port when an address configuration completion instruction is received through the first parallel port.

[0007] A third aspect of this application provides an electronic device, which serves as a master device. The electronic device includes: a parallel port for connecting to a slave device; a memory for storing computer-readable instructions; and a processor for executing the computer-readable instructions stored in the memory to implement the address allocation method.

[0008] A fourth aspect of this application provides a multi-device system, the multi-device system including multiple electronic devices; the multiple electronic devices are configured with a master device and a slave device; the master device is connected to the slave device through a parallel port; the slave device is connected to the master device or other slave devices through a parallel port; wherein the master device executes to implement the address allocation method.

[0009] A fifth aspect of this application provides a computer-readable storage medium storing computer-readable instructions, which are executed by a processor in an electronic device to implement the address allocation method. Attached Figure Description

[0010] Figure 1 This is an application scenario diagram of an address allocation method provided in an embodiment of this application.

[0011] Figure 2 This is a flowchart of the address allocation method provided in the embodiments of this application.

[0012] Figure 3 This is a schematic diagram of the parallel port in the master device provided in the embodiments of this application.

[0013] Figure 4 This is a schematic diagram of the slave device address number provided in the embodiments of this application.

[0014] Figure 5 This is a flowchart of an address allocation method provided in another embodiment of this application.

[0015] Figure 6 This is a flowchart of an address allocation method provided in another embodiment of this application.

[0016] Figure 7 This is a functional block diagram of the address allocation device provided in the embodiments of this application.

[0017] Figure 8 This is a schematic diagram of the structure of an electronic device that implements the address allocation method according to an embodiment of this application. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of this application clearer, the application will be described in detail below with reference to the accompanying drawings and specific embodiments.

[0019] It should be noted that in this application, "at least one" means one or more, and "more than one" means two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The terms "first," "second," "third," "fourth," etc. (if present) in the specification, claims, and drawings of this application are used to distinguish similar objects, not to describe a specific order or sequence.

[0020] In the embodiments of this application, the terms "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design solutions. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a specific manner. Unless otherwise specified, the following embodiments and features described herein can be combined with each other.

[0021] In a master-slave architecture, such as a multi-device system for energy storage devices (e.g., battery packs), the master device uses the same communication bus to communicate with multiple slave devices. When the master device detects a slave device connecting, it assigns an address to the connected slave device. However, when multiple slave devices connect to the master device simultaneously, the address assignment command sent by the master device is received by all slave devices connected to the communication bus. In this situation, it's impossible to determine which specific slave device the address assignment command is for, leading to the master device being unable to accurately assign addresses to the multiple connected slave devices. The following section discusses this further. Figure 1 This application describes an application scenario for an address allocation method provided in this embodiment.

[0022] like Figure 1The multi-device system 100 shown includes a master device 10 and at least one slave device (such as...). Figure 1 The system includes slave devices A1, A2, ..., An, B1, B2, ..., Bn. The master device 10 is configured with multiple parallel ports, and it connects to at least one slave device through each parallel port. A slave device can also connect to the master device 10 or other slave devices through a parallel port. Slave devices are connected to the master device 10 in a cascading manner. When the master device 10 detects a slave device connected to the multi-device system 100, it assigns an address to the connected slave device.

[0023] like Figure 1 As shown, the master device 10 in the multi-device system 100 is connected to two slave device links. Since the control logic of the two slave device links is consistent, for ease of description, this embodiment uses one slave device link for illustration. Specifically, the master device 10 starts the parallel port a0. When slave device A1 detects that the master device 10 outputs a signal through the parallel port a0, slave device A1 will send a feedback signal to the master device 10. At this time, the master device 10 determines that the parallel port a0 is connected to slave device A1, and then the master device 10 will allocate an address to slave device A1. After slave device A1 completes the address allocation, slave device A1 outputs a signal through its own parallel port a1. When slave device A2 detects the output signal sent by slave device A1 through the parallel port a1, slave device A2 will send a feedback signal to slave device A1. When slave device A1 detects the feedback signal, slave device A1 will notify the master device 10 that slave device A2 has been connected to the multi-device system 100, and the master device 10 will allocate an address to slave device A2.

[0024] When the master device 10 simultaneously detects feedback signals from both slave devices A1 and B1, the addresses allocated by the master device 10 will be received by both slave devices A1 and B1 simultaneously. Similarly, when slave devices A1, A2, B1, and B2 have all been allocated addresses, if slave devices A3 and B3 simultaneously access the multi-device system 100, slave devices A2 and B2 will simultaneously send their access information back to the master device 10. In this case, the addresses allocated by the master device 10 will also be received by both slave devices A3 and B3 simultaneously, resulting in the master device 10 being unable to allocate addresses to slave devices in an orderly manner, leading to low accuracy in address allocation.

[0025] To address the aforementioned problems, this application provides an address allocation method that enables the master device to allocate addresses to slave devices in an orderly manner, ensuring the accuracy of address allocation. The following will combine... Figure 2 The flowchart shown illustrates the address allocation method.

[0026] Both the master device and the slave device in the embodiments of this application can be energy storage devices. The energy storage device can be a battery pack with only the function of storing or discharging electricity, or it can be a mobile energy storage device with the function of power conversion. For example, the energy storage device can also be applied to self-moving devices such as automotive equipment, lawn mowing equipment, sweeping equipment, mine clearance equipment, and cruise equipment, without limitation.

[0027] like Figure 2 The diagram shown is a flowchart of an address allocation method provided in an embodiment of this application. The address allocation method is applied to a master device (e.g., Figure 1 In the main device 10), the main device can be an electronic device, such as an energy storage device. Depending on different needs, the order of the steps in this flowchart can be changed, and some steps can be omitted.

[0028] S201, when an address allocation request is received through the first parallel port, the address allocation function of other parallel ports besides the first parallel port is disabled; the first parallel port is any parallel port of the master device.

[0029] In at least one embodiment of this application, an address allocation request can be triggered when a slave device is connected to any parallel port of the master device, or when a slave device that has already completed address allocation is connected to another slave device. Other parallel ports besides the first parallel port may include: parallel ports connected to slave devices with unassigned addresses and parallel ports not connected to any slave devices.

[0030] In one embodiment, when the master device disables the address allocation function for parallel ports other than the first parallel port, the other parallel ports (e.g., Figure 3 Port 03 can still connect to new slave devices, but port 03 will not send address allocation instructions to the connected slave device C0, nor will it respond to address allocation requests from slave device C0. In one embodiment, after the address allocation function is disabled, the parallel port can still perform other functions, such as charging and discharging. By disabling the address allocation function of parallel ports other than the first parallel port, it is possible to prevent the address allocated by the master device to the slave device of the first parallel port from being received by other slave devices, thereby improving the orderliness of address allocation.

[0031] In another embodiment, the master device disables all parallel ports other than the first parallel port. When the master device disables all parallel ports other than the first parallel port, all functions of these parallel ports are disabled. Even if a new slave device is connected, the new slave device only has a physical connection to the parallel port, not an electrical connection; that is, there is no communication or power transmission between them. Therefore, the slave device connected to this parallel port cannot receive the address assigned by the master device to the first parallel port. In one embodiment, disabling the parallel port may simply disable its address allocation function, that is, only prohibiting the parallel port from sending address allocation instructions to connected slave devices or not responding to address allocation requests from connected slave devices. By disabling all parallel ports other than the first parallel port, the master device can avoid receiving address allocation requests from other parallel ports when allocating addresses to slave devices connected to the first parallel port. This avoids the inability to allocate addresses in an orderly manner due to the simultaneous connection of multiple slave devices, improving the accuracy of address allocation.

[0032] In another embodiment, the master device disables other parallel ports not connected to slave devices besides the first parallel port, and sends a disable command to other parallel ports connected to slave devices besides the first parallel port. The disable command instructs devices connected to slave devices without assigned addresses to disable the corresponding parallel ports. The device connected to a slave device without assigned address can be either the master device itself or a slave device. That is, when disabling the address allocation function of other parallel ports besides the first parallel port, the decision is based on the connected slave devices. Specifically, when no slave device is connected to the parallel port of the master device or slave device, the parallel port can be directly disabled; when a slave device without assigned address is connected to the master device or slave device, the corresponding parallel port will also be disabled.

[0033] Combination Figure 3 This application describes the parallel port in the master device provided in the embodiments. For example... Figure 3As shown, the parallel ports of the master device 10 include port 01, port 02, port 03, and port 04. Port 02 is not connected to any slave device. Port 03 is connected to slave device C0, which has not been assigned an address. Port 04 is connected to slave device C1, which has been assigned an address. Slave device C1 is connected to slave device C2, which has not been assigned an address. Assuming the first parallel port is port 01, when the master device 10 receives an address allocation request through port 01, it sends a disable command to ports 02, 03, and 04, and also sends the disable command to the corresponding slave devices C0 and C1 through ports 03 and 04. The disable command is used to instruct the master device 10 to disable ports 02 and 03 and to instruct slave device C1 to disable its own parallel port connected to slave device C2, thereby disabling the address allocation function of the parallel ports other than port 01.

[0034] Since other parallel ports that are not connected to slave devices and other parallel ports that have connected slave devices with unassigned addresses are disabled, the slave devices on the corresponding parallel ports cannot detect the signals output by the master device or the slave devices at the next higher level. Therefore, it is possible to prevent the address assigned by the master device to the slave device of the first parallel port (e.g., port 01) from being received by other slave devices with unassigned addresses, so that the master device can assign addresses to slave devices in an orderly manner.

[0035] In at least one embodiment of this application, if a slave device C1 is connected to a slave device with an unassigned address, the master device determines that the slave device C1 has completed the disabling of the corresponding parallel port when it receives the response signal of the slave device C1 to the disable command.

[0036] S202, send an address allocation instruction to the first parallel port; the address allocation instruction is used to allocate an address to the slave device that sent the address allocation request.

[0037] In at least one embodiment of this application, the slave device sending the address allocation request may be a slave device directly connected to the master device (e.g., Figure 3 The newly added slave device (in the context) can also be a slave device connected to an already assigned address, such as... Figure 3 The slave device C2.

[0038] In at least one embodiment of this application, the master device determines the port address of the first parallel port and the hierarchical relationship of the slave device that sent the address allocation request in the multi-device system, and further allocates an address to the slave device that sent the address allocation request based on the port address and the hierarchical relationship.

[0039] Combination Figure 4 This describes the slave device address number provided in the embodiments of this application. For example... Figure 4As shown, assume the master device includes a first port and a second port. The first port is connected to slave devices D1, D2, ..., Dn in sequence, and the second port is connected to slave device E1. If the port address of the first port is 10x, since slave device D1 is at level 1 in the multi-device system, the address number of the master device for slave device D1 can be 101; since slave device D2 is at level 2 in the multi-device system, the address number of the master device for slave device D2 can be 102, and so on. Correspondingly, the port address of the second port can be 20x, and since slave device E1 is at level 1 in the multi-device system, the address number of the master device for slave device E1 can be 201.

[0040] By combining port addresses and hierarchical relationships to assign addresses to slave devices, the rationality of address allocation can be improved. In this application, different address combinations are configured for different parallel ports of the master device, facilitating the differentiation and management of slave devices on different parallel ports and improving the control efficiency of slave devices.

[0041] S203, when receiving the address configuration completion instruction through the first parallel port, enables the address allocation function of other parallel ports besides the first parallel port.

[0042] In at least one embodiment of this application, after the master device enables the address allocation function of parallel ports other than the first parallel port, all parallel ports are restored to normal function, capable of receiving address allocation requests from newly connected slave devices and transmitting the address allocation instructions generated by the master device to the corresponding slave devices.

[0043] Using the above address allocation method, when the first parallel port receives an address allocation request, by disabling the address allocation function of other parallel ports besides the first parallel port, it is possible to prevent the address allocated by the master device for the slave device that sent the address allocation request from being received by other slave devices, thereby improving the orderliness of address allocation and thus improving the accuracy of address allocation.

[0044] like Figure 5 The diagram shown is a flowchart of an address allocation method provided in another embodiment of this application. This address allocation method is applied to a master device (e.g., Figure 1 In the context of main equipment 10), the main equipment can be electronic equipment, such as energy storage equipment. For example... Figure 5 As shown, the address allocation method may include the following steps S501-S505. Depending on different requirements, the order of the steps in this flowchart may be changed, and some may be omitted.

[0045] S501 obtains the status of the master device after receiving an address allocation request through the first parallel port.

[0046] In at least one embodiment of this application, the state of the master device includes an address allocation state and a non-address allocation state. This state can be read using a corresponding state identifier. For example, a state identifier of a first preset value indicates that the master device is in an address allocation state, while a second preset value indicates that the master device is not in an address allocation state, i.e., a non-address allocation state. It is understood that the corresponding state can also be determined based on all current execution states of the master device. For example, when address allocation is disabled or when address allocation is being performed, it is determined to be in an address allocation state; otherwise, it is determined to be in a non-address allocation state.

[0047] S502 detects whether the master device is in address allocation state.

[0048] In at least one embodiment of this application, the specific value of the aforementioned status identifier can be used to detect whether the master device is allocating an address to the slave device. If the status identifier is detected to be a first preset value, it is determined that the master device is in the address allocation state, and step S506 is executed. If it is confirmed that the master device is in the non-address allocation state, step S503 is executed.

[0049] S503, when the master device is not in the address allocation state, responds to the address allocation request, enters the address allocation state, and performs the function of disabling the address allocation of other parallel ports except the first parallel port.

[0050] After entering the address allocation state, the value corresponding to the state is updated to a first preset value to indicate that the current state is in address allocation. The address allocation state can include two phases: a disable phase and an execute phase. The disable phase refers to disabling the address allocation function of parallel ports other than the first parallel port. If there are no other parallel ports besides the first parallel port, it is not necessary to enter the disable phase. The execute phase corresponds to the phase in S504.

[0051] S504, send an address allocation instruction to the first parallel port; the address allocation instruction is used to allocate an address to the slave device that sent the address allocation request.

[0052] S505: When an address configuration completion instruction is received through the first parallel port, the address allocation function of other parallel ports besides the first parallel port is enabled, and the address allocation state is exited.

[0053] When exiting the address allocation state, the status flag is updated to a second preset value to indicate that the master device is not currently in the address allocation state.

[0054] For details of steps S503 to S505, please refer to the above text. Figure 2 The detailed descriptions of steps S201 to S203 are provided in the original text and will not be repeated here.

[0055] In this embodiment, before responding to an address allocation request, the status of the master device is checked. Only when it is determined that the master device is not in the address allocation state will the address allocation request be responded to. Furthermore, when performing address allocation in response to the address allocation request, the master device enters the address allocation state. At this time, the master device will not send addresses to parallel ports other than the first parallel port, thereby effectively preventing the address generated by the master device from being received by multiple slave devices.

[0056] S506 does not respond to address allocation requests when the master device is in address allocation state.

[0057] In at least one embodiment of this application, when the master device is in the address allocation state, even if a new slave device is connected, the master device will not respond to the address allocation request issued by the slave device. Instead, it will wait for the previous address allocation to be completed and exit the address allocation state before continuing to respond to the address allocation request.

[0058] like Figure 6 The diagram shown is a flowchart of an address allocation method provided in another embodiment of this application. This address allocation method is applied to a master device (e.g., Figure 1 In the context of main equipment 10), the main equipment can be electronic equipment, such as energy storage equipment. For example... Figure 6 As shown, the address allocation method may include the following steps S601-S604. Depending on different requirements, the order of the steps in this flowchart may be changed, and some may be omitted.

[0059] S601, upon receiving a new hardware presence signal through the first parallel port, determines that an address allocation request has been received through the first parallel port.

[0060] Combination Figure 3 This describes the reception of the hardware presence signal. For example... Figure 3 As shown, slave device C1 is connected to slave device C2. Slave device C1 outputs a signal to slave device C2, and slave device C2 outputs a feedback signal upon receiving the signal. When slave device C1 receives the feedback signal, and the value of the feedback signal is valid (such as a preset high or low level), slave device C1 confirms receipt of the presence signal from slave device C2 and sends it to master device 10. Master device 10 receives the hardware presence signal through port 04. When a new slave device C0 is connected through port 03, it is confirmed that port 03 has received a new hardware presence signal.

[0061] S602, disable the address allocation function of parallel ports other than the first parallel port; the first parallel port is any parallel port of the master device.

[0062] S603, send an address allocation instruction to the first parallel port; the address allocation instruction is used to allocate an address to the slave device that sent the address allocation request.

[0063] S604, when receiving an address configuration completion instruction through the first parallel port, enables the address allocation function of other parallel ports besides the first parallel port.

[0064] For details on steps S602 to S604, please refer to the above text. Figure 2 The detailed descriptions of steps S201 to S203 are provided in the original text and will not be repeated here.

[0065] In this embodiment of the application, when a new hardware presence signal is received, an address allocation request is determined to have been received, thereby triggering the master device to allocate an address to the slave device that is responding to the hardware presence signal, thus improving the timeliness of address allocation.

[0066] like Figure 7 The diagram shown is a functional block diagram of the address allocation device provided in this application embodiment. The address allocation device 11 operates as the master device in a multi-device system. The master device is connected to slave devices through a parallel port; slave devices are connected to the master device or other slave devices through a parallel port. The address allocation device 11 includes a disable unit 110, a send unit 111, a control unit 112, an acquire unit 113, a response unit 114, an exit unit 115, and a determine unit 116. The module / unit referred to in this application refers to a series of computer-readable instruction segments that can be acquired by the processor 13 and perform a fixed function, and which are stored in memory.

[0067] The disable unit 110 is used to disable the address allocation function of other parallel ports besides the first parallel port when an address allocation request is received through the first parallel port; the first parallel port is any parallel port of the master device; the send unit 111 is used to send an address allocation instruction to the first parallel port; the address allocation instruction is used to allocate an address to the slave device that sent the address allocation request; the control unit 112 is used to enable the address allocation function of other parallel ports besides the first parallel port when an address configuration completion instruction is received through the first parallel port.

[0068] Further, the acquisition unit 113 is used to acquire the status of the master device; the response unit 114 is used to respond to the address allocation request, enter the address allocation state, and perform the step of disabling the address allocation function of parallel ports other than the first parallel port when the master device is not in the address allocation state. The response unit 114 is also used to not respond to the address allocation request when the master device is in the address allocation state.

[0069] Furthermore, the exit unit 115 is used to exit the address allocation state when an address configuration completion instruction is received through the first parallel port.

[0070] Furthermore, the determining unit 116 is used to determine that an address allocation request has been received through the first parallel port when a new hardware presence signal is received through the first parallel port.

[0071] For detailed information on the functions of each module / unit, please refer to the above text. Figure 2 The detailed description will not be repeated here.

[0072] As can be seen from the above technical solutions, when the first parallel port receives an address allocation request, the embodiments of this application can prevent the address allocated by the master device for the slave device that sent the address allocation request from being received by other slave devices by disabling the address allocation function of other parallel ports besides the first parallel port, thereby improving the orderliness of address allocation and thus improving the accuracy of address allocation.

[0073] like Figure 8 The diagram shown is a schematic diagram of the structure of an electronic device that implements the address allocation method according to an embodiment of this application.

[0074] In one embodiment of this application, the electronic device 10 includes, but is not limited to, a parallel port 14, a memory 12, a processor 13, and computer-readable instructions, such as an address allocation program, stored in the memory 12 and executable on the processor 13. The parallel port 14 is used to connect to a slave device.

[0075] Those skilled in the art will understand that the schematic diagram is merely an example of the electronic device 10 and does not constitute a limitation on the electronic device 10. It may include more or fewer components than shown, or combine certain components, or different components. For example, the electronic device 10 may also include input / output devices, network access devices, buses, etc.

[0076] Processor 13 can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor can be a microprocessor or any conventional processor. Processor 13 is the computational core and control center of electronic device 10, connecting various parts of electronic device 10 via various interfaces and lines, and executing the operating system of electronic device 10, as well as various installed application programs and program code.

[0077] For example, computer-readable instructions can be divided into one or more modules / units, one or more of which are stored in memory 12 and executed by processor 13 to complete this application. One or more modules / units can be a series of computer-readable instruction segments capable of performing a specific function, which describe the execution process of the computer-readable instructions in electronic device 10. For example, computer-readable instructions can be divided into a disable unit 110, a send unit 111, a control unit 112, an acquire unit 113, a respond unit 114, an exit unit 115, and a determine unit 116.

[0078] The memory 12 can be used to store computer-readable instructions and / or modules. The processor 13 implements various functions of the electronic device 10 by running or executing the computer-readable instructions and / or modules stored in the memory 12 and by calling the data stored in the memory 12. The memory 12 may mainly include a program storage area and a data storage area. The program storage area may store the operating system, application programs required for at least one function (such as sound playback function, image playback function, etc.), etc.; the data storage area may store data created according to the use of the electronic device, etc. The memory 12 may include non-volatile and volatile memory, such as: hard disk, memory, plug-in hard disk, smart media card (SMC), secure digital (SD) card, flash card, at least one disk storage device, flash memory device, or other storage devices.

[0079] The memory 12 can be the external memory and / or internal memory of the electronic device 10. Furthermore, the memory 12 can be a physical memory, such as a memory stick, a TF card (Trans-flash Card), etc.

[0080] If the modules / units integrated in the electronic device 10 are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, all or part of the processes in the methods of the above embodiments can also be implemented by instructing related hardware through computer-readable instructions. The computer-readable instructions can be stored in a computer-readable storage medium, and when executed by a processor, they can implement the steps of the various method embodiments described above.

[0081] Computer-readable instructions include computer-readable instruction code, which can be in the form of source code, object code, executable files, or certain intermediate forms. Computer-readable media can include: any entity or device capable of carrying computer-readable instruction code, recording media, USB flash drives, portable hard drives, magnetic disks, optical disks, computer memory, read-only memory (ROM), and random access memory (RAM).

[0082] Combination Figure 2-6 The memory 12 in the electronic device 10 stores computer-readable instructions, and the processor 13 can execute the computer-readable instructions stored in the memory 12 to achieve, for example, Figure 2 The address allocation method shown.

[0083] Specifically, the specific implementation method of the processor 13 for the above-mentioned computer-readable instructions can be found in [reference]. Figure 2-6 The descriptions of the relevant steps in the corresponding embodiments are not repeated here.

[0084] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of modules is only a logical functional division, and other division methods may be used in actual implementation.

[0085] The modules described as separate components may or may not be physically separate. The components shown as modules may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0086] Furthermore, the functional modules in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or in the form of hardware plus software functional modules.

[0087] Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of this application is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be embraced within this application. No appended diagram markings in the claims should be construed as limiting the scope of the claims.

[0088] Furthermore, it is clear that the word "including" does not exclude other units or steps, and the singular does not exclude the plural. Multiple units or devices can also be implemented by a single unit or device through software or hardware. Terms such as "first," "second," etc., are used to indicate names and do not indicate any specific order.

[0089] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application and are not intended to limit it. Although this application has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of this application without departing from the spirit and scope of the technical solutions of this application.

Claims

1. An address allocation method, characterized in that, A master device used in a multi-device system, wherein the master device is connected to the slave devices via a parallel port; The slave device is connected to the master device or other slave devices via a parallel port; the method includes: When an address allocation request is received through the first parallel port, the address allocation function of other parallel ports besides the first parallel port is disabled; the first parallel port can be any parallel port of the master device; wherein, after the address allocation function of other parallel ports besides the first parallel port is disabled, the other parallel ports can still connect new slave devices, but will not send address allocation instructions to the connected slave devices, nor respond to the address allocation requests of the connected slave devices; after the address allocation function is disabled, the parallel port can still perform other functions besides the address allocation function; Send an address allocation instruction to the first parallel port; the address allocation instruction is used to allocate an address to the slave device that sent the address allocation request, and allocating an address to the slave device that sent the address allocation request includes: determining the port address of the first parallel port, and determining the hierarchical relationship of the slave device that sent the address allocation request in the multi-device system, and allocating an address to the slave device that sent the address allocation request according to the port address and the hierarchical relationship; When an address configuration completion instruction is received through the first parallel port, the address allocation function of other parallel ports besides the first parallel port is enabled.

2. The method according to claim 1, characterized in that, Disabling the address allocation function for parallel ports other than the first parallel port includes: Disable all parallel ports other than the first parallel port.

3. The method according to claim 1, characterized in that, Disabling the address allocation function for parallel ports other than the first parallel port includes: Disable other parallel ports that are not connected to slave devices, except for the first parallel port; Send a disable command to other parallel ports connected to slave devices other than the first parallel port; the disable command is used to instruct the device connected to the slave device with an unassigned address to disable the corresponding parallel port.

4. The method according to claim 1, characterized in that, After receiving the address allocation request through the first parallel port, the method further includes: Obtain the status of the master device; When the master device is not in the address allocation state, it responds to the address allocation request, enters the address allocation state, and executes the step of disabling the address allocation function of other parallel ports besides the first parallel port.

5. The method according to claim 4, characterized in that, The method further includes: Upon receiving an address configuration completion instruction through the first parallel port, exit the address allocation state.

6. The method according to claim 1, characterized in that, The method further includes: When the master device is in address allocation state, it does not respond to the address allocation request.

7. The method according to claim 1, characterized in that, The method further includes: When a new hardware presence signal is received through the first parallel port, it is determined that the address allocation request has been received through the first parallel port.

8. An electronic device, characterized in that, As the main device, the electronic device includes: Parallel port, used to connect to slave devices; Memory, which stores computer-readable instructions; and The processor executes computer-readable instructions stored in the memory to implement the address allocation method as described in any one of claims 1 to 7.

9. A multi-device system, characterized in that, It includes multiple electronic devices; among the multiple electronic devices, there are master devices and slave devices; The master device is connected to the slave device via a parallel port; the slave device is connected to the master device or other slave devices via a parallel port. The master device performs the address allocation method as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-readable instructions that are executed by a processor in an electronic device to implement the address allocation method as described in any one of claims 1 to 7.

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