Display panel, driving method and display device

Abstract

This invention discloses a display panel, driving method, and display device, relating to the field of display technology. The display panel includes a pixel driving circuit and scan lines and light-emitting control lines connected to the pixel driving circuit. The pixel driving circuit includes a driving transistor, a first reset module, and a light-emitting element. The output terminal of the first reset module is connected to the gate of the driving transistor, and the output terminal of the driving transistor is electrically connected to the light-emitting element. The input terminal of the first reset module is connected to either the scan line or the light-emitting control line. The scan signal provided by the scan line, or the light-emitting control signal provided by the light-emitting control line, is multiplexed into a first reset signal provided by the first reset module to the gate of the driving transistor. This invention multiplexes the scan signal or the light-emitting control signal into a first reset signal, eliminating the need for additional reset lines and saving wiring space. In high-density display panels, it avoids the problems of small trace spacing, leakage current, and crosstalk caused by excessive traces.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more specifically, to a display panel, a driving method, and a display device. Background Technology

[0002] From the CRT (Cathode Ray Tube) era to the LCD (Liquid Crystal Display) era, and now to the OLED (Organic Light-Emitting Diode) and LED display era, the display industry has undergone decades of rapid development. The display industry is now inextricably linked to our lives; from traditional mobile phones, tablets, televisions, and PCs to today's smart wearable devices, VR, and automotive displays, all electronic devices rely heavily on display technology.

[0003] In related technologies, for display panels of the same size, higher resolution requires more pixels and pixel driving circuits. Since the display area is fixed, the size of the pixel driving circuit needs to be further reduced. The numerous components in the pixel driving circuit further reduce the space available for wiring. Overly compact wiring can lead to problems such as leakage and crosstalk. Summary of the Invention

[0004] In view of this, the present invention provides a display panel, a driving method, and a display device, which can reduce the number of wires.

[0005] In a first aspect, the present invention provides a display panel, including a pixel driving circuit and scan lines and light emission control lines connected to the pixel driving circuit;

[0006] The pixel driving circuit includes a driving transistor, a first reset module, and a light-emitting element. The output terminal of the first reset module is connected to the gate of the driving transistor, and the output terminal of the driving transistor is electrically connected to the light-emitting element.

[0007] The input terminal of the first reset module is connected to the scan line or the light emission control line; the scan signal provided by the scan line, or the light emission control signal provided by the light emission control line, is multiplexed into a first reset signal provided by the first reset module to the gate of the driving transistor.

[0008] In a second aspect, the present invention provides a driving method for driving the pixel driving circuit provided in the first aspect of the present invention. The pixel driving circuit includes: a driving transistor, a power supply voltage writing module, a data writing module, a compensation module, a light emission control module, a first reset module, a second reset module, and a light emission element;

[0009] The driving method includes at least: a reset phase, a data writing phase, and a light emission phase;

[0010] During the reset phase, the first reset module and the second reset module are turned on; the first reset module transmits a first reset signal to the gate of the driving transistor to reset the gate of the driving transistor; the second reset module transmits a second reset signal to the anode of the light-emitting element to reset the anode of the light-emitting element.

[0011] During the data writing phase, the data writing module and the compensation module are turned on; the data writing module transmits the data signal provided by the data signal terminal to the gate of the driving transistor, and the compensation module performs threshold compensation on the driving transistor;

[0012] During the light-emitting stage, the power supply voltage writing module and the light-emitting control module are turned on; the power supply voltage writing module transmits the first voltage signal provided by the first power signal line to the driving transistor, driving the driving transistor to form a current that is transmitted to the light-emitting element.

[0013] Thirdly, the present invention provides a display device including the display panel provided in the first aspect.

[0014] Compared with the prior art, the display panel, driving method, and display device provided by the present invention achieve at least the following beneficial effects:

[0015] The embodiments provided by this invention electrically connect the input terminal of the first reset signal module to the scan line or the light emission control line, and the output terminal to the gate of the driving transistor. The scan signal provided by the scan line or the light emission control signal provided by the light emission control line is multiplexed into a first reset signal, which is transmitted to the gate of the driving transistor through the first reset module to reset the gate of the driving transistor. Multiplexing the scan signal or the light emission control signal into a first reset signal eliminates the need for additional reset lines, saving wiring space. In high-density display panels, this avoids the problems of small trace spacing, leakage current, and crosstalk caused by excessive traces.

[0016] Of course, any product implementing this invention does not necessarily need to achieve all of the technical effects described above at the same time.

[0017] Other features and advantages of the invention will become clear from the following detailed description of exemplary embodiments of the invention with reference to the accompanying drawings. Attached Figure Description

[0018] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments of the invention and, together with their description, serve to explain the principles of the invention.

[0019] Figure 1 This is a schematic diagram of the circuit structure of a display panel provided in an embodiment of the present invention;

[0020] Figure 2 This is a schematic diagram of a pixel driving circuit provided in an embodiment of the present invention;

[0021] Figure 3 This is a schematic diagram of another pixel driving circuit provided in an embodiment of the present invention;

[0022] Figure 4 This is a schematic diagram of another pixel driving circuit provided in an embodiment of the present invention;

[0023] Figure 5 This is a schematic diagram of another pixel driving circuit provided in an embodiment of the present invention;

[0024] Figure 6 A flowchart of a driving method provided in an embodiment of the present invention;

[0025] Figure 7 for Figure 5 The timing diagram of the pixel driving circuit is shown.

[0026] Figure 8 This is a schematic diagram of another pixel driving circuit provided in an embodiment of the present invention;

[0027] Figure 9 for Figure 8 The timing diagram of the pixel driving circuit is shown.

[0028] Figure 10 This is a schematic diagram of another pixel driving circuit provided in an embodiment of the present invention;

[0029] Figure 11 for Figure 10 The timing diagram of the pixel driving circuit is shown.

[0030] Figure 12 This is a schematic diagram of another pixel driving circuit provided in an embodiment of the present invention;

[0031] Figure 13 This is a schematic diagram of another pixel driving circuit provided in an embodiment of the present invention;

[0032] Figure 14 for Figure 13 The timing diagram of the pixel driving circuit is shown.

[0033] Figure 15 This is a schematic diagram of another pixel driving circuit provided in an embodiment of the present invention;

[0034] Figure 16 This is a schematic diagram of another pixel driving circuit provided in an embodiment of the present invention;

[0035] Figure 17 for Figure 16 The timing diagram of the pixel driving circuit is shown.

[0036] Figure 18 This is another timing diagram of the pixel driving circuit provided by the present invention;

[0037] Figure 19 This is a top view of a display device provided in an embodiment of the present invention. Detailed Implementation

[0038] Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that, unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps set forth in these embodiments do not limit the scope of the invention.

[0039] The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit the invention or its application or use.

[0040] Techniques, methods, and equipment known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and equipment should be considered part of the specification.

[0041] In all the examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not as limitations. Therefore, other examples of exemplary embodiments may have different values.

[0042] It should be noted that similar labels and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be discussed further in subsequent figures.

[0043] In related technologies, for display panels of the same size, higher resolution requires more pixels and pixel driving circuits. Since the display area is fixed, the size of the pixel driving circuit needs to be further reduced. The numerous components in the pixel driving circuit further reduce the space available for wiring. Overly compact wiring can lead to problems such as leakage and crosstalk.

[0044] To address the aforementioned technical problems, embodiments of the present invention provide a display panel, as shown below. Figure 1 and Figure 2 As shown, where, Figure 1 This is a schematic diagram of the circuit structure of a display panel provided in an embodiment of the present invention; Figure 2This is a schematic diagram of a pixel driving circuit provided in an embodiment of the present invention. A display panel 100 includes at least: a pixel driving circuit 200 and a scan line Scan and an emission control line Emit connected to the pixel driving circuit 200;

[0045] The pixel driving circuit 200 includes a driving transistor M0, a first reset module 10, and a light-emitting element D. The output terminal of the first reset module 10 is connected to the gate of the driving transistor M0, and the output terminal of the driving transistor M0 is electrically connected to the light-emitting element D.

[0046] The input terminal of the first reset module 10 is connected to either the scan line Scan or the light emission control line Emit; the scan signal provided by the scan line Scan, or the light emission control signal provided by the light emission control line Emit, is multiplexed into a first reset signal provided by the first reset module 10 to the gate of the driving transistor M0.

[0047] Understandably, referring to Figure 1 As shown, the display panel 100 includes multiple sub-pixels arranged in an array. It also includes a scan driver, a power supply unit, and a data driver. The scan driver provides drive signals to the sub-pixels via multiple drive signal lines, such as the scan signal line Scan and the emissive control line Emit. The power supply unit provides power signals to the sub-pixels via power signal lines, such as the first power signal PVDD and the second power signal PVEE. The data driver provides data signals to the sub-pixels via the data signal line Vdata.

[0048] Reference Figure 2 As shown, each sub-pixel includes a pixel driving circuit 200. The pixel driving circuit 200 includes at least a driving transistor M0 and a light-emitting element D. A first power signal line PVDD, the driving transistor M0, the light-emitting element D, and a second power signal line PVEE are connected in series. The voltage difference between the first power signal provided by the first power signal line PVDD and the second power signal provided by the second power signal line PVEE drives the driving transistor M0 to generate a driving current, which is then transmitted to the light-emitting element D. The light-emitting element D emits light under the action of the driving current.

[0049] Furthermore, the pixel driving circuit 200 also includes a first reset module 10. The output terminal of the first reset module 10 is connected to the gate of the driving transistor M0. The first reset signal output by the first reset module 10 can reset the gate of the driving transistor M0, clearing the residual voltage of the gate of the driving transistor M0 in the previous light emission, so that the current light emission can be performed according to the preset voltage, thereby improving the display accuracy.

[0050] Furthermore, the display panel 100 includes a scan line (Scan) and an emission control line (Emit). The input terminal of the first reset module 10 is electrically connected to either the scan line (Scan) or the emission control line (Emit). The scan signal provided by the scan line (Scan) or the emission control signal provided by the emission control line (Emit) is multiplexed into a first reset signal.

[0051] It should be noted that the scan signal line provided by the Scan line or the light emission control signal provided by the Emit line are multiplexed as the first reset signal. The first reset signal needs to be set according to the type of the driving transistor M0. For example, when the driving transistor M0 is a P-type transistor, the first reset signal is a low-level signal. That is, when the first reset module 10 is turned on, and the scan signal line provided by the Scan line or the light emission control signal provided by the Emit line is a low-level signal, the gate of the driving transistor M0 is reset. When the driving transistor M0 is an N-type transistor, the first reset signal is a high-level signal. That is, when the first reset module 10 is turned on, and the scan signal line provided by the Scan line or the light emission control signal provided by the Emit line is a high-level signal, the gate of the driving transistor M0 is reset.

[0052] In the embodiments provided by this invention, the input terminal of the first reset signal module 10 is electrically connected to the scan line Scan or the light emission control line Emit, and the output terminal is electrically connected to the gate of the driving transistor M0. The scan signal provided by the scan line Scan or the light emission control signal provided by the light emission control line Emit is multiplexed into a first reset signal, which is transmitted to the gate of the driving transistor M0 through the first reset module 10 to reset the gate of the driving transistor M0. Multiplexing the scan signal or the light emission control signal into a first reset signal eliminates the need for additional reset lines, saving wiring space. In high-density display panels, this avoids the problems of small trace spacing, leakage current, and crosstalk caused by excessive traces.

[0053] In one optional embodiment provided by the present invention, reference continues to... Figure 2 As shown, the pixel driving circuit 200 also includes a second reset module 20, the output terminal of which is connected to the anode of the light-emitting element D;

[0054] The input terminal of the second reset module 20 is connected to either the scan line Scan or the light emission control line Emit; the scan signal provided by the scan line Scan, or the light emission control signal provided by the light emission control line Emit, is multiplexed into a second reset signal provided by the second reset module 20 to the anode of the light emission element D.

[0055] It is understood that the pixel driving circuit 200 also includes a second reset module 20. The output terminal of the second reset module 20 is electrically connected to the anode of the light-emitting element D. The second reset signal output by the second reset module 20 can reset the anode of the light-emitting element D, clearing the residual voltage of the anode of the light-emitting element D in the previous light emission, so that the light emission can be performed according to the preset voltage in this light emission, thereby improving the display accuracy.

[0056] Furthermore, the input terminal of the second reset module 20 is connected to either the scan line Scan or the light emission control line Emit. The scan signal provided by the scan line Scan or the light emission control signal provided by the light emission control line Emit is multiplexed into the second reset signal.

[0057] In the embodiments provided by this invention, the input terminal of the second reset signal module 20 is electrically connected to the scan line Scan or the light emission control line Emit, and the output terminal is electrically connected to the anode of the light-emitting element D. The scan signal provided by the scan line Scan or the light emission control signal provided by the light emission control line Emit is multiplexed into a second reset signal, which is transmitted to the anode of the light-emitting element D through the second reset module 20 to reset the anode of the light-emitting element D. Multiplexing the scan signal or the light emission control signal into a second reset signal eliminates the need for additional reset lines, saving wiring space. In high-density display panels, this avoids the problems of small trace spacing, leakage current, and crosstalk caused by excessive traces.

[0058] In one optional embodiment provided by the present invention, reference continues to... Figure 1 As shown, the scan line Scan includes a first scan line Scan1 and a second scan line Scan2;

[0059] The first scan line Scan1 provides the first scan signal, and the second scan line Scan2 provides the second scan signal.

[0060] Understandably, the scan driver of the display panel 100 provides scan signals to the pixel driving circuit 200 through scan lines Scan. Specifically, the scan lines Scan include at least a first scan line Scan1 and a second scan line Scan2. The first scan line Scan1 and the second scan line Scan2 provide a first scan signal and a second scan signal, respectively.

[0061] Reference Figure 1 As shown, in one optional embodiment, the scan driver in the display panel 100 provides a first scan line Scan1 and a second scan line Scan2 to each row of sub-pixels. The pixel driving circuit 200 of the sub-pixels in the same row obtains a first scan signal and a second scan signal from the first scan line Scan1 and the second scan line Scan2 of each row, respectively.

[0062] In another alternative embodiment, the second scan line Scan2 in the nth row is multiplexed as the first scan line Scan1 in the (n+1)th row pixel driving circuit 200, where n is an integer and n≥1. In other words, scan lines Scan can be multiplexed between adjacent rows. For example, one side of the first row pixel driving circuit 200 is provided with a first scan line Scan1 and a second scan line Scan2 extending along the row direction. The first scan line Scan and the second scan line Scan2 provide a first scan signal and a second scan signal to the first row pixel driving circuit 200, respectively. A second scan line Scan2 extending along the row direction is provided between the first row pixel driving circuit 200 and the second row pixel driving circuit 200, providing a second scan line for the second row pixel driving circuit 200. Simultaneously, the second scan line Scan2 on one side of the first row pixel circuit 200 is multiplexed as the first scan line Scan1 of the second row pixel driving circuit 200.

[0063] In the embodiments provided by this invention, the scan line Scan is further disclosed to include a first scan line Scan1 and a second scan line Scan2, and two arrangement methods for the first scan line Scan1 and the second scan line Scan2 are disclosed. When the data writing module 30 in the pixel driving circuit 200 of the nth row is turned on and performs data writing under the control of the second scan signal, the second scan signal simultaneously controls the first reset module 10 in the pixel driving circuit 200 of the (n+1)th row to be turned on, resetting the gate of the driving transistor M0. This not only reduces wiring, saves wiring space, and reduces crosstalk and leakage current between adjacent traces, but also makes full use of signals, reduces display response time, and improves display effect.

[0064] In one optional embodiment provided by the present invention, reference continues to... Figure 2 As shown, the display panel 100 also includes a power supply voltage writing module 30. The power supply voltage writing module 30 is connected in series between the driving transistor M0 and the first power signal line PVDD. The control terminal of the power supply voltage writing module 30 is connected to the light emission control line Emit. The input terminal of the power supply voltage writing module 30 is connected to the first power signal line PVDD. The output terminal of the power supply voltage writing module 30 is connected to the input terminal of the driving transistor M0.

[0065] The data writing module 40 is connected in series between the driving transistor M0 and the data signal line Vdata. The control terminal of the data writing module 40 is connected to the second scan line Scan2, the input terminal of the data writing module 40 is connected to the data signal line Vdata, and the output terminal of the data writing module 40 is connected to the input terminal of the driving transistor M0.

[0066] The compensation module 50 is connected in series between the gate of the driving transistor M0 and the output terminal of the driving transistor M0. The control terminal of the compensation module 50 is connected to the second scan line Scan2, the input terminal of the compensation module 50 is connected to the output terminal of the driving transistor M0, and the output terminal of the compensation module 50 is connected to the gate of the driving transistor M0.

[0067] The light-emitting control module 60 is connected in series between the driving transistor M0 and the light-emitting element D. The control terminal of the light-emitting control module 60 is connected to the light-emitting control line Emit, the input terminal of the light-emitting control module 60 is connected to the output terminal of the driving transistor M0, and the output terminal of the light-emitting control module 60 is connected to the anode of the light-emitting element D.

[0068] Capacitor C, with its first terminal connected to the first power signal line PVDD, and its second terminal connected to the gate of the driving transistor M0.

[0069] Understandably, the power supply voltage writing module 30 is connected in series between the driving transistor M0 and the first power signal line PVDD. The control terminal of the power supply voltage writing module 30 is connected to the light emission control line Emit. During the light emission stage, the power supply voltage writing module 30 is turned on under the control of the light emission control signal provided by the light emission control line Emit, transmitting the first voltage signal provided by the first power signal line PVDD to the input terminal of the driving transistor M0.

[0070] Furthermore, the data writing module 40 is connected in series between the driving transistor M0 and the data signal line Vdata. The control terminal of the data writing module 40 is connected to the second scan line Scan2. During the data writing phase, the data writing module 40 is turned on under the control of the second scan signal provided by the second scan line Scan2, and transmits the data signal provided by the data signal line Vdata to the first node N1 through the driving transistor M0.

[0071] Furthermore, the compensation module 50 is connected in series between the gate and output terminal of the driving transistor M0. The control terminal of the compensation module 50 is connected to the second scan line Scan2. During the data writing phase, the compensation module 50 is turned on under the control of the second scan signal provided by the second scan line Scan2 to detect and compensate for the deviation of the threshold voltage of the driving transistor M0.

[0072] Furthermore, the light-emitting control module 60 is connected in series between the driving transistor M0 and the light-emitting element D. The control terminal of the light-emitting control module 60 is connected to the light-emitting control line Emit. During the light-emitting stage, the light-emitting control module 60 is turned on under the control of the light-emitting control signal provided by the light-emitting control line Emit, transmitting the driving current generated by the driving transistor M0 to the anode of the light-emitting element D, causing the light-emitting element D to emit light.

[0073] Furthermore, capacitor C is connected in series between the first power supply signal line PVDD and the gate of the driving transistor M0. Capacitor C is used to maintain the potential of the gate of the driving transistor M0.

[0074] In the embodiments provided by the present invention, during the data writing stage, the data writing module transmits the data signal provided by the data line Vdata to the input terminal of the driving transistor M0, and the compensation module 50 compensates for the deviation of the threshold voltage of the driving transistor M0; then, the capacitor C maintains the potential of the gate of the driving transistor M0; during the light emission stage, the power supply voltage writing module 40 and the light emission control module 60 are turned on, and the first voltage signal provided by the first power supply signal line is transmitted to the input terminal of the driving transistor M0, causing the driving transistor M0 to generate a driving current, which is transmitted to the light emission element D through the light emission control module 60 to realize the display function.

[0075] In one optional embodiment provided by the present invention, refer to Figure 3 As shown, Figure 3 This is a schematic diagram of another pixel driving circuit provided in an embodiment of the present invention. The first reset module 10 includes a first transistor M1, the gate of the first transistor M1 is connected to the first scan line Scan1, the first electrode of the first transistor M1 is connected to the first scan line Scan1, or the second scan line Scan2, or the light emission control line Emit, and the second electrode of the first transistor M1 is connected to the gate of the driving transistor M0.

[0076] It is understood that the first reset module 10 includes a first transistor M1. The gate of the first transistor M1 is the control terminal of the first reset module 10; the first electrode of the first transistor M1 is the input terminal of the first reset module 10; and the second electrode of the first transistor M1 is the output terminal of the first reset module 10. Therefore, the gate of the first transistor M1 is electrically connected to the first scan line Scan1 in the scan line Scan, and the first scan signal provided by the first scan line Scan1 controls the on / off state of the first transistor M1.

[0077] Furthermore, when the first transistor M1 is turned on, the first scan signal, or the second scan signal, or the light emission control signal provided by the first scan line Scan1, or the second scan line Scan2, or the light emission control signal connected to the first terminal of the first transistor M1 is multiplexed into a first reset signal and transmitted to the gate of the driving transistor M0 through the first transistor M1 to reset the gate of the driving transistor M0, clearing the residual voltage on the gate of the driving transistor M0 in the previous light emission, so that the current light emission can emit light according to the preset voltage, thereby improving the display accuracy.

[0078] It should be noted that the first transistor M1 can be either a P-type transistor or an N-type transistor. When the first transistor M1 is a P-type transistor, it is turned on when its gate is at a low potential. That is, when the first scan signal Scan1 provides a low-level signal, the first transistor M1 is turned on. When the first transistor M1 is an N-type transistor, it is turned on when its gate is at a high potential. That is, when the first scan signal Scan1 provides a high-level signal, the first transistor M1 is turned on. (Appendix) Figure 3 In this illustration, the first transistor M1 is shown as a P-type transistor, but this does not constitute a limitation on the type of the first transistor M1. The first transistor M1 can be either a P-type transistor or an N-type transistor.

[0079] In the embodiments provided by this invention, the first terminal of the first transistor M1 is electrically connected to the first scan line Scan1, or the second scan line Scan2, or the light emission control line Emit; the second terminal is electrically connected to the gate of the driving transistor M0; and the gate is electrically connected to the first scan line Scan1. The first transistor M1 is turned on / off under the control of the first scan signal provided by the first scan line Scan1 at the gate. When the first transistor M1 is turned on, the first scan signal provided by the first scan line Scan1, or the second scan signal provided by the second scan line Scan2, or the light emission control signal provided by the light emission control line Emit is multiplexed into a first reset signal, which is transmitted to the gate of the driving transistor M0 through the first transistor M1 to reset the gate of the driving transistor M0. Multiplexing the first scan signal, or the second scan signal, or the light emission control signal into a first reset signal eliminates the need for additional reset lines, saving wiring space. In high-density display panels, this avoids the problems of leakage and crosstalk between traces caused by excessive wiring and small trace spacing. Meanwhile, the first reset module 10 is constructed by the first transistor M1. The on / off performance of the first transistor M1 can be controlled by the potential of the gate of the first transistor M1, thereby realizing the control of the first reset module 10 and simplifying the process.

[0080] In one optional embodiment provided by the present invention, reference continues to... Figure 3 As shown, the second reset module 20 includes a second transistor M2, the gate of the second transistor M2 is connected to the first scan line Scan1, the first electrode of the second transistor is connected to the first scan line Scan1, or the second scan line Scan2, or the light emission control line Emit, and the second electrode of the second transistor M2 is connected to the anode of the light emission element D.

[0081] It is understood that the second reset module 20 includes a second transistor M2. The gate of the second transistor M2 is the control terminal of the second reset module 20; the first electrode of the second transistor M2 is the input terminal of the second reset module 20; and the second electrode of the second transistor M2 is the output terminal of the second reset module 20. Therefore, the gate of the second transistor M2 is electrically connected to the first scan line Scan1 in the scan line Scan, and the first scan signal provided by the first scan line Scan1 controls the on / off state of the second transistor M2.

[0082] Furthermore, when the second transistor M2 is turned on, the first scan signal, second scan signal, or light emission control signal provided by the first scan line Scan1, the second scan line Scan2, or the light emission control line Emit connected to the first electrode of the second transistor M2 is multiplexed into a second reset signal, which is transmitted to the anode of the light-emitting element D through the second transistor M2 to reset the anode of the light-emitting element D, clearing the residual voltage of the anode of the light-emitting element D in the previous light emission, so that the current light emission can emit light according to the preset voltage, thereby improving the display accuracy.

[0083] It should be noted that the second transistor M2 can be either a P-type transistor or an N-type transistor. When the second transistor M2 is a P-type transistor, it is turned on when its gate is at a low potential. That is, when the first scan signal Scan1 provides a low-level signal, the second transistor M2 is turned on. When the second transistor M2 is an N-type transistor, it is turned on when its gate is at a high potential. That is, when the first scan signal Scan1 provides a high-level signal, the second transistor M2 is turned on. (Appendix) Figure 5 In this illustration, the second transistor M2 is shown as a P-type transistor, but this does not limit the type of the second transistor M2. The second transistor M2 can be either a P-type transistor or an N-type transistor.

[0084] In the embodiments provided by this invention, the first terminal of the second transistor M2 is electrically connected to the first scan line Scan1, the second scan line Scan2, or the light emission control line Emit; the second terminal is electrically connected to the anode of the light-emitting element D; and the gate is electrically connected to the first scan line Scan1. The second transistor M2 is turned on / off under the control of the first scan signal provided by the first scan line Scan1 at the gate. When the second transistor M2 is turned on, the first scan signal provided by the first scan line Scan1, the second scan signal provided by the second scan line Scan2, or the light emission control signal provided by the light emission control line Emit is multiplexed into a second reset signal, which is transmitted to the anode of the light-emitting element D through the second transistor M2 to reset the anode of the light-emitting element D. Multiplexing the second scan signal or the light emission control signal into a second reset signal eliminates the need for additional reset lines, saving wiring space. In high-density display panels, this avoids the problems of small trace spacing, leakage current, and crosstalk caused by excessive traces. Meanwhile, the second reset module 20 is constructed by the second transistor M2. The on / off performance of the second transistor M2 can be controlled by the potential of the gate of the second transistor M2, thereby realizing the control of the second reset module 20 and simplifying the process.

[0085] In one optional embodiment provided by the present invention, refer to Figure 4 As shown, Figure 4 This is a schematic diagram of another pixel driving circuit provided in an embodiment of the present invention. The power supply voltage writing module 30 includes a third transistor M3, the gate of the third transistor M3 is connected to the light emission control line Emit, the first terminal of the third transistor M3 is connected to the first power supply signal line PVDD, and the second terminal of the third transistor M3 is connected to the input terminal of the driving transistor M0;

[0086] The data writing module 40 includes a fourth transistor M4, the gate of the fourth transistor M4 is connected to the second scan line Scan2, the first terminal of the fourth transistor M4 is connected to the data signal line Vdata, and the second terminal of the fourth transistor M4 is connected to the input terminal of the driving transistor M0.

[0087] The compensation module 50 includes a fifth transistor M5, the gate of the fifth transistor M5 is connected to the second scan line Scan2, the first terminal of the fifth transistor M5 is connected to the output terminal of the driving transistor M0, and the second terminal of the fifth transistor M5 is connected to the gate of the driving transistor M0.

[0088] The light-emitting control module 60 includes a sixth transistor M6, the gate of the sixth transistor M6 is connected to the light-emitting control line Emit, the first terminal of the sixth transistor M6 is connected to the output terminal of the driving transistor M0, and the second terminal of the sixth transistor M0 is connected to the anode of the light-emitting element D.

[0089] It is understood that the power supply voltage writing module 30 includes a third transistor M3. The gate of the third transistor M3 is the control terminal of the power supply voltage writing module 30, the first terminal is the input terminal of the power supply voltage writing module 30, and the second terminal is the output terminal of the power supply voltage writing module 30. The gate of the third transistor M3 is connected to the light emission control signal line Emit. The light emission control signal provided by the light emission control signal line Emit controls the conduction / cutoff of the third transistor M3.

[0090] Furthermore, the data writing module 40 includes a fourth transistor M4. The gate of the fourth transistor M4 is the control terminal of the data writing module 40; the first electrode of the fourth transistor M4 is the input terminal of the data writing module 40; and the second electrode of the fourth transistor M4 is the output terminal of the data writing module 40. The gate of the fourth transistor M4 is electrically connected to the second scan line Scan2, and the second scan signal provided by the second scan line Scan2 controls the on / off state of the fourth transistor M4.

[0091] Furthermore, the compensation module 50 includes a fifth transistor M5. The gate of the fifth transistor M5 is the control terminal of the compensation module 50, the first terminal is the input terminal of the compensation module 50, and the second terminal is the output terminal of the compensation module 50. The gate of the fifth transistor M5 is connected to the second scan line Scan2, and the second scan signal provided by the second scan line Scan2 controls the on / off state of the fifth transistor M5.

[0092] Furthermore, the light-emitting control module 60 includes a sixth transistor M6. The gate of the sixth transistor M6 is the control terminal of the light-emitting control module 60, the first electrode is the input terminal of the light-emitting control module 60, and the second electrode is the output terminal of the light-emitting control module 60. The gate of the sixth transistor M6 is connected to the light-emitting control signal line Emit, and the light-emitting control signal provided by the light-emitting control signal line Emit controls the conduction / cutoff of the sixth transistor M6.

[0093] In the embodiments provided by this invention, the power supply voltage writing module 30 includes a third transistor M3, the data writing module 40 includes a fourth transistor M4, the compensation module 50 includes a fifth transistor M5, and the light emission control module 60 includes a sixth transistor M6. The display panel 100 can turn the functional modules on or off by switching the transistors on and off. The gates of the third transistor M3, the fourth transistor M4, the fifth transistor M5, and the sixth transistor M6 are electrically connected to the light emission control line Emit or the second scan line Scan2, respectively. The power supply voltage writing module 30, the data writing module 40, the compensation module 50, or the light emission control module 60 can be controlled to turn on or off using the light emission control signal provided by the light emission control line Emit or the high-level / low-level signal at different times in the timing sequence of the second scan signal provided by the second scan line Scan2.

[0094] In one optional embodiment provided by the present invention, refer to Figures 5 to 7 As shown, Figure 5 This is a schematic diagram of another pixel driving circuit provided in an embodiment of the present invention; Figure 6 A flowchart of a driving method provided in an embodiment of the present invention; Figure 7 for Figure 5 The timing diagram of the pixel driving circuit is shown. Driving transistor M0, first transistor M1, second transistor M2, third transistor M3, and sixth transistor M6 are P-type transistors.

[0095] The fourth transistor M4 and the fifth transistor M5 are N-type transistors;

[0096] The first terminal of the first transistor M1 is connected to the second scan line Scan2; the second scan signal provided by the second scan line Scan2 is multiplexed into a first reset signal Vref1 provided by the first transistor M1 to the gate of the driving transistor M0;

[0097] The first terminal of the second transistor M2 is connected to the second scan line Scan2; the second scan signal provided by the second scan line Scan2 is multiplexed into a second reset signal Vref2 provided by the second transistor M2 to the anode of the light-emitting element D.

[0098] It is understood that P-type transistors conduct when the gate is at a low level and are cut off when the gate is at a high level. N-type transistors conduct when the gate is at a high level and are cut off when the gate is at a low level. Therefore, in the embodiments provided by this invention, the timing design of the pixel driving circuit 200 is performed by combining the types of each transistor in the pixel driving circuit 200. Specifically, the pixel driving circuit 200 includes at least three stages: a reset stage T1, a data writing stage T2, and a light-emitting stage T3. In the reset stage T1, the pixel driving circuit 200 resets the gate of the driving transistor M0 and the anode of the light-emitting element D; in the data writing stage T2, the pixel driving circuit 200 writes a data signal to the gate of the driving transistor M0; in the light-emitting stage, the light-emitting element D in the pixel driving circuit 200 conducts and emits light.

[0099] specifically refer to Figure 7As shown, during the reset phase T1, the first scan signal provided by the first scan line Scan1 is a low-level signal, and the second scan signal provided by the second scan line Scan2 is a low-level signal. Since the first transistor M1 and the second transistor M2 are P-type transistors, during the reset phase T1, the first transistor M1 and the second transistor M2 are turned on, transmitting the low-level signal provided by the second scan line Scan2 to the gate of the driving transistor M0 and the anode of the light-emitting element D. Because the driving transistor M0 is a P-type transistor, its gate is reset when its potential is low, and the anode of the light-emitting element D is also reset when its potential is low.

[0100] During the data writing phase T2, the second scan signal provided by the second scan line Scan2 is a high-level signal. Since the fourth transistor M4 and the fifth transistor M5 are N-type transistors, during the data writing phase T2, the fourth transistor M4 and the fifth transistor M5 are turned on. The data signal at the data signal terminal Vdata is transmitted to the gate of the driving transistor M0 through the fourth transistor M4, and the fifth transistor M5 performs detection and threshold compensation on the driving transistor M0.

[0101] During the light-emitting stage T3, the light-emitting control signal provided by the Emit control line is a low-level signal. Since the third transistor M3 and the sixth transistor M6 are P-type transistors, they are turned on during T3. The third transistor M3 transmits the first voltage signal from the first power supply signal line PVDD to the input terminal of the driving transistor M0, causing the driving transistor M0 to generate a driving current. The sixth transistor M6 then transmits this driving current to the light-emitting element D, causing the light-emitting element D to emit light.

[0102] In the embodiments provided by this invention, the gates of the first transistor M1 and the second transistor M2 are both connected to the first scan line Scan1, and the first electrodes of the first transistor M1 and the second transistor M2 are both connected to the second scan line Scan2. During the reset phase T1, the first transistor M1 and the second transistor M2 are turned on by the low-level signal provided by the first scan line Scan1 connected to their gates, transmitting the low-level signal provided by the second scan line Scan2 to the gate of the driving transistor M0 and the anode of the light-emitting element D respectively for reset. In the embodiments provided by this invention, by multiplexing the second scan signal provided by the second scan line Scan2 into a first reset signal and a second reset signal during the reset phase T1, a separate reset signal line is avoided, saving wiring space in the display panel 100, increasing the spacing between traces, and preventing crosstalk between adjacent traces.

[0103] In one optional embodiment provided by the present invention, refer to Figure 6 , Figure 8 and Figure 9 As shown, where, Figure 8 This is a schematic diagram of another pixel driving circuit provided in an embodiment of the present invention;

[0104] Figure 9 for Figure 8 The timing diagram of the pixel driving circuit is shown. Driving transistor M0, first transistor M1, second transistor M2, fourth transistor M4, and fifth transistor M5 are P-type transistors.

[0105] The third transistor M3 and the sixth transistor M6 are N-type transistors;

[0106] The first terminal of the first transistor M1 is connected to the light emission control line Emit; the light emission control signal provided by the light emission control line Emit is multiplexed into a first reset signal Vref1 provided by the first transistor M1 to the gate of the driving transistor M0;

[0107] The first terminal of the second transistor M2 is connected to the light-emitting control line Emit; the light-emitting control signal provided by the light-emitting control line Emit is multiplexed into a second reset signal Vref2 provided by the second transistor M2 to the anode of the light-emitting element D.

[0108] Understandably, during the reset phase T1, the first scan signal provided by the first scan line Scan1 is a low-level signal, and the light emission control signal provided by the light emission control line Emit is a low-level signal. Since the first transistor M1 and the second transistor M2 are P-type transistors, during the reset phase T1, the first transistor M1 and the second transistor M2 are turned on, transmitting the low-level signal provided by the light emission control line Emit to the gate of the driving transistor M0 and the anode of the light-emitting element D. Because the driving transistor M0 is a P-type transistor, its gate is reset when its potential is low, and the anode of the light-emitting element D is also reset when its potential is low.

[0109] During the data writing phase T2, the second scan signal provided by the second scan line Scan2 is a low-level signal. Since the fourth transistor M4 and the fifth transistor M5 are P-type transistors, during the data writing phase T2, the fourth transistor M4 and the fifth transistor M5 are turned on. The data signal at the data signal terminal Vdata is transmitted to the gate of the driving transistor M0 through the fourth transistor M4, and the fifth transistor M5 performs detection and threshold compensation on the driving transistor M0.

[0110] During the light-emitting stage T3, the light-emitting control signal provided by the Emit control line is a high-level signal. Since the third transistor M3 and the sixth transistor M6 are N-type transistors, they are turned on during T3. The third transistor M3 transmits the first voltage signal from the first power supply signal line PVDD to the input terminal of the driving transistor M0, causing the driving transistor M0 to generate a driving current. The sixth transistor M6 then transmits this driving current to the light-emitting element D, causing the light-emitting element D to emit light.

[0111] In the embodiments provided by this invention, the gates of the first transistor M1 and the second transistor M2 are both connected to the first scan line Scan1, and the first electrodes of the first transistor M1 and the second transistor M2 are both connected to the light-emitting control line Emit. During the reset phase T1, the first transistor M1 and the second transistor M2 are turned on by the low-level signal provided by the first scan line Scan1 connected to their gates, transmitting the low-level signal provided by the light-emitting control line Emit to the gate of the driving transistor M0 and the anode of the light-emitting element D for reset. In the embodiments provided by this invention, by multiplexing the light-emitting control signal provided by the light-emitting control line Emit into a first reset signal and a second reset signal during the reset phase T1, a separate reset signal line is avoided, saving wiring space in the display panel 100, increasing the spacing between traces, and preventing crosstalk between adjacent traces.

[0112] In one optional embodiment provided by the present invention, refer to Figure 6 , Figure 10 and Figure 11 As shown, Figure 10 This is a schematic diagram of another pixel driving circuit provided in an embodiment of the present invention; Figure 11 for Figure 10 The timing diagram of the pixel driving circuit is shown. The third transistor M3 and the sixth transistor M6 are P-type transistors;

[0113] The driving transistor M0, the first transistor M1, the second transistor M2, the fourth transistor M4, and the fifth transistor M5 are N-type transistors;

[0114] The first terminal of the first transistor M1 is connected to the light emission control line Emit; the light emission control signal provided by the light emission control line Emit is multiplexed into a first reset signal Vref1 provided by the first transistor M1 to the gate of the driving transistor M0;

[0115] The first terminal of the second transistor M2 is connected to the second scan line Scan2; the second scan signal provided by the second scan line Scan2 is multiplexed into a second reset signal Vref2 provided by the second transistor M2 to the anode of the light-emitting element D.

[0116] Understandably, during the reset phase T1, the first scan signal provided by the first scan line Scan1 is a high-level signal, the second scan signal provided by the second scan line Scan2 is a low-level signal, and the light emission control signal provided by the light emission control line Emit is a high-level signal. Since the first transistor M1 and the second transistor M2 are N-type transistors, during the reset phase T1, both transistors are turned on. The first transistor M1 transmits the high-level signal provided by the light emission control line Emit to the gate of the driving transistor M0, and the second transistor M2 transmits the low-level signal provided by the second scan line Scan2 to the anode of the light-emitting element D. Because the driving transistor M0 is an N-type transistor, its gate is reset when its potential is high, and the anode of the light-emitting element D is reset when its potential is low.

[0117] During the data writing phase T2, the second scan signal provided by the second scan line Scan2 is a high-level signal. Since the fourth transistor M4 and the fifth transistor M5 are N-type transistors, during the data writing phase T2, the fourth transistor M4 and the fifth transistor M5 are turned on. The data signal at the data signal terminal Vdata is transmitted to the gate of the driving transistor M0 through the fourth transistor M4, and the fifth transistor M5 performs detection and threshold compensation on the driving transistor M0.

[0118] During the light-emitting stage T3, the light-emitting control signal provided by the Emit control line is a low-level signal. Since the third transistor M3 and the sixth transistor M6 are P-type transistors, they are turned on during T3. The third transistor M3 transmits the first voltage signal from the first power supply signal line PVDD to the input terminal of the driving transistor M0, causing the driving transistor M0 to generate a driving current. The sixth transistor M6 then transmits this driving current to the light-emitting element D, causing the light-emitting element D to emit light.

[0119] In the embodiments provided by this invention, the gates of the first transistor M1 and the second transistor M2 are both connected to the first scan line Scan1. The first electrode of the first transistor M1 is connected to the light emission control line Emit, and the first electrode of the second transistor M2 is connected to the second scan line Scan2. During the reset phase T1, the first transistor M1 and the second transistor M2 are turned on by the high-level signal provided by the first scan line Scan1 connected to their gates, transmitting the high-level signal provided by the light emission control line Emit and the low-level signal provided by the second scan line Scan2 to the gate of the driving transistor M0 and the anode of the light-emitting element D, respectively, for reset. In the embodiments provided by this invention, by multiplexing the light emission control signal provided by the light emission control line Emit as the first reset signal and the second scan signal provided by the second scan line Scan2 as the second reset signal during the reset phase T1, a separate reset signal line is avoided, saving wiring space in the display panel 100, increasing the spacing between traces, and preventing crosstalk between adjacent traces.

[0120] In one optional embodiment provided by the present invention, refer to Figure 6 , Figure 11 and Figure 12 As shown, Figure 12 This is a schematic diagram of another pixel driving circuit provided in an embodiment of the present invention. The third transistor M3 and the sixth transistor M6 are P-type transistors;

[0121] The driving transistor M0, the first transistor M1, the second transistor M2, the fourth transistor M4, and the fifth transistor M5 are N-type transistors;

[0122] The first terminal of the first transistor M1 is connected to the first scan line Scan1; the first scan signal provided by the first scan line Scan1 is multiplexed into a first reset signal Vref1 provided by the first transistor M1 to the gate of the driving transistor M0;

[0123] The first terminal of the second transistor M2 is connected to the second scan line Scan2; the second scan signal provided by the second scan line Scan2 is multiplexed into a second reset signal Vref2 provided by the second transistor M2 to the anode of the light-emitting element D.

[0124] Understandably, during the reset phase T1, the first scan signal provided by the first scan line Scan1 is a high-level signal, the second scan signal provided by the second scan line Scan2 is a low-level signal, and the light emission control signal provided by the light emission control line Emit is a high-level signal. Since the first transistor M1 and the second transistor M2 are N-type transistors, during the reset phase T1, both transistors are turned on. The first transistor M1 transmits the high-level signal provided by the light emission control line Emit to the gate of the driving transistor M0, and the second transistor M2 transmits the low-level signal provided by the second scan line Scan2 to the anode of the light-emitting element D. Because the driving transistor M0 is an N-type transistor, its gate is reset when its potential is high, and the anode of the light-emitting element D is reset when its potential is low.

[0125] During the data writing phase T2, the second scan signal provided by the second scan line Scan2 is a high-level signal. Since the fourth transistor M4 and the fifth transistor M5 are N-type transistors, during the data writing phase T2, the fourth transistor M4 and the fifth transistor M5 are turned on. The data signal at the data signal terminal Vdata is transmitted to the gate of the driving transistor M0 through the fourth transistor M4, and the fifth transistor M5 performs detection and threshold compensation on the driving transistor M0.

[0126] During the light-emitting stage T3, the light-emitting control signal provided by the Emit control line is a low-level signal. Since the third transistor M3 and the sixth transistor M6 are P-type transistors, they are turned on during T3. The third transistor M3 transmits the first voltage signal from the first power supply signal line PVDD to the input terminal of the driving transistor M0, causing the driving transistor M0 to generate a driving current. The sixth transistor M6 then transmits this driving current to the light-emitting element D, causing the light-emitting element D to emit light.

[0127] In the embodiments provided by this invention, the gates of the first transistor M1 and the second transistor M2 are both connected to the first scan line Scan1. The first electrode of the first transistor M1 is connected to the light-emitting control line Emit, and the first electrode of the second transistor M2 is connected to the second scan line Scan2. During the reset phase T1, the first transistor M1 and the second transistor M2 are turned on by the high-level signal provided by the first scan line Scan1 connected to their gates, transmitting the high-level signal provided by the light-emitting control line Emit and the low-level signal provided by the second scan line Scan2 to the gate of the driving transistor M0 and the anode of the light-emitting element D, respectively, for reset. In the embodiments provided by this invention, by multiplexing the first scan signal provided by the first scan line Scan1 as the first reset signal and the second scan signal provided by the second scan line Scan2 as the second reset signal during the reset phase T1, a separate reset signal line is avoided, saving wiring space in the display panel 100, increasing the spacing between traces, and preventing crosstalk between adjacent traces.

[0128] In one optional embodiment provided by the present invention, refer to Figure 6 , Figure 13 and Figure 14 As shown, Figure 13 This is a schematic diagram of another pixel driving circuit provided in an embodiment of the present invention; Figure 14 for Figure 13 The timing diagram of the pixel driving circuit is shown. Driving transistor M0, first transistor M1, second transistor M2, third transistor M3, fourth transistor M4, fifth transistor M5, and sixth transistor M6 are N-type transistors.

[0129] The first terminal of the first transistor M1 is connected to the first scan line Scan1; the first scan signal provided by the first scan line Scan1 is multiplexed into a first reset signal Vref1 provided by the first transistor M1 to the gate of the driving transistor M0;

[0130] The first terminal of the second transistor M2 is connected to the second scan line Scan2; the second scan signal provided by the second scan line Scan2 is multiplexed into a second reset signal Vref2 provided by the second transistor M2 to the anode of the light-emitting element D.

[0131] Understandably, during the reset phase T1, the first scan signal provided by the first scan line Scan1 is a high-level signal, and the second scan signal provided by the second scan line Scan2 is a low-level signal. Since the first transistor M1 and the second transistor M2 are N-type transistors, during the reset phase T1, both transistors are turned on. The first transistor M1 transmits the high-level signal provided by the first scan line Scan1 to the gate of the driving transistor M0, and the second transistor M2 transmits the low-level signal provided by the second scan line Scan2 to the anode of the light-emitting element D. Because the driving transistor M0 is an N-type transistor, its gate is reset when its potential is high, and the anode of the light-emitting element D is reset when its potential is low.

[0132] During the data writing phase T2, the second scan signal provided by the second scan line Scan2 is a high-level signal. Since the fourth transistor M4 and the fifth transistor M5 are N-type transistors, during the data writing phase T2, the fourth transistor M4 and the fifth transistor M5 are turned on. The data signal at the data signal terminal Vdata is transmitted to the gate of the driving transistor M0 through the fourth transistor M4, and the fifth transistor M5 performs detection and threshold compensation on the driving transistor M0.

[0133] During the light-emitting stage T3, the light-emitting control signal provided by the Emit control line is a high-level signal. Since the third transistor M3 and the sixth transistor M6 are N-type transistors, they are turned on during T3. The third transistor M3 transmits the first voltage signal from the first power supply signal line PVDD to the input terminal of the driving transistor M0, causing the driving transistor M0 to generate a driving current. The sixth transistor M6 then transmits this driving current to the light-emitting element D, causing the light-emitting element D to emit light.

[0134] In the embodiments provided by this invention, the gates of the first transistor M1 and the second transistor M2 are both connected to the first scan line Scan1. The first electrode of the first transistor M1 is connected to the first scan line Scan1, and the first electrode of the second transistor M2 is connected to the second scan line Scan2. During the reset phase T1, the first transistor M1 and the second transistor M2 are turned on by the high-level signal provided by the first scan line Scan1 connected to their gates, transmitting the high-level signal provided by the first scan line Scan1 and the low-level signal provided by the second scan line Scan2 to the gate of the driving transistor M0 and the anode of the light-emitting element D, respectively, for reset. In the embodiments provided by this invention, by multiplexing the first scan signal provided by the first scan line Scan1 as the first reset signal and the second scan signal provided by the second scan line Scan2 as the second reset signal during the reset phase T1, separate reset signal lines are avoided, saving wiring space in the display panel 100, increasing the spacing between traces, and preventing crosstalk between adjacent traces.

[0135] In one optional embodiment provided by the present invention, refer to Figure 6 , Figure 14 and Figure 15 As shown, Figure 15 This is a schematic diagram of another pixel driving circuit provided in an embodiment of the present invention. Driving transistor M0, first transistor M1, second transistor M2, third transistor M3, fourth transistor M4, fifth transistor M5, and sixth transistor M6 are N-type transistors.

[0136] The first terminal of the first transistor M1 is connected to the first scan line Scan1; the first scan signal provided by the first scan line Scan1 is multiplexed into a first reset signal Vref1 provided by the first transistor M1 to the gate of the driving transistor M0;

[0137] The first terminal of the second transistor M2 is connected to the light-emitting control line Emit; the light-emitting control signal provided by the light-emitting control line Emit is multiplexed into a second reset signal Vref2 provided by the second transistor M2 to the anode of the light-emitting element D.

[0138] Understandably, during the reset phase T1, the first scan signal provided by the first scan line Scan1 is a high-level signal, and the light-emitting control signal provided by the light-emitting control line Emit is a low-level signal. Since the first transistor M1 and the second transistor M2 are N-type transistors, during the reset phase T1, both transistors are turned on. The first transistor M1 transmits the high-level signal provided by the first scan line Scan1 to the gate of the driving transistor M0, and the second transistor M2 transmits the low-level signal provided by the second scan line Scan2 to the anode of the light-emitting element D. Because the driving transistor M0 is an N-type transistor, its gate is reset when its potential is high, and the anode of the light-emitting element D is reset when its potential is low.

[0139] During the data writing phase T2, the second scan signal provided by the second scan line Scan2 is a high-level signal. Since the fourth transistor M4 and the fifth transistor M5 are N-type transistors, during the data writing phase T2, the fourth transistor M4 and the fifth transistor M5 are turned on. The data signal at the data signal terminal Vdata is transmitted to the gate of the driving transistor M0 through the fourth transistor M4, and the fifth transistor M5 performs detection and threshold compensation on the driving transistor M0.

[0140] During the light-emitting stage T3, the light-emitting control signal provided by the Emit control line is a low-level signal. Since the third transistor M3 and the sixth transistor M6 are P-type transistors, they are turned on during T3. The third transistor M3 transmits the first voltage signal from the first power supply signal line PVDD to the input terminal of the driving transistor M0, causing the driving transistor M0 to generate a driving current. The sixth transistor M6 then transmits this driving current to the light-emitting element D, causing the light-emitting element D to emit light.

[0141] In the embodiments provided by this invention, the gates of the first transistor M1 and the second transistor M2 are both connected to the first scan line Scan1. The first electrode of the first transistor M1 is connected to the first scan line Scan1, and the first electrode of the second transistor M2 is connected to the light emission control line Emit. During the reset phase T1, the first transistor M1 and the second transistor M2 are turned on by the high-level signal provided by the first scan line Scan1 connected to their gates, transmitting the high-level signal provided by the first scan line Scan1 and the low-level signal provided by the light emission control line Emit to the gate of the driving transistor M0 and the anode of the light-emitting element D, respectively, for reset. In the embodiments provided by this invention, by multiplexing the first scan signal provided by the first scan line Scan1 as the first reset signal and the light emission control signal provided by the light emission control line Emit as the second reset signal during the reset phase T1, a separate reset signal line is avoided, saving wiring space in the display panel 100, increasing the spacing between traces, and preventing crosstalk between adjacent traces.

[0142] In one optional embodiment provided by the present invention, refer to Figure 6 , Figure 16 and Figure 17 As shown, Figure 16 This is a schematic diagram of another pixel driving circuit provided in an embodiment of the present invention; Figure 17 for Figure 16 The timing diagram of the pixel driving circuit is shown. Driving transistor M0, first transistor M1, second transistor M2, third transistor M3, fourth transistor M4, fifth transistor M5, and sixth transistor M6 are P-type transistors.

[0143] The first terminal of the first transistor M1 is connected to the first scan line Scan1; the first scan signal provided by the first scan line Scan1 is multiplexed into a first reset signal Vref1 provided by the first transistor M1 to the gate of the driving transistor M0;

[0144] The first terminal of the second transistor M2 is connected to the first scan line Scan1; the first scan signal provided by the first scan line Scan1 is multiplexed into a second reset signal Vref2 provided by the second transistor M2 to the anode of the light-emitting element D.

[0145] Understandably, during the reset phase T1, the first scan signal provided by the first scan line Scan1 is a low-level signal. Since the first transistor M1 and the second transistor M2 are P-type transistors, during the reset phase T1, the first transistor M1 and the second transistor M2 are turned on, transmitting the low-level signal provided by the first scan line Scan1 to the gate of the driving transistor M0 and the anode of the light-emitting element D, respectively. Because the driving transistor M0 is a P-type transistor, its gate is reset when its potential is low, and the anode of the light-emitting element D is also reset when its potential is low.

[0146] During the data writing phase T2, the second scan signal provided by the second scan line Scan2 is a low-level signal. Since the fourth transistor M4 and the fifth transistor M5 are P-type transistors, during the data writing phase T2, the fourth transistor M4 and the fifth transistor M5 are turned on. The data signal at the data signal terminal Vdata is transmitted to the gate of the driving transistor M0 through the fourth transistor M4, and the fifth transistor M5 performs detection and threshold compensation on the driving transistor M0.

[0147] During the light-emitting stage T3, the light-emitting control signal provided by the Emit control line is a low-level signal. Since the third transistor M3 and the sixth transistor M6 are P-type transistors, they are turned on during T3. The third transistor M3 transmits the first voltage signal from the first power supply signal line PVDD to the input terminal of the driving transistor M0, causing the driving transistor M0 to generate a driving current. The sixth transistor M6 then transmits this driving current to the light-emitting element D, causing the light-emitting element D to emit light.

[0148] In the embodiments provided by this invention, the gates of the first transistor M1 and the second transistor M2 are both connected to the first scan line Scan1, and the first terminals H of the first transistor M1 and the second transistor M2 are both connected to the first scan line Scan1. During the reset phase T1, the first transistor M1 and the second transistor M2 are turned on by the low-level signal provided by the first scan line Scan1 connected to their gates, transmitting the low-level signal provided by the first scan line Scan1 to the gate of the driving transistor M0 and the anode of the light-emitting element D respectively for reset. In the embodiments provided by this invention, by multiplexing the first scan signal provided by the first scan line Scan1 into a first reset signal and a second reset signal during the reset phase T1, a separate reset signal line is avoided, saving wiring space in the display panel 100, increasing the spacing between traces, and preventing crosstalk between adjacent traces.

[0149] On the other hand, refer to Figure 18 As shown, Figure 18This is another timing diagram of the pixel driving circuit provided by the present invention. In the above embodiments, the reset stage T1 can be multiplexed as the scan signal of the reset signal (see attached diagram). Figure 18 China and Israel Figure 16 Taking the pixel driving circuit shown as an example, the pulse width of the first scan signal provided by the first scan line Scan1 (multiplexed into the first reset signal and the second reset signal during the reset phase T1) is narrowed. This makes the voltage of the reset signal during the reset phase T1 less than the absolute value of the high / low level of the scan signal or the light emission control signal. Narrowing the pulse width of the scan signal that multiplexes the reset phase T1 into the reset signal can shorten the maximum frame time, which is beneficial for achieving a high frame rate and thus improving the display effect.

[0150] Based on the same inventive concept, the present invention also provides a driving method, and continues to refer to... Figure 2 and Figure 6 As shown, the pixel driving circuit 200 includes: a driving transistor M0, a power supply voltage writing module 30, a data writing module 40, a compensation module 50, a light emission control module 60, a first reset module 10, a second reset module 20, and a light emission element D.

[0151] The driving method includes at least: a reset phase T1, a data writing phase T2, and a light emission phase T3;

[0152] During the reset phase T1, the first reset module 10 and the second reset module 20 are turned on; the first reset module 10 transmits the first reset signal to the gate of the driving transistor M0 to reset the gate of the driving transistor M0; the second reset module 20 transmits the second reset signal to the anode of the light-emitting element D to reset the anode of the light-emitting element D.

[0153] During the data writing phase T2, the data writing module 30 and the compensation module 50 are turned on; the data writing module 30 transmits the data signal provided by the data signal terminal Vdata to the gate of the driving transistor M0, and the compensation module 50 performs threshold compensation on the driving transistor M0.

[0154] During the light-emitting stage T3, the power supply voltage writing module 40 and the light-emitting control module 60 are turned on; the power supply voltage writing module 40 transmits the first voltage signal provided by the first power signal line PVDD to the driving transistor M0, driving the driving transistor M0 to form a current that is transmitted to the light-emitting element D.

[0155] Based on the same inventive concept, the present invention also provides a display device, referring to... Figure 19 As shown, Figure 19 This is a top view of a display device provided in an embodiment of the present invention. The display device 300 includes the display panel 100 in any of the above embodiments.

[0156] Optionally, the display panel provided in this embodiment can be a display panel using organic light-emitting diode display technology, i.e., an OLED display panel. The basic structure of an OLED display panel typically includes a hole transport layer, an emissive layer, and an electron transport layer. When a suitable voltage is supplied, holes from the anode and electrons from the cathode combine in the emissive layer to produce light. Compared to liquid crystal display panels, OLED display panels have the characteristics of high visibility and high brightness, and are also more energy-efficient, lighter, and thinner.

[0157] The display device 300 provided in this embodiment of the invention can be any electronic device with display function, such as a touch screen, mobile phone, tablet computer, laptop computer, e-reader, or television. The display device 300 provided in this embodiment of the invention has the beneficial effects of the display panel 100 provided in this embodiment of the invention. For details, please refer to the specific descriptions of the display panel 100 in the above embodiments; these descriptions will not be repeated here.

[0158] Understandable, Figure 19 The rectangular structure is used as an example to illustrate one shape of the display device 300. In some other embodiments of the present invention, the display device 300 may also be embodied as a rounded rectangle, a circle, an ellipse or any other feasible shape. The present invention does not specifically limit this.

[0159] In summary, the display panel, driving method, and display device provided by the present invention achieve at least the following beneficial effects:

[0160] The embodiments provided by this invention electrically connect the input terminal of the first reset signal module to the scan line or the light emission control line, and the output terminal to the gate of the driving transistor. The scan signal provided by the scan line or the light emission control signal provided by the light emission control line is multiplexed into a first reset signal, which is transmitted to the gate of the driving transistor through the first reset module to reset the gate of the driving transistor. Multiplexing the scan signal or the light emission control signal into a first reset signal eliminates the need for additional reset lines, saving wiring space. In high-density display panels, this avoids the problems of small trace spacing, leakage current, and crosstalk caused by excessive traces.

[0161] While specific embodiments of the invention have been described in detail by way of examples, those skilled in the art should understand that the examples are for illustrative purposes only and not intended to limit the scope of the invention. Those skilled in the art should understand that modifications can be made to the above embodiments without departing from the scope and spirit of the invention. The scope of the invention is defined by the appended claims.

Claims

1. A display panel, characterized by, At least including: A pixel driving circuit and a scan line and a light emission control line connected to the pixel driving circuit; The pixel driving circuit includes a driving transistor, a first reset module, and a light-emitting element. The output terminal of the first reset module is connected to the gate of the driving transistor, and the output terminal of the driving transistor is electrically connected to the light-emitting element. The input terminal of the first reset module is connected to the scan line or the light emission control line; the scan signal provided by the scan line, or the light emission control signal provided by the light emission control line, is multiplexed into a first reset signal provided by the first reset module to the gate of the driving transistor; The scan lines include a first scan line and a second scan line; The pixel driving circuit has a first scan line and a second scan line extending along the row direction on one side; The second scan line in the nth row is multiplexed as the first scan line in the pixel driving circuit in the (n+1)th row, where n is an integer and n≥1; The pixel driving circuit further includes a second reset module, the output terminal of which is connected to the anode of the light-emitting element; The input terminal of the second reset module is connected to the scan line or the light emission control line; the scan signal provided by the scan line, or the light emission control signal provided by the light emission control line, is multiplexed into a second reset signal provided by the second reset module to the anode of the light emission element; The input terminal of the first reset module is connected to a different signal line than the input terminal of the second reset module, wherein the signal line is the scan line or the light emission control line.

2. The display panel according to claim 1, characterized in that, The first scan line provides a first scan signal, and the second scan line provides a second scan signal.

3. The display panel of claim 2, wherein, Also includes: A power supply voltage writing module is connected in series between the driving transistor and the first power signal line. The control terminal of the power supply voltage writing module is connected to the light emission control line, the input terminal of the power supply voltage writing module is connected to the first power signal line, and the output terminal of the power supply voltage writing module is connected to the input terminal of the driving transistor. A data writing module is connected in series between the driving transistor and the data signal line. The control terminal of the data writing module is connected to the second scan line, the input terminal of the data writing module is connected to the data signal line, and the output terminal of the data writing module is connected to the input terminal of the driving transistor. A compensation module is connected in series between the gate of the driving transistor and the output terminal of the driving transistor. The control terminal of the compensation module is connected to the second scan line, the input terminal of the compensation module is connected to the output terminal of the driving transistor, and the output terminal of the compensation module is connected to the gate of the driving transistor. A light-emitting control module is connected in series between the driving transistor and the light-emitting element. The control terminal of the light-emitting control module is connected to the light-emitting control line, the input terminal of the light-emitting control module is connected to the output terminal of the driving transistor, and the output terminal of the light-emitting control module is connected to the anode of the light-emitting element. A capacitor, wherein the first terminal of the capacitor is connected to the first power signal line, and the second terminal of the capacitor is connected to the gate of the driving transistor; The first reset module includes a first transistor; The second reset module includes a second transistor.

4. The display panel according to claim 2, characterized in that, The first reset module includes a first transistor, the gate of the first transistor is connected to the first scan line, the first electrode of the first transistor is connected to the first scan line, or the second scan line, or the light emission control line, and the second electrode of the first transistor is connected to the gate of the driving transistor.

5. The display panel according to claim 2, characterized in that, The second reset module includes a second transistor, the gate of the second transistor is connected to the first scan line, the first electrode of the second transistor is connected to the first scan line, or the second scan line, or the light emission control line, and the second electrode of the second transistor is connected to the anode of the light emission element.

6. The display panel of claim 3, wherein, The power supply voltage writing module includes a third transistor, the gate of which is connected to the light emission control line, the first terminal of which is connected to the first power signal line, and the second terminal of which is connected to the input terminal of the driving transistor. The data writing module includes a fourth transistor, the gate of which is connected to the second scan line, the first terminal of which is connected to the data signal line, and the second terminal of which is connected to the input terminal of the driving transistor. The compensation module includes a fifth transistor, the gate of which is connected to the second scan line, the first terminal of which is connected to the output terminal of the driving transistor, and the second terminal of which is connected to the gate of the driving transistor. The light-emitting control module includes a sixth transistor, the gate of which is connected to the light-emitting control line, the first terminal of which is connected to the output terminal of the driving transistor, and the second terminal of which is connected to the anode of the light-emitting element.

7. The display panel of claim 6, wherein, The third transistor and the sixth transistor are P-type transistors; The driving transistor, the first transistor, the second transistor, the fourth transistor, and the fifth transistor are N-type transistors; The first electrode of the first transistor is connected to the light-emitting control line; The light emission control signal provided by the light emission control line is multiplexed into the first reset signal provided by the first transistor to the gate of the driving transistor; The first terminal of the second transistor is connected to the second scan line; the second scan signal provided by the second scan line is multiplexed into the second reset signal provided by the second transistor to the anode of the light-emitting element.

8. The display panel of claim 6, wherein, The driving transistor, the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor are N-type transistors; The first terminal of the first transistor is connected to the first scan line; the first scan signal provided by the first scan line is multiplexed into the first reset signal provided by the first transistor to the gate of the driving transistor; The first electrode of the second transistor is connected to the light-emitting control line; The light emission control signal provided by the light emission control line is multiplexed into the second reset signal provided by the second transistor to the anode of the light emission element.

9. A driving method for driving the display panel described in any one of claims 1 to 8, characterized by, The display panel includes: a driving transistor, a power supply voltage writing module, a data writing module, a compensation module, a light emission control module, a first reset module, a second reset module, and a light emission element; The driving method includes at least: a reset phase, a data writing phase, and a light emission phase; During the reset phase, the first reset module and the second reset module are turned on; the first reset module transmits a first reset signal to the gate of the driving transistor to reset the gate of the driving transistor; the second reset module transmits a second reset signal to the anode of the light-emitting element to reset the anode of the light-emitting element. During the data writing phase, the data writing module and the compensation module are turned on; the data writing module transmits the data signal provided by the data signal terminal to the gate of the driving transistor, and the compensation module performs threshold compensation on the driving transistor; During the light-emitting stage, the power supply voltage writing module and the light-emitting control module are turned on; the power supply voltage writing module transmits the first voltage signal provided by the first power signal line to the driving transistor, driving the driving transistor to form a current that is transmitted to the light-emitting element.

10. A display device, characterized in that, Includes the display panel as described in any one of claims 1-8.

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