Packaging method
By employing multiple wafer stacking processes and curved dielectric layer treatments, the problem of right-angle damage to wafer edges was resolved, thereby improving the performance and reliability of semiconductor structures.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SEMICON MFG INT (SHANGHAI) CORP
- Filing Date
- 2021-12-23
- Publication Date
- 2026-05-12
AI Technical Summary
In existing technologies, right angles at the edges of wafers can easily damage tools during the trimming process, resulting in residues on the wafer surface that affect the performance of the semiconductor structure.
By performing multiple wafer stacking operations, a boss-shaped wafer is formed and an arc-shaped dielectric layer is formed on the surface of the boss, which reduces tool damage and residue. Multi-layer wafer stacking improves device density and integration.
This reduces the probability of tool damage and wafer surface residues, improving the performance and reliability of semiconductor structures.
Smart Images
Figure CN116403890B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a packaging method. Background Technology
[0002] In some existing semiconductor processes, such as 3D-IC wafer bonding and subsequent wafer thinning processes, trimming is required to ensure the integrity and smoothness of the wafer edges.
[0003] Before bonding two adjacent wafers, one of the wafers needs to undergo a first trimming process. Then, the two adjacent wafers are bonded. The top wafer is first ground and thinned, and then a second trimming process is used to obtain the ideal edge.
[0004] In the multi-wafer stacking process, repeat the previous steps. Summary of the Invention
[0005] The problem addressed by the embodiments of the present invention is to provide a packaging method that improves the performance of semiconductor structures.
[0006] To address the aforementioned problems, embodiments of the present invention provide a packaging method, comprising: providing a first wafer; performing multiple wafer stacking operations, wherein the wafer stacking operations include: forming a first wafer to be bonded in the shape of a boss, including a base and a protrusion protruding from the base, wherein forming the first wafer to be bonded includes: performing a first trimming process on the edge region of the front side of the first wafer, the remaining first wafer after the first trimming process serving as the first wafer to be bonded; facing the protrusion toward a second wafer to be bonded, and bonding it with the second wafer to be bonded to form a stacked wafer; after bonding, ... The back side of the first wafer to be bonded is thinned, and the thickness of the thinning process is at least the thickness of the first substrate. After the thinning process, a first dielectric layer is formed on the surface of the protrusion, and the corner of the first dielectric layer is arc-shaped. After the first dielectric layer is formed, a second trimming process is performed on the edge region of the protrusion and the edge region of the second wafer to be bonded, so that the remaining second wafer to be bonded after the second trimming process is in the shape of a boss, and the remaining stacked wafer after the second trimming process serves as the first wafer to be bonded in the next wafer stacking process.
[0007] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:
[0008] This invention provides a packaging method that performs multiple wafer stacking operations. The wafer stacking operations include: facing a protrusion towards a second wafer to be bonded and bonding it to the second wafer to be bonded to form a stacked wafer; after bonding, thinning the back side of the first wafer to be bonded, the thickness of the thinning process being at least the thickness of the first substrate; after the thinning process, forming a first dielectric layer on the surface of the protrusion, the corners of the first dielectric layer being arc-shaped. During the second trimming process, because the corners of the first dielectric layer are arc-shaped and the first dielectric layer is in close contact with the surface of the protrusion and the surface of the second wafer to be bonded, the damage to the tools used in the second trimming process is reduced. Correspondingly, in the subsequent thinning process, the probability of residues remaining on the surface of the second wafer to be bonded is reduced, thereby improving the performance of the semiconductor structure. Attached Figure Description
[0009] Figures 1 to 5 This is a structural diagram showing the steps in an encapsulation method.
[0010] Figures 6 to 13 This is a schematic diagram of the structure corresponding to each step in one embodiment of the packaging method of the present invention. Detailed Implementation
[0011] The performance of current semiconductor structures needs improvement. This paper analyzes the reasons why the performance of a particular packaging method needs further improvement.
[0012] Figures 1 to 5 This is a structural diagram showing the steps in an encapsulation method.
[0013] refer to Figure 1 , providing the first wafer 10.
[0014] refer to Figure 2 The first wafer 10 is subjected to a first trimming process to form a first wafer 13 to be bonded in the shape of a boss. The first wafer 13 to be bonded includes a base 11 and a protrusion 12 protruding from the base 11.
[0015] refer to Figure 3 The protrusion 12 is oriented toward the second wafer to be bonded 15, and the first wafer to be bonded 13 and the second wafer to be bonded 15 are bonded together by the bonding layer 16.
[0016] refer to Figure 4 After bonding, the back side of the first wafer to be bonded 13 is thinned, and the thickness of the thinning process is at least the thickness of the first substrate 11.
[0017] refer to Figure 5After the thinning process, a second trimming process is performed on the edge region of the protrusion 12 and the edge region of the second wafer to be bonded 15. The remaining second wafer to be bonded 15 after the second trimming process is in the shape of a protrusion.
[0018] Research has revealed that because the corners of the edge region of the first wafer 10 are right angles, these corners are prone to causing damage to the tools used in the first trimming process. In the subsequent second trimming process, tools with this damage (e.g., blades) will further amplify the damage (e.g., significant groove wear on the blades). Consequently, using tools with this damage for the second trimming process can easily leave residues on the surface of the remaining second wafer 15 to be bonded (e.g.,...). Figure 5 (As shown in the dashed coil in the middle), thereby affecting the performance of the semiconductor structure.
[0019] To address the aforementioned technical problem, embodiments of the present invention provide a packaging method, comprising: providing a first wafer; performing multiple wafer stacking operations, the wafer stacking operations comprising: forming a first wafer to be bonded in the shape of a boss, including a base and a protrusion protruding from the base, the formation of the first wafer to be bonded comprising: performing a first trimming process on the edge region of the front side of the first wafer, the remaining first wafer after the first trimming process serving as the first wafer to be bonded; facing the protrusion toward a second wafer to be bonded, and bonding it with the second wafer to be bonded to form a stacked wafer; after bonding... The back side of the first wafer to be bonded is thinned, and the thickness of the thinning process is at least the thickness of the first substrate. After the thinning process, a first dielectric layer is formed on the surface of the protrusion, and the corner of the first dielectric layer is arc-shaped. After the first dielectric layer is formed, a second trimming process is performed on the edge region of the protrusion and the edge region of the second wafer to be bonded, so that the remaining second wafer to be bonded after the second trimming process is in the shape of a protrusion, and the remaining stacked wafer after the second trimming process is used as the first wafer to be bonded in the next wafer stacking process.
[0020] In the scheme disclosed in this embodiment of the invention, multiple wafer stacking operations are performed. The wafer stacking operation includes: facing the protrusion towards the second wafer to be bonded and bonding it with the second wafer to be bonded to form a stacked wafer; after bonding, the back side of the first wafer to be bonded is thinned, and the thickness of the thinning process is at least the thickness of the first substrate; after the thinning process, a first dielectric layer is formed on the surface of the protrusion. The corner of the first dielectric layer is arc-shaped. During the second trimming process, since the corner of the first dielectric layer is arc-shaped, the damage to the tools used in the second trimming process is reduced. Correspondingly, in the subsequent thinning process, the probability of residues remaining on the surface of the second wafer to be bonded is reduced, thereby improving the performance of the semiconductor structure.
[0021] To make the above-mentioned objects, features and advantages of the embodiments of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
[0022] Figures 6 to 13 This is a schematic diagram of the structure corresponding to each step in one embodiment of the packaging method of the present invention.
[0023] refer to Figure 6 , providing the first wafer 100.
[0024] The first wafer 100 provides the process basis for the subsequent first trimming process, and the first wafer 100 is used to bond with other wafers.
[0025] The first wafer 100 is a completed wafer, and the first wafer 100 can be manufactured using integrated circuit manufacturing technology.
[0026] In this embodiment, the first wafer 100 includes a first substrate, NMOS devices and PMOS devices formed on the first substrate by processes such as deposition and etching, and structures such as dielectric layers and metal interconnects formed on the devices.
[0027] In this embodiment, the first substrate is a silicon substrate. In other embodiments, the material of the first substrate may also be germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium dihydrogen phosphate, etc. The first substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, etc. The material of the first substrate may be a material suitable for process requirements or easy to integrate.
[0028] refer to Figures 7 to 13 Multiple wafer stacking operations are performed.
[0029] As the minimum linewidth gets closer to the physical limit, the Moore's Law approach becomes increasingly unworkable.
[0030] Multiple wafer stacking operations increase the wiring (device) density per unit volume by stacking multiple wafers.
[0031] The steps of the wafer stacking operation are described in detail below with reference to the accompanying drawings.
[0032] refer to Figure 7 A first wafer 103 to be bonded is formed in the shape of a boss, including a base 101 and a protrusion 102 protruding from the base 101. The formation of the first wafer 103 includes: performing a first trimming process on the edge region of the front side of the first wafer 100, and the remaining first wafer 100 after the first trimming process is used as the first wafer 103 to be bonded.
[0033] Specifically, the first trimming process is performed because the edge area on the front side of the first wafer is usually not flat enough, which can easily lead to gaps when the first wafer is bonded to other wafers in the future. Therefore, by removing the uneven part of the edge area on the front side of the first wafer through the first trimming process, the probability of gaps appearing at the bonding surface between the first wafer and other wafers is reduced, thereby improving the bonding reliability.
[0034] In this embodiment, a blade is used for the first trimming process.
[0035] Specifically, the first wafer 100 is mechanically worn by the rotation of the blade itself, thereby achieving the effect of trimming.
[0036] In this embodiment, the blade is a circular blade.
[0037] The circular blade mechanically wears down the first wafer 100 by rotating at a constant speed, thus achieving the effect of trimming the edges.
[0038] refer to Figure 8 The protrusion 102 is oriented toward the second wafer to be bonded 105 and bonded to the second wafer to be bonded 105 to form a stacked wafer 200.
[0039] Compared to traditional wafers that place all modules on the same surface, stacked wafers allow multiple wafers to be stacked and enable vertical communication between the stacked wafers through through-silicon via (TSV) technology, thereby improving the performance and integration of the device.
[0040] In this embodiment, the bonding process between the protrusion 102 and the second wafer 105 to be bonded is a fusion bonding process.
[0041] In other embodiments, the process of bonding the protrusion to the second wafer to be bonded may be one or more of the following: hybrid bonding process, temporary bonding process, adhesive bonding process, anodic bonding process, and bump bonding process.
[0042] It should be noted that the first wafer to be bonded 103 and the second wafer to be bonded 105 are bonded together by a bonding layer 106.
[0043] Specifically, the bonding layer 106 is made of one or more of silicon oxide, silicon nitride, and silicon carbide nitride.
[0044] Silicon oxide, silicon nitride, and silicon carbide are all commonly used materials in bonding processes and have strong bonding capabilities, which ensures that the bonding strength between the protrusion 102 and the second wafer 105 to be bonded meets the process requirements.
[0045] refer to Figure 9 After bonding, the back side of the first wafer to be bonded 103 is thinned, and the thickness of the thinning process is at least the thickness of the first substrate 101.
[0046] Specifically, the back side of the first wafer to be bonded 103 is thinned to provide a process basis for the subsequent second trimming process and another wafer stacking operation.
[0047] In this embodiment, the back side of the first wafer to be bonded 103 can be thinned by first using coarse grinding and then fine grinding. Coarse grinding is performed quickly using a coarse grinding machine, and fine grinding is performed, for example, using a chemical mechanical polishing process.
[0048] refer to Figure 10 After the thinning process is performed, a first dielectric layer 107 is formed on the surface of the protrusion 102, and the corner of the first dielectric layer 107 is arc-shaped.
[0049] Specifically, by forming a first dielectric layer 107 on the surface of the protrusion, the corners of the first dielectric layer 107 are arc-shaped, and the first dielectric layer 107 is in close contact with the surface of the protrusion 102 and the surface of the second wafer to be bonded 105, during the subsequent second trimming process, the arc-shaped corners of the first dielectric layer 107 reduce the damage to the tools used in the second trimming process (e.g., causing groove wear to the blade). Correspondingly, in the subsequent thinning process, the probability of residues remaining on the surface of the second wafer to be bonded 105 is reduced, thereby improving the performance of the semiconductor structure.
[0050] In this embodiment, the process for forming the first dielectric layer 107 includes atomic layer deposition.
[0051] Specifically, the atomic layer deposition process includes multiple atomic layer deposition cycles, which has good step coverage capability, helps to improve the thickness uniformity of the first dielectric layer 107, and enables the first dielectric layer 107 to cover the surface and corners of the protrusion 102, thereby making it easy to make the corners of the first dielectric layer 107 arc-shaped.
[0052] In other embodiments, a chemical vapor deposition (CVD) process can also be used to form the first dielectric layer. Due to the inherent coverage capability of CVD, the corners of the first dielectric layer can also be made arc-shaped.
[0053] In this embodiment, during the formation of the first dielectric layer 107, the first dielectric layer 107 also covers the top surface and sidewalls of the second wafer to be bonded 105, and the first dielectric layer 107 is arc-shaped at the corner of the second wafer to be bonded 105.
[0054] It should be noted that the first dielectric layer 107 is arc-shaped at the corner of the second wafer to be bonded 105, which reduces the probability of damage to the blade during the subsequent second trimming process on the front edge area of the second wafer to be bonded 105.
[0055] In this embodiment, the material of the first dielectric layer 107 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide nitride.
[0056] Specifically, silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide are all commonly used materials for dielectric films. During the deposition process to form the first dielectric layer 107, the first dielectric layer 107 is easy to adhere tightly to the surface of the protrusion, and the first dielectric layer 107 is arc-shaped at the corner of the second wafer to be bonded 105.
[0057] It should be noted that the thickness of the first dielectric layer 107 should not be too large or too small. If the thickness of the first dielectric layer 107 is too large, it increases the difficulty of the subsequent second trimming process on the edge region of the protrusion 102 and the edge region of the second wafer 105 to be bonded, reduces process efficiency, and also increases the probability of damage to the cutting tool. If the thickness of the first dielectric layer 107 is too small, it is easy to reduce the coverage effect of the first dielectric layer 107 at the corner of the protrusion 102. During the subsequent second trimming process on the edge region of the protrusion 102 and the edge region of the second wafer 105 to be bonded, the protection effect on the tool used for the second trimming process is reduced, increasing the probability of damage to the tool. Correspondingly, the probability of residues remaining on the surface of the second wafer 105 to be bonded is still relatively high during the subsequent thinning process. Therefore, in this embodiment, the thickness of the first dielectric layer 107 is 500 nanometers to 2900 nanometers.
[0058] refer to Figure 11 After the first dielectric layer 107 is formed, a second trimming process is performed on the edge region of the protrusion 102 and the edge region of the second wafer to be bonded 105, so that the remaining second wafer to be bonded 105 after the second trimming process is in the shape of a protrusion, and the remaining stacked wafer 200 after the second trimming process is used as the first wafer to be bonded in the next wafer stacking process.
[0059] Specifically, after the thinning process, edge gaps are likely to appear at the interface between the edge region of the protrusion 102 and the second wafer 105 to be bonded, which can easily lead to a deterioration in the edge bonding effect between the protrusion 102 and the second wafer 105 to be bonded. Therefore, by performing a second trimming process on the edge region of the protrusion 102 and the edge region of the second wafer 105 to be bonded, the part of the protrusion 102 and the second wafer 105 to be bonded with lower bonding strength is removed, thereby ensuring the bonding strength of the remaining stacked wafers 200 after the second trimming process.
[0060] Since the tools used in the first trimming process and the second trimming process are the same, in this embodiment, the second trimming process is performed with reference to the aforementioned first trimming process.
[0061] It should be noted that the trimming depth should not be too large or too small. If the trimming depth is too large, the base of the second wafer 105 to be bonded may be completely removed, resulting in a significant reduction in the product yield. If the trimming depth is too small, the amount of material removed from the edge region of the second wafer 105 to be bonded may be too small, increasing the probability of edge gaps appearing at the interface between the edge region of the protrusion 102 and the second wafer 105 to be bonded, thus reducing the bonding strength of the remaining stacked wafers 200 after the second trimming process, thereby affecting the performance of the semiconductor structure. Therefore, in this embodiment, the trimming depth ranges from 20 micrometers to 200 micrometers.
[0062] It should also be noted that the trimming width should not be too large or too small. If the trimming width is too large, the effective area of the remaining stacked wafer 200 after the second trimming process will be too small, resulting in a decrease in the performance of the semiconductor device. If the trimming width is too small, the amount of edge region removal of the second wafer 105 to be bonded will be too small, increasing the probability that edge gaps will easily appear at the interface between the edge region of the protrusion 102 and the second wafer 105 to be bonded, reducing the bonding strength of the remaining stacked wafer 200 after the second trimming process, thereby affecting the performance of the semiconductor structure.
[0063] It should be noted that the second trimming process also includes: removing the first dielectric layer 107 covering the edge region of the protrusion 102 and the edge region of the second wafer to be bonded 105.
[0064] refer to Figure 12 The first dielectric layer 107 at the top of the protrusion 102 is planarized.
[0065] Specifically, after the thinning process, the flatness of the top surface of the protrusion 102 is not high enough to meet the process requirements. Therefore, the first dielectric layer 107 at the top of the protrusion 102 is planarized to improve the flatness of the top surface of the protrusion 102 and provide a good process foundation for the next wafer stacking.
[0066] In this embodiment, during the planarization process, all of the first dielectric layer 107 on the top of the protrusion 102 is removed, thereby improving the flatness of the top surface of the protrusion 102.
[0067] In other embodiments, during the planarization process, a portion of the thickness of the first dielectric layer at the top of the protrusion may be removed, resulting in a higher flatness of the remaining top surface of the first dielectric layer, providing a good process foundation for the next wafer stacking.
[0068] In this embodiment, the process of planarizing the first dielectric layer 107 on the top of the protrusion 102 includes a chemical mechanical polishing process.
[0069] refer to Figure 13 A second dielectric layer 108 is formed on the sidewall of the protrusion 102.
[0070] It should be noted that in the step of providing the first wafer 100, interconnect wires (not shown) are also formed in the protrusion 102. Since the first wafer 100 has undergone a first trimming process and a second trimming process, a second dielectric layer 108 is formed on the sidewall of the protrusion 102 to provide protection for the sidewall of the protrusion 102, reducing the probability of the interconnect wires being exposed, thereby improving the performance of the semiconductor structure.
[0071] In this embodiment, the second dielectric layer 108 is formed on the top and sidewall of the protrusion 102, and on the top of the second wafer to be bonded 105.
[0072] On the one hand, after the second trimming process, some particles or powdery wafers may remain on the surface of the second wafer to be bonded 105 and the protrusion 102. During the planarization process of the first dielectric layer 107 on the top of the protrusion 102, the top surface of the protrusion 102 and the second wafer to be bonded 105 may be damaged. Therefore, a second dielectric layer 108 is formed on the top and sidewall of the protrusion 102 and the top of the second wafer to be bonded 105. This layer can repair or cover the defects on the top surface of the protrusion 102 and the second wafer to be bonded 105, thereby improving the product yield.
[0073] On the other hand, a second dielectric layer 108 is formed on the top of the protrusion 102, which also prepares for the next wafer stacking. The second dielectric layer 108 can be directly used as the bonding layer for the next wafer stacking.
[0074] In this embodiment, the process for forming the second dielectric layer 108 includes atomic layer deposition or chemical vapor deposition.
[0075] Taking atomic layer deposition (ALD) as an example, specifically, the ALD process includes multiple ALD cycles, which has good step coverage capability, which is beneficial to improving the thickness uniformity of the second dielectric layer 108, and enabling the second dielectric layer 108 to cover the top and sidewalls of the protrusion 102, as well as the top of the second wafer to be bonded 105.
[0076] The material of the second dielectric layer 108 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide nitride.
[0077] Specifically, silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide are all commonly used materials for dielectric films. During the deposition process to form the second dielectric layer 108, they are easy to adhere tightly to the top and sidewalls of the protrusion 102 and the top of the second wafer to be bonded 105.
[0078] It should be noted that the thickness of the second dielectric layer 108 should not be too large or too small. If the thickness of the second dielectric layer 108 is too large, it can easily cause greater stress on the stacked wafer 200, increasing the probability of deformation and thus affecting the performance of the semiconductor structure. If the thickness of the second dielectric layer 108 is too small, it can easily lead to a poorer coverage effect on the sidewalls of the protrusion 102, resulting in a decrease in the protection effect on the interconnect wires in the protrusion 102. Furthermore, during the next wafer stacking process, the bonding strength effect of the second dielectric layer 108 at the top of the protrusion 102 decreases, thereby affecting the performance of the semiconductor structure. Therefore, in this embodiment, the thickness of the second dielectric layer 108 is 50 nanometers to 100 nanometers.
[0079] In this embodiment, the remaining stacked wafer after the second trimming process serves as the first wafer to be bonded in the next wafer stacking process, thereby repeating the wafer stacking operation multiple times to complete the packaging process. The specific steps of the subsequent wafer stacking operations are the same as described above and will not be repeated here.
[0080] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.
Claims
1. A packaging method, characterized in that, include: Provide the first wafer; Perform multiple wafer stacking operations, the wafer stacking operations including: A first wafer to be bonded is formed in the shape of a boss, including a base and a protrusion protruding from the base. The formation of the first wafer to be bonded includes: performing a first trimming process on the edge region of the front side of the first wafer, and the first wafer remaining after the first trimming process is used as the first wafer to be bonded. The protrusion is oriented toward the second wafer to be bonded and bonded to the second wafer to be bonded to form a stacked wafer; After bonding, the back side of the first wafer to be bonded is thinned, and the thickness of the thinning process is at least the thickness of the substrate. After the thinning process is performed, a first dielectric layer is formed on the surface of the protrusion, and the corners of the first dielectric layer are arc-shaped. After the first dielectric layer is formed, a second trimming process is performed on the edge region of the protrusion and the edge region of the second wafer to be bonded, so that the remaining second wafer to be bonded after the second trimming process is in the shape of a protrusion, and the remaining stacked wafer after the second trimming process is used as the first wafer to be bonded in the next wafer stacking process.
2. The packaging method as described in claim 1, characterized in that, The wafer stacking operation further includes forming a second dielectric layer on the sidewall of the protrusion after the second trimming process.
3. The packaging method as described in claim 2, characterized in that, The wafer stacking operation further includes: after the second trimming process and before forming the second dielectric layer, planarizing the first dielectric layer on the top of the protrusion; In the step of forming the second dielectric layer, the second dielectric layer is formed on the top and sidewalls of the protrusion, and on the top of the second wafer to be bonded.
4. The packaging method as described in claim 1, characterized in that, The process for forming the first dielectric layer includes atomic layer deposition or chemical vapor deposition.
5. The packaging method as described in claim 2, characterized in that, The process for forming the second dielectric layer includes atomic layer deposition or chemical vapor deposition.
6. The packaging method as described in claim 1, characterized in that, In the step of forming the first dielectric layer, the material of the first dielectric layer includes one or more of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide nitride.
7. The packaging method as described in claim 2, characterized in that, In the step of forming the second dielectric layer, the material of the second dielectric layer includes one or more of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide nitride.
8. The packaging method as described in claim 1, characterized in that, In the step of forming the first dielectric layer, the thickness of the first dielectric layer is 500 nanometers to 2900 nanometers.
9. The packaging method as described in claim 2, characterized in that, In the step of forming the second dielectric layer, the thickness of the second dielectric layer is 50 nanometers to 100 nanometers.
10. The packaging method as described in claim 1, characterized in that, The first and second trimming processes are performed using a blade.
11. The packaging method as described in claim 1, characterized in that, The parameters for the second trimming process include: trimming depth ranging from 20 micrometers to 200 micrometers; and trimming width ranging from 0.5 micrometers to 5 micrometers.