High-temperature-resistant high-performance CMOS based on SiC substrate and preparation method thereof

Abstract

The application relates to a high-temperature-resistant high-performance CMOS based on a SiC substrate and a preparation method thereof, and belongs to the technical field of microelectronics. The SiC N-type channel MOS tube and the GaN P-type channel MOS tube are prepared on the same SiC substrate and are connected in series, the high-temperature-resistant high-performance CMOS is prepared on the SiC substrate, and thus the prepared CMOS has the advantages of high-temperature resistance, high breakdown voltage, low on-resistance, high speed, high integration and the like.

Description

Technical Field

[0001] This invention relates to a high-temperature resistant, high-performance CMOS based on a SiC substrate and its fabrication method, belonging to the field of microelectronics technology. Background Technology

[0002] CMOS (Complementary Metal-Oxide-Semiconductor) architecture is one of the most important structures in integrated circuit systems. Early CMOS devices quickly dominated the digital chip market due to their high integration density, ease of scaling, and the fact that their evolved gate circuits only consume power during switching. Subsequently, CMOS technology, with its advantage of integrating analog and digital circuits on the same chip to improve overall performance and reduce packaging costs, quickly opened the door to the analog chip market. As the feature size of CMOS devices shrinks and frequencies increase, the required power supply voltage also decreases. Therefore, CMOS devices are widely used in many fields such as temperature sensors, image sensors, and RF power amplifiers.

[0003] In today's era of rapid development in high-tech industries, fundamental sectors such as aerospace, oil exploration, high-speed rail, and metallurgy and chemicals all require operation in harsh environments with extreme temperatures. This places higher demands on the reliability of electronic devices, making electronic devices and integrated circuits that can maintain stability at high temperatures particularly crucial. However, the physical limitations of Si-based CMOS make it unsuitable for harsh working environments such as high temperatures. Traditional semiconductor materials such as Si and GaAs, due to their inherent material properties, are more suitable for system electronic devices and integrated circuits in medium- and low-temperature environments. Although high-temperature resistant Si devices have made significant progress over decades of research, they still cannot break through their theoretical limits. Problems such as junction temperature rise and leakage current surge caused by the self-heating effect of Si-based devices at high temperatures remain unresolved, and the maximum operating temperature of their power electronic devices generally does not exceed 200°C. Therefore, from a materials perspective, in order to enable devices to operate in higher-temperature environments, it is necessary to find other semiconductor materials with better high-temperature and heat dissipation properties. Summary of the Invention

[0004] To address the shortcomings of existing technologies, this invention provides a high-temperature resistant, high-performance CMOS based on a SiC substrate and its fabrication method. By fabricating SiC N-channel MOS transistors and GaN P-channel MOS transistors on the same SiC substrate and connecting them in series, a high-temperature resistant, high-performance CMOS is fabricated on the SiC substrate. This results in a CMOS with advantages such as high temperature resistance, high breakdown voltage, low on-resistance, high speed, and high integration.

[0005] The technical solution of the present invention is as follows:

[0006] A high-temperature resistant, high-performance CMOS based on a SiC substrate includes a SiC substrate and an n-type SiC epitaxial layer grown on the SiC substrate. A p-type GaN epitaxial layer is disposed above the n-type SiC epitaxial layer, and an oxide layer is disposed above the p-type GaN epitaxial layer. Ohmic contact metal source and ohmic contact metal drain are fabricated on both sides of the oxide layer. A Schottky contact metal gate is formed above the oxide layer, creating a GaN p-channel MOS transistor. Another portion of the n-type SiC epitaxial layer contains a p-type SiC shielding region, within which are two symmetrical n-type SiC shielding regions. + Type SiC ion implantation region, two n + An ohmic contact metal source and an ohmic contact metal drain are fabricated above the ion-implanted region of a SiC substrate, with the remaining surface covered by an oxide layer. A Schottky contact metal gate is disposed above the oxide layer between the ohmic contact metal source and the ohmic contact metal drain, forming a SiC N-channel MOS transistor. The ohmic contact metal drain of the GaN P-channel MOS transistor is connected to the ohmic contact metal drain of the SiC N-channel MOS transistor, and the Schottky contact metal gate of the GaN P-channel MOS transistor is connected to the Schottky contact metal gate of the SiC N-channel MOS transistor, forming a CMOS device on a SiC substrate.

[0007] Traditional semiconductor material Si, due to its inherent properties, is more suitable for system electronic devices and integrated circuits in low- to medium-temperature environments. At high temperatures, the intrinsic carrier concentration of Si increases dramatically, and the self-heating effect causes problems such as increased junction temperature and a surge in leakage current, leading to severe device drift and affecting reliability. Although high-temperature resistant Si devices have made significant progress over decades of research, they still cannot break through their theoretical limits. Therefore, Si-based CMOS cannot adapt to harsh operating environments such as high temperatures, and its maximum operating temperature generally does not exceed 200℃. In contrast, third-generation semiconductor material SiC has a large bandgap, and its intrinsic carrier concentration remains low even in high-temperature environments. Furthermore, due to its high thermal conductivity, SiC accelerates heat dissipation, significantly alleviating the heat dissipation pressure on devices. Therefore, SiC devices can operate stably at 600℃. In addition, SiC has a large breakdown electric field and low on-resistance. Combined with the higher saturation drift velocity and hole mobility of p-type GaN, this allows CMOS devices to achieve higher breakdown voltage, higher power density, and lower power loss.

[0008] According to a preferred embodiment of the present invention, the doping concentration of the n-type SiC epitaxial layer is 1×10⁻⁶. 15 -1×10 16 cm -3 The thickness of the n-type SiC epitaxial layer is 5-15 μm.

[0009] More preferably, the doping concentration of the n-type SiC epitaxial layer is 5 × 10⁻⁶. 15 cm -3 The thickness of the n-type SiC epitaxial layer is 10 μm.

[0010] According to a preferred embodiment of the present invention, the doping concentration of the p-type SiC shielding region is 1×10⁻⁶. 16 -1×10 17 cm -3 The thickness of the p-type SiC shielding region is 400-600 nm.

[0011] More preferably, the doping concentration of the p-type SiC shielding region is 5 × 10⁻⁶. 16 cm -3 The thickness of the p-type SiC shielding region is 500 nm.

[0012] According to a preferred embodiment of the present invention, n + The ion doping concentration of the SiC ion implantation region is 5 × 10⁻⁶. 17 -5×10 18 cm -3 ;n + The thickness of the SiC ion implantation region is 0.5-1.5 μm;

[0013] Further optimized, n + The ion doping concentration of the SiC ion implantation region is 1×10⁻⁶. 18 cm -3 ,n + The thickness of the SiC ion implantation region is 1 μm.

[0014] According to a preferred embodiment of the present invention, the ion doping concentration of the p-type GaN epitaxial layer is 1×10⁻⁶. 18 -1×10 20 cm -3 The thickness of the p-type GaN epitaxial layer is 70-130 nm.

[0015] Further preferably, the ion doping concentration of the p-type GaN epitaxial layer is 1×10⁻⁶. 19 cm -3 The thickness of the p-type GaN epitaxial layer is 100 nm.

[0016] According to a preferred embodiment of the present invention, the thickness of the oxide layer is 30-70 nm;

[0017] More preferably, the thickness of the oxide layer is 50 nm.

[0018] According to a preferred embodiment of the present invention, the materials of the ohmic contact metal source and ohmic contact metal drain of the SiC N-channel MOS transistor are any one of Ni metal, Al / Ti metal stack, and Ni / Ti / Ni metal stack;

[0019] The material of the Schottky contact metal gate of the SiC N-channel MOSFET is any one of Ni metal, Ni / Au metal stack, or Ti / Au metal stack.

[0020] The materials for the ohmic contact metal source and ohmic contact metal drain of the GaN P-type channel MOSFET are any one of Ti / Al / Ni / Au metal stack, Ti / Al / Ti / Au metal stack, or Ti / Al / Mo / Au metal stack.

[0021] The material of the Schottky contact metal gate of the GaN P-type channel MOSFET is any one of Ni / Au metal stack, Pt / Au alloy or Pd / Au metal stack;

[0022] More preferably, the materials for the ohmic contact metal source and ohmic contact metal drain of the SiC N-type channel MOSFET are Ni metal, and the material for the Schottky contact metal gate is Ni metal; the materials for the ohmic contact metal source and ohmic contact metal drain of the GaN P-type channel MOSFET are Ti / Al / Ni / Au metal stacks, and the material for the Schottky contact metal gate is Ni / Au metal stacks.

[0023] Compared to GaN N-channel MOSFETs used in other technologies, the GaN P-channel MOSFETs used in this application have the advantages of simple fabrication and high device reliability. Ordinary GaN N-channel devices are depletion-mode devices. If GaN N-channel MOSFETs are used in CMOS, special processes such as epitaxial p-GaN cap layer or fluorine ion implantation are required to fabricate them as enhancement-mode devices. Currently, the technologies for fabricating GaN enhancement-mode devices are not mature, and introducing special processes can significantly reduce device reliability, thus affecting the overall performance of CMOS devices. Furthermore, the SiC N-channel MOSFETs used in this application have simple and mature fabrication processes, and the excellent heat dissipation characteristics of the SiC substrate also contribute to improving the performance and stability of CMOS devices.

[0024] A method for fabricating the above-mentioned high-temperature resistant, high-performance CMOS based on a SiC substrate includes the following steps:

[0025] S1. Grow an n-type SiC epitaxial layer on a SiC substrate;

[0026] S2. Prepare a p-type SiC shielding region in a specific region of the n-type SiC epitaxial layer and perform high-temperature annealing;

[0027] S3. Prepare n in a specific region of the p-type SiC shielding region. + SiC ion implantation region is formed and then subjected to high-temperature annealing;

[0028] S4. Grow a p-type GaN epitaxial layer on the other side of the n-type SiC epitaxial layer;

[0029] S5. An oxide layer is grown on the surface;

[0030] S6. Remove the oxide layer above the ohmic contact metal source and ohmic contact metal drain of SiC N-channel MOSFET and GaN P-channel MOSFET.

[0031] S7, in n + SiC N-channel MOS transistor ohmic contact metal source and ohmic contact metal drain are deposited on the SiC ion implantation region and then annealed.

[0032] S8. Deposit the ohmic contact metal source and ohmic contact metal drain of the GaN P-type channel MOS transistor on the p-type GaN epitaxial layer, and then perform annealing treatment.

[0033] S9. A Schottky contact metal gate is deposited on the oxide layer between the ohmic contact metal source and the ohmic contact metal drain of the GaN P-type channel MOSFET.

[0034] S10. A Schottky contact metal gate is deposited on the oxide layer between the ohmic contact metal source and the ohmic contact metal drain of the SiC N-channel MOSFET.

[0035] S11. Electrically (by electrode deposition) connect the ohmic contact metal drain of the SiC N-channel MOSFET and the ohmic contact metal drain of the GaN P-channel MOSFET.

[0036] S12. Electrically (by electrode deposition) connect the Schottky contact metal gate of the SiC N-channel MOSFET and the Schottky contact metal gate of the GaN P-channel MOSFET.

[0037] S13. Connect the ohmic contact metal source electrode of the GaN P-channel MOSFET.

[0038] S14. Connect the ohmic contact metal source electrode of the SiC N-channel MOSFET.

[0039] According to a preferred embodiment of the present invention, in step S2, a p-type SiC shielding region is prepared on an n-type SiC epitaxial layer by ion implantation technology.

[0040] According to a preferred embodiment of the present invention, in step S3, n-type SiC shielded regions are prepared using conventional ion implantation techniques. + Type SiC ion implantation region.

[0041] According to a preferred embodiment of the present invention, in step S4, a p-type GaN epitaxial layer is grown using metal-organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE).

[0042] More preferably, in step S4, the p-type GaN epitaxial layer is grown using metal-organic chemical vapor deposition (MOCVD), specifically including the following steps:

[0043] S4-1. Deposit a mask layer on an n-type SiC epitaxial layer;

[0044] S4-2. Using photolithography on the mask layer, the metal-organic chemical vapor deposition growth region is exposed;

[0045] S4-3. Remove the mask layer from the growth area of ​​the metal-organic chemical vapor deposition method, and retain the mask layer in other areas to achieve mask layer patterning;

[0046] S4-4. Grow p-type GaN epitaxial layers using metal-organic chemical vapor deposition equipment;

[0047] S4-5. Remove the mask layer and the p-type GaN epitaxial layer above it using a conventional stripping process.

[0048] According to a preferred embodiment of the present invention, in step S5, an oxide layer is grown using atomic layer deposition (ALD) or a low-pressure chemical vapor deposition (LPCVD) system; when using atomic layer deposition (ALD) to grow the oxide layer, the oxide layer above SiC can be grown using a high-temperature thermal oxidation furnace.

[0049] According to a preferred embodiment of the present invention, in step S6, the oxide layer is removed by inductively coupled plasma etching (ICP) or wet etching with buffered oxide etchant.

[0050] According to a preferred embodiment of the present invention, the specific process of etching the oxide layer by inductively coupled plasma etching (ICP) in step S6 is as follows:

[0051] S6-1. Coat the oxide layer with photoresist;

[0052] S6-2. Using photolithography and development technology, the oxide layer area to be etched is exposed on the photoresist;

[0053] S6-3. Etching the oxide layer using an inductively coupled plasma device;

[0054] S6-4. Remove the coated photoresist and completely remove the oxide layer above the ohmic contact metal source and ohmic contact metal drain of SiC N-channel MOS transistors and GaN P-channel MOS transistors.

[0055] The beneficial effects of this invention are as follows:

[0056] 1. Excellent high-temperature resistance. SiC material has a large bandgap, and its intrinsic carrier concentration is very low even in high-temperature environments. Furthermore, due to the high thermal conductivity of SiC material, heat dissipation can be accelerated, significantly alleviating the heat dissipation pressure of devices. Therefore, CMOS devices based on SiC substrates have the ability to operate stably at high temperatures.

[0057] 2. High saturation drift rate and hole mobility. P-type GaN epitaxial layers have high saturation drift rate and hole mobility, which improves the operating frequency and power density of the device.

[0058] 3. Mature and simple process. The industrialization of SiC MOSFET devices has laid a solid process foundation for stable SiC-based CMOS devices. It does not require special design of the CMOS device fabrication process, and the conditions for forming ohmic contacts on p-type GaN and SiC are roughly similar, making the device process flow relatively simple.

[0059] 4. High integration. Compared to external lead connections on a chip, on-chip integration significantly reduces the size of the device and increases its integration level. The better heat dissipation performance also facilitates circuit integration design, further promoting the miniaturization of CMOS devices on SiC substrates. Attached Figure Description

[0060] Figure 1 This is a schematic diagram of the structure obtained after step S1.

[0061] Figure 2 This is a schematic diagram of the structure obtained after step S2.

[0062] Figure 3 This is a schematic diagram of the structure obtained after step S3.

[0063] Figure 4 This is a schematic diagram of the structure obtained after step S4.

[0064] Figure 5 This is a schematic diagram of the structure obtained after step S5.

[0065] Figure 6 This is a schematic diagram of the structure obtained after step S6.

[0066] Figure 7 This is a schematic diagram of the structure obtained after step S7.

[0067] Figure 8 This is a schematic diagram of the structure obtained after step S8.

[0068] Figure 9 This is a schematic diagram of the structure obtained after step S9.

[0069] Figure 10 This is a schematic diagram of the structure obtained after step S10.

[0070] Figure 11 This is a schematic diagram of the structure obtained after step S11.

[0071] Figure 12 This is a schematic diagram of the structure obtained after step S12.

[0072] Figure 13 This is a schematic diagram of the structure obtained after step S13.

[0073] Figure 14 This is a schematic diagram of the structure obtained after step S14.

[0074] 1. SiC substrate, 2. n-type SiC epitaxial layer, 3. p-type SiC shielding region, 4. n + 5. p-type GaN ion implantation region; 6. oxide layer; 7. Ohmic contact metal source of SiC N-type channel MOSFET; 8. Ohmic contact metal drain of SiC N-type channel MOSFET; 9. Ohmic contact metal source of GaN P-type channel MOSFET; 10. Ohmic contact metal drain of GaN P-type channel MOSFET; 11. Schottky contact metal gate of GaN P-type channel MOSFET; 12. Schottky contact metal gate of SiC N-type channel MOSFET. Detailed Implementation

[0075] The present invention will be further described below with reference to the embodiments and accompanying drawings, but is not limited thereto.

[0076] Example 1:

[0077] A high-temperature resistant, high-performance CMOS based on a SiC substrate, such as Figure 14 As shown, the structure includes a SiC substrate 1 and an n-type SiC epitaxial layer 2 grown on the SiC substrate 1. Above the n-type SiC epitaxial layer 2 is a p-type GaN epitaxial layer 5, and above the p-type GaN epitaxial layer 5 is an oxide layer 6. On both sides of the oxide layer 6 are formed ohmic contact metal source 9 and ohmic contact metal drain 10 for a GaN p-type channel MOSFET. Above the oxide layer 6 is a Schottky contact metal gate 11 for a GaN p-type channel MOSFET, forming a GaN p-type channel MOSFET. Another portion of the n-type SiC epitaxial layer 2 contains a p-type SiC shielding region 3, and the p-type SiC shielding region 3 contains two symmetrical n-type SiC epitaxial layers. + Type 4 SiC ion implantation region, two n +Above the SiC ion-implanted region 4, ohmic contact metal source 7 and ohmic contact metal drain 8 of a SiC N-channel MOS transistor are respectively fabricated, with the remaining surface covered by an oxide layer 6. Above the oxide layer 6 between the ohmic contact metal source 7 and ohmic contact metal drain 8 of the SiC N-channel MOS transistor is the Schottky contact metal gate 12 of the SiC N-channel MOS transistor. The ohmic contact metal drain 10 of the GaN P-channel MOS transistor is connected to the ohmic contact metal drain 8 of the SiC N-channel MOS transistor through metal deposition, and the Schottky contact metal gate 11 of the GaN P-channel MOS transistor is connected to the Schottky contact metal gate 12 of the SiC N-channel MOS transistor through metal deposition, forming a CMOS device on a SiC substrate. The p-type SiC shielding region 3 and the p-type GaN epitaxial layer 5 are both fabricated in different regions on the n-type SiC epitaxial layer.

[0078] The doping concentration of the n-type SiC epitaxial layer 2 is 5 × 10⁻⁶. 15 cm -3 The thickness of the n-SiC epitaxial layer 2 is 10 μm; the doping concentration of the p-type SiC shielding region is 5 × 10⁻⁶. 16 cm -3 The thickness of the p-type SiC shielding region is 500 nm. + The ion doping concentration of the SiC ion implantation region is 1×10⁻⁶. 18 cm -3 ,n + The thickness of the SiC ion-implanted region is 1 μm. The ion doping concentration of the p-type GaN epitaxial layer is 1 × 10⁻⁶. 19 cm -3 The thickness of the p-type GaN epitaxial layer is 100 nm. The thickness of the oxide layer is 50 nm. For the SiC N-type channel MOSFET, the ohmic contact metal source and drain are made of Ni metal, and the Schottky contact metal gate is also made of Ni metal. For the GaN P-type channel MOSFET, the ohmic contact metal source and drain are made of a Ti / Al / Ni / Au metal stack, and the Schottky contact metal gate is made of a Ni / Au metal stack.

[0079] Traditional semiconductor material Si, due to its inherent properties, is more suitable for system electronic devices and integrated circuits in low- to medium-temperature environments. At high temperatures, the intrinsic carrier concentration of Si increases dramatically, and the self-heating effect causes problems such as increased junction temperature and a surge in leakage current, leading to severe device drift and affecting reliability. Although high-temperature resistant Si devices have made significant progress over decades of research, they still cannot break through their theoretical limits. Therefore, Si-based CMOS cannot adapt to harsh operating environments such as high temperatures, and its maximum operating temperature generally does not exceed 200℃. In contrast, third-generation semiconductor material SiC has a large bandgap, and its intrinsic carrier concentration remains low even in high-temperature environments. Furthermore, due to its high thermal conductivity, SiC accelerates heat dissipation, significantly alleviating the heat dissipation pressure on devices. Therefore, SiC devices can operate stably at 600℃. In addition, SiC has a large breakdown electric field and low on-resistance. Combined with the higher saturation drift velocity and hole mobility of p-type GaN, this allows CMOS devices to achieve higher breakdown voltage, higher power density, and lower power loss.

[0080] Example 2

[0081] The high-temperature resistant, high-performance CMOS based on a SiC substrate provided in Example 1 differs in that:

[0082] The doping concentration of the n-type SiC epitaxial layer 2 is 1×10⁻⁶. 15 cm -3 The thickness of the n-SiC epitaxial layer 2 is 5 μm.

[0083] The doping concentration of p-type SiC shielding region 3 is 1×10⁻⁶. 16 The thickness of the p-type SiC shielding region 3 is 400 nm.

[0084] n + The ion doping concentration of SiC ion implantation region 4 is 5 × 10⁻⁶. 17 cm -3 ;n + The thickness of the SiC ion implantation region 4 is 0.5 μm.

[0085] The ion doping concentration of p-type GaN epitaxial layer 5 is 1×10⁻⁶. 18 cm -3 The thickness of the p-type GaN epitaxial layer 5 is 70 nm.

[0086] The thickness of oxide layer 6 is 30 nm.

[0087] The materials of the ohmic contact metal source 7 and ohmic contact metal drain 8 of the SiC N-channel MOSFET are Al / Ti metal stacks.

[0088] The material of the Schottky contact metal gate 12 of the SiC N-channel MOSFET is a Ni / Au metal stack;

[0089] The materials of the ohmic contact metal source 9 and ohmic contact metal drain 10 of the GaN P-type channel MOSFET are Ti / Al / Ti / Au metal stacks.

[0090] The material of the Schottky contact metal gate 11 of the GaN P-channel MOSFET is a Pt / Au alloy.

[0091] Example 3

[0092] The high-temperature resistant, high-performance CMOS based on a SiC substrate provided in Example 1 differs in that:

[0093] The doping concentration of the n-type SiC epitaxial layer 2 is 1×10⁻⁶. 16 cm -3 The thickness of the n-SiC epitaxial layer 2 is 15 μm.

[0094] The doping concentration of p-type SiC shielding region 3 is 1×10⁻⁶. 17 cm -3 The thickness of the p-type SiC shielding region 3 is 600 nm.

[0095] n + The ion doping concentration of SiC ion implantation region 4 is 5 × 10⁻⁶. 18 cm -3 ;n + The thickness of the SiC ion implantation region 4 is 1.5 μm.

[0096] The ion doping concentration of p-type GaN epitaxial layer 5 is 1×10⁻⁶. 20 cm -3 The thickness of the p-type GaN epitaxial layer 5 is 130 nm.

[0097] The thickness of oxide layer 6 is 70 nm.

[0098] The materials of the ohmic contact metal source 7 and ohmic contact metal drain 8 of the SiC N-channel MOSFET are Ni / Ti / Ni metal stacks.

[0099] The material of the Schottky contact metal gate 12 of the SiC N-channel MOSFET is a Ti / Au metal stack;

[0100] The materials of the ohmic contact metal source 9 and ohmic contact metal drain 10 of the GaN P-type channel MOSFET are Ti / Al / Mo / Au metal stacks.

[0101] The material of the Schottky contact metal gate 11 of the GaN P-channel MOSFET is a Pd / Au metal stack.

[0102] Example 4

[0103] The method for fabricating a high-temperature resistant, high-performance CMOS on a SiC substrate as described in Example 1 includes the following steps:

[0104] S1, such as Figure 1 As shown, an n-type SiC epitaxial layer 2 is grown on SiC substrate 1;

[0105] S2, such as Figure 2 As shown, a p-type SiC shielding region 3 is prepared in a specific region of the n-type SiC epitaxial layer 2 and then subjected to high-temperature annealing;

[0106] In step S2, a p-type SiC shielding region 3 is prepared on the n-SiC epitaxial layer 2 by ion implantation technology.

[0107] S3, such as Figure 3 As shown, n is prepared in a specific region of the p-type SiC shielding region 3. + Type 4 SiC ion implantation region, followed by high-temperature annealing;

[0108] In step S3, n-type SiC shielded region 3 is prepared by ion implantation. + Type 4 SiC ion implantation region.

[0109] S4, such as Figure 4 As shown, a p-type GaN epitaxial layer 5 is grown on the other side of the n-type SiC epitaxial layer 2;

[0110] In step S4, a p-type GaN epitaxial layer 5 is grown using metal-organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE).

[0111] In step S4, the p-type GaN epitaxial layer 5 is grown using metal-organic chemical vapor deposition (MOCVD), specifically including the following steps:

[0112] S4-1. Deposit a mask layer on the n-type SiC epitaxial layer 2;

[0113] S4-2. Using photolithography on the mask layer, the metal-organic chemical vapor deposition growth region is exposed;

[0114] S4-3. Remove the mask layer from the growth area of ​​the metal-organic chemical vapor deposition method, and retain the mask layer in other areas to achieve mask layer patterning;

[0115] S4-4. Grow p-type GaN epitaxial layers using metal-organic chemical vapor deposition equipment;

[0116] S4-5. Remove the mask layer and the p-type GaN epitaxial layer above it using a stripping process.

[0117] S5, such as Figure 5 As shown, an oxide layer 6 is grown on the surface;

[0118] In step S5, an oxide layer 6 is grown using atomic layer deposition (ALD); the oxide layer above SiC can be grown using a high-temperature thermal oxidation furnace.

[0119] S6, such as Figure 6 As shown, the oxide layer 6 above the ohmic contact metal source and ohmic contact metal drain of SiC N-channel MOSFET and GaN P-channel MOSFET is removed.

[0120] In step S6, the oxide layer is removed by inductively coupled plasma etching (ICP) or wet etching with buffered oxide etchant.

[0121] In step S6, the specific process of etching the oxide layer using inductively coupled plasma etching (ICP) is as follows:

[0122] S6-1. Coat the oxide layer with photoresist;

[0123] S6-2. Using photolithography and development technology, the oxide layer area to be etched is exposed on the photoresist;

[0124] S6-3. Etching the oxide layer using an inductively coupled plasma device;

[0125] S6-4. Remove the coated photoresist and completely remove the oxide layer above the ohmic contact metal source and ohmic contact metal drain of SiC N-channel MOS transistors and GaN P-channel MOS transistors.

[0126] S7, such as Figure 7 As shown, in n + SiC N-channel MOS transistor ohmic contact metal source 7 and ohmic contact metal drain 8 are deposited on the SiC ion implantation region 4 and then annealed.

[0127] S8, such as Figure 8 As shown, GaN P-channel MOS transistor ohmic contact metal source 9 and ohmic contact metal drain 10 are deposited on the p-type GaN epitaxial layer 5 and then annealed.

[0128] S9, such as Figure 9 As shown, a Schottky contact metal gate 11 is deposited on the oxide layer between the ohmic contact metal source 9 and the ohmic contact metal drain 10 of the GaN P-type channel MOS transistor.

[0129] S10, such as Figure 10 As shown, a Schottky contact metal gate 12 is deposited on the oxide layer between the ohmic contact metal source 7 and the ohmic contact metal drain 8 of the SiC N-channel MOS transistor.

[0130] S11, such as Figure 11 As shown, the ohmic contact metal drain 8 of the SiC N-channel MOSFET and the ohmic contact metal drain 10 of the GaN P-channel MOSFET are electrically (by electrode deposition) connected.

[0131] S12, such as Figure 12 As shown, the Schottky contact metal gate 12 of the SiC N-channel MOSFET and the Schottky contact metal gate 11 of the GaN P-channel MOSFET are electrically (by electrode deposition) connected.

[0132] S13, such as Figure 13 As shown, the ohmic contact metal source 9 of the GaN P-type channel MOS transistor is led out.

[0133] S14, such as Figure 14 As shown, the ohmic contact metal source 7 of the SiC N-channel MOS transistor is led out.

Claims

1. A high-temperature resistant, high-performance CMOS based on a SiC substrate, characterized in that, The transistor comprises a SiC substrate and an n-type SiC epitaxial layer grown on the SiC substrate. A p-type GaN epitaxial layer is formed on top of the n-type SiC epitaxial layer, and an oxide layer is formed above the p-type GaN epitaxial layer. Ohmic contact metal source and ohmic contact metal drain are formed on both sides of the oxide layer, and a Schottky contact metal gate is formed above the oxide layer, forming a GaN p-type channel MOS transistor. Another portion of the n-type SiC epitaxial layer contains a p-type SiC shielding region, within which are two symmetrical n-type SiC shielding regions. + Type SiC ion implantation region, two n + An ohmic contact metal source and an ohmic contact metal drain are fabricated above the ion-implanted region of a SiC substrate, with the remaining surface covered by an oxide layer. A Schottky contact metal gate is disposed above the oxide layer between the ohmic contact metal source and the ohmic contact metal drain, forming a SiC N-channel MOS transistor. The ohmic contact metal drain of the GaN P-channel MOS transistor is connected to the ohmic contact metal drain of the SiC N-channel MOS transistor, and the Schottky contact metal gate of the GaN P-channel MOS transistor is connected to the Schottky contact metal gate of the SiC N-channel MOS transistor, forming a CMOS device on a SiC substrate.

2. The high-temperature resistant, high-performance CMOS based on a SiC substrate according to claim 1, characterized in that, The doping concentration of the n-type SiC epitaxial layer is 1×10⁻⁶. 15 - 1×10 16 cm -3 The thickness of the n-type SiC epitaxial layer is 5-15 μm.

3. The high-temperature resistant, high-performance CMOS based on a SiC substrate according to claim 2, characterized in that, The doping concentration of the n-type SiC epitaxial layer is 5 × 10⁻⁶. 15 cm -3 The thickness of the n-type SiC epitaxial layer is 10 μm.

4. The high-temperature resistant, high-performance CMOS based on a SiC substrate according to claim 1, characterized in that, The doping concentration of the p-type SiC shielding region is 1×10⁻⁶. 16 - 1×10 17 cm -3 The thickness of the p-type SiC shielding region is 400-600 nm.

5. The high-temperature resistant, high-performance CMOS based on a SiC substrate according to claim 4, characterized in that, The doping concentration of the p-type SiC shielding region is 5 × 10⁻⁶. 16 cm -3 The thickness of the p-type SiC shielding region is 500 nm.

6. The high-temperature resistant, high-performance CMOS based on a SiC substrate according to claim 1, characterized in that, n + The ion doping concentration of the SiC ion implantation region is 5 × 10⁻⁶. 17 - 5×10 18 cm -3 ;n + The thickness of the SiC ion implantation region is 0.5-1.5 μm.

7. The high-temperature resistant, high-performance CMOS based on a SiC substrate according to claim 6, characterized in that, n + The ion doping concentration of the SiC ion implantation region is 1×10⁻⁶. 18 cm -3 , n + The thickness of the SiC ion implantation region is 1 μm.

8. The high-temperature resistant, high-performance CMOS based on a SiC substrate according to claim 1, characterized in that, The ion doping concentration of the p-type GaN epitaxial layer is 1×10⁻⁶. 18 - 1×10 20 cm -3 The thickness of the p-type GaN epitaxial layer is 70-130 nm.

9. The high-temperature resistant, high-performance CMOS based on a SiC substrate according to claim 8, characterized in that, The ion doping concentration of the p-type GaN epitaxial layer is 1×10⁻⁶. 19 cm -3 The thickness of the p-type GaN epitaxial layer is 100 nm.

10. The high-temperature resistant, high-performance CMOS based on a SiC substrate according to claim 1, characterized in that, The thickness of the oxide layer is 30-70 nm.

11. The high-temperature resistant, high-performance CMOS based on a SiC substrate according to claim 10, characterized in that, The oxide layer is 50 nm thick.

12. The high-temperature resistant, high-performance CMOS based on a SiC substrate according to claim 1, characterized in that, The materials for the ohmic contact metal source and ohmic contact metal drain of the SiC N-channel MOSFET are any one of Ni metal, Al / Ti metal stack, and Ni / Ti / Ni metal stack. The material of the Schottky contact metal gate of the SiC N-channel MOSFET is any one of Ni metal, Ni / Au metal stack, or Ti / Au metal stack. The materials for the ohmic contact metal source and ohmic contact metal drain of the GaN P-type channel MOSFET are any one of Ti / Al / Ni / Au metal stack, Ti / Al / Ti / Au metal stack, or Ti / Al / Mo / Au metal stack. The material of the Schottky contact metal gate of a GaN P-type channel MOSFET is any one of Ni / Au metal stack, Pt / Au alloy, or Pd / Au metal stack.

13. A method for fabricating a high-temperature resistant, high-performance CMOS based on a SiC substrate as described in claim 1, characterized in that, The steps include the following: S1. Grow an n-type SiC epitaxial layer on a SiC substrate; S2. Prepare a p-type SiC shielding region in a specific region of the n-type SiC epitaxial layer and perform high-temperature annealing; the specific region mentioned in this step is located on one side of the n-type SiC epitaxial layer, from the upper surface of the n-type SiC epitaxial layer to the interior of the n-type SiC epitaxial layer; S3. Prepare n in a specific region of the p-type SiC shielding region. + The p-type SiC ion implantation region is subjected to high-temperature annealing; the specific region mentioned in this step is located on both sides of the p-type SiC shielding region in step S2, and extends from the upper surface of the p-type SiC shielding region to the interior of the p-type SiC shielding region. S4. Grow a p-type GaN epitaxial layer on the other side of the n-type SiC epitaxial layer; S5. An oxide layer is grown on the surface; S6. Remove the oxide layer above the ohmic contact metal source and ohmic contact metal drain of SiC N-channel MOSFET and GaN P-channel MOSFET. S7, in n + SiC N-channel MOS transistor ohmic contact metal source and ohmic contact metal drain are deposited on the SiC ion implantation region and then annealed. S8. Deposit the ohmic contact metal source and ohmic contact metal drain of the GaN P-type channel MOS transistor on the p-type GaN epitaxial layer, and then perform annealing treatment. S9. A Schottky contact metal gate is deposited on the oxide layer between the ohmic contact metal source and the ohmic contact metal drain of the GaN P-type channel MOSFET. S10. A Schottky contact metal gate is deposited on the oxide layer between the ohmic contact metal source and the ohmic contact metal drain of the SiC N-channel MOSFET. S11. Electrically connect the ohmic contact metal drain of the SiC N-channel MOSFET and the ohmic contact metal drain of the GaN P-channel MOSFET. S12. Electrically connect the Schottky contact metal gate of the SiC N-channel MOSFET and the Schottky contact metal gate of the GaN P-channel MOSFET. S13. Connect the ohmic contact metal source electrode of the GaN P-channel MOSFET. S14. Lead out the ohmic contact metal source electrode of the SiC N-channel MOS transistor.

14. The method for fabricating a high-temperature resistant, high-performance CMOS based on a SiC substrate according to claim 13, characterized in that, In step S2, a p-type SiC shielding region is prepared on an n-type SiC epitaxial layer using ion implantation technology; In step S3, n-type SiC shielded regions are prepared by ion implantation. + Type SiC ion implantation region; In step S4, a p-type GaN epitaxial layer is grown using metal-organic chemical vapor deposition or molecular beam epitaxy. In step S5, an oxide layer is grown using an atomic layer deposition (ALD) or low-pressure chemical vapor deposition (LPCVD) system; the oxide layer is grown using atomic layer deposition (ALD), and the oxide layer above SiC is grown using a high-temperature thermal oxidation furnace. In step S6, the oxide layer is removed by inductively coupled plasma etching (ICP) or wet etching with buffered oxide etchant.

15. The method for fabricating a high-temperature resistant, high-performance CMOS based on a SiC substrate according to claim 14, characterized in that, In step S4, a p-type GaN epitaxial layer is grown using metal-organic chemical vapor deposition, specifically including the following steps: S4-1. Deposit a mask layer on an n-type SiC epitaxial layer; S4-2. Using photolithography on the mask layer, the metal-organic chemical vapor deposition growth region is exposed; S4-3. Remove the mask layer from the growth area of ​​the metal-organic chemical vapor deposition method, and retain the mask layer in other areas to achieve mask layer patterning; S4-4. Grow p-type GaN epitaxial layers using metal-organic chemical vapor deposition equipment; S4-5. Remove the mask layer and the p-type GaN epitaxial layer above it using a stripping process; In step S6, the specific process of etching the oxide layer using inductively coupled plasma etching (ICP) is as follows: S6-1. Coat the oxide layer with photoresist; S6-2. Using photolithography and development technology, the oxide layer area to be etched is exposed on the photoresist; S6-3. Etching the oxide layer using an inductively coupled plasma device; S6-4. Remove the coated photoresist and completely remove the oxide layer above the ohmic contact metal source and ohmic contact metal drain of SiC N-channel MOS transistors and GaN P-channel MOS transistors.

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