A four-channel quadrature splitter-recombiner amplifier circuit

Abstract

The application provides a low-power four-channel quadrature splitting-recombining amplifier circuit, which comprises a four-layer stacked input stage circuit, a current copying sampling stage circuit and a current recombination output stage circuit; the four-layer stacked input stage only uses one current source, realizes four-channel differential mode voltage input through a four-layer stacked structure, and then is converted into sixteen current signals through quadrature splitting; the current copying sampling stage circuit copies and samples the sixteen current signals in proportion through a current mirror structure; the current recombination output stage comprises four groups of circuits, each group of circuits recombines and adds eight current signals, converts into a differential output voltage of one channel, and four groups of circuits finally generate four-channel differential output voltages. The amplifier of the application realizes low-power four-channel signal amplification function while avoiding crosstalk among multiple channels, on the basis of the four-layer stacked structure sharing one current source, and through splitting and recombination addition of only eight current signals for each channel.

Description

Technical Field

[0001] This invention belongs to the field of microelectronics technology, specifically relating to a four-channel orthogonal split-recombination amplifier circuit. Background Technology

[0002] In situations where medical resources are limited, portable vital sign monitoring devices can effectively alleviate pressure on hospitals and enable quick and convenient monitoring of vital signs. Assessing health can be achieved by detecting key signals in the body, such as electrocardiogram (ECG), electroencephalogram (EEG), and blood pressure. However, due to the irregular nature of cardiovascular and cerebrovascular diseases and the limitations of medical testing services, going to the hospital anytime, anywhere for ECG examinations is virtually impossible for these patients. With the development of new technologies such as the Internet of Medical Things (IoMT), integrated circuit technology, cloud computing, and wireless sensor nodes, portable vital sign monitoring devices have experienced rapid growth, and many medical hardware devices are becoming miniaturized, wireless, and intelligent. However, currently, portable vital sign monitoring devices are all battery-powered and can only collect vital sign signals from a single channel, unable to quantize and transmit signals, severely limiting the miniaturization of microelectronic devices and nodes, and the scope of portable monitoring applications for microelectronic devices.

[0003] Multi-channel, high-quality raw vital sign electrical signals are a crucial foundation for research and medical diagnosis in cardioencephalopathy and cerebrovascular diseases. High-precision, high signal-to-noise ratio, and high real-time performance of raw bioelectrical signals can fundamentally reduce the difficulty and complexity of signal processing and data analysis, thereby enabling more accurate diagnosis of brain neural activity. Because key human vital sign signals are diverse, extremely weak in amplitude, and cover a wide frequency range, higher demands are placed on the performance of vital sign detection and processing chips. Multi-chip systems often have to sacrifice device size and power consumption, significantly reducing the battery life and user experience of smart devices. Therefore, intelligent acquisition and processing systems for multi-channel biosignals not only need to acquire biosignals accurately, in real-time, and securely, but also must possess intelligent feature classification and extraction, and low-power wireless transceiver capabilities to enable portable vital sign monitoring and processing systems to be truly applied in daily life and clinical medicine.

[0004] Biosignal analog front-end amplifier circuits require two main characteristics: low power consumption and multiple channels. Therefore, they often employ multi-layer stacked input stages to orthogonally split multi-channel differential input signals into multiple current signals. These current signals are then replicated using a current mirror, and finally, specific current signals are selected and added together. After IV-V conversion in the output stage, the corresponding output voltage is generated, achieving signal amplification from four-channel differential input voltage to differential output voltage. Multi-layer stacked input stages can reduce the total supply voltage by using current multiplexing to operate each layer's input pairs in the subthreshold region, thus reducing power consumption. However, because the N-channel differential input voltage needs to be converted to 2... N The current signal of each path is copied, combined, and added together to convert it into a differential output voltage signal. Each path current will generate power consumption and will also increase the complexity of the circuit. Summary of the Invention

[0005] To address the aforementioned problems in the prior art, this invention provides a four-channel quadrature split-reassemble amplifier circuit. The technical problem to be solved by this invention is achieved through the following technical solution:

[0006] The present invention provides a four-channel quadrature split-reconstruction amplifier circuit comprising: a four-layer stacked input stage circuit 21, a current replication sampling stage circuit 22, and a current reconstruction output stage circuit 23 connected in sequence;

[0007] The four-layer stacked input stage circuit 21 uses a four-layer differential input pair structure to sequentially orthogonally split the input current source into two, four, eight, and sixteen current signals.

[0008] Among them, each of the sixteen current signals contains the input voltage information of the input pair transistors it passes through;

[0009] The current replication sampling stage circuit 22 uses a current mirror structure to sample and replicate sixteen current signals proportionally, generating two sets of identical current signals. Each set of current signals contains sixteen current signals, and the current signals within the same set are different.

[0010] The current reconstruction output stage circuit 23 selects four current signals from two identical current signals generated by the current replication sampling stage circuit 22 according to the expression of the four-channel differential output voltage. It then performs different combination calculations on the four current signals and generates four-channel differential output voltages through the IV conversion of the output stage. Each channel's differential output voltage includes both positive and negative voltage signals, realizing signal amplification from four-channel differential input voltage to differential output voltage.

[0011] The beneficial effects of this invention are:

[0012] This invention provides a four-channel orthogonal split-reconstruction amplifier circuit, comprising a four-layer stacked input stage circuit, a current replication sampling stage circuit, and a current reconstruction output stage circuit. The four-layer stacked input stage uses only one current source, achieving four-channel differential voltage input through the four-layer stacked structure. This voltage is then orthogonally split into sixteen current signals. The current replication sampling stage uses a current mirror structure to proportionally replicate and sample these sixteen current signals. The current reconstruction output stage contains four sets of circuits, each set reconstructing and summing eight current signals to convert them into a single channel's differential output voltage. The four sets of circuits ultimately produce four channels of differential output voltage. Based on a four-layer stacked structure sharing a single current source, this amplifier achieves low-power four-channel signal amplification by splitting, reconstructing, and summing only eight current signals per channel, thus avoiding crosstalk between multiple channels.

[0013] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0014] Figure 1 This is a schematic diagram of the circuit structure of a four-channel orthogonal split-reassemble amplifier according to the present invention;

[0015] Figure 2 The schematic diagram of a four-layer stacked input stage circuit is shown;

[0016] Figure 3 The schematic diagram of the current replication sampling stage circuit is shown;

[0017] Figure 4 The schematic diagram of the current recombination output stage circuit is shown;

[0018] Figure 5 Bode plots of the amplifier are shown at process angles TT, SS, and FF, and at -47°C, 27°C, and 125°C. Detailed Implementation

[0019] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0020] like Figure 1 As shown, the present invention provides a four-channel quadrature split-reconstruction amplifier circuit, including: a four-layer stacked input stage circuit 21, a current replication sampling stage circuit 22, and a current reconstruction output stage circuit 23 connected in sequence;

[0021] The four-layer stacked input stage circuit 21 uses a four-layer differential input pair structure to sequentially orthogonally split the input current source into two, four, eight, and sixteen current signals.

[0022] Among them, each of the sixteen current signals contains the input voltage information of the input pair transistors it passes through;

[0023] The current replication sampling stage circuit 22 uses a current mirror structure to sample and replicate sixteen current signals proportionally, generating two sets of identical current signals. Each set of current signals contains sixteen current signals, and the current signals within the same set are different.

[0024] The current reconstruction output stage circuit 23 selects four current signals from two identical current signals generated by the current replication sampling stage circuit 22 according to the expression of the four-channel differential output voltage. It then performs different combination calculations on the four current signals and generates four-channel differential output voltages through the IV conversion of the output stage. Each channel's differential output voltage includes both positive and negative voltage signals, realizing signal amplification from four-channel differential input voltage to differential output voltage.

[0025] refer to Figure 2 The four-layer stacked input stage circuit 21 includes: a first-layer differential input pair structure, a second-layer differential input pair structure, a third-layer differential input pair structure, and a fourth-layer differential input pair structure.

[0026] The first layer of differential input pair structure includes MOS transistors M1 and M2. The sources of M1 and M2 are connected and serve as the input terminals of the input current source. The gate of M1 is Vin1, and the gate of M2 is -Vin1.

[0027] The second-layer differential input pair structure includes MOSFETs M3-M6. The source of M3 and the source of M4 are connected to the drain of M1; the source of M5 and the source of M6 are connected to the drain of M2; the gate of M3 is Vin2, and the gate of M6 is Vin2 terminal; the gate of M4 is connected to the gate of M5 and serves as -Vin2 terminal.

[0028] The third-layer differential input pair structure includes MOSFETs M7-M14. The sources of M7 and M8 are connected to the drain of M3; the sources of M9 and M10 are connected to the drain of M4; the drains of M11, M12, and M5 are connected; the sources of M13 and M14 are connected to the drain of M6; the gates of M8 and M9 are connected together and serve as the -Vin3 terminal; the gates of M10 and M11 are connected together and serve as the Vin3 terminal; the gates of M12 and M13 are connected together and serve as the -Vin3 terminal; the gates of M7 and M14 are Vin3.

[0029] The fourth-layer differential input pair structure includes MOSFETs M15-M46; M i The source, M i+1 The source and M jThe drains are connected together, j takes values ​​from 7 to 14, and i = 2j + 1; when i is odd, M i+1 The gate and M i+2 The gates are connected together and serve as the -Vin4 terminal. When i is even, M i+1 The gate and M i+2 The gates are connected together and serve as the Vin4 terminal;

[0030] The gates of M31-M46 are connected together. The drain of M15 is connected to the drain of M31, the drain of M16 is connected to the drain of M32, the drain of M17 is connected to the drain of M32, the drain of M18 is connected to the drain of M33, the drain of M19 is connected to the drain of M34, the drain of M20 is connected to the drain of M35, the drain of M21 is connected to the drain of M36, the drain of M22 is connected to the drain of M37, the drain of M23 is connected to the drain of M38, the drain of M24 is connected to the drain of M39, the drain of M25 is connected to the drain of M40, and the drain of M26 is connected to the drain of M40. The drain of M27 is connected to the drain of M41; the drain of M28 is connected to the drain of M42; the drain of M29 is connected to the drain of M43; the drain of M30 is connected to the drain of M46; the source of M31 is connected to the source of M32; the source of M33 is connected to the source of M34; the source of M35 is connected to the source of M36; the source of M37 is connected to the source of M38; the source of M39 is connected to the source of M40; the source of M41 is connected to the source of M42; the source of M43 is connected to the source of M44; the source of M45 is connected to the source of M46; the sources of M31-M46 are all grounded.

[0031] Specifically, such as Figure 2As shown, in the four-layer stacked input stage, the lower end of the current source Ibias is connected to the source terminals of the differential input pair PMOS transistors M1 and M2. The positive input Vin1 of the first-channel differential input is connected to the gate terminal of M1, and the negative input -Vin1 of the first-channel differential input is connected to the gate terminal of M2. The drain terminal of M1 is connected to the source terminals of the differential input pair PMOS transistors M3 and M4, the drain terminal of M2 is connected to the source terminals of the differential input pair PMOS transistors M5 and M6, and the positive input Vin2 of the second-channel differential input is connected to the gate terminals of M3 and M6. The negative input -Vin2 is connected to the gate terminals of M4 and M5; the drain terminal of M3 is connected to the source terminals of the differential input pair PMOS transistors M7 and M8; the drain terminal of M4 is connected to the source terminals of the differential input pair PMOS transistors M9 and M10; the drain terminal of M5 is connected to the source terminals of the differential input pair PMOS transistors M11 and M12; the drain terminal of M6 is connected to the source terminals of the differential input pair PMOS transistors M13 and M14; the positive input Vin3 of the three-channel differential input is connected to the gate terminals of M7, M10, M11, and M14; and the negative input -Vin... Connect M3 to the gate terminals of M8, M9, M12, and M13; connect the drain of M7 to the source terminals of differential input pair PMOS transistors M15 and M16; connect the drain of M8 to the source terminals of differential input pair PMOS transistors M17 and M18; connect the drain of M9 to the source terminals of differential input pair PMOS transistors M19 and M20; connect the drain of M10 to the source terminals of differential input pair PMOS transistors M21 and M22; connect the drain of M11 to the source terminals of differential input pair PMOS transistors M23 and M24; and connect the drain of M12 to the differential input pair PMOS transistor M00. The source terminals of S-channel transistors M25 and M26 are connected to the source terminals of differential input PMOS transistors M27 and M28. The drain terminal of M13 is connected to the source terminals of differential input PMOS transistors M29 and M30. The positive input Vin4 of the four-channel differential input is connected to the gate terminals of M15, M18, M19, M22, M23, M26, M27, and M30. The negative input -Vin4 of the four-channel differential input is connected to the gate terminals of M16, M17, M20, M21, M24, M25, M28, and M29. The drain terminals of M15 to M30 are connected to the drain terminals of NMOS transistors M31 to M46 in sequence. The gate terminals of M31 to M46 are connected to the bias voltage Vbn1. The source terminals of M31 to M46 are grounded to GND. The source-drain small-signal currents of M15 to M30 are i1 to i16, respectively.

[0032] In this structure, the differential input pair structure of the first layer divides the input current source into two currents; then the two currents are further divided into four currents by the differential input pairs of the second layer with two sets of two channels; then the four currents are further divided into eight currents by the differential input pairs of the third layer with four sets of three channels; then the eight currents are further divided into sixteen currents by the differential input pairs of the fourth layer with eight sets of four channels, thus realizing the conversion of the differential input voltage of the four channels into sixteen current signals through the orthogonally split four-layer stacked structure.

[0033] Figure 2 A four-layer stacked input stage circuit according to the present invention is shown. A single-channel differential input is located in the first stage, with an input pair transistor width-to-length ratio of Wp / Lp; a two-channel differential input is located in the second stage, with an input pair transistor width-to-length ratio of Wp / 2Lp; a three-channel differential input is located in the third stage, with an input pair transistor width-to-length ratio of Wp / 4Lp; and a four-channel differential input is located in the fourth stage, with an input pair transistor width-to-length ratio of Wp / 8Lp. Assuming that the overdrive voltage of all differential input pairs is equal, then...

[0034]

[0035] in, This represents the transconductance of the first-layer input pair transistors M1 and M2. This indicates the transconductance of the second-layer input pair transistors M3 to M6. This indicates the transconductance of the third-layer input pair transistors M7 to M14. This indicates the transconductance of the fourth layer input pair transistors M15 to M30.

[0036] If current i1 comprises one times the current of M15, half the current of M7, one-quarter the current of M3, and one-eighth the current of M1, then...

[0037] Furthermore, all input transistor pairs are biased in the subthreshold region, which not only provides greater transconductance but also reduces power consumption. The expressions for all sixteen current matrices are as follows:

[0038]

[0039] refer to Figure 3 The current replication sampling stage circuit 22 includes 16 current replication sampling sub-circuits;

[0040] Each current replication sampling sub-circuit includes four MOSFETs. The sources of the first, second, and third MOSFETs are connected together and connected to the power supply VDD. The gates of the first, second, and third MOSFETs, the drain of the first MOSFET, and the drain of the fourth MOSFET are connected together.

[0041] In the Nth current replication sampling sub-circuit, the source of the fourth MOS transistor outputs the Nth current signal, and the drains of the second and third MOS transistors respectively output the replicated Nth current signal.

[0042] It should be noted that: in Figure 3 The structural characteristics of the medium current mirror itself, the input current is Figure 3 The input is represented by an arrow.

[0043] Specifically, such as Figure 3As shown, the current replication sampling stage 22 replicates i1 to i16 into two sets of I1 to I16 currents according to a ratio K. i1 is connected to the source of NMOS transistor M47, and the drain of M47 is connected to the gate of PMOS transistors M48, M49, and M50 and the drain of M48. The drains of M49 and M50 output equal current signals I1; i2 is connected to the source of NMOS transistor M51, and the drain of M51 is connected to the gate of PMOS transistors M52, M53, and M54 and the drain of M52. The drains of M53 and M54 output equal current signals I2; i3 is connected to the source of NMOS transistor M55, and the drain of M55 is connected to the gate of PMOS transistors M56, M57, and M58 and the drain of M56. The drains of M57 and M58 output equal current signals I3; i4 is connected to the source of NMOS transistor M59, and the drain of M59... The drain of transistor i5 is connected to the gate of PMOS transistors M60, M61, and M62, and the drain of M60. The drains of M61 and M62 output equal current signals I4. The drain of NMOS transistor M63 is connected to the source of NMOS transistor M63, and the drain of M63 is connected to the gate of PMOS transistors M64, M65, and M66, and the drain of M64. The drains of M65 and M66 output equal current signals I5. The drain of NMOS transistor M67 is connected to the source of NMOS transistor M67, and the drain of M67 is connected to the gate of PMOS transistors M68, M69, and M70, and the drain of M68. The drains of M69 and M70 output equal current signals I6. The drain of NMOS transistor M71 is connected to the source of PMOS transistor M71, and the drain of M71 is connected to the drain of PMOS transistors M72, M73, and M74. The gate and drain of M72, and the drains of M73 and M74 output equal current signals I7; i8 is connected to the source of NMOS transistor M75, and the drain of M75 is connected to the gate of PMOS transistors M76, M77, and M78, and the drain of M76. The drains of M77 and M78 output equal current signals I8; i9 is connected to the source of NMOS transistor M79, and the drain of M79 is connected to the gate of PMOS transistors M80, M81, and M82, and the drain of M80. The drains of M81 and M82 output equal current signals I9; i10 is connected to the source of NMOS transistor M83, and the drain of M83 is connected to the gate of PMOS transistors M84, M85, and M86, and the drain of M84. The drains of M85 and M86 output equal current signals I7; i8 is connected to the source of NMOS transistor M83, and the drain of M83 is connected to the gate of PMOS transistors M84, M85, and M86, and the drain of M84. i11 is connected to the source of NMOS transistor M87, and the drain of M87 is connected to the gate of PMOS transistors M88, M89, and M90, and the drain of M88. The drains of M89 and M90 output equal current signals I11. i12 is connected to the source of NMOS transistor M91, and the drain of M91 is connected to the gate of PMOS transistors M92, M93, and M94, and the drain of M92. The drains of M93 and M94 output equal current signals I12. i13 is connected to the source of NMOS transistor M95, and the drain of M95 is connected to the gate of PMOS transistors M96, M97, and M98, and the drain of M96. The drains of M97 and M98 output equal current signals I13.i14 is connected to the source of NMOS transistor M99. The drain of M99 is connected to the gates of PMOS transistors M100, M101, and M102, and the drain of M100. The drains of M101 and M102 output equal current signals I14. i15 is connected to the source of NMOS transistor M103. The drain of M103 is connected to the gates of PMOS transistors M104, M105, and M106, and the drain of M104. The drains of M105 and M106 output equal current signals I15. i16 is connected to the source of NMOS transistor M107. The drain of M107 is connected to the gates of PMOS transistors M108, M109, and M110, and the drain of M108. The drains of M109 and M109 output equal current signals I15. The current signal I16 is connected to the power supply terminal VDD for the following M48 to M50, M52 to M54, M56 to M58, M60 to M62, M64 to M66, M68 to M70, M72 to M74, M76 to M78, M80 to M82, M84 to M86, M88 to M90, M92 to M94, M96 to M98, M100 to M102, M104 to M106, and M108 to M110. The gate terminals of M47, M51, M55, M59, M63, M67, M71, M75, M79, M83, M87, M91, M95, M99, M103, and M107 are connected to the voltage bias Vbn2.

[0044] Figure 3 A current replication sampling stage circuit according to an embodiment of the present invention is shown. Based on the width-to-length ratio K of the current mirror transistor, i1 to i... 16 Transform sequentially into I1=(1 / K) i1 to I 16 =(1 / K) i 16 .

[0045] refer to Figure 4 The current recombination output stage circuit 23 includes four current recombination output sub-circuits, each of which includes six MOSFETs and a common-mode feedback CMFB.

[0046] In this configuration, the gates of the first and second MOSFETs are connected together. The source of the first MOSFET receives one set of four current signals, and the source of the second MOSFET receives another set of four current signals. The drains of the first and third MOSFETs are connected to the first output terminal of the common-mode feedback CMFB. The drains of the second and fourth MOSFETs are connected to the second output terminal of the common-mode feedback CMFB. The gates of the third and fourth MOSFETs are connected together as the Vbn3 terminal. The source of the third MOSFET is connected to the drain of the fifth MOSFET. The source of the fourth MOSFET is connected to the drain of the sixth MOSFET. The sources of the fifth and sixth MOSFETs are both grounded.

[0047] Specifically, such as Figure 4As shown, the current recombination output stage 23, based on the expression for the four-channel differential output voltage, selects and adds eight specific current signals, performs IV conversion on the output stage, and generates the corresponding differential output voltage, thus realizing signal amplification from four-channel differential input voltage to differential output voltage. Currents I11, I12, I15, and I16 are connected to the source of PMOS transistor M111; currents I1, I2, I5, and I6 are connected to the source of PMOS transistor M112; the drain of M111 is connected to the drain of NMOS transistor M113 and the negative output terminal Vout1- of the first-channel differential output voltage; the drain of M112 is connected to the drain of NMOS transistor M114 and the positive output terminal Vout1+ of the first-channel differential output voltage; the source of M113 is connected to the drain of NMOS transistor M115; the source of M114 is connected to the drain of NMOS transistor M116; and M111 and... The gate of M112 is connected to the voltage bias Vbp2; the gates of M113 and M114 are connected to the voltage bias Vbn3; the gates of M115 and M116 are connected to the common-mode feedback CMFB of the differential output; currents I11, I12, I8, and I7 are connected to the source of PMOS transistor M117; currents I3, I4, I15, and I16 are connected to the source of PMOS transistor M118; the drain of M117 is connected to the drain of NMOS transistor M119 and the negative output terminal Vout2- of the two-channel differential output voltage; the drain of M118 is connected to the drain of NMOS transistor M120 and the two-channel... The positive output terminal Vout2+ of the differential output voltage is connected to the source of M119, which is connected to the drain of NMOS transistor M121. The source of M120 is connected to the drain of NMOS transistor M122. The gates of M117 and M118 are connected to the voltage bias Vbp2. The gates of M119 and M120 are connected to the voltage bias Vbn3. The gates of M121 and M122 are connected to the common-mode feedback CMFB of the differential output. Currents I14, I13, I5, and I6 are connected to the source of PMOS transistor M123. Currents I1, I2, I9, and I10 are connected to the source of PMOS transistor M124. The drain of M123 is connected to the drain of NMOS transistor M125 and the negative output terminal Vout3- of the three-channel differential output voltage. The drain of M124 is connected to the drain of NMOS transistor M126 and the positive output terminal Vout3+ of the three-channel differential output voltage. The source of M125 is connected to the drain of NMOS transistor M127. The source of M126 is connected to the drain of NMOS transistor M128. The gates of M123 and M124 are connected to the voltage bias Vbp2. The gates of M125 and M126 are connected to the voltage bias Vbn3. The gates of M127 and M128 are connected to the common-mode feedback CMFB of the differential output terminal.Currents I14, I10, I7, and I3 are connected to the source of PMOS transistor M129; currents I13, I9, I8, and I4 are connected to the source of PMOS transistor M130; the drain of M129 is connected to the drain of NMOS transistor M131 and the negative output terminal Vout4- of the four-channel differential output voltage; the drain of M130 is connected to the drain of NMOS transistor M132 and the positive output terminal Vout4+ of the four-channel differential output voltage; the source of M131 is connected to the drain of NMOS transistor M133; the source of M132 is connected to the drain of NMOS transistor M134; the gates of M129 and M130 are connected to the voltage bias Vbp2; the gates of M131 and M132 are connected to the voltage bias Vbn3; and the gates of M133 and M134 are connected to the common-mode feedback CMFB of the differential output.

[0048] The first current recombination output sub-circuit in the current recombination output stage circuit 23 adds the currents of the first, second, fifth and sixth channels, and after IV conversion of the output stage, generates a positive output voltage of a differential output voltage channel; by adding the currents of the eleventh, twelfth, fifteenth and sixteenth channels, and after IV conversion of the output stage, it generates a negative output voltage of a differential output voltage channel.

[0049] The second current recombination output sub-circuit adds the currents from the third, fourth, fifteenth, and sixteenth channels, and generates a positive output voltage for the two-channel differential output voltage through the IV conversion of the output stage; it adds the currents from the seventh, eighth, eleventh, and twelfth channels, and generates a negative output voltage for the two-channel differential output voltage through the IV conversion of the output stage.

[0050] The third current recombination output sub-circuit adds the currents from the first, second, ninth, and tenth channels, and after IV conversion in the output stage, generates a positive output voltage for the three-channel differential output voltage; it adds the currents from the fifth, sixth, thirteenth, and fourteenth channels, and after IV conversion in the output stage, generates a negative output voltage for the three-channel differential output voltage.

[0051] The fourth current recombination output sub-circuit adds the currents from the fourth, eighth, ninth, and thirteenth channels, and after IV conversion in the output stage, generates a positive output voltage for the four-channel differential output voltage; it adds the currents from the third, seventh, tenth, and fourteenth channels, and after IV conversion in the output stage, generates a negative output voltage for the four-channel differential output voltage.

[0052] Figure 4 A current recombination output stage circuit according to the present invention is shown, based on... Figure 4 It can be seen that the four sets of differential voltage signals output are:

[0053]

[0054]

[0055] Where K represents the scaling factor for current replication in the current mirror. Routb This indicates the output resistance of the current recombination output stage.

[0056] According to the above formula, the four current signals can be recombined and added together, and then converted into the output voltage signal of each channel through the output resistor. The four-channel orthogonal split-recombination amplifier of this invention has three advantages. First, the vector matrix of the output voltage expression is orthogonal, thus eliminating cross-coupling interference between channels. Second, the amplifier gain can be adjusted by regulating the equivalent output resistance R. outb And the transconductance g of the input pair m Finally, because the amount of current that needs to be recombine and added is minimal, the power consumption of the entire amplifier can be reduced to a minimum.

[0057] Figure 5 The Bode plots of the amplifier according to the present invention are shown at process angles TT, SS, and FF, and at temperatures of -47°C, 27°C, and 125°C. Simulation results demonstrate that the low-power four-channel quadrature split-reassembler amplifier of the present invention maintains a phase margin of over 75° under different process angles and extreme temperature conditions, exhibiting excellent reliability.

[0058] This invention provides a low-power four-channel orthogonal split-reconstruction amplifier circuit, comprising a four-layer stacked input stage circuit, a current replication sampling stage circuit, and a current reconstruction output stage circuit. The four-layer stacked input stage uses only one current source, achieving four channels of differential voltage input through the four-layer stacked structure. This voltage is then orthogonally split into sixteen current signals. The current replication sampling stage uses a current mirror structure to proportionally replicate and sample these sixteen current signals. The current reconstruction output stage contains four sets of circuits, each set reconstructing and summing eight current signals to convert them into a single channel of differential output voltage. The four sets of circuits ultimately produce four channels of differential output voltage. Based on a four-layer stacked structure sharing a single current source, this amplifier achieves low-power four-channel signal amplification by splitting, reconstructing, and summing only eight current signals per channel, thus avoiding crosstalk between multiple channels.

[0059] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0060] Although this application has been described herein in conjunction with various embodiments, those skilled in the art will understand and implement other variations of the disclosed embodiments by reviewing the accompanying drawings, the disclosure, and the appended claims in carrying out the claimed application. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality.

[0061] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A four-channel quadrature split-reassemble amplifier circuit, characterized in that, include: The four-layer stacked input stage circuit (21), current replication sampling stage circuit (22), and current reconstruction output stage circuit (23) are connected in sequence. The four-layer stacked input stage circuit (21) sequentially splits the input current source into two, four, eight and sixteen current signals through a four-layer differential input pair structure. Among them, each of the sixteen current signals contains the input voltage information of the input pair transistors it passes through; The current replication sampling stage circuit (22) samples and replicates sixteen current signals proportionally through a current mirror structure to generate two identical sets of current signals. Each set of current signals contains sixteen current signals, and the current signals within the same set are different. The current reconstruction output stage circuit (23) selects four current signals from two identical current signals generated by the current replication sampling stage circuit (22) according to the expression of the four-channel differential output voltage, performs different combination calculations on the four current signals, and then generates four-channel differential output voltages through the IV conversion of the output stage. The differential output voltage of each channel includes positive and negative voltage signals, realizing signal amplification from four-channel differential input voltage to differential output voltage. The four-layer stacked input stage circuit (21) includes: a first-layer differential input pair structure, a second-layer differential input pair structure, a third-layer differential input pair structure, and a fourth-layer differential input pair structure; The first layer of differential input pair structure includes MOS transistors M1 and M2. The sources of M1 and M2 are connected and serve as the input terminals of the input current source. The gate of M1 is Vin1, and the gate of M2 is -Vin1. The second-layer differential input pair structure includes MOSFETs M3-M6. The source of M3 and the source of M4 are connected to the drain of M1; the source of M5 and the source of M6 are connected to the drain of M2; the gate of M3 is Vin2, and the gate of M6 is Vin2 terminal; the gate of M4 is connected to the gate of M5 and serves as -Vin2 terminal. The third-layer differential input pair structure includes MOSFETs M7-M14. The sources of M7 and M8 are connected to the drain of M3; the sources of M9 and M10 are connected to the drain of M4; the drains of M11, M12, and M5 are connected; the sources of M13 and M14 are connected to the drain of M6; the gates of M8 and M9 are connected together and serve as the -Vin3 terminal; the gates of M10 and M11 are connected together and serve as the Vin3 terminal; the gates of M12 and M13 are connected together and serve as the -Vin3 terminal; the gates of M7 and M14 are Vin3. The fourth-layer differential input pair structure includes MOSFETs M15-M46; M i The source, M i+1 The source and M j The drains are connected together, j takes values ​​from 7 to 14, and i = 2j + 1; when i is odd, M i+1 The gate and M i+2 The gates are connected together and serve as the -Vin4 terminal. When i is even, M i+1 The gate and M i+2 The gates are connected together and form the Vin4 terminal.

2. The four-channel quadrature split-reassemble amplifier circuit according to claim 1, characterized in that, The gates of M31-M46 are connected together. The drain of M15 is connected to the drain of M31. The drain of M16 is connected to the drain of M32. The drain of M17 is connected to the drain of M32. The drain of M18 is connected to the drain of M33. The drain of M19 is connected to the drain of M34. The drain of M20 is connected to the drain of M35. The drain of M21 is connected to the drain of M36. The drain of M22 is connected to the drain of M37. The drain of M23 is connected to the drain of M46. The drain of M38 is connected; the drain of M24 is connected to the drain of M39; the drain of M25 is connected to the drain of M40; the drain of M26 is connected to the drain of M40; the drain of M27 is connected to the drain of M41; the drain of M28 is connected to the drain of M42; the drain of M29 is connected to the drain of M43; the drain of M30 is connected to the drain of M46; the source of M31 is connected to the source of M32; the source of M33 is connected to the source of M34. The source of M35 is connected to the source of M36; the source of M37 is connected to the source of M38; the source of M39 is connected to the source of M40; and the source of M41 is connected to the source of M42. The source of M43 is connected to the source of M44; the source of M45 is connected to the source of M46. The sources of M31-M46 are all grounded.

3. The four-channel quadrature split-reassemble amplifier circuit according to claim 2, characterized in that, The first layer of differential input transistor structure divides the input current source into two current paths; then the two current paths are further divided into four current paths by the second layer with two sets of two-channel differential input transistors; then the four current paths are further divided into eight current paths by the third layer with four sets of three-channel differential input transistors; then the eight current paths are further divided into sixteen current paths by the fourth layer with eight sets of four-channel differential input transistors, thus realizing the conversion of the four-channel differential input voltage into sixteen current signals through the orthogonally split four-layer stacked structure.

4. The four-channel orthogonal split-reassemble amplifier circuit according to claim 1, characterized in that, The current replication sampling stage circuit (22) includes 16 current replication sampling sub-circuits; Each current replication sampling sub-circuit includes four MOSFETs. The sources of the first, second, and third MOSFETs are connected together and connected to the power supply VDD. The gates of the first, second, and third MOSFETs, the drain of the first MOSFET, and the drain of the fourth MOSFET are connected together. In the Nth current replication sampling sub-circuit, the source of the fourth MOSFET is connected to the Nth current signal; the source of the fourth MOSFET outputs the Nth current signal, and the drains of the second and third MOSFETs respectively output the replicated Nth current signal.

5. The four-channel quadrature split-reassemble amplifier circuit according to claim 1, characterized in that, The current recombination output stage circuit (23) includes four current recombination output sub-circuits, each of which includes six MOSFETs and a common-mode feedback CMFB. In this configuration, the gates of the first and second MOSFETs are connected together. The source of the first MOSFET receives one set of four current signals, and the source of the second MOSFET receives another set of four current signals. The drains of the first and third MOSFETs are connected to the first output terminal of the common-mode feedback CMFB. The drains of the second and fourth MOSFETs are connected to the second output terminal of the common-mode feedback CMFB. The gates of the third and fourth MOSFETs are connected together as the Vbn3 terminal. The source of the third MOSFET is connected to the drain of the fifth MOSFET. The source of the fourth MOSFET is connected to the drain of the sixth MOSFET. The sources of the fifth and sixth MOSFETs are both grounded.

6. The four-channel quadrature split-reassemble amplifier circuit according to claim 5, characterized in that, The first current reorganization output sub-circuit in the current reorganization output stage circuit (23) adds the currents of the first, second, fifth and sixth paths, and generates a positive output voltage of a differential output voltage through the IV conversion of the output stage; and generates a negative output voltage of a differential output voltage through the addition of the currents of the eleventh, twelfth, fifteenth and sixteenth paths, and generates a negative output voltage of a differential output voltage through the IV conversion of the output stage. The second current recombination output sub-circuit adds the currents from the third, fourth, fifteenth, and sixteenth channels, and generates a positive output voltage for the two-channel differential output voltage through the IV conversion of the output stage; it adds the currents from the seventh, eighth, eleventh, and twelfth channels, and generates a negative output voltage for the two-channel differential output voltage through the IV conversion of the output stage. The third current recombination output sub-circuit adds the currents from the first, second, ninth, and tenth channels, and after IV conversion by the output stage, generates a positive output voltage for the three-channel differential output voltage. By summing the currents of the fifth, sixth, thirteenth, and fourteenth channels and converting them through the IV conversion of the output stage, a negative output voltage of the three-channel differential output voltage is generated. The fourth current recombination output sub-circuit adds the currents from the fourth, eighth, ninth, and thirteenth channels, and after IV conversion in the output stage, generates a positive output voltage for the four-channel differential output voltage. By summing the currents from the third, seventh, tenth, and fourteenth channels and performing IV conversion in the output stage, a negative output voltage of the four-channel differential output voltage is generated.

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