A noise-shaping successive approximation analog-to-digital converter and its control method
By combining a capacitive charge pump with passive integration, passive and lossless integration is achieved, which solves the problem of weak noise shaping effect of passive integration, reduces power consumption and enhances noise shaping effect, while compensating for signal loss and simplifying circuit design.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2023-03-10
- Publication Date
- 2026-04-03
AI Technical Summary
Traditional passive integrator loop filters have weak noise shaping effects, low power consumption, and strong robustness, but their noise transfer function is smooth; active integrator loop filters have high power consumption, complex circuitry, and are sensitive to changes in manufacturing processes.
By combining a capacitive charge pump with passive integration, passive and lossless integration is achieved. The capacitive charge pump compensates for the loss of residual voltage signal, while the passive integration provides low power consumption and good noise shaping effect.
It achieves low power consumption and strong noise shaping effect through passive integration, while compensating for part of the signal loss of the margin voltage and simplifying the subsequent circuit design.
Smart Images
Figure CN116405032B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of integrated circuit technology, specifically relating to a noise-shaping successive approximation analog-to-digital converter and its control method. Background Technology
[0002] As a channel between the analog and digital domains, analog-to-digital converters (ADCs) are facing increasingly higher performance requirements, especially in high-precision sensors, audio decoders, and wearable medical applications, where the demand for high-precision ADCs is even greater.
[0003] In traditional architectures, successive approximation architecture analog-to-digital converters (ADCs) are highly efficient, consume little power, and have good process compatibility. However, they suffer from drawbacks such as serial conversion and low sampling rate. Furthermore, the requirement for comparator noise increases exponentially with the number of bits, which limits their development in terms of high precision. Σ-Δ architecture ADCs have very high precision, but they have low sampling rate and efficiency, high power consumption, and poor compatibility with advanced processes, which limits their development in terms of low power consumption.
[0004] Noise-shaping successive approximation analog-to-digital converters (ADCs) combine the advantages of successive approximation ADCs and Σ-Δ ADCs, exhibiting both low power consumption and high accuracy, demonstrating good potential for high efficiency and low cost. For noise-shaping successive approximation ADCs employing a cascaded integral feedback architecture, the design of the loop filter in the loop filtering stage is crucial for achieving good noise shaping. When using an integrator as the loop filter, two types can be used: active integrator and passive integrator. Passive integrator loop filters are simple, have low power consumption, and are robust, but their noise transfer function is smooth, resulting in a weaker noise shaping effect. Active integrator loop filters can achieve a clear noise transfer function and have good noise shaping effect, but they have high power consumption, are more sensitive to process variations, and have complex circuitry. Summary of the Invention
[0005] To address the shortcomings of existing technologies, such as the simplicity, low power consumption, and robustness of passive integrator loop filters, which result in smooth noise transfer functions but weak noise shaping effects, and the high power consumption, sensitivity to process variations, and circuit complexity of active integrator loop filters, this invention provides a noise-shaping successive approximation analog-to-digital converter and its control method. This invention combines a capacitive charge pump with passive integrator technology to achieve a passive, lossless integrator loop filter. This allows it to retain the advantages of passive integrator technology (low power consumption and robustness) while providing strong noise shaping (achieving a clear noise transfer function). Simultaneously, the capacitive charge pump provides a certain gain, which can compensate for some signal loss due to the margin voltage, reducing the difficulty of subsequent circuit design.
[0006] This invention is achieved through the following technical solution:
[0007] A noise-shaping successive approximation analog-to-digital converter includes a sample-and-hold circuit, a comparator, a logic control circuit, a digital-to-analog converter, and a loop filter; the input of the sample-and-hold circuit is connected to the analog input V. in Used for analog input V in The sample-and-hold operation is performed; the output of the sample-and-hold circuit and the output of the digital-to-analog converter are both connected to the input of the loop filter; the output of the loop filter is connected to the input of the comparator, which has M inputs and is used to compare the integral margin voltage with the margin voltage; the output of the comparator is connected to the input of the logic control circuit, which is used to send the comparator result to the logic control circuit for logical operation; the output of the logic control circuit is connected to the input of the digital-to-analog converter, which is used to output an N-bit digital code and convert the output N-bit digital code into an analog voltage through the digital-to-analog converter and feed it back to the loop filter for the next step of the operation.
[0008] Furthermore, each cycle of the noise-shaping successive approximation analog-to-digital converter sequentially includes a sample-and-hold phase, a successive approximation conversion phase, and a loop filtering phase; the sample-and-hold phase is used to process the analog input voltage V. in The sampling and holding process is performed. The successive approximation conversion stage is used to switch the digital-to-analog converter to generate the voltage required for the successive approximation stage, which is then fed into the comparator. The successive approximation operation is completed using the comparison result of the comparator. The loop filtering stage is used to perform noise shaping on the margin voltage using the loop filter, and the integrated margin voltage is then fed into the comparator.
[0009] Furthermore, the loop filter includes a switch φ OUT φ RS Sampling margin voltage capacitor C RES and capacitor-type charge pump; switch φ OUT Connected to the digital-to-analog converter array capacitor C DAC Upper plate and sampling margin voltage capacitor C RES Between the upper plates, switch φ RS Connected to the sampling margin voltage capacitor C RES Between the upper and lower plates (lower plate grounded), the sampling margin voltage capacitor C RES The upper plate is connected to the input terminal of a capacitive charge pump; the capacitive charge pump includes multiple integrating capacitors C. INT1 With multiple switches; the multiple switches are used to regulate multiple integrating capacitors C INT1 Parallel and series connections; the working process of the loop filter includes a reset stage, a margin voltage sampling stage, and an integration stage; among which, the switch φ OUTThe conduction period is used for the margin voltage sampling stage, switch φ RS The conduction period of the capacitor charge pump is used for the reset phase, and the conduction period of the capacitor charge pump switch is used for the integration phase; sampling margin voltage capacitor C RES Used with digital-to-analog converter array capacitor C DAC Charge sharing is performed during the margin voltage sampling phase.
[0010] Further, the integrating capacitor includes a first integrating capacitor and a second integrating capacitor; the switch includes a switch connecting the input terminal of the capacitive charge pump to the upper plate of the first integrating capacitor, two switches connected in parallel between the first integrating capacitor and ground, a switch connecting the upper plate of the first integrating capacitor and the upper plate of the second integrating capacitor, a switch connecting the upper plate of the first integrating capacitor and the lower plate of the second integrating capacitor, and a switch connecting the second integrating capacitor and ground; the two integrating capacitors C INT1 In φ NS1 Parallel connection is used during conduction, at φ NS1_1 During conduction, a series connection is used for the first integration phase.
[0011] On the other hand, the present invention also provides a control method for a noise-shaping successive approximation analog-to-digital converter, specifically including the following steps:
[0012] First, during the reset phase, control the sampling margin voltage capacitor C. RES The switch clears the charge remaining from the previous cycle; the integrating capacitor C... INT1 The remaining charge on the capacitor is not cleared; then, the sampling margin voltage capacitor C is controlled. RES The switch performs digital-to-analog converter array capacitor C DAC With sampling margin voltage capacitor C RES The charge sharing is used for passive sampling, entering the margin voltage sampling stage. After the successive approximation conversion stage operation and the loop filter reset stage operation in the noise shaping successive approximation analog-to-digital converter cycle are completed, the margin voltage is obtained on the digital-to-analog converter. The margin voltage is the difference between the analog input voltage obtained by the sample-and-hold circuit and the analog voltage corresponding to the output digital code, and it is sampled. Then, by controlling the integration capacitor switch and changing the series and parallel connection of the capacitors in the capacitive charge pump, the integration loss and signal loss existing in the traditional passive integration are compensated, and passive lossless integration is achieved.
[0013] Compared with the prior art, the advantages of the present invention are as follows:
[0014] The present invention discloses a noise-shaping successive approximation analog-to-digital converter and control method, which combines a capacitive charge pump with passive integration to achieve passive and lossless integration. This gives it the advantages of passive integration while providing a strong noise-shaping effect. At the same time, the capacitive charge pump has a certain gain, which can compensate for part of the signal loss of the margin voltage and reduce the design difficulty of subsequent circuits. Attached Figure Description
[0015] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the accompanying drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. In all the drawings, similar elements or parts are generally identified by similar reference numerals. In the drawings, the elements or parts are not necessarily drawn to scale.
[0016] Figure 1 This is a schematic diagram of the structure of a noise-shaping successive approximation analog-to-digital converter according to the present invention;
[0017] Figure 2 This is a schematic diagram of traditional passive integrating signal loss and integration loss;
[0018] Figure 3 This is a schematic diagram of a traditional first-order passive integrator loop filter;
[0019] Figure 4 This is a schematic diagram of the first-order passive lossless integral loop filter of the present invention;
[0020] Figure 5 This is a schematic diagram of a capacitive charge pump. Detailed Implementation
[0021] To clearly and completely describe the technical solution and its specific working process of the present invention, the specific embodiments of the present invention are as follows, in conjunction with the accompanying drawings:
[0022] Example 1
[0023] Figure 1 This embodiment provides a schematic diagram of a noise-shaping successive approximation analog-to-digital converter (ADC); the successive approximation ADC includes a sample-and-hold circuit, a comparator, a logic control circuit, a digital-to-analog converter, a loop filter, and a capacitive charge pump.
[0024] The noise-shaping successive approximation analog-to-digital converter provided in this embodiment includes a sample-and-hold stage, a successive approximation conversion stage, and a loop filtering stage; wherein, the sample-and-hold circuit operates in the sample-and-hold stage, and its input terminal is connected to the analog input V. in Used for analog input V inThe system performs a sample-and-hold operation. The comparator, logic control circuit, and digital-to-analog converter (DAC) operate in the successive approximation conversion stage. The comparator's output is connected to the logic control circuit's input, feeding the comparator result into the logic control circuit for logical operations. The DAC's input is connected to the logic control circuit's output, which feeds back the comparison result to the DAC. The DAC converts the result into an analog voltage, which is then fed back to the loop filter, simultaneously outputting an N-bit digital code. The loop filter operates in the loop filtering stage, with its output connected to the comparator's input. The comparator can have M input ports for comparing the integral margin voltage with the margin voltage.
[0025] like Figure 2 The diagram shows the traditional passive integral signal loss and integral loss. Taking the first-order integral as an example, it is the signal flow graph of a noise-shaping successive approximation analog-to-digital converter based on passive sampling and a first-order passive lossy integral architecture. Here, V... RES (z) is the margin voltage, V INT (z) represents the integration margin voltage, which is divided into the following three stages: The first stage is the reset stage, which involves sampling the margin voltage capacitor C. RES Grounding the upper and lower plates clears the charge on the capacitor to zero. This operation is not shown in the diagram. At this time, there is... The gain loss can be compensated by subsequent gain amplification, after which the margin voltage sampling stage begins; the second stage is the margin voltage sampling stage, at which time the sampling margin voltage capacitor C is connected. RES and digital-to-analog converter array capacitor C DAC The switch between them is closed, connected to the integrating capacitor C. INT and sampling margin voltage capacitor C RES The switch between them is open, and the digital-to-analog converter array capacitor C is open. DAC With sampling margin voltage capacitor C RES Charge sharing occurs at this time. The signal loss; the third stage is the integration stage, at which time the integrating capacitor C is connected. INT and sampling margin voltage capacitor C RES The switch between them is closed, connected to the sampling margin voltage capacitor C. RES and digital-to-analog converter array capacitor C DAC When the switch is open, the remaining voltage is in the integrating capacitor C. INT Integrating, at this point, there exists The integral loss.
[0026] like Figure 3 The diagram shown is a schematic of a traditional passive integrator loop filter. Taking a first-order passive integrator as an example, V... RES (z) is the margin voltage, V INT(z) is the residual integral voltage, assuming C DAC =C RES =C INT Taking this as an example; in the traditional passive integration process, the first stage is the reset stage, at which time φ S The voltage level is high, while φ1 and φ2 are low, meaning the switch φ... s When the circuit is closed, switches φ1 and φ2 are open. During this process, the sampling margin voltage capacitor C is... RES The upper and lower plates are grounded to clear the charge and reset. Afterwards, there is a 1 / 2 gain loss in the residual voltage, which can be compensated for by subsequent gain amplification. Then, the residual voltage sampling stage begins, at which point φ1 is high and φ... S When φ2 is low, i.e., switch φ1 is closed, switch φ S When the switch φ2 is disconnected, the residual voltage is measured by the residual voltage capacitor C. RES and digital-to-analog converter array capacitor C DAC Charge sharing occurs between them, and half of the signal is lost during the sharing process. This signal loss can be compensated for by subsequent gain amplification. Finally, the integration phase begins, at which point φ2 is high and φ S When φ1 is low, that is, when switch φ2 is closed, switch φ S When disconnected from switch φ1, the voltage experiences a 1 / 2 integral loss during the integration process.
[0027] according to Figure 3 From the signal flow graph of a first-order conventional passive integrator, the integration margin voltage V can be obtained. INT The formula for (n) is as follows:
[0028]
[0029] As can be seen from formula (1), the earlier the margin voltage is applied, the greater the signal loss, i.e., V RES (1) has the largest integral loss, followed by V. RES (2), and so on.
[0030] Signal loss can cause positive poles in the noise transfer function, and a large integral loss can cause the zeros of the noise transfer function to be less than 1. Signal loss can be compensated for by using multipath comparators, gain amplifiers, etc. Figure 3Signal loss compensation with a gain of 2 is performed, but integral loss cannot be compensated using this method. Active integrators, which are high-power and circuit-complex, are lossless integrators, while passive integrators, which are low-power, simple, and robust, are lossy integrators. Lossy integrators result in a flat response of the noise transfer function at low frequencies, leading to reduced noise attenuation within the frequency band. Therefore, compensating for both signal loss and integral loss in passive integrators can enhance noise shaping, improve the resolution of successive approximation analog-to-digital converters (ADCs), and relax the bit-width requirements for DACs and the noise requirements for comparators. This invention combines a capacitive charge pump with passive integrators to realize a passive lossless integrator loop filter, which possesses the advantages of passive integrators while also exhibiting strong noise shaping effects.
[0031] like Figure 4 The diagram shown is a schematic of a first-order passive lossless integrator loop filter according to this embodiment; where V RES (z) is the margin voltage, V INT (z) is the residual integral voltage, assuming C DAC =C RES =C INT Take a first-order integral as an example;
[0032] The first stage is the reset stage, during which the switch φ... RS During the connection period, φ RS With φ NS1_1 High level, φ OUT With φ NS1 It is at a low level, i.e., switch φ RS With switch φ NS1_1 Close, switch φ OUT With switch φ NS1 Disconnection, this process affects the sampling margin voltage capacitor C. RES The charge on the capacitor is reset to zero, that is, the sampling margin voltage capacitor C is sampled. RES The upper and lower plates are grounded to prepare for the margin voltage sampling phase of period (N-1); then the margin voltage sampling phase begins, during the switching φ phase of period (N-1). OUT During the connection period, φ OUT High level, φ NS1_1 φ RS With φ NS1 It is at a low level, i.e., switch φ OUT Close, switch φ NS1_1 , switch φ RS With switch φ NS1 Disconnection occurs during this process; the digital-to-analog converter array capacitor C... DAC With sampling margin voltage capacitor C RESCharge sharing is performed during this stage, which is also the margin voltage sampling stage. A 1 / 2 gain loss occurs during this sharing process, which can be compensated for by subsequent gain amplification circuitry. The switching Φ within the period (N-1)... NS1 During the connection period, φ NS1 High level, φ NS1_1 φ RS With φ OUT It is at a low level, i.e., switch φ NS1 Close, switch φ NS1_1 , switch φ RS With switch φ OUT Disconnection, during which the integrating capacitor C INT1 Using a parallel connection, the sampling margin voltage capacitor C RES With integrating capacitor C INT1 Charge sharing is implemented, and according to the principle of charge conservation, the voltage and capacitance C stored in the sampling margin during the period (N-1) are... RES The margin voltage and the period (N-2) stored in the integrating capacitor C INT1 Half of the margin voltage was lost, where the sampling margin voltage capacitor C... RES The loss is the signal loss, and the integrating capacitor C INT1 The loss is the integral loss, and this stage is the first integration stage; the switch φ during the period (N-1) NS1_1 During the connection period, φ NS1_1 High level, φ NS1 With φ OUT Low level, φ RS During this period, the switch φ changes from a low level to a high level. NS1_1 Close, switch φ NS1 With switch φ OUT Disconnect, switch φ RS During this period, the circuit goes from open to closed, and the integrating capacitor C... INT1 A series connection is used to compensate for the signal loss and integral loss of the margin voltage with a gain of 2. During the compensation period, a reset phase of period (N-1) is entered, i.e., the switch φ... RS When connected, φ RS With φ NS1_1 High level, φ OUT With φ NS1 It is at a low level, i.e., switch φ RS With switch φ NS1_1 Close, switch φ OUT With switch φ NS1 Disconnect to prepare for the residual voltage sampling phase of period N.
[0033] according to Figure 4From the signal flow graph of the first-order passive lossless integrator loop filter in this embodiment, the integration margin voltage V can be obtained. INT The formula for (n) is as follows:
[0034]
[0035] As can be seen from formula (2), the passive lossless integral loop filter of the present invention does not have integral loss, that is, it has a good noise shaping effect, and can also compensate for part of the signal loss of the residual voltage, reducing the difficulty of subsequent circuit design.
[0036] like Figure 5 The diagram shows the schematic of the capacitor-type charge pump used in this invention. The connection method during its operation is shown in the figure. It is assumed that the two capacitor values are equal. Specifically, at switch φ... NS1 During the on-time period, the switch connecting the input terminal of the capacitive charge pump to the upper plate of the left integrating capacitor is closed; one of the two switches connected in parallel between the left integrating capacitor and ground is closed and the other is open; the switch connecting the upper plate of the left integrating capacitor to the upper plate of the right integrating capacitor is closed; the switch connecting the upper plate of the left integrating capacitor to the lower plate of the right integrating capacitor is open; and the switch connecting the right integrating capacitor to ground is closed. At this time, the integrating capacitor C... INT1 Using a parallel connection, at switch φ NS1_1 During the on-time period, the switch connecting the input terminal of the capacitive charge pump to the upper plate of the left integrating capacitor is open; one of the two switches connected in parallel between the left integrating capacitor and ground is closed and the other is open; the switch connecting the upper plate of the left integrating capacitor to the upper plate of the right integrating capacitor is open; the switch connecting the upper plate of the left integrating capacitor to the lower plate of the right integrating capacitor is closed; and the switch connecting the right integrating capacitor to ground is open. At this time, the integrating capacitor C... INT1 Using a series connection, based on the principle of charge conservation, switch φ NS1_1 The voltage of the capacitor top plate after the period is φ NS1 The passive gain of this capacitor charge pump is 2, which is twice the voltage of the top plate of the capacitor after the period.
[0037] The preferred embodiments of the present invention have been described in detail above with reference to the accompanying drawings. However, the present invention is not limited to the specific details of the above embodiments. Within the scope of the technical concept of the present invention, various simple modifications can be made to the technical solution of the present invention, and these simple modifications all fall within the protection scope of the present invention.
[0038] It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction. In order to avoid unnecessary repetition, the present invention will not describe the various possible combinations separately.
[0039] Furthermore, various different embodiments of the present invention can be combined in any way, as long as they do not violate the spirit of the present invention, they should also be regarded as the content disclosed by the present invention.
Claims
1. A noise-shaping successive approximation analog-to-digital converter, characterized in that, It includes a sample-and-hold circuit, a comparator, a logic control circuit, a digital-to-analog converter, and a loop filter; the input of the sample-and-hold circuit is connected to the analog input V. in Used for analog input V in A sample-and-hold operation is performed; the output of the sample-and-hold circuit and the output of the digital-to-analog converter are both connected to the input of the loop filter; the output of the loop filter is connected to the input of the comparator, which has M inputs and is used to compare the integral margin voltage with the margin voltage; the output of the comparator is connected to the input of the logic control circuit, which sends the comparator result to the logic control circuit for logical operation; the output of the logic control circuit is connected to the input of the digital-to-analog converter, which outputs an N-bit digital code and converts the output N-bit digital code into an analog voltage through the digital-to-analog converter, feeding it back to the loop filter for the next step of the operation. The loop filter includes a switch. OUT ɸ RS Sampling margin voltage capacitor C RES and capacitive charge pumps; switches OUT Connected to the digital-to-analog converter array capacitor C DAC Upper plate and sampling margin voltage capacitor C RES Between the upper plates, switch ɸ RS Connected to the sampling margin voltage capacitor C RES Between the upper and lower plates, the sampling margin voltage capacitor C RES The upper plate is connected to the input terminal of a capacitive charge pump; the capacitive charge pump includes multiple integrating capacitors C. INT1 With multiple switches; the multiple switches are used to regulate multiple integrating capacitors C INT1 Parallel and series connections; the working process of the loop filter includes a reset stage, a margin voltage sampling stage, and an integration stage; among which, the switch ɸ OUT The conduction period is used for the margin voltage sampling stage, switch ɸ RS The conduction period of the capacitor charge pump is used for the reset phase, and the conduction period of the capacitor charge pump switch is used for the integration phase; the sampling margin voltage capacitor C RES Used with digital-to-analog converter array capacitor C DAC Charge sharing is performed during the margin voltage sampling phase; The integrating capacitor includes a first integrating capacitor and a second integrating capacitor; the switch includes a switch connecting the input terminal of the capacitive charge pump to the upper plate of the first integrating capacitor, two switches connected in parallel between the first integrating capacitor and ground, a switch connecting the upper plate of the first integrating capacitor and the upper plate of the second integrating capacitor, a switch connecting the upper plate of the first integrating capacitor and the lower plate of the second integrating capacitor, and a switch connecting the second integrating capacitor to ground; the two integrating capacitors C INT1 In ɸ NS1 During conduction, a parallel connection is used, at ɸ NS1_1 During conduction, a series connection is used for the first integration phase.
2. The noise-shaping successive approximation analog-to-digital converter as described in claim 1, characterized in that, Each cycle of the noise-shaping successive approximation analog-to-digital converter sequentially includes a sample-and-hold phase, a successive approximation conversion phase, and a loop filtering phase; the sample-and-hold phase is used to adjust the analog input voltage V. in The sampling and holding process is performed. The successive approximation conversion stage is used to switch the digital-to-analog converter to generate the voltage required for the successive approximation stage, which is then fed into the comparator. The successive approximation operation is completed using the comparison result of the comparator. The loop filtering stage is used to perform noise shaping on the margin voltage using the loop filter, and the integrated margin voltage is then fed into the comparator.
3. The control method for a noise-shaping successive approximation analog-to-digital converter as described in claim 1, characterized in that, Specifically, the steps include the following: First, during the reset phase, control the sampling margin voltage capacitor C. RES The switch clears the charge remaining from the previous cycle; the integrating capacitor C... INT1 The remaining charge on the capacitor is not cleared; then, the sampling margin voltage capacitor C is controlled. RES The switch performs digital-to-analog converter array capacitor C DAC With sampling margin voltage capacitor C RES Charge sharing is achieved through passive sampling, leading to the margin voltage sampling stage. After the successive approximation conversion stage and loop filter reset stage of the noise-shaping successive approximation analog-to-digital converter cycle are completed, a margin voltage is obtained on the digital-to-analog converter. The margin voltage is the difference between the analog input voltage obtained from the sample-and-hold circuit and the analog voltage corresponding to the output digital code, which is sampled. Then, by controlling the integrating capacitor and the switch, and by changing the series and parallel connection of the capacitors in the capacitive charge pump, the integration loss and signal loss existing in the traditional passive integration are compensated, thus achieving passive and lossless integration.