A sar-assisted pipeline analog-to-digital converter and a method for operating the same

Abstract

This invention belongs to the technical field of integrated circuit manufacturing, and discloses a SAR-assisted pipelined analog-to-digital converter and its control method. The analog-to-digital converter includes a two-stage SAR ADC module, and the first stage capacitor array includes C 1 1 ~C 1 M‑1 C 1 2 ~C 1 M‑1 The reference voltage is V ref C 1 1 The reference voltage is V cm =V ref / 2, an improved monotonic switching scheme using redundant capacitors can perform successive approximation comparisons to obtain an M-bit digital code. After completing the first-stage conversion, a passive residual transfer scheme is used, along with inter-stage bit transfer, to enter the second-stage conversion. This second-stage conversion employs the same improved monotonic switching scheme as the first stage, performing successive approximation comparisons to obtain an N-bit digital code. Finally, through timing alignment, an M+N-bit digital code is obtained. This design saves device area and improves conversion efficiency.

Description

A SAR-assisted pipelined analog-to-digital converter and its control method Technical Field

[0001] This invention belongs to the technical field of integrated circuit manufacturing, and more specifically, relates to a SAR-assisted pipeline analog-to-digital converter and its control method. Background Technology

[0002] For SAR (Successive Approximation) assisted pipelined analog-to-digital converters (Pipe-SAR ADCs), the residual amplification between stages and the switching power consumption of a single-stage capacitor array are the two main sources of power consumption. To address the huge power consumption caused by residual amplification and the low energy efficiency of analog-to-digital conversion, a passive residual transfer scheme based on charge redistribution is a good alternative. However, the disadvantage of this scheme is that in order for the residual to be transferred correctly, the second stage requires a huge redundant capacitor, the value of which is basically equivalent to the total capacitance of the first stage. This will cause the area of ​​the analog-to-digital converter to increase exponentially with the increase of resolution.

[0003] Therefore, in order to overcome the disadvantage in area and enable the passive residual transfer scheme based on charge redistribution to be more widely used, it is necessary to propose an optimized structure for the analog-to-digital converter (ADC) and a corresponding control method specifically designed to address this problem. This will improve the energy efficiency of the ADC while minimizing its area, thereby maximizing the energy efficiency of the ADC. Summary of the Invention

[0004] In view of the above-mentioned defects or improvement needs of the existing technology, the present invention provides a SAR-assisted pipeline analog-to-digital converter and its control method, which aims to solve the problems of low energy efficiency and large area of ​​existing analog-to-digital converters.

[0005] To achieve the above objectives, the present invention is proposed.

[0006] According to a first aspect of the present invention, a SAR-assisted pipelined analog-to-digital converter is provided, comprising:

[0007] The first SAR ADC module includes a first capacitor array C. 1 The first comparator G1 and the first SAR logic unit S1, with the positive and negative inputs of G1 respectively connected to differential analog signals via sampling switches; C 1 Includes M-1 capacitor banks C whose upper plates are connected to the input terminal of G1 to adjust the input voltage of G1. 1 1~C 1 M-1 S1 is used to convert the output level of G1 after M approximation comparisons into an M-bit digital code {Q}. M-1 ,……, Q1,Q0},Q i Control C 1i The lower-level board is connected to a reference voltage or ground to regulate the voltage, and S1 generates Q in the next approximation comparison. i-1 , i=1,2,……,M-1; C 1 2~C 1 M-1 The reference voltage is V ref C 1 The reference voltage for 1 is V. cm = V ref / 2; M is a positive integer greater than 2;

[0008] The second SAR ADC module includes a second capacitor array C. 2 The second comparator G2 and the second SAR logic unit S2 are connected one-to-one with the positive and negative inputs of G1 via inter-stage switches to achieve passive residual transfer; C 2 Includes N capacitor groups C whose upper plates are connected to the input terminal of G2 to adjust the voltage at the input terminal of G2. 2 1~C 2 N And redundant capacitor bank C that does not participate in voltage regulation 2 0, S2 is used to convert the output level of G2 after N approximation comparisons into an N-bit digital code {H}. N-1 ,……, H1,H0},H j Control C 2 j The lower-level board is connected to a reference voltage or ground to regulate the voltage, and S2 generates H in the next approximation comparison. j-1 j=1,2,……,N; H N =Q0, C 2 2~C 2 N The reference voltage is V cm C 2 The reference voltage for 1 is V. cm / 2; N is a positive integer greater than 2;

[0009] The timing alignment module is used to align {Q} M-1 ,……, Q1,Q0} and {H N-1 The concatenation of {H1,H0} into an M+N bit digital code {Q} M-1 ,……, Q1,Q0, H N-1 ,……, H1,H0}.

[0010] According to a second aspect of the present invention, a method for controlling a SAR-assisted pipelined analog-to-digital converter is provided, comprising:

[0011] Initialization settings: Control the first capacitor array C 1The highest-order capacitor group C in 1 M-1 and the second capacitor array C 2 The highest-order capacitor group C in 2 N Each of the lower-level boards is connected to its corresponding reference voltage, and the lower-level boards of the remaining capacitor banks are all grounded;

[0012] Entering the first-level sampling mode: controlling the first SAR ADC module to sample the differential analog input signal and hold it on the upper plate of the first capacitor array;

[0013] Entering the first-level conversion mode: the first SAR ADC module is controlled to perform M rounds of successive approximation comparisons on the sampled differential analog input signal to obtain the M-bit digital code {Q}. M-1 ,……, Q1,Q0};

[0014] Entering residual transfer mode: Turn on the interstage switch and transfer the residual voltage from the upper plate of the first capacitor array to the upper plate of the second capacitor array through a passive residual transfer scheme based on charge redistribution. After the transfer is completed, turn off the interstage switch.

[0015] Inter-stage bit transmission: The second capacitor array C is controlled according to the bit digital code Q0 output by the first SAR ADC module. 2 The highest-order capacitor group C in 2 N The lower-level board performs voltage switching;

[0016] Entering the second-level conversion mode: the second SAR ADC module is controlled to perform N rounds of successive approximation comparisons on the transferred residual to obtain an N-bit digital code {H}. N-1 ,……, H1,H0};

[0017] Timing alignment: The timing alignment control module will control {Q} M-1 ,……, Q1,Q0} and {H N-1 After timing alignment, H1, H0} are concatenated to form an M+N bit digital code {Q}. M-1 ,……, Q1,Q0, H N-1 ,……, H1,H0}.

[0018] Overall, compared with the prior art, the technical solutions conceived in this invention have the following beneficial effects.

[0019] In this invention, to achieve M-bit resolution, the first SAR ADC module is designed with only M-1 capacitor banks, and the reference voltage is divided into V... ref and V cm = V ref / 2, where C 12~C 1 M-1 The reference voltage is V ref C 1 The reference voltage for 1 is V. cm For the second SAR ADC module, its reference voltage is also divided into two types, namely V cm and V cm / 2, C 2 2~C 2 N The reference voltage is V cm C 2 The reference voltage for 1 is V. cm / 2, and moreover, the two-stage ADC employs an inter-stage bit transfer scheme when connecting them, meaning the last bit of the first stage controls the most significant bit of the capacitor bank in the second stage. Through this design, the C in the first capacitor array can be... 1 1 and C in the second capacitor array 2 This invention not only participates in voltage regulation, realizing the final voltage conversion process, but also stores the remaining charge after conversion. Compared to the traditional circuit structure that uses a separate redundant capacitor to store the remaining charge after conversion, this invention saves the highest and second-highest bit capacitors in the capacitor array. Therefore, the area can be reduced by 75% compared to the traditional solution, reducing the manufacturing cost of a single ADC chip. At the same time, the significant reduction in capacitor area also means that this circuit structure will have less dynamic power consumption during the successive approximation operation of voltage conversion, improving the overall energy efficiency of the analog-to-digital converter. Moreover, the inter-stage bit transfer conversion scheme ensures the correctness of the conversion and eliminates the need for a residual amplifier with extremely high power consumption, further improving the overall core energy efficiency of the analog-to-digital converter. Attached Figure Description

[0020] Figure 1 is a schematic diagram of the structure of a SAR-assisted pipelined analog-to-digital converter according to an embodiment of the present invention.

[0021] Figure 2 is a flowchart of the operation method of a SAR-assisted pipeline analog-to-digital converter according to an embodiment of the present invention. Detailed Implementation

[0022] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention. Furthermore, the technical features involved in the various embodiments of this invention described below can be combined with each other as long as they do not conflict with each other.

[0023] This invention provides a SAR-assisted pipelined analog-to-digital converter.

[0024] Figure 1 shows a schematic diagram of the structure of a SAR-assisted pipeline analog-to-digital converter in one embodiment of the present invention. The analog-to-digital converter includes a first SAR ADC module, a second SAR ADC module, and a timing alignment module.

[0025] The first SAR ADC module includes a first capacitor array C 1 The first comparator G1 and the first SAR logic unit S1, wherein the positive and negative input terminals of the first comparator G1 are respectively connected to the differential analog signal through sampling switches; the first capacitor array C 1 This includes M-1 capacitor banks C whose upper plates are connected to the input of the first comparator G1 to adjust the voltage at the input of the first comparator G1. 1 1~C 1 M-1 The first SAR logic unit S1 is used to convert the output level of the first comparator G1 after M approximation comparisons into an M-bit digital code {Q}. M-1 ,……, Q1,Q0},Q i Control C 1 i The lower-level board is connected to a reference voltage or ground to regulate the voltage, and the first SAR logic unit S1 generates Q in the next approximation comparison. i-1 i=1,2,……,M-1; capacitor bank C 1 2~C 1 M-1 The reference voltage is V ref capacitor bank C 1 The reference voltage for 1 is V. cm = V ref / 2.

[0026] Specifically, in the conventional design of a SAR ADC, the upper plate of each capacitor in the capacitor array is connected to the input terminal of the comparator. More specifically, each capacitor group includes a positive terminal capacitor and a negative terminal capacitor. The upper plate of the positive terminal capacitor is connected to the positive input terminal of the comparator, and the negative terminal capacitor is connected to the negative input terminal of the comparator. The lower plate of each capacitor selects whether to connect to the reference voltage or ground based on the output result of the SAR logic unit. SS By adjusting the voltage at the corresponding input terminal, successive approximation comparisons are achieved. Among the capacitors involved in the conversion, the capacitance of the (k-1)th capacitor group is half that of the kth capacitor group, the capacitance of the lowest-order capacitor is equal to that of the second-lowest-order capacitor, and the capacitance of the positive terminal capacitor is equal to that of the negative terminal capacitor.

[0027] The basic working principle of a SAR ADC is as follows: After the voltage at the positive and negative input terminals of the comparator is adjusted by the k-th capacitor group, the comparator compares again and outputs the comparison result. Based on this comparison result, the voltage of the lower stage board of the (k-1)-th capacitor group is controlled. Specifically, the lower stage board of the capacitor connected to the higher voltage input terminal of the comparator in the (k-1)-th capacitor group is grounded, and the lower stage board of the capacitor connected to the lower voltage input terminal of the comparator is connected to the reference voltage. The voltage at the two input terminals of the comparator is adjusted by charge redistribution, and then the next approximation comparison is entered. This pattern continues until the last comparison is completed, and the analog-to-digital conversion result is obtained. For example, if the bit code is 1, it indicates that the voltage at the positive input terminal of the comparator is higher and the voltage at the negative input terminal is lower. At this time, the lower stage board of the next capacitor connected to the positive input terminal is grounded, and the lower stage board of the next capacitor connected to the negative input terminal is connected to its reference voltage.

[0028] In this invention, the first SAR ADC module has a total of M-1 capacitor groups C involved in voltage regulation. 1 1~C 1 M-1 C 1 1 and C 1 The capacitances of 2 are equal, C 1 2~C 1 M-1 In the middle, C 1 k-1 The capacitance is C 1 k Half of this can achieve M approximation comparisons (an initial comparison is performed when the analog signal is first connected, followed by M-1 comparisons by successively adjusting M-1 voltage pairs), resulting in an M-bit digital code {Q}. M-1 The total resolution of the first SAR ADC module is M bits, where Q1, Q0, ..., Q1. Specifically, the output of the first comparator G1 is connected to the first SAR logic unit S1, which outputs a total of M bits of digital code {Q...}. M-1 ,……, Q1,Q0}, where the first M-1 bits of the digital code {Q M-1 ,……, Q1} is fed back to the first capacitor array to successively control M-1 capacitor groups C 1 M-1 ~C 1 1. Participates in voltage regulation, the last capacitor C 1 After participating in voltage regulation, the last 1-bit digital code Q0 is compared and output. After timing alignment, the digital code Q0 is passed to the second capacitor array, where M is a positive integer greater than 2.

[0029] The second SAR ADC module includes a second capacitor array C. 2The second comparator G2 and the second SAR logic unit S2 are connected one-to-one with the positive and negative inputs of G1 via inter-stage switches to achieve passive residual transfer; C 2 Includes N capacitor groups C whose upper plates are connected to the input terminal of G2 to adjust the voltage at the input terminal of G2. 2 1~C 2 N And redundant capacitor bank C that does not participate in voltage regulation 2 0, S2 is used to convert the output level of G2 after N approximation comparisons into an N-bit digital code {H}. N-1 ,……, H1,H0},H j Control C 2 j The lower-level board is connected to a reference voltage or ground to regulate the voltage, and S2 generates H in the next approximation comparison. j-1 j=1,2,……,N; H N =Q0, C 2 2~C 2 N The reference voltage connected during regulation is V. cm C 2 1. The reference voltage connected when participating in regulation is V. cm / 2. In one embodiment, the positive and negative input terminals of the first comparator G1 are respectively connected to a differential analog signal (V) via a bootstrap switch. ip V in ).

[0030] Specifically, after completing the initial analog-to-digital conversion (ADC), the first SAR ADC module transfers the residual at the input of the first comparator to the second SAR ADC module for subsequent ADC conversion. The principle of the second SAR ADC module's ADC conversion is the same as that of the first SAR ADC module, as detailed above, and will not be repeated here.

[0031] In this invention, the first SAR ADC module and the second SAR ADC module are connected via a switch, employing a passive residual transfer scheme based on charge redistribution. This eliminates the need for a residual amplifier, and the residual transferred to the second stage is half of the residual from the first stage. In one embodiment, the positive and negative input terminals of the second comparator G2 are respectively connected to the positive and negative input terminals of the first comparator G1 via differential complementary CMOS switches to achieve passive residual transfer.

[0032] In this invention, the second SAR ADC module has a total of N capacitor groups C that participate in voltage regulation. 2 1~C 2 N C 2 1 and C 2 The capacitances of 2 are equal, C2 2~C 2 N In the middle, C 2 k-1 The capacitance is C 2 k Half of 1 / 2 can be used to perform N approximation comparisons to obtain an N-bit digital code {H}. N-1 The total resolution of the second SAR ADC module is N bits, where H1, H0, ..., H0. Specifically, the output of the second comparator G2 is connected to the second SAR logic unit S2, which outputs a total of N bits of digital code {H...}. N-1 ,……, H1,H0}, where the first N-1 bits of the digital code {H N-1 The feedback from H1 to the second capacitor array is used to sequentially control N-1 capacitor groups C. 2 N-1 ~ C 2 1 participates in voltage regulation, while capacitor bank C 2 N It is controlled by the last bit of the digital code Q0 in the first stage of analog-to-digital conversion, and the last capacitor C. 2 After participating in voltage regulation, the last bit of the digital code is compared and output, thus ending the analog-to-digital conversion, where N is a positive integer greater than 2.

[0033] The timing alignment module is used to convert the M-bit digital code {Q} obtained from the first-stage analog-to-digital conversion. M-1 The N-bit digital code {H} obtained from the second-level analog-to-digital conversion is {..., Q1,Q0}. N-1 After timing alignment, H1, H0} are concatenated to form an M+N bit digital code {Q}. M-1 ,……, Q1,Q0, H N-1 ,……, H1,H0}, denoted as the analog-to-digital conversion result. In a specific embodiment, the timing alignment module includes two levels of D flip-flops controlled by SAR logic units and a chain of inverters. This module receives M-bit digital code from the first SAR logic unit and N-bit digital code from the second SAR logic unit, and after timing alignment, concatenates them into an M+N-bit final output digital code D. out The first M bits are the high-order bits, and the last N bits are the low-order bits. In one embodiment, the analog-to-digital converter further includes a buffer unit for buffering the M+N bits of digital code output by the timing alignment module, and then outputting it with high drive force through the output buffer.

[0034] In one embodiment, the last bit Q0 output by the first SAR ADC module is time-aligned by a timing alignment module. This alignment is performed after the second SAR ADC module completes residual transfer and before entering analog-to-digital conversion, thus aligning the most significant bit C of the second capacitor array. 2 N The control is as follows: Specifically, after the second capacitor array ends the sampling mode and before entering the conversion mode, the last bit of the digital code converted by the first capacitor array is read from the timing alignment unit and used as the reference voltage of the highest bit capacitor of the second capacitor array to realize the inter-stage transfer of bits.

[0035] In a conventional SAR ADC module, a uniform reference voltage is used, and a redundant capacitor that does not participate in regulation is connected at the end to store the input voltage after the last conversion. Thus, according to conventional design, if the first SAR ADC module needs to achieve a total resolution of M bits, it needs to design M capacitor groups that participate in voltage regulation and 1 redundant capacitor group to store the remaining charge after the conversion.

[0036] In this invention, to achieve M-bit resolution, the first SAR ADC module is designed with only M-1 capacitor banks, and the reference voltage is divided into V... ref and V cm = V ref / 2, where the reference voltage for the M-2 capacitor banks corresponding to the higher bits is V. ref The reference voltage of the last capacitor bank is V. cm For the second SAR ADC module, its voltage conversion structure must be consistent with that of the first SAR ADC module. Therefore, its reference voltage is also divided into two types. Since the voltage is reduced by half when the residual is transferred to the second SAR ADC module, the reference voltage used by the second SAR ADC module is also reduced by half compared to the first SAR ADC module, namely V. cm and V cm / 2, similar to the second SAR ADC module, among the capacitors involved in voltage conversion, the reference voltage for the N-1 capacitor groups corresponding to the higher bits is V. cm The reference voltage for the last capacitor bank is V. cm / 2. In other words, apart from needing to receive one inter-stage transfer bit and halving the overall reference voltage while adding redundant capacitors, the second capacitor array is identical to the first capacitor array in structure and conversion method. The redundant capacitors in the second capacitor array ensure that the total capacitance of the second capacitor array is the same as that of the first capacitor array. The two-stage ADC uses an inter-stage bit transfer scheme when connecting, where the last bit of the first stage controls the highest-order capacitor group of the second stage. This design allows the redundant capacitor groups in each capacitor array, used to store the remaining charge after conversion, to also participate in voltage regulation, achieving the final voltage conversion process. Compared to traditional circuit structures, this saves the highest and second-highest-order capacitors in the capacitor array, thus reducing the area by 75% compared to traditional solutions, lowering the manufacturing cost of a single ADC chip. The significant reduction in capacitor area also means that this circuit structure will have less dynamic power consumption during successive approximation operations of voltage conversion, improving the overall energy efficiency of the analog-to-digital converter.

[0037] The present invention also provides a method for controlling the above-mentioned SAR-assisted pipeline analog-to-digital converter.

[0038] Figure 2 shows a flowchart of the control method for a SAR-assisted pipelined analog-to-digital converter according to an embodiment of the present invention. The control method will be described in detail below.

[0039] Initialization settings: Control the first capacitor array C 1 The highest-order capacitor group C in 1 M-1 and the second capacitor array C 2 The highest-order capacitor group C in 2 N Each of the lower-level boards is connected to its corresponding reference voltage, and the lower-level boards of the remaining capacitor banks are all grounded.

[0040] Specifically, C 1 M-1 The lower-level board is connected to the reference voltage V ref C 2 N The lower-level board is connected to the reference voltage V cm The lower plate of the remaining capacitors is grounded (V). SS .

[0041] Entering the first-level sampling mode: controlling the first SAR ADC module to sample the differential analog input signal and hold it on the upper plate of the first capacitor array.

[0042] Specifically, when the sampling clock CLKs goes high, the first SAR ADC module enters sampling mode, first by sampling the differential analog input signal V through a pair of differential bootstrap switches. ip and V inPerform high-precision sampling, V ip and V in The first SAR ADC module enters conversion mode when the sampling clock CLKs goes low, sampling with a precision higher than the overall resolution and holding the sample on the upper plate of the first capacitor array.

[0043] Entering the first-level conversion mode: the first SAR ADC module is controlled to perform M rounds of successive approximation comparisons on the sampled differential analog input signal to obtain the M-bit digital code {Q}. M-1 ,……, Q1,Q0}.

[0044] Specifically, the comparator clock CLKc can be set, and M rounds of successive approximation comparisons are performed as the comparator clock CLKc is used. The specific process is as follows.

[0045] First comparison: Directly compare the sampled differential analog voltages to obtain the bit digital code Q. M-1 This process involves no capacitor voltage switching, and the energy consumption is zero.

[0046] Second comparison: Due to the initial highest bit capacitance C 1 M-1 The lower plate is connected to a reference voltage, and the rest are grounded. When the highest bit result Q... M-1 When outputting, C 1 M-1 The capacitor with the higher voltage on the upper plate serves as the target switching capacitor, while its lower plate is switched by the reference voltage V. ref Switch to V SS Meanwhile, the lower plate of the other capacitor remains unchanged. Consequently, the voltage across the upper plate of the target switching capacitor drops by V. ref / 2, and based on the principle of charge closed-loop recovery, the voltage switching of the target switching capacitor in this case does not generate switching energy, and the energy consumption is 0.

[0047] From the third to the (M-1)th comparison, the switching logic changes are consistent with the monotonic switching scheme: the switching state of the side with higher voltage remains unchanged, while the reference level of the side with lower voltage changes from V... SS Switch to V ref .

[0048] By the Mth comparison, the last capacitor C is... 1 1 also participates in the switching conversion; the voltage level of the lower plate of the capacitor on the side with the lower output voltage is changed by V. SS Convert to V cm V cm = V ref / 2.

[0049] Because an improved monotonic switching scheme with redundant capacitors in the conversion is adopted, capacitors are saved. Therefore, the least significant bit of the digital code of the first SARADC module cannot be fed back to the upper plate of the first capacitor array, resulting in the residual voltage resolution being M-1 bits. To overcome the lack of precision here, this conversion method proposes an inter-stage bit transfer scheme. That is, after the first SAR logic unit generates the first least significant bit Q0, although it cannot be fed back to the first capacitor array, it can be first input into the timing alignment module for storage through the first SAR logic unit. At the same time, it is aligned with the working timing of the second SARADC module in the timing alignment module, waiting for the second SAR ADC to enter the conversion mode.

[0050] Entering residual transfer mode: Turn on the interstage switch and transfer the residual voltage from the upper plate of the first capacitor array to the upper plate of the second capacitor array through a passive residual transfer scheme based on charge redistribution. After the transfer is completed, turn off the interstage switch.

[0051] Specifically, after the first SAR ADC module completes the mode conversion, it outputs an RDY signal. This RDY signal is simultaneously transmitted to the second SAR ADC module and the timing alignment module. Upon receiving this signal, the differential MOS switch spanning the two stages in the second SAR ADC module opens, directly connecting the upper plates of the capacitor arrays of the two stages. A passive residual transfer scheme based on charge redistribution is used to transfer the residual voltage from the upper plate of the first capacitor array to the upper plate of the second capacitor array. To ensure that the residual voltage on the upper plate of the second capacitor array after the transfer is half of the original voltage, a large redundant capacitor C needs to be mounted on the second capacitor array. 2 0. The upper plate of this redundant capacitor is connected to the upper plate of the second capacitor array, and the lower plate is always grounded. It does not participate in the voltage conversion process of the second SAR ADC module and does not need to undergo the charging and discharging process of the capacitor. It is a truly redundant capacitor. Therefore, its size will not increase the energy consumption of the second SAR ADC module in voltage conversion. Its existence is only to ensure the correctness and stability of residual transfer.

[0052] After the second capacitor array acquires the residual voltage, the connected differential CMOS switch is turned off. At the same time, the first capacitor array performs a new round of high-precision sampling of the analog input differential signal, which is carried out in parallel with the conversion mode of the second capacitor array.

[0053] Inter-stage bit transmission: The second capacitor array C is controlled according to the bit digital code Q0 output by the first SAR ADC module. 2 The highest-order capacitor group C in 2 N The lower-level board performs voltage switching.

[0054] Specifically, after the residual transfer mode ends and before entering the conversion mode, the control logic reads the last bit Q0 of the first capacitor array conversion from the timing alignment module, and adjusts the highest bit capacitor C of the second capacitor array accordingly. 2 N The lower plate voltage, that is, before the second capacitor array conversion, the last bit of the first capacitor array conversion Q0=D N The feedback is sent to the highest-order capacitor of the second capacitor array, changing the voltage difference between the upper plates of the second capacitor array at this time. This completes the entire inter-stage bit transfer scheme, ensuring the correctness of the two-stage SAR ADC in continuously converting the same pair of differential analog voltages.

[0055] Furthermore, due to the initial highest bit capacitance C 2 N The lower plate is connected to a reference voltage, and the rest are grounded. When Q0 outputs, C... 2 N The capacitor with the higher voltage on the upper plate serves as the target switching capacitor, while its lower plate is switched by the reference voltage V. cm Switch to V SS Meanwhile, the lower plate of the other capacitor remains unchanged. Consequently, the voltage across the upper plate of the target switching capacitor drops by V. cm / 2, and based on the charge closed-loop recovery principle, the voltage switching of the target switching capacitor in this case does not generate switching energy, and the comparison energy consumption is 0, further reducing the power consumption of the ADC.

[0056] Entering the second-level conversion mode: the second SAR ADC module is controlled to perform N rounds of successive approximation comparisons on the transferred residual to obtain an N-bit digital code {H}. N-1 ,……, H1,H0}.

[0057] Specifically, this process can be referred to in the introduction of the first-level conversion mode.

[0058] Timing alignment: The timing alignment control module will control {Q} M-1 ,……, Q1,Q0} and {H N-1 After timing alignment, H1, H0} are concatenated to form an M+N bit digital code {Q}. M-1 ,……, Q1,Q0, H N-1 ,……, H1,H0}.

[0059] Specifically, the overall timing sequence of the PipeSAR ADC employing the interstage bit transfer scheme is as follows: First, sampling mode; second, conversion mode; interstage bit storage; passive residual transfer (which is also the second sampling mode); interstage bit transfer; second, conversion mode; and finally, timing alignment and splicing of the two-stage output codes to obtain the final M+N bit digital output code. The final M+N bit digital code, denoted as {D... M+N-1 ,……, D N+1 D N D N-1 If ,……, D1,D0}, then:

[0060] D M+N-1 =Q M-1 D M+N-2 =Q M-2 ,……,D N+1 =Q1,D N = Q0, D N-1 =H N-1 ,……, D1=H1,D0=H0.

[0061] It should be noted that since the residual after transfer is half of the original residual, in order to ensure the consistency and correctness of the two-stage conversion, the range of the second stage should also be reduced to half of the range of the first stage. Therefore, the range of the second stage is V. SS ~V cm The first level is connected to V. ref The capacitor is connected to the second V. cm Therefore, the last capacitor in the second stage should be connected to V. cm The binary relationship of voltage conversion can only be satisfied by a ratio of 2. Therefore, apart from the need to add redundant capacitors, receive one inter-stage transfer bit, and halve the overall reference voltage, the second stage is the same as the first capacitor array in terms of structure and conversion method.

[0062] Since this invention employs a passive residual transfer scheme, the total capacitance of the first and second capacitor arrays must be equal, which typically leads to a significant increase in the ADC area. Therefore, this invention utilizes an improved monotonic switching scheme for the shared capacitance of the capacitor used in the last conversion of the two stages of the PipeSAR ADC and the redundant capacitor storing the charge after conversion. This scheme, combined with the passive residual transfer scheme, reduces the area of ​​the first capacitor array by 75%, while simultaneously reducing the area of ​​the second capacitor array by 75%, saving a significant amount of area occupied by capacitors in the ADC. As a result, it achieves higher energy efficiency compared to traditional schemes. Finally, an inter-stage bit transfer scheme is added to ensure the compatibility of the scheme and the correctness of the conversion. Ultimately, this achieves high energy efficiency in a small area while maintaining the conversion accuracy of the PipeSAR ADC.

[0063] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as the combination of these technical features does not contradict each other, it should be considered within the scope of this specification. It should be noted that the terms "in one embodiment," "for example," and "again" are intended to illustrate the present invention and are not intended to limit the present invention.

[0064] The embodiments described above are merely examples of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention.

Claims

1. A SAR-assisted pipelined analog-to-digital converter, characterized in that, include: The first SAR ADC module includes a first capacitor array C. 1 The first comparator G1 and the first SAR logic unit S1, with the positive and negative inputs of G1 respectively connected to differential analog signals via sampling switches; C 1 Includes M-1 capacitor banks C whose upper plates are connected to the input terminal of G1 to adjust the input voltage of G1. 1 1~C 1 M-1 S1 is used to convert the output level of G1 after M approximation comparisons into an M-bit digital code {Q}. M-1 ,……, Q1,Q0},Q i Control C 1 i The lower-level board is connected to a reference voltage or ground to regulate the voltage, and S1 generates Q in the next approximation comparison. i-1 , i=1,2,……,M-1; C 1 2~C 1 M-1 The reference voltage is V ref C 1 The reference voltage for 1 is V. cm = V ref / 2; M is a positive integer greater than 2; the second SAR ADC module includes a second capacitor array C 2 The second comparator G2 and the second SAR logic unit S2 are connected one-to-one with the positive and negative inputs of G1 via inter-stage switches to achieve passive residual transfer; C 2 Includes N capacitor groups C whose upper plates are connected to the input terminal of G2 to adjust the voltage at the input terminal of G2. 2 1~C 2 N And redundant capacitor bank C that does not participate in voltage regulation 2 0, S2 is used to convert the output level of G2 after N approximation comparisons into an N-bit digital code {H}. N-1 ,……, H1,H0},H j Control C 2 j The lower-level board is connected to a reference voltage or ground to regulate the voltage, and S2 generates H in the next approximation comparison. j-1 j=1,2,……,N; H N =Q0, C 2 2~C 2 N The reference voltage is V cm C 2 The reference voltage for 1 is V. cm / 2; N is a positive integer greater than 2; timing alignment module, used to align {Q M-1 ,……, Q1,Q0} and {H N-1 The concatenation of {H1,H0} into an M+N bit digital code {Q} M-1 ,……, Q1,Q0, H N-1 ,……, H1,H0};and the last bit of digital code Q0 output by the first SAR ADC module is time-aligned by the timing alignment module, so as to realize the timing alignment of the highest bit capacitor group C of the second capacitor array after the second SAR ADC module completes the residual transfer and before entering the analog-to-digital conversion. 2 N Regulation.

2. The analog-to-digital converter as described in claim 1, characterized in that, The analog-to-digital converter also includes a buffer unit for buffering the M+N bit digital code output by the timing alignment module.

3. The analog-to-digital converter as described in claim 1, characterized in that, The sampling switch is a bootstrap switch.

4. The analog-to-digital converter as described in claim 1, characterized in that, The interstage switch is a differential complementary CMOS switch.

5. The analog-to-digital converter as described in claim 1, characterized in that, The timing alignment module includes two levels of D flip-flops controlled by SAR logic units and a chain of inverters.

6. A method for controlling a SAR-assisted pipelined analog-to-digital converter as described in any one of claims 1 to 5, characterized in that, Includes: Initialization settings: Controlling the first capacitor array C 1 The highest-order capacitor group C in 1 M-1 and the second capacitor array C 2 The highest-order capacitor group C in 2 N Each of the lower-level boards is connected to its corresponding reference voltage, and the lower-level boards of the remaining capacitor banks are all grounded; enter the first-level sampling mode: control the first SAR ADC module to sample the differential analog input signal and hold it on the upper plate of the first capacitor array; Entering the first-level conversion mode: the first SAR ADC module is controlled to perform M rounds of successive approximation comparisons on the sampled differential analog input signal to obtain the M-bit digital code {Q}. M-1 ,……, Q1,Q0};Entering residual transfer mode: Turn on the interstage switch, and transfer the residual voltage from the upper plate of the first capacitor array to the upper plate of the second capacitor array through a passive residual transfer scheme based on charge redistribution. After the transfer is completed, turn off the interstage switch. Inter-stage bit transmission: The second capacitor array C is controlled according to the bit digital code Q0 output by the first SAR ADC module. 2 The highest-order capacitor group C in 2 N The lower-level board performs voltage switching; Entering the second-level conversion mode: the second SAR ADC module is controlled to perform N rounds of successive approximation comparisons on the transferred residual to obtain an N-bit digital code {H}. N-1 ,……, H1,H0};Timing alignment: The timing alignment module controls {Q M-1 ,……, Q1,Q0} and {H N-1 After timing alignment, H1, H0} are concatenated to form an M+N bit digital code {Q}. M-1 ,……, Q1,Q0, H N-1 ,……, H1,H0}.

7. The control method as described in claim 6, characterized in that, After the first SAR ADC module completes the conversion, it outputs an RDY signal. When the RDY signal appears, the inter-stage switch is turned on, and the residual transfer mode is entered.

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