Negative voltage generation circuit for sar adc

Abstract

The application discloses a negative voltage generating circuit for a SAR ADC, which comprises a first inverter, a first capacitor, a second capacitor, a discharging switch unit, a charging switch unit, a first resistor and a third capacitor; an external clock signal is input into the first inverter and the second capacitor respectively, the output end of the first inverter is connected with the first capacitor, the first capacitor is further connected with one end of the discharging switch unit and one input end of the charging switch unit respectively, the second capacitor is further connected with the other end of the discharging switch unit and the other input end of the charging switch unit respectively, the first resistor is connected with the output end of the discharging switch unit and the third capacitor, and one end of the third capacitor is an output end to output a negative voltage. The negative voltage generating circuit can directly generate a negative voltage to provide for the SAR ADC, can systematically offset the decision threshold of a comparator, can compensate for the inherent positive offset voltage, and can make the actual jump point of the comparator return to the ideal zero differential input position.

Description

Technical Field

[0001] This invention relates to the field of integrated circuits, and more specifically to a negative voltage generation circuit for a SAR ADC. Background Technology

[0002] In SAR ADCs, the comparator is a critical module that determines the overall system accuracy, speed, and power consumption. An ideal comparator should transition when the input differential voltage is zero. However, process variations in actual manufacturing can lead to inherent input offset voltages in the comparator. This offset voltage is directly superimposed on the input signal being compared, introducing static errors and severely degrading the ADC's overall linearity and effective resolution.

[0003] To calibrate or eliminate comparator offset voltage, the industry commonly employs techniques such as input offset storage, output offset storage, or dynamic component matching. However, these methods all increase circuit complexity to some extent, and power consumption and noise also increase accordingly. They may also reduce response speed and be limited by calibration accuracy.

[0004] Therefore, the present invention provides a negative voltage generation circuit for SAR ADC to eliminate the influence of offset voltage in SAR ADC, thereby overcoming the above-mentioned defects of SAR ADC. Summary of the Invention

[0005] The purpose of this invention is to provide a negative voltage generation circuit for SAR ADC. The negative voltage generation circuit of this invention can directly generate a negative voltage to provide to the SAR ADC, which can systematically offset the decision threshold of the comparator, thereby compensating for its inherent positive offset voltage and returning the actual switching point of the comparator to the ideal zero differential input position.

[0006] To achieve the above objectives, the present invention provides a method for SAR The negative voltage generation circuit of the ADC includes a first inverter, a first capacitor, a second capacitor, a discharge switch unit, a charge switch unit, a first resistor, and a third capacitor. An external clock signal is input to the input terminal of the first inverter and one end of the second capacitor. The output terminal of the first inverter is connected to one end of the first capacitor. The other end of the first capacitor is connected to one end of the discharge switch unit and one input terminal of the charge switch unit. The other end of the second capacitor is connected to the other end of the discharge switch unit and the other input terminal of the charge switch unit. One end of the first resistor is connected to the output terminal of the discharge switch unit, and its other end is connected to one end of the third capacitor. The other end of the third capacitor is grounded, and one end of the third capacitor forms the output terminal of the negative voltage generation circuit for the SARADC to output a negative voltage. When the external clock signal is high, the voltage at the other end of the first capacitor is negative and charges the third capacitor through the charge switch unit, while the other end of the second capacitor discharges to ground through the discharge switch unit. When the external clock signal is low, the voltage at the other end of the second capacitor is negative and charges the third capacitor through the charge switch unit, while the other end of the first capacitor discharges to ground through the discharge switch unit.

[0007] Preferably, the capacitance value of the third capacitor is much larger than the capacitance values ​​of the first capacitor and the second capacitor.

[0008] Preferably, the negative voltage generation circuit for the SAR ADC further includes a second inverter, the input terminal of which is connected to the output terminal of the first inverter, and the output terminal of the second inverter is connected to one end of the second capacitor.

[0009] Preferably, the first inverter includes a first MOSFET and a second MOSFET, and the second inverter includes a third MOSFET and a fourth MOSFET. An external clock signal is input to the gates of the first MOSFET and the second MOSFET respectively. The drains of the first MOSFET and the second MOSFET are connected together to form the output terminal of the first inverter. The source of the first MOSFET is connected to the power supply voltage, and the source of the second MOSFET is grounded. The output terminal of the first inverter is connected to the gates of the third MOSFET and the fourth MOSFET respectively. The drains of the third MOSFET and the fourth MOSFET are connected together to form the output terminal of the second inverter and are connected to one end of the second capacitor. The source of the third MOSFET is connected to the power supply voltage, and the source of the fourth MOSFET is grounded.

[0010] Preferably, the aspect ratio of the first MOSFET, the second MOSFET, the third MOSFET, and the fourth MOSFET is 20-50.

[0011] Preferably, the discharge switch unit includes a fifth MOS transistor and a sixth MOS transistor. The source of the fifth MOS transistor and the gate of the sixth MOS transistor are both connected to the other end of the first capacitor. The source of the sixth MOS transistor and the gate of the fifth MOS transistor are both connected to the other end of the second capacitor. The drains of the fifth MOS transistor and the sixth MOS transistor are both grounded.

[0012] Preferably, the charging switch unit includes a seventh MOS transistor and an eighth MOS transistor. The source of the eighth MOS transistor and the gate of the seventh MOS transistor are both connected to the other end of the second capacitor. The drain of the seventh MOS transistor and the gate of the eighth MOS transistor are both connected to the other end of the first capacitor. The source of the seventh MOS transistor and the drain of the eighth MOS transistor are both grounded.

[0013] Compared with the prior art, the negative voltage generation circuit for SAR ADC of the present invention, by setting the first capacitor, the second capacitor, the discharge switch unit and the charging switch unit, can charge the third capacitor twice within one clock cycle of the external clock signal, thereby speeding up the charging speed until the voltage of the third capacitor is charged to the negative power supply voltage, so that the third capacitor can output a stable negative voltage. In this way, the decision threshold of the comparator in the SAR ADC can be systematically offset, thereby compensating for its inherent positive offset voltage and returning the actual switching point of the comparator to the ideal zero differential input position.

[0014] The invention will become clearer from the following description, taken in conjunction with the accompanying drawings, which are used to explain embodiments of the invention. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of the negative voltage generation circuit for SAR ADC of the present invention.

[0016] Figure 2 This is a schematic diagram of one embodiment of the negative voltage generation circuit for SAR ADC of the present invention. Detailed Implementation

[0017] Embodiments of the invention will now be described with reference to the accompanying drawings, in which similar element reference numerals represent similar elements. As described above, the present invention provides a negative voltage generation circuit for a SAR ADC. This negative voltage generation circuit can directly generate a negative voltage to be supplied to the SAR ADC, which can systematically offset the decision threshold of the comparator, thereby compensating for its inherent positive offset voltage and returning the actual switching point of the comparator to the ideal zero-differential input position.

[0018] Please refer to Figure 1 , Figure 1This is a schematic diagram of the negative voltage generation circuit for SAR ADC of the present invention. Figure 1As shown, the negative voltage generation circuit for a SAR ADC of the present invention includes a first inverter INV1, a first capacitor C1, a second capacitor C2, a discharge switch unit, a charge switch unit, a first resistor R1, and a third capacitor C3. An external clock signal CLK1 is input to the input terminal of the first inverter INV1 and one end of the second capacitor C2 to provide a clock signal for the negative voltage generation circuit. The output terminal of the first inverter INV1 is connected to one end of the first capacitor C1 to invert the input clock signal CLK1 into a clock signal CLK2, which is then input to the first capacitor C1. This results in the clock signals applied to the first capacitor C1 and the second capacitor C2 being a pair of clock signals with opposite phases, thus causing the voltage values ​​on the two capacitors to be different. The other end of the first capacitor C1 is connected to one end of the discharge switch unit and one input terminal of the charging switch unit, respectively. The other end of the second capacitor C2 is connected to the other end of the discharge switch unit and the other input terminal of the charging switch unit, respectively. One end of the first resistor R1 is connected to the output terminal of the discharge switch unit, and the other end is connected to one end of the third capacitor C3. The other end of the third capacitor C3 is grounded, so that the first capacitor C1 and the second capacitor C2 can discharge through the discharge unit at different times and charge the third capacitor C3 through the charging unit. Specifically, when the external clock signal CLK1 is high, the voltage at the other end of the first capacitor C1 is negative and charges the third capacitor C3 through the charging switch unit, while the other end of the second capacitor C2 discharges to ground through the discharge switch unit. When the external clock signal CLK1 is low, the voltage at the other end of the second capacitor C2 is negative and charges the third capacitor C3 through the charging switch unit, while the other end of the first capacitor C1 discharges to ground through the discharge switch unit. In addition, one end of the third capacitor C3 forms the SAR... The output terminal of the negative voltage generation circuit of the ADC outputs the negative voltage charged into the third capacitor C3 by the first capacitor C1 and the second capacitor C2, i.e., outputting a negative voltage Vout. In addition, as a preferred embodiment of the present invention, the capacitance value of the third capacitor C3 is much larger than the capacitance values ​​of the first capacitor C1 and the second capacitor C2, so that the third capacitor C3 can store enough charge to be used as a power source, thereby continuously providing a negative voltage to the SAR ADC. In the present invention, in order for the third capacitor C3 to store enough negative charge to provide a stable negative voltage output voltage Vout, the capacitance value of the third capacitor C3 is usually set to 1000 times or more the capacitance of the first capacitor C1 or the second capacitor C2.Therefore, the negative voltage generation circuit of this invention provides a negative voltage to the SAR ADC, enabling most of the circuitry in the SAR ADC to operate at low power supply voltages. This eliminates the influence of offset voltage in the SAR ADC and improves the overall circuit response speed and calibration accuracy. The first resistor R1 and the third capacitor C3 form a filter circuit to filter out potential noise at the output, ensuring the stability of the output voltage Vout.

[0019] Please refer to the references. Figure 2 , Figure 2This is a schematic diagram of one embodiment of the negative voltage generation circuit for SAR ADC of the present invention. In this embodiment, the negative voltage generation circuit for SAR ADC further includes a second inverter INV2. The input terminal of the second inverter INV2 is connected to the output terminal of the first inverter INV1, and the output terminal of the second inverter INV2 is connected to one end of the second capacitor C2. By setting the second inverter INV2, the clock signal CLK2 is inverted and output as a clock signal CLK3, which means that the clock signal input to one end of the second capacitor C2 is CLK3. Obviously, the clock signal CLK3 is in phase and frequency with the clock signal CLK1. However, the driving capability of the clock signal CLK1 generated by the external circuit is usually relatively low. After being converted by the second inverter INV2, the driving capability of the clock signal CLK3 input to the second capacitor C2 is improved. Specifically: The first inverter INV1 includes a first MOSFET M1 and a second MOSFET M2, and the second inverter INV2 includes a third MOSFET M3 and a fourth MOSFET M4. An external clock signal CLK1 is input to the gates of the first MOSFET M1 and the second MOSFET M2 respectively. The drains of the first MOSFET M1 and the second MOSFET M2 are connected together to form the output terminal of the first inverter INV1. The source of the first MOSFET M1 is connected to the power supply voltage AVD, and the source of the second MOSFET M2 is grounded. The output terminal of the first inverter INV1 outputs a clock signal CLK2, and the clock signal CLK2 has the same frequency and opposite phase to the input clock signal CLK1. The output terminal of the first inverter INV1 is connected to the gates of the third MOSFET M3 and the fourth MOSFET M4 respectively, so as to input the clock signal CLK2 to the second inverter INV2. The drains of the third MOSFET M3 and the fourth MOSFET M4 are connected together to form the output terminal of the second inverter INV2 and connected to one end of the second capacitor C2. The source of the third MOSFET M3 is connected to the power supply voltage AVD, and the source of the fourth MOSFET M4 is grounded. Furthermore, the aspect ratio of the first MOSFET M1, the second MOSFET M2, the third MOSFET M3, and the fourth MOSFET M4 is 20-50, so that the aspect ratio of the first MOSFET M1, the second MOSFET M2, the third MOSFET M3, and the fourth MOSFET M4 is large enough, so that the current is larger when it is turned on. The larger the current, the faster the charging, thereby realizing rapid charging of the first capacitor C1 and the second capacitor C2, improving the driving capability of the clock signals CLK2 and CLK3, and reducing or even eliminating the problem of insufficient driving force of the externally input clock signal CLK1.

[0020] The discharge switch unit includes a fifth MOSFET M5 and a sixth MOSFET M6. The source of the fifth MOSFET M5 and the gate of the sixth MOSFET M6 are both connected to the other end of the first capacitor C1 to form node a. The source of the sixth MOSFET M6 and the gate of the fifth MOSFET M5 are both connected to the other end of the second capacitor C2 to form node b. The drains of the fifth MOSFET M5 and the sixth MOSFET M6 are both grounded. Nodes a and b serve as the two endpoints of the discharge switch unit. Since the drains of the fifth MOSFET M5 and the sixth MOSFET M6 are both grounded, when the fifth MOSFET M5 is turned on, node a can discharge to ground through the fifth MOSFET M5. Correspondingly, when the sixth MOSFET M6 is turned on, node b can discharge to ground through the sixth MOSFET M6.

[0021] The charging switch unit includes a seventh MOSFET M7 and an eighth MOSFET M8. The source of the eighth MOSFET M8 and the gate of the seventh MOSFET M7 are both connected to the other end of the second capacitor C2 (forming node b). The drain of the seventh MOSFET M7 and the gate of the eighth MOSFET M8 are both connected to the other end of the first capacitor C1 (forming node a). The source of the seventh MOSFET M7 and the drain of the eighth MOSFET M8 are both grounded. Node b and node a serve as the two input terminals of the charging switch unit. Specifically, when the seventh MOSFET M7 is turned on, node a, as the input terminal, charges the third capacitor C3 through the seventh MOSFET M7. Correspondingly, when the eighth MOSFET M8 is turned on, node b, as the input terminal, charges the third capacitor C3 through the eighth MOSFET M8.

[0022] Below, in conjunction with Figure 1 and Figure 2 The operation of the negative voltage generation circuit for SAR ADC of the present invention is described as follows: In the initial state, the power supply voltage AVD has just been powered on, and at this time the voltages of nodes a and b are both at ground level.

[0023] When the external clock signal CLK1 is high (first stage), clock signal CLK2 is low, and clock signal CLK3 is also high. At this time, because clock signal CLK2 suddenly goes low, the voltage at node a drops to -AVD. Because clock signal CLK3 suddenly goes high, the voltage at node b rises to the power supply voltage AVD. This causes the seventh MOSFET M7 to turn on and the eighth MOSFET M8 to turn off. After the seventh MOSFET M7 turns on, node a charges the third capacitor C3, resulting in a negative input charge, causing the output voltage Vout to become negative. The voltage at node a also changes from negative to ground as the charging of the third capacitor C3 is completed. Simultaneously, because the voltage at node a is negative, the sixth MOSFET M6 turns on, connecting node b to ground. Therefore, node b discharges to ground through the sixth MOSFET M6, causing its voltage to drop to ground.

[0024] Thus, both nodes a and b return to ground voltage, and clock signal CLK1 jumps low (second stage). At this time, clock signal CLK2 suddenly goes high, and clock signal CLK3 suddenly goes low, causing the voltage of node a to suddenly change to the power supply voltage AVD, and the voltage of node b to suddenly change to -AVD. At this time, the seventh MOSFET M7 turns off, and the eighth MOSFET M8 turns on. Node b begins to charge the third capacitor C3 through the eighth MOSFET M8, thus inputting negative charge. Since the voltage of node b is negative, the fifth MOSFET M5 turns on, and node a discharges to ground through the fifth MOSFET M5. The voltage of node a will drop to ground level, while the voltage of node b will rise to ground level due to charging C3.

[0025] As described above, after each stage, the voltages of nodes a and b will return to ground level. During each stage, either node a or node b will input a negative charge to the third capacitor C3, repeating the first and second stages (that is, repeating the clock cycle of the clock signal CLK1) until the voltage of the third capacitor C3 drops to -AVD. At this time, the negative voltage charging of the third capacitor C3 is completed, so that the output voltage Vout at the output terminal is stable at -AVD, that is, a stable negative voltage is generated.

[0026] In summary, the negative voltage generation circuit for SAR ADC of the present invention, by setting the first capacitor C1, the second capacitor C2, the discharge switch unit, and the charging switch unit, can charge the third capacitor C3 twice within one clock cycle of the external clock signal CLK1, thereby accelerating the charging speed until the voltage of the third capacitor C3 is charged to -AVD. This allows the third capacitor C3 to output a stable negative voltage, thereby systematically offsetting the decision threshold of the comparator in the SAR ADC, thus compensating for its inherent positive offset voltage, and returning the actual switching point of the comparator to the ideal zero differential input position.

[0027] The present invention has been described above in conjunction with the preferred embodiments, but the present invention is not limited to the embodiments disclosed above, but should cover various modifications and equivalent combinations made in accordance with the essence of the present invention.

Claims

1. A negative voltage generation circuit for a SAR ADC, characterized in that, The circuit includes a first inverter, a first capacitor, a second capacitor, a discharge switch unit, a charging switch unit, a first resistor, and a third capacitor. An external clock signal is input to the input terminal of the first inverter and one end of the second capacitor. The output terminal of the first inverter is connected to one end of the first capacitor. The other end of the first capacitor is connected to one end of the discharge switch unit and one input terminal of the charging switch unit. The other end of the second capacitor is connected to the other end of the discharge switch unit and the other input terminal of the charging switch unit. One end of the first resistor is connected to the output terminal of the discharge switch unit, and its other end is connected to one end of the third capacitor. The other end of the third capacitor is grounded, and one end of the third capacitor forms the output terminal of the negative voltage generation circuit for the SAR ADC to output a negative voltage. When the external clock signal is high, the voltage at the other end of the first capacitor is negative and charges the third capacitor through the charging switch unit, while the other end of the second capacitor discharges to ground through the discharge switch unit. When the external clock signal is low, the voltage at the other end of the second capacitor is negative and charges the third capacitor through the charging switch unit, while the other end of the first capacitor discharges to ground through the discharge switch unit.

2. The negative voltage generation circuit for SAR ADC as described in claim 1, characterized in that, The capacitance value of the third capacitor is much greater than that of the first capacitor and the second capacitor.

3. The negative voltage generation circuit for SAR ADC as described in claim 2, characterized in that, It also includes a second inverter, the input of which is connected to the output of the first inverter, and the output of which is connected to one end of the second capacitor.

4. The negative voltage generation circuit for SAR ADC as described in claim 3, characterized in that, The first inverter includes a first MOSFET and a second MOSFET, and the second inverter includes a third MOSFET and a fourth MOSFET. An external clock signal is input to the gates of the first MOSFET and the second MOSFET respectively. The drains of the first MOSFET and the second MOSFET are connected together to form the output terminal of the first inverter. The source of the first MOSFET is connected to the power supply voltage, and the source of the second MOSFET is grounded. The output terminal of the first inverter is connected to the gates of the third MOS transistor and the fourth MOS transistor respectively. The drains of the third MOS transistor and the fourth MOS transistor are connected together to form the output terminal of the second inverter and connected to one end of the second capacitor. The source of the third MOS transistor is connected to the power supply voltage, and the source of the fourth MOS transistor is grounded.

5. The negative voltage generation circuit for SAR ADC as described in claim 4, characterized in that, The width-to-length ratio of the first MOSFET, the second MOSFET, the third MOSFET, and the fourth MOSFET is 20-50.

6. The negative voltage generation circuit for SAR ADC as described in claim 3, characterized in that, The discharge switch unit includes a fifth MOS transistor and a sixth MOS transistor. The source of the fifth MOS transistor and the gate of the sixth MOS transistor are both connected to the other end of the first capacitor. The source of the sixth MOS transistor and the gate of the fifth MOS transistor are both connected to the other end of the second capacitor. The drains of the fifth MOS transistor and the sixth MOS transistor are both grounded.

7. The negative voltage generation circuit for SAR ADC as described in claim 3, characterized in that, The charging switch unit includes a seventh MOS transistor and an eighth MOS transistor. The source of the eighth MOS transistor and the gate of the seventh MOS transistor are both connected to the other end of the second capacitor. The drain of the seventh MOS transistor and the gate of the eighth MOS transistor are both connected to the other end of the first capacitor. The source of the seventh MOS transistor and the drain of the eighth MOS transistor are both grounded.

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