DC voltage standard source and generation method for engine test system calibration

Abstract

The present invention relates to a DC voltage standard source, and in particular to a DC voltage standard source and generation method for calibrating an engine test system, which solves the technical problem that the existing programmable linear voltage divider cannot meet the design requirements of the influence of thermoelectric potential, noise and external interference factors caused by temperature difference on the output of the programmable linear voltage divider, and the performance change of the programmable linear voltage divider during long-term use. The DC voltage standard source for calibrating an engine test system has an input end of a modulation control signal generator connected to the output end of a control unit CPU. According to the n value set by the control unit CPU, it generates a pulse sequence with a period of T and a pulse width of (n / m)T, and sends it to a shaping circuit through an optoelectronic isolation circuit; the shaping circuit shapes the pulse sequence into a pair of complementary pulse sequences, and the pair of complementary pulse sequences respectively drive the control ends of a first switch S1 and a second switch S2, and modulates the DC voltage V of the reference voltage source. i Modulate to achieve linear voltage division.

Description

Technical Field

[0001] The present invention relates to a DC voltage standard source, in particular to a DC voltage standard source for calibrating an engine test system and a generation method thereof. Background Art

[0002] Engine testing is an essential component of engine development. It utilizes a dedicated test system to measure the outputs of all test bench sensors. Since the final test result is the measured data obtained during the test, calibrating the test system used in the engine test process is essential and meaningful.

[0003] Each liquid engine test platform's measurement and control room is equipped with dedicated test systems for different parameters, enabling data measurement and analysis of various parameters during testing. Previously, the metrology department performed "single-unit calibration" of the liquid engine test platform's test systems in a standard metrology laboratory. The actual operating environment of the equipment deviated from the calibration environment, and the impact of factors such as the system connection structure, noise, and long-distance signal transmission on the test system's performance at the test site was not assessed. Research, analysis, and experimental verification have shown that the impact of environmental deviations and long-distance transmission on the test system's performance is as low as 0.5%. While strictly controlling payload mass, it is necessary to accurately measure the payload capacity, requiring the engine test platform's test system to maintain an accuracy of 0.3%. Furthermore, because the measurement systems for each parameter are complex and bulky, frequent disassembly and assembly are generally not permitted. Therefore, sending them to the laboratory for verification and calibration is impractical and time-consuming. Therefore, on-site calibration of the liquid engine test platform's test systems is urgently needed, without changing the connection structure, signal transmission method, or original position, ensuring that the calibration status is consistent with the actual operating status.

[0004] Field calibration involves placing the dedicated test system and calibration device simultaneously under on-site conditions for liquid rocket engine testing. This calibration method aligns the operating conditions of the dedicated test system with the calibration conditions, eliminating the need to consider the impact of environmental factors on the performance of the dedicated test system; only the impact of environmental factors on the calibration standard device needs to be considered. While this increases the technical difficulty of developing the calibration standard device, field calibration only requires carefully considering the impact of environmental factors on a single (or a small number of) calibration standards. Compared to laboratory calibration, which requires clarifying the impact of environmental factors on a variety of dedicated test systems, it is more economical and easier to implement. Sensors all output weak electrical signals with very low signal energy. Generating these weak, low-level standard signals presents various technical challenges. For example, generating a DC low-voltage standard source requires addressing thermoelectric potential and drift, reducing noise voltage, and addressing nonlinearity in the DC low-voltage output. Outputting a low DC current requires addressing current noise, material surface leakage, and electromagnetic interference in space.

[0005] The programmable linear voltage divider adjusts a fixed reference voltage to a DC voltage corresponding to the set output DC low voltage. It is the core component for achieving linear regulation of the output low voltage. During engine test system calibration, a high-performance voltage reference source generates a 10V reference voltage. Based on the set output DC low voltage, the microprocessor controls a 6-digit decimal programmable linear voltage divider to divide the reference voltage into 0 to ±10V DC voltages. The design requirements are a voltage divider nonlinearity error of less than 0.001% and an output voltage noise (Vp-p) of ≤ 1μV (0.1Hz to 10Hz). Furthermore, the design of the programmable linear voltage divider must fully consider the impact of temperature differences on the output of the programmable linear voltage divider, noise within the programmable linear voltage divider, and external interference. Performance variations over long-term use must be considered, and appropriate calibration methods must be implemented. Therefore, the design requirements are a transfer coefficient uncertainty of 0.002%, output voltage noise (Vp-p) ≤ 100nV (0.1Hz to 10Hz), and a thermoelectric potential of 10nV / °C.

[0006] However, the existing DC voltage standard source cannot meet the above requirements. Summary of the Invention

[0007] The purpose of the present invention is to solve the technical problems that the existing DC voltage standard source cannot meet the design requirements of the influence of thermoelectric potential, noise and external interference factors on the output of the DC voltage standard source caused by temperature difference, and the performance changes of the DC voltage standard source during long-term use. Instead, a DC voltage standard source and a generation method for calibrating an engine test system are provided to achieve the transfer coefficient uncertainty of 0.002%; output voltage noise Vp-p≤100nV (0.1Hz~10Hz); thermoelectric potential 10nV / ℃ required by the design of a programmable linear voltage divider.

[0008] In order to solve the above technical problems, the technical solution adopted by the present invention is:

[0009] A DC voltage standard source for calibrating an engine test system, which is special in that it includes a control unit CPU, a reference voltage source and a programmable linear voltage divider;

[0010] The reference voltage source is used to provide a DC voltage V i ;

[0011] The programmable linear voltage divider includes an input follower, a pulse train generation module, a first switch S1, a second switch S2, a pulse width follower, a filter and an output follower;

[0012] The input end of the input follower is connected to a reference voltage source, and the output end thereof is connected to one end of a first switch S1, and the other end of the first switch S1 is connected to the input end of the pulse width follower; one end of the second switch S2 is grounded, and the other end thereof is connected to the input end of the pulse width follower; the output end of the pulse width follower is connected to the input end of the filter; the output end of the filter is connected to the input end of the output follower; the output end of the output follower serves as the output end of the programmable linear voltage divider;

[0013] The pulse sequence generation module includes a modulation control signal generator, a photoelectric isolation circuit and a shaping circuit;

[0014] The input end of the modulation control signal generator is connected to the output end of the control unit CPU. It generates a pulse sequence with a period of T and a pulse width of (n / m)T according to the n value corresponding to the voltage division ratio set by the control unit CPU, where m is a constant, and sends it to the shaping circuit through the optoelectronic isolation circuit;

[0015] The shaping circuit shapes the pulse sequence into a pair of complementary pulse sequences, which drive the control terminals of the first switch S1 and the second switch S2 respectively, and the DC voltage V i Modulate to achieve linear voltage division.

[0016] Furthermore, it also includes a range switching unit;

[0017] The range switching unit includes a photoelectric isolation circuit, a driving circuit, a resistance switching circuit and an output resistor;

[0018] The resistance switching circuit includes a plurality of resistance branches connected in parallel, each resistance branch includes a switching switch and a switching resistor connected in series; the resistance values ​​of the switching resistors in different resistance branches are different from each other;

[0019] One end of the resistance switching circuit is connected to the output end of the output follower, and the other end thereof is connected to one end of the output resistor, and the other end of the output resistor is grounded;

[0020] One end of the photoelectric isolation circuit is connected to the output end of the control unit CPU, and the other end thereof is respectively connected to the control ends of the switching switches of the plurality of resistance branches through the driving circuit.

[0021] Furthermore, the modulation control signal generator includes a D flip-flop, a clock generator, a first frequency divider, a second frequency divider and a positive logic RS flip-flop;

[0022] The input D terminal of the D flip-flop is connected to the output terminal of the control unit CPU, and the output Q terminal thereof is connected to the LD terminal of the first frequency divider and the second frequency divider respectively;

[0023] The first frequency divider is a presettable m-frequency divider, whose initial value is 0, and whose output terminal is connected to the R terminal of the positive logic RS flip-flop;

[0024] The second frequency divider is a presettable m-frequency divider, whose initial value is n, and whose output terminal is connected to the S terminal of the positive logic RS flip-flop;

[0025] The output clock of the clock generator is respectively fed into the clock input terminals of the D flip-flop, the first frequency divider and the second frequency divider;

[0026] The positive logic RS flip-flop outputs a pulse train to the shaping circuit.

[0027] Furthermore, the filter is a low-pass Butterworth filter;

[0028] The first switch S1 and the second switch S2 are both AD7502J analog switches;

[0029] The switch uses a relay or a CMOS analog switch.

[0030] Furthermore, the filter is a seventh-order low-pass Butterworth filter with a cut-off frequency of 2 Hz.

[0031] Furthermore, the transfer function of the seventh-order low-pass Butterworth filter is:

[0032]

[0033] Where: B0~B7 are constant coefficients; B0=2.02083545×10 -8 ; B1=1.141221693×10 -6 ;B2=3.222394702×10 -5 ;B3=5.851525672×10 -4 ;B4=7.353244025×10 -3 ;B5=6.394525549×10 -2 ;B6=3.57617974×10 -1 ;B7=1.

[0034] At the same time, the present invention also provides a method for generating a DC voltage standard source for calibrating an engine test system, comprising the following steps:

[0035] Step 1) The modulation control signal generator generates a pulse sequence with a period of T and a pulse width of (n / m)T according to the value n corresponding to the voltage divider ratio set by the control unit CPU. After the pulse sequence is isolated by the optoelectronic isolation circuit, a pair of complementary pulse sequences is generated by the shaping circuit. The pair of complementary pulse sequences respectively drives the first switch S1 and the second switch S2;

[0036] Step 2) The first switch S1 and the second switch S2 are driven by a pair of complementary pulse sequences to input a DC voltage V i Modulate to generate pulse width adjustable and amplitude equal to V i The pulse sequence is filtered to separate the DC component V o And output.

[0037] Furthermore, the specific steps for the modulation control signal generator to generate a pulse sequence in step 1) are as follows: under the clock drive of the clock generator with a period of T0, the D trigger synchronously drives two presettable m-dividers to work according to the setting command sent by the control unit CPU, wherein the initial value input port of one presettable m-divider inputs the n value corresponding to the voltage division ratio, and its output signal is sent to the S end of the positive logic RS trigger, and the initial value input port of the other presettable m-divider inputs 0, and its output signal is sent to the R end of the positive logic RS trigger, then the output end of the positive logic RS trigger can obtain a pulse sequence with a period of: T=m×T0 and a pulse width of (n / m)T.

[0038] Furthermore, in step 1), the control unit CPU sends a setting command when it detects that the output of the first frequency divider changes from 1 to 0.

[0039] Compared with the prior art, the beneficial effects of the technical solution of the present invention are:

[0040] The present invention provides a DC voltage standard source and generation method for calibrating an engine test system. By controlling the pulse width of the DC voltage output by the reference voltage source, the voltage divider ratio can be controlled, thereby facilitating programmable linear adjustment and achieving an accurate voltage divider ratio. In principle, the accuracy of the voltage divider ratio is determined by the accuracy of the modulated pulse duty cycle. The programmable linear voltage divider of the present invention is only affected by the digital circuit, allowing for easy acquisition of a high-resolution voltage divider ratio while requiring minimal drive power. With only one signal linking the digital and analog circuits, isolation is facilitated, resulting in a long service life, a compact size, and low cost. Although ripples are present, a properly designed low-pass filter can be used to suppress these ripples and achieve the desired result. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 Schematic diagram of the pulse width modulation programmable linear voltage divider of the present invention;

[0042] Figure 2 The waveform diagram of the pulse sequence of the modulation control signal generator in the present invention, wherein T is the period of a pulse sequence, and (n / m)T is the pulse width of a single pulse sequence;

[0043] Figure 3 Schematic diagram of the principle of the modulation control signal generator of the present invention;

[0044] Figure 4 Schematic diagram of the structure of the seventh-order low-pass Butterworth filter in the present invention;

[0045] Figure 5 for Figure 4 Schematic diagram of the equivalent circuit, where Y(jω) is the equivalent admittance;

[0046] Figure 6 for Figure 1 In the equivalent circuit, the second switch S2 is grounded, where Ron1 and Ron2 are the on-resistance values ​​of the first switch S1 and the second switch S2, respectively. s～out C is the capacitance between the S terminal and the output terminal OUT of any positive logic RS flip-flop. out is the capacitance value of OUT terminal to ground, Cs is the input capacitance value of output follower;

[0047] Figure 7 Schematic diagram of an ideal square wave of the pulse sequence in the present invention;

[0048] Figure 8 Schematic diagram of a distorted square wave caused by the influence of the distributed parameters of the first switch S1 and the second switch S2 in the pulse sequence of the present invention;

[0049] Figure 9 A schematic diagram of the structure of the direct voltage division of the resistance switching circuit of the present invention;

[0050] Figure 10 It is a schematic diagram of the range switching principle of the range switching unit circuit of the present invention. DETAILED DESCRIPTION

[0051] The technical solution of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the embodiments described are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of the present invention.

[0052] A DC voltage standard source for calibrating an engine test system, comprising a control unit CPU, a reference voltage source, a programmable linear voltage divider, and a range switching unit;

[0053] The reference voltage source is used to provide a DC voltage V i ;

[0054] The programmable linear voltage divider includes an input follower, a pulse train generation module, a first switch S1, a second switch S2, a pulse width follower, a filter and an output follower;

[0055] The input end of the input follower is connected to a reference voltage source, and the output end thereof is connected to one end of a first switch S1, and the other end of the first switch S1 is connected to the input end of the pulse width follower; one end of the second switch S2 is grounded, and the other end thereof is connected to the input end of the pulse width follower; the output end of the pulse width follower is connected to the input end of the filter; the output end of the filter is connected to the input end of the output follower; the output end of the output follower serves as the output end of the programmable linear voltage divider;

[0056] The pulse sequence generation module includes a modulation control signal generator, a photoelectric isolation circuit and a shaping circuit;

[0057] The input end of the modulation control signal generator is connected to the output end of the control unit CPU. It generates a pulse sequence with a period of T and a pulse width of (n / m)T according to the n value corresponding to the voltage division ratio set by the control unit CPU, where m is a constant, and sends it to the shaping circuit through the optoelectronic isolation circuit;

[0058] The shaping circuit shapes the pulse sequence into a pair of complementary pulse sequences, which drive the control terminals of the first switch S1 and the second switch S2 respectively, and the DC voltage V i Modulate to achieve linear voltage division.

[0059] The range switching unit includes a photoelectric isolation circuit, a driving circuit, a resistance switching circuit and an output resistor;

[0060] The resistance switching circuit includes a plurality of resistance branches connected in parallel, each resistance branch includes a switching switch and a switching resistor connected in series; the resistance values ​​of the switching resistors in different resistance branches are different from each other;

[0061] One end of the resistance switching circuit is connected to the output end of the output follower, and the other end thereof is connected to one end of the output resistor, and the other end of the output resistor is grounded;

[0062] One end of the photoelectric isolation circuit is connected to the output end of the control unit CPU, and the other end thereof is respectively connected to the control ends of the switching switches of the plurality of resistance branches through the driving circuit.

[0063] The modulation control signal generator includes a D flip-flop, a clock generator, a first frequency divider, a second frequency divider and a positive logic RS flip-flop;

[0064] The input D terminal of the D flip-flop is connected to the output terminal of the control unit CPU, and its output Q terminal is connected to the LD terminal of the first frequency divider and the second frequency divider respectively; the first frequency divider is a presettable m frequency divider, its initial value is 0, and its output terminal is connected to the R terminal of the positive logic RS flip-flop; the second frequency divider is a presettable m frequency divider, its initial value is n, and its output terminal is connected to the S terminal of the positive logic RS flip-flop; the output clock of the clock generator is respectively sent to the clock input terminals of the D flip-flop, the first frequency divider and the second frequency divider; the positive logic RS flip-flop outputs a pulse sequence to the shaping circuit.

[0065] In this embodiment, the filter is a low-pass Butterworth filter, specifically a seventh-order low-pass Butterworth filter with a cutoff frequency of 2 Hz; the first switch S1 and the second switch S2 are both AD7502J analog switches; the switching switch is a relay or a CMOS analog switch.

[0066] Among them, the transfer function of the seventh-order low-pass Butterworth filter is:

[0067]

[0068] Where: B0~B7 are constant coefficients; B0=2.02083545×10 -8 ; B1=1.141221693×10 -6 ;B2=3.222394702×10 -5 ;B3=5.851525672×10 -4 ;B4=7.353244025×10 -3 ;B5=6.394525549×10 -2 ;B6=3.57617974×10 -1 ;B7=1.

[0069] like Figure 1 As shown in the figure, it is a pulse width modulation programmable linear voltage divider. The pulse width modulation programmable linear voltage divider can be used to adjust a DC voltage V of the reference voltage source. i Modulate to generate pulse width adjustable and amplitude equal to DC voltage V i The pulse sequence is filtered to separate the DC component V o This link is equivalent to a DC voltage V i As input, the DC component V o It is a linear voltage divider for DC program control of the output.

[0070] The modulation control signal generator generates a pulse sequence with a period of T and a pulse width of (n / m)T according to the n value corresponding to the voltage division ratio set by the control unit CPU. After the pulse sequence is isolated by the photoelectric isolation circuit, a pair of complementary pulse sequences are generated by the shaping circuit. The pair of complementary pulse sequences respectively drive the first switch S1 and the second switch S2 to adjust the DC voltage V i Modulate to form Figure 2 The V 01 The Fourier series form of the waveform is:

[0071]

[0072] The DC component separated by the filter is:

[0073]

[0074] This is equivalent to a voltage divider, and its voltage divider coefficient is:

[0075]

[0076] In the above formula, m is a constant, k and n are linearly related, and the minimum step of the voltage divider coefficient is 1 / m.

[0077] like Figure 3 The following is the principle block diagram of the modulation control signal generator, where f0 = 10 MHz, T0 = 10-7 s, m = 2 20 -1. Normally, the control unit CPU sets the command L1=1 and loads the command LD=1. When a new voltage divider ratio k is to be set, the value n corresponding to the voltage divider ratio k is sent to the initial value input port of the presettable m-divider 2, and then sends the setting command: "Set L1=0 and keep it for more than 0.2μs, then restore L1=1." Since the D flip-flop plays a synchronous role, no matter when the control unit CPU issues the setting command "(L1=0)" and "restore command (L1=1)", it ensures that the first divider and the second divider, that is, the two presettable m-dividers, have sufficient setup time and hold time for the load command LD. At this time, at the output end of the positive logic RS flip-flop, the period can be obtained as: T=m×T0=104.858ms, and the pulse width is n×10 -7 s pulse sequence.

[0078] After testing, it was found that if the transition process is not taken into account, there will be a large disturbance when the setting value is changed, and the disturbance amount is random, which makes the step setting and step value assessment difficult during the assessment process and future use. The ideal design should be to set the number at the moment when all bits of the first divider are 0 (that is, the moment when the highest bit changes from 1 to 0), so that there will be no disturbance. In order to make the least possible hardware changes, the present invention adopts a solution combining software and hardware for improvement: before changing the setting value, the control unit CPU first detects when the output of the first divider changes from 1 to 0, and then sends a setting command, and reduces the disturbance value to a smaller value through synchronization technology.

[0079] Converting the pulsating waveform of the width modulated pulse into a flat DC signal requires a good high-order low-pass filter. The present invention uses a low-pass Butterworth filter, preferably a 7-order low-pass Butterworth filter. Under the condition of the same order, the amplitude-frequency characteristic of the Butterworth low-pass filter is closest to the ideal low-pass filter near zero frequency, and is flattest in the passband and stopband, but the transition band is wider than the Chebyshev filter and the elliptic filter, and narrower than the Bessel filter. The phase-frequency characteristic is not as good as the Bessel filter, but better than the Chebyshev filter and the elliptic filter. Compared with the Chebyshev filter, the amplitude-frequency characteristic fluctuates in the passband, monotonically decays in the stopband, has a narrow transition band, and has poor phase-frequency characteristics. The amplitude-frequency characteristic of the elliptic function filter fluctuates in both the passband and the stopband, has the narrowest transition band, and has the worst phase-frequency characteristics.

[0080] According to the noise requirements of the overall design, the ripple needs to be attenuated to 10 -6 , using a seventh-order low-pass Butterworth filter, when n = 7, the cutoff frequency f c It should be designed to be below 3Hz. To ensure the performance of the programmable linear voltage divider, the cutoff frequency of the seventh-order low-pass Butterworth filter is designed to be 2Hz.

[0081] The standard transfer function of a seventh-order low-pass Butterworth filter is:

[0082]

[0083] Its normalized parameters are: a0=1.00000, a1=4.49396, a2=10.09783, a3=14.59179, a4=14.59179, a5=10.09783, a6=4.49396, a7=1.00000.

[0084] According to the formula:

[0085] i=0, 1, 2, 3,…7…………………………………………(5)

[0086] Get the transfer function:

[0087]

[0088] Where: B0~B7 are constant coefficients; B0=2.02083545×10 -8 ; B1=1.141221693×10 -6 ;B2=3.222394702×10 -5 ;B3=5.851525672×10 -4 ;B4=7.353244025×10 -3 ;B5=6.394525549×10 -2 ;B6=3.57617974×10 -1 ;B7=1.

[0089] In order to avoid the influence of operational amplifier offset and drift, select Figure 4 The seventh-order low-pass Butterworth filter shown in Figure 4 The circuit can be equivalent to Figure 5 The circuit shown in Figure 1 is the circuit in which Y(jω) is the equivalent admittance.

[0090] At this point, the transfer function of the circuit can be expressed as:

[0091] H(s)=1 / (RY(s)+1)…………………………………………(7)

[0092] from Figure 4 、 Figure 5 The circuit can be obtained:

[0093] Y(s)=(C1+C2)s+(R1+R2)C1C2s2+C1C2R1R2s2{(C3+C4)s+C3C4(R3+R4)s2+C3C4R3R4s2[(C5+C6)s+C5C6(R5+R6)s2+C5C6C7R5R6s2]}………………(8) Substituting into formula (7), we can get the transfer function:

[0094]

[0095] in:

[0096] b7=1;

[0097] b6=R(C1+C2);

[0098] b5=R(R1+R2)C1C2;

[0099] b4=RC1C2(C3+C4)R1R2;

[0100] b3=RC1C2C3C4 R1R2(R3+R4);

[0101] b2=RC1C2C3C4(C5+C6)R1R2R3R4;

[0102] b1=RC1C2C3C4C5C6 R1R2R3R4(R5+R6);

[0103] b0=RC1C2C3C4C5C6 R1R2R3R4R5R6C7;

[0104] From formula (9), the circuit structure parameters that meet the transfer parameters are: C1 = C2 = C3 = C4 = C5 = C6 = C7 = 4.7 μF; R = 38.044 kΩ; R1 = 60.772 kΩ; R2 = 15.316 kΩ; R3 = 36.328 kΩ; R4 = 7.535 kΩ; R5 = 7.542 kΩ; R6 = 7.528 kΩ.

[0105] In order to achieve better DC transmission characteristics and better dynamic characteristics, it is planned to use AD7502J analog switch as Figure 1 The first switch S1 and the second switch S2 are obtained in the equation; considering that the internal resistance of the reference voltage source Rs→0 and the load impedance R4→∞, the second switch S2 is grounded, and the AD7502J equivalent circuit is obtained, as shown in Figure 5 shown. Figure 5 Middle C s～out is the capacitance between any S terminal and the output terminal (OUT), C s～out ≈5pF; Cout is the capacitance of the OUT terminal to ground, Cout≈15pF; Cs is the input capacitance of the operational amplifier, Cs<20pF; Is is the leakage current when the first switch S1 or the second switch S2 is turned off, Is≈0.2nA; Ron1 and Ron2 are the on-resistance values ​​of the first switch S1 or the second switch S2, respectively, both of which are 170Ω. It is not difficult to obtain the DC transfer characteristics:

[0106] When the first switch S1 is closed and the second switch S2 is open: V0 = V i1 ±3×10 -7 V;

[0107] When the first switch S1 is open and the second switch S2 is closed: V0 = ±3×10 -7 V;

[0108] Dynamic characteristics:

[0109] At t=0, the first switch S1 is closed and the second switch S2 is open, so:

[0110] At t=0, the first switch S1 is open and the second switch S2 is closed, so:

[0111] τ1=R 0n1 C0;

[0112] τ2=R 0n2 C0;

[0113] Since (R0n1-R0n2) / R0n1≤50%, τ1≈τ2≈340×50×10 -12 <50(ns).

[0114] Since the input DC voltage V i The DC voltage transmission error is 10V and the modulation period T is 100ms.

[0115] Δk1=3×10 -7 V / 10V=3×10 -8

[0116] like Figure 6 The ideal waveform of the pulse train shown has a voltage divider ratio of:

[0117]

[0118] like Figure 7 As shown, considering the influence of the distributed parameters of the first switch S1 and the second switch S2, the dynamic transmission error is calculated; the actual voltage division ratio is calculated based on the distorted waveform:

[0119]

[0120]

[0121] ∵T>>τ1,T>>τ2

[0122]

[0123] The quantization error of the programmable linear voltage divider is:

[0124] The error caused by the output follower offset current is: Δk4<10pA×20kΩ=2×10 -7

[0125] The error caused by the output follower offset voltage is: Δk4<1×10 -6

[0126] Voltage division ratio uncertainty:

[0127] Δk=3×10 -8 +2×10 -7 +1×10-7 +2×10 -7 +1×10 -6 <1.5×10 -6 ………(12)

[0128] The output follower of the pulse width modulation programmable linear voltage divider adopts an operational amplifier in-phase follower amplifier circuit. The output resistance of the operational amplifier is about 100Ω, and the open-loop gain of the operational amplifier is A>10 6 , the output resistance of the in-phase follower amplifier circuit is: 100Ω / (1+A)<10 -4 Ω.

[0129] Considering that the test objects of the designed "multi-channel DC voltage standard source" all have high input impedance, the internal resistance requirement of the range switching unit of this design is 100Ω, which is not very high. Therefore, the following can be used: Figure 9 As shown in FIG, the solution of directly dividing the voltage by resistors is beneficial to improving the reliability and stability of the device.

[0130] To output a DC low voltage by dividing a 10V DC voltage, a programmable linear voltage divider and an output follower are required. The thermoelectric potential at the output end is sufficiently small, and the noise voltage is sufficiently small. The effects of device noise, contact thermoelectric potential, and contact performance of the switching device on the performance of the programmable linear voltage divider must be fully considered. Figure 10 .

[0131] The internal resistance of each range switching unit of the present invention is 100Ω, that is, R0 = 100Ω. In the 1mV output range, switch S1 is closed and other switches are open, and the transfer coefficient is 1×10 －4 , we can calculate: R1 = 1MΩ. To allow for a certain margin of adjustment during calibration, the control unit CPU makes a correction and sets R1 to 990kΩ. This provides a certain margin of adjustment. In the 10mV output range, with switch S2 closed and the other switches open, the transfer coefficient is 1×10 －3 , R2 is 990kΩ. In the 100mV output range, switch S3 is closed and the other switches are open, and the transfer coefficient is 1×10 －2 Similarly, R3 is set to 9.8kΩ. In the 1V output range, switch S4 is closed and the other switches are open, and the transfer coefficient is 1×10 －1 Similarly, R3 is set to 890Ω.

[0132] Switches generally use relays or CMOS analog switches. Analog switches have advantages such as long life, fast action, low drive power and no contact potential, but they have a large on-resistance (R on >0.8Ω), the off resistance is relatively small (R off <10 10Ω, resulting in a 0.01nA off-state current), has certain thermal noise, poor control and signal isolation, and other disadvantages. Therefore, this invention will not adopt it at present. If, after actual testing, the on-resistance, leakage current, and especially the noise voltage can meet the design requirements, it can be used as an alternative solution.

[0133] The relay has a small on-resistance (R on <50mΩ), the off resistance is relatively large (R off <10 12 Ω), and no thermal noise, but there are disadvantages such as certain thermal noise in the contact potential, high driving power, short life, and large size. In particular, the driving coil will emit heat when it is energized for a long time, changing the temperature of nearby nodes and generating thermoelectric potential, which is the parameter that the present invention pays most attention to. For this reason, a self-locking low thermal potential relay is adopted, that is, as long as a closing or opening signal is given to the relay at the moment of switching the range (t=5ms), the relay will always remain in the closed or open state after the operation. The driving coil no longer has a driving current. Since the switching of the range takes a very short time in the entire measurement process, the influence of the thermoelectric potential introduced by the heat dissipation of the driving coil on the sensitive nodes can be ignored.

[0134] The present invention also provides a method for generating a DC voltage standard source for calibrating an engine test system, comprising the following steps:

[0135] Step 1) The modulation control signal generator generates a pulse sequence with a period of T and a pulse width of (n / m)T according to the value n corresponding to the voltage divider ratio set by the control unit CPU. After the pulse sequence is isolated by the optoelectronic isolation circuit, a pair of complementary pulse sequences is generated by the shaping circuit. The pair of complementary pulse sequences respectively drives the first switch S1 and the second switch S2;

[0136] Driven by a clock with a period of T0 of the clock generator, when the control unit CPU detects that the output of the first frequency divider changes from 1 to 0, it sends a setting command; the D flip-flop synchronously drives the two presettable m frequency dividers to work according to the setting command sent by the control unit CPU, wherein the initial value input port of one presettable m frequency divider inputs the n value corresponding to the voltage dividing ratio K, and its output signal is sent to the S end of the positive logic RS flip-flop, and the initial value input port of the other presettable m frequency divider inputs 0, and its output signal is sent to the R end of the positive logic RS flip-flop, then the output end of the positive logic RS flip-flop can obtain a pulse sequence with a period of: T = m × T0 and a pulse width of (n / m)T.

[0137] Step 2) The first switch S1 and the second switch S2 are driven by a pair of complementary pulse sequences to input a DC voltage V i Modulate to generate pulse width adjustable and amplitude equal to V i The pulse sequence is filtered to separate the DC component Vo And output.

Claims

1. A DC voltage standard source for calibrating an engine test system, characterized by: It includes a control unit CPU, a reference voltage source, a programmable linear voltage divider, and a range switching unit; The reference voltage source is used to provide a DC voltage V i ; The programmable linear voltage divider includes an input follower, a pulse train generation module, a first switch S1, a second switch S2, a pulse width follower, a filter and an output follower; The input end of the input follower is connected to a reference voltage source, and the output end thereof is connected to one end of a first switch S1, and the other end of the first switch S1 is connected to the input end of the pulse width follower; one end of the second switch S2 is grounded, and the other end thereof is connected to the input end of the pulse width follower; the output end of the pulse width follower is connected to the input end of the filter; the filter is a seventh-order low-pass Butterworth filter with a cut-off frequency of 2Hz, and the output end thereof is connected to the input end of the output follower; the output end of the output follower serves as the output of the programmable linear voltage divider; The pulse sequence generation module includes a modulation control signal generator, a photoelectric isolation circuit and a shaping circuit; The input end of the modulation control signal generator is connected to the output end of the control unit CPU, and generates a pulse sequence with a period of T and a pulse width of (n / m)T according to the n value corresponding to the voltage division ratio set by the control unit CPU, where m is a constant, and sends it to the shaping circuit through the photoelectric isolation circuit; The modulation control signal generator includes a D flip-flop, a clock generator, a first frequency divider, a second frequency divider, and a positive logic RS flip-flop; the input D terminal of the D flip-flop is connected to the output terminal of the control unit CPU, and the output Q terminal thereof is connected to the LD terminal of the first frequency divider and the second frequency divider respectively; the first frequency divider is a presettable m frequency divider, whose initial value is 0, and whose output terminal is connected to the R terminal of the positive logic RS flip-flop; the second frequency divider is a presettable m frequency divider, whose initial value is n, and whose output terminal is connected to the S terminal of the positive logic RS flip-flop; the output clock of the clock generator is respectively fed into the clock input terminals of the D flip-flop, the first frequency divider, and the second frequency divider; the positive logic RS flip-flop outputs a pulse sequence to the shaping circuit; The shaping circuit shapes the pulse sequence into a pair of complementary pulse sequences, which respectively drive the control ends of the first switch S1 and the second switch S2 to control the DC voltage V i Modulation is performed to achieve linear voltage division; the first switch S1 and the second switch S2 are both AD7502J type analog switches; the range switching unit includes a photoelectric isolation circuit, a drive circuit, a resistance switching circuit and an output resistor; the resistance switching circuit includes multiple resistance branches in parallel, and each resistance branch includes a switching switch and a switching resistor in series; the switching switch adopts a relay or a CMOS analog switch; one end of the resistance switching circuit is connected to the output end of the output follower, and the other end is connected to one end of the output resistor, and the other end of the output resistor is grounded; one end of the photoelectric isolation circuit is connected to the output end of the control unit CPU, and the other end is connected to the control ends of the switching switches of multiple resistance branches through the drive circuit.

2. A DC voltage standard source for calibrating an engine test system according to claim 1, characterized in that: The transfer function of the seventh-order low-pass Butterworth filter is: Where: B0~B7 are constant coefficients; B0=2.02083545×10 -8 ; B1=1.141221693×10 -6 ;B2=3.222394702×10 -5 ;B3=5.851525672×10 -4 ;B4=7.353244025×10 -3 ;B5=6.394525549×10 -2 ;B6=3.57617974×10 -1 ;B7=1.

3. A method for generating a DC voltage standard source for calibrating an engine test system, based on the DC voltage standard source for calibrating an engine test system according to claim 1 or 2, characterized in that: The following steps are involved: Step 1) The modulation control signal generator generates a pulse sequence with a period of T and a pulse width of (n / m)T according to the value n corresponding to the voltage divider ratio set by the control unit CPU. After the pulse sequence is isolated by the optical isolation circuit, a pair of complementary pulse sequences is generated by the shaping circuit. The pair of complementary pulse sequences respectively drives the first switch S1 and the second switch S2; Step 2) The first switch S1 and the second switch S2 are driven by a pair of complementary pulse sequences to input a DC voltage V i Modulate to generate pulse width adjustable and amplitude equal to V i The pulse sequence is filtered to separate the DC component V o And output.

4. The method for generating a DC voltage standard source for calibrating an engine test system according to claim 3, characterized in that: The specific steps of the modulation control signal generator generating the pulse sequence in step 1) are as follows: Driven by a clock with a period of T0 of the clock generator, the D flip-flop synchronously drives two presettable m-dividers to work according to the setting command sent by the control unit CPU, wherein the initial value input port of one presettable m-divider inputs the n value corresponding to the voltage division ratio, and its output signal is sent to the S terminal of the positive logic RS flip-flop, and the initial value input port of the other presettable m-divider inputs 0, and its output signal is sent to the R terminal of the positive logic RS flip-flop, then the output terminal of the positive logic RS flip-flop can obtain a pulse sequence with a period of: T=m×T0 and a pulse width of (n / m)T.

5. The method for generating a DC voltage standard source for calibrating an engine test system according to claim 4, characterized in that: In step 1), the control unit CPU sends a setting command when it detects that the output of the first frequency divider changes from 1 to 0.

Images