Wafer test system and test method thereof

Abstract

The present disclosure provides a die test system and a test method thereof. The die test system includes a control device to provide a test command and a test device. The test device includes a die under test having a temperature compensation resistor string and a calibration resistor string. The test device performs a frequency test operation according to the test command. The frequency test operation includes: at a first temperature, sequentially adjusting the temperature compensation resistor string to a plurality of temperature compensation resistor values, and sequentially adjusting the calibration resistor string to perform output frequency calibration on the die under test to generate a plurality of calibration resistor values; performing interpolation operation on the plurality of temperature compensation resistor values and the plurality of calibration resistor values; sequentially performing output frequency test at a second temperature and a third temperature according to the plurality of interpolated temperature compensation resistor values and the plurality of interpolated calibration resistor values to generate a plurality of output frequencies.

Description

Technical Field

[0001] The present invention relates to a bare die testing system, and more particularly to a bare die testing system capable of performing output frequency testing under different temperature conditions and a testing method thereof. Background Art

[0002] Traditionally, semiconductor component testing can be divided into pre-package testing (bare die testing) and post-package testing. Pre-package testing generally uses a probe card to test the bare die, while post-package testing tests the pins after packaging. Traditionally, the output frequency of the bare die is tested at room temperature, low temperature, and high temperature using multiple sets of temperature compensation coefficients (the resistance values ​​of the temperature compensation resistor string). However, if the bare die yield is found to be too low and a different set of temperature compensation coefficients is desired, the traditional method requires repeated high and low temperature cycling to collect data, which consumes a significant amount of testing time. Summary of the Invention

[0003] The present invention provides a bare die testing system and a testing method thereof, which are used to solve the problem that bare die testing cannot quickly test multiple groups of temperature compensation coefficients.

[0004] An embodiment of the present invention provides a bare crystal testing system. The bare crystal testing system includes but is not limited to a control device and a test device. The control device is used to provide a test command to the test device. The test device includes a bare crystal to be tested having a temperature compensation resistor string and a calibration resistor string, and the test device performs a frequency test operation according to the test command. The frequency test operation includes: at a first temperature, the test device sequentially adjusts the temperature compensation resistor string to a plurality of temperature compensation resistor values ​​according to the test command, and sequentially adjusts the calibration resistor string to perform output frequency calibration on the bare crystal to be tested, so as to generate a plurality of calibration resistor values ​​corresponding to the plurality of temperature compensation resistor values; the control device interpolates the plurality of temperature compensation resistor values ​​and the plurality of calibration resistor values ​​to generate a plurality of interpolated temperature compensation resistor values ​​and a plurality of interpolated calibration resistor values; the test device sequentially performs an output frequency test according to the plurality of interpolated temperature compensation resistor values ​​and the plurality of interpolated calibration resistor values ​​at a second temperature and a third temperature, so as to generate a plurality of output frequencies corresponding to the plurality of interpolated temperature compensation resistor values ​​and the plurality of interpolated calibration resistor values.

[0005] An embodiment of the present invention provides a bare die testing method applicable to a bare die testing system, wherein the bare die testing system includes but is not limited to a control device and a test device. The control device is used to provide a test command, and the test device includes a bare die to be tested having a temperature compensation resistor string and a calibration resistor string. The frequency testing method includes: at a first temperature, sequentially adjusting the temperature compensation resistor string to a plurality of temperature compensation resistor values ​​according to the test command, and sequentially adjusting the calibration resistor string to perform output frequency calibration on the bare die to be tested to generate a plurality of calibration resistor values ​​corresponding to the plurality of temperature compensation resistor values; performing interpolation operations on the plurality of temperature compensation resistor values ​​and the plurality of calibration resistor values ​​to generate a plurality of interpolated temperature compensation resistor values ​​and a plurality of interpolated calibration resistor values; and sequentially performing output frequency testing based on the plurality of interpolated temperature compensation resistor values ​​and the plurality of interpolated calibration resistor values ​​at a second temperature and a third temperature to generate a plurality of output frequencies corresponding to the plurality of interpolated temperature compensation resistor values ​​and the plurality of interpolated calibration resistor values.

[0006] Based on the above, in an embodiment of the present invention, interpolation is used to increase the number of sets of temperature compensation resistor values ​​and calibration resistor values, thereby sequentially generating multiple output frequencies at low and high temperatures. Since interpolation is performed only once at both low and high temperatures to obtain multiple sets of interpolated temperature compensation resistor values ​​and interpolated calibration resistor values ​​for output frequency testing, repeated high and low temperature ramping and testing are unnecessary, significantly saving testing time.

[0007] In order to make the above features and advantages of the present invention more easily understood, embodiments accompanied by drawings are described in detail below. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and together with the description serve to explain the principles of the invention.

[0009] Figure 1 FIG. 1 is a block diagram illustrating a bare die testing system according to an embodiment of the present invention.

[0010] Figure 2 FIG. 1 is a flow chart illustrating a bare die testing method according to an embodiment of the present invention.

[0011] Figure 3 FIG. 1 is a flow chart illustrating a frequency test method of a bare die test according to an embodiment of the present invention.

[0012] Figure 4A 、 Figure 4B 、 Figure 4C 、 Figure 4D 、 Figure 4E 、 Figure 4F 、 Figure 4G 、 Figure 4HFIG. 4 shows a plurality of output frequency drift curves according to an embodiment of the present invention. DETAILED DESCRIPTION

[0013] Reference will now be made in detail to the embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numerals are used in the drawings and the specification to refer to the same or like parts.

[0014] Figure 1 FIG2 is a block diagram showing a bare die test system according to an embodiment of the present invention. Figure 1 The bare crystal test system 10 includes but is not limited to a control device 110 and a test device 120. The control device 110 has an input-output circuit 111, a processor 112 and a memory 113. The control device 110 is used to provide a test command CMD to the test device 120. The input-output circuit is used to provide a test command CMO and receive an output frequency CKO. The processor 112 is coupled to the input-output circuit 111 to provide a test command CMO and perform related operations and data processing in the frequency test operation. The memory 113 is used to store data in the frequency test operation. The test device 120 includes a bare crystal to be tested 121. The bare crystal to be tested 121 has a temperature compensation resistor string 122, a calibration resistor string 123, a processor 124 and an input-output circuit 125. The processor 124 in the bare crystal to be tested 121 is used to generate an output frequency CKO in combination with other circuits of the bare crystal to be tested 121. The test device 120 receives the test command CMD via the input / output circuit 125 and provides an output frequency CKO to the control device 110. The control device 110 and the test device 120 perform frequency testing operations based on the test command CMD. The temperature-compensating resistor string 122 and the calibration resistor string 123 may be variable resistor strings. The temperature-compensated resistance value of the temperature-compensating resistor string 112 and the calibration resistance value of the calibration resistor string 123 are controlled by the control device 110.

[0015] Figure 2 Flowchart showing a bare die testing method according to an embodiment of the present invention. Regarding the frequency test operation, in step S210, at a first temperature, the test device can sequentially adjust a plurality of temperature compensation resistor strings to a plurality of temperature compensation resistance values ​​according to a test command, and sequentially adjust the calibration resistor string to perform frequency calibration on the bare die to be tested, so as to generate a plurality of calibration resistance values ​​corresponding to the plurality of temperature compensation resistance values. For example, at 25 degrees Celsius (the first temperature), the test device 120 can sequentially adjust the temperature compensation resistor string 122 in the test device 120 to a plurality of temperature compensation resistance values ​​according to a test command CMD, and sequentially adjust the calibration resistor string 123 to perform output frequency calibration on the bare die to be tested 121, so as to obtain a plurality of calibration resistance values ​​corresponding to the plurality of temperature compensation resistance values.

[0016] Furthermore, the multiple temperature compensation resistance values ​​include a default temperature compensation resistance value RT1, a maximum temperature compensation resistance value RT2, and a minimum temperature compensation resistance value RT3, and the maximum temperature compensation resistance value RT2 is greater than the default temperature compensation resistance value RT1, and the default temperature compensation resistance value RT1 is greater than the minimum temperature compensation resistance value RT3. The test device 120 first adjusts the temperature compensation resistor string 122 to the default temperature compensation resistance value RT1 according to the test command CMD, and then adjusts the calibration resistance value to the calibration resistance value RC1 corresponding to the default temperature compensation resistance value RT1, so that the output frequency of the bare die 121 to be tested is calibrated to the reference frequency REF, where the reference frequency REF is, for example, 12 MHz. Next, the temperature compensation resistor string 122 is adjusted to the maximum temperature compensation resistance value RT2, and then the calibration resistance value is adjusted to the calibration resistance value RC2 corresponding to the maximum temperature compensation resistance value RT2, so that the output frequency of the bare die 121 to be tested is calibrated to the reference frequency REF. Finally, the temperature compensation resistor string 122 is adjusted to the minimum temperature compensation resistance RT3, and the calibration resistance value is adjusted to the calibration resistance value RC3 corresponding to the minimum temperature compensation resistance RT3, so that the output frequency of the bare die 121 to be tested is calibrated to the reference frequency REF.

[0017] Next, in step S220, the control device 110 performs an interpolation operation on the multiple sets of temperature-compensated resistance values ​​and calibration resistance values. The interpolation operation may be a Newton polynomial interpolation operation to generate a plurality of interpolated temperature-compensated resistance values ​​and a plurality of interpolated calibrated resistance values. Specifically, the control device 110 may perform an interpolation operation on the default temperature-compensated resistance value RT1 and its corresponding calibration resistance value RC1, the maximum temperature-compensated resistance value RT2 and its corresponding calibration resistance value RC2, and the minimum temperature-compensated resistance value RT3 and its corresponding calibration resistance value RC3 to generate eight sets of interpolated temperature-compensated resistance values ​​IT1-IT8 and their corresponding interpolated calibration resistance values ​​IC1-IC8. Please note that the number of eight sets is merely an example, and the present invention does not limit the number of values ​​generated by the interpolation operation. For example, the interpolation operation may first set the interpolated temperature-compensated resistance value IT4 to the default temperature-compensated resistance value RT1 and the corresponding interpolated calibration resistance value IC4 to the calibration resistance value RC1. The interpolated temperature-compensated resistance value IT8 is set as the maximum temperature-compensated resistance value RT2, and the corresponding interpolated calibration resistance value IC8 is set as the calibration resistance value RC2. The interpolated temperature-compensated resistance value IT1 is set as the minimum temperature-compensated resistance value RT3, and the corresponding interpolated calibration resistance value IC1 is set as the calibration resistance value RC3, as shown in Table 1.

[0018] Table 1

[0019] IT1 IT2 IT3 IT4 IT5 IT6 IT7 IT8 RT3 RT1 RT2 IC1 IC2 IC3 IC4 IC5 IC6 IC7 IC8 RC3 RC1 RC2

[0020] Next, the control device 110 interpolates (IT1, IC1) and (IT4, IC4) to obtain interpolated temperature-compensated resistance values ​​IT2-IT3 between (RT3, RC3) and (RT1, RC1), and their corresponding interpolated calibration resistance values ​​IC2-IC3. The control device 110 also interpolates (IT4, IC4) and (IT8, IC8) to obtain interpolated temperature-compensated resistance values ​​IT5-IT7 between (RT1, RC1) and (RT2, RC2), and their corresponding interpolated calibration resistance values ​​IC5-IC7.

[0021] It should be noted that after the interpolation operation, the interpolated temperature-compensated resistance values ​​IT1-IT8 gradually increase. That is, the interpolated temperature-compensated resistance value IT1 is smaller than the interpolated temperature-compensated resistance value IT2, which is smaller than the interpolated temperature-compensated resistance value IT3, which is smaller than the interpolated temperature-compensated resistance value IT4, and so on, with the interpolated temperature-compensated resistance value IT8 being the maximum value. For example, the interpolated temperature-compensated resistance values ​​IT1-IT8 can have values ​​of 443, 450, 457, 464, 471, 478, 485, and 492, respectively. "Step" is a schematic unit representing the adjustable number of steps in the resistor string, not the actual unit. Furthermore, there are eight sets of interpolated temperature-compensated resistance values ​​IT1-IT8, which is greater than the three sets of multiple compensation resistance values ​​RT1-RT3. Furthermore, the number of the plurality of interpolated calibration resistance values ​​IC1 - IC8 is 8 groups, which is greater than the number of the plurality of calibration resistance values ​​RC1 - RC3 is 3 groups.

[0022] In step S230, the testing device 120 may sequentially perform output frequency testing based on the plurality of interpolated temperature-compensated resistance values ​​and the plurality of interpolated correction resistance values ​​at the second temperature and the third temperature to generate a plurality of output frequencies corresponding to the plurality of interpolated temperature-compensated resistance values ​​and the plurality of interpolated correction resistance values. In one embodiment, the second temperature is lower than the first temperature, and the third temperature is higher than the first temperature. For example, the second temperature and the third temperature may be -40 degrees Celsius and 125 degrees Celsius, respectively. The testing device 120 may perform output frequency testing based on the plurality of interpolated temperature-compensated resistance values ​​IT1-IT8 and the plurality of interpolated correction resistance values ​​IC1-IC8 to generate a plurality of output frequencies CKO1-CKO8 corresponding to the plurality of interpolated temperature-compensated resistance values ​​IT1-IT8 and the plurality of interpolated correction resistance values ​​IC1-IC8. In one embodiment, the test device 120 may first adjust the temperature compensating resistor string 122 and the calibration resistor string 123 in the die under test 124 at -40 degrees Celsius based on the interpolated temperature compensating resistor values ​​IC1-IC8 and the interpolated calibration resistor values ​​IT1-IT8, thereby generating eight output frequencies CKO1-CKO8 corresponding to the eight interpolated temperature compensating resistor values ​​IC1-IC8 and the interpolated calibration resistor values ​​IT1-IT8 at -40 degrees Celsius. Next, the test device 120 may adjust the temperature compensating resistor string 122 and the calibration resistor string 123 in the die under test 124 at 125 degrees Celsius based on the interpolated temperature compensating resistor values ​​IC1-IC8 and the interpolated calibration resistor values ​​IT1-IT8, thereby generating eight output frequencies CKO9-CKO16 corresponding to the eight interpolated temperature compensating resistor values ​​IC1-IC8 and the interpolated calibration resistor values ​​IT1-IT8 at 125 degrees Celsius.

[0023] Figure 3 This is a flowchart showing the frequency test method of the bare die test according to an embodiment of the present invention. Figure 2 and Figure 3 In step S310, the bare die test system 10 starts the frequency test operation. Step S320 corresponds to Figure 2 Step S210 includes steps S321 to S329. In step S321, the control device 110 loads the default temperature compensation resistance value RT1 to the test device 120 according to the test command CMD, so that the temperature compensation resistor string 122 is adjusted to have the default temperature compensation resistance value RT1. In step S322, the control device 110 adjusts the calibration resistor string 123 to the calibration resistance value RC1 through the test device 120 to perform output frequency calibration, so that the output frequency CKO is calibrated to the reference frequency REF, for example, 12 MHz. Then, in step S323, when the output frequency CKO is calibrated to the reference frequency REF, the control device 120 stores the calibration resistance value RC1 corresponding to the default temperature compensation resistance value RT1 to address 1 in the memory 113.

[0024] At step S324, the control device 110 loads the maximum temperature compensation resistance value RT2 to the testing device 120 according to the testing command CMD, so that the temperature compensation resistance string 122 is adjusted to have the maximum temperature compensation resistance value RT2. At step S325, the control device 110 adjusts the calibration resistance string 123 to the calibration resistance value RC2 by the testing device 120 to perform the output frequency calibration, so that the output frequency CKO is calibrated to the reference frequency REF, for example, 12MHz. Then, at step S326, the control device 120 stores the calibration resistance value RC2 corresponding to the maximum temperature compensation resistance value RT2 to the address 2 in the memory 113 under the condition that the output frequency CKO is calibrated to the reference frequency REF.

[0025] At step S327, the control device 110 loads the minimum temperature compensation resistance value RT3 to the testing device 120 according to the testing command CMD, so that the temperature compensation resistance string 122 is adjusted to have the minimum temperature compensation resistance value RT3. At step S328, the control device 110 adjusts the calibration resistance string 123 to the calibration resistance value RC3 by the testing device 120 to perform the output frequency calibration, so that the output frequency CKO is calibrated to the reference frequency REF, for example, 12MHz. Then, at step S329, the control device 120 stores the calibration resistance value RC3 corresponding to the minimum temperature compensation resistance value RT3 to the address 3 in the memory 113 under the condition that the output frequency CKO is calibrated to the reference frequency REF.

[0026] Then, step S330 corresponds to step S220 of Figure 2 The control device 110 performs the interpolation operation on the temperature compensation resistance values RT1-RT3 and the calibration resistance values RC1-RC3 to generate the interpolated temperature compensation resistance values IT1-IT8 and the interpolated calibration resistance values IC1-IC8.

[0027] Step S340 corresponds to step S230 of Figure 2Step S230 includes steps S341 to S344. In step S341, the test device 120 first cools down to -40 degrees Celsius and sequentially loads the interpolated temperature-compensated resistance values ​​IC1-IC8 and the corresponding interpolated correction resistance values ​​IT1-IT8 to generate output frequencies CKO1-CKO8. Specifically, at -40 degrees Celsius, the control device 110 may first adjust the temperature-compensated resistor string 122 to have the interpolated temperature-compensated resistance value IC1 and the correction resistor string to have the interpolated correction resistance value IT1 through the test device 120. The test device 120 then performs an output frequency test to generate the output frequency CKO1. The same applies to the output frequencies CKO2-CKO8, and no further details are given. In step S342, the control device 120 records and stores the output frequencies CKO1-CKO8 in the memory 113, for example, at addresses other than addresses 1 to 4.

[0028] In step S343, the test device 120 is heated to 125°C and sequentially loads the interpolated temperature-compensated resistor values ​​IC1-IC8 and the corresponding interpolated calibration resistor values ​​IT1-IT8 to generate output frequencies CKO9-CKO16. Specifically, at 125°C, the control device 110 may first adjust the temperature-compensated resistor string 122 to have the interpolated temperature-compensated resistor value IC1 and the calibration resistor string to have the interpolated calibration resistor value IT1 through the test device 120. The test device 120 then performs an output frequency test to generate output frequency CKO9. The same procedure applies to output frequencies CKO10-CKO16 and is not further described. In step S344, the control device 120 records and stores the output frequencies CKO9-CKO16 in the memory 113, for example, at addresses other than addresses 1 to 4.

[0029] In step S350, please refer to Figures 4A to 4H The control device 110 calculates the optimal temperature compensation resistance value according to the above test results. Specifically, the control device 110 generates the optimal temperature compensation resistance value according to the interpolated temperature compensation resistance value IT1-IT8, the interpolated calibration resistance value IC1-IC8, the reference frequency REF and the output frequency CKO1-CKO16. Figures 4A to 4H The temperature versus output frequency drift curve. Figure 4A For example, the control device 110 generates the output frequency CKO1 and the output frequency CKO9 according to 25 degrees (first temperature), -40 degrees (second temperature), 125 degrees (third temperature), the reference frequency REF, Figure 4A The temperature versus output frequency drift curve. The horizontal axis of the temperature versus output frequency drift curve is temperature, and the vertical axis is the output frequency drift ratio. For example, Figure 4AIn the figure, at room temperature of 25 degrees, since the output frequency is calibrated to the reference frequency REF, the output frequency drift ratio is 0%. At -40 degrees, the temperature compensation resistor string 122 is adjusted to the interpolated temperature compensation resistance value IT1, the calibration resistor string 123 is adjusted to the interpolated calibration resistance value IC1, the output frequency CKO1 of the bare crystal 121 to be tested is 11.676MHz, and the corresponding output frequency drift ratio is -2.7%. At 125 degrees, the temperature compensation resistor string 122 is adjusted to the interpolated temperature compensation resistance value IT1, the calibration resistor string 123 is adjusted to the interpolated calibration resistance value IC1, the output frequency CKO1 of the bare crystal 121 to be tested is 12.246MHz, and the corresponding output frequency drift ratio is 2.05%. From the above three points, we can obtain Figure 4A The temperature versus output frequency drift curve in Figure 2 is as follows. Figures 4B to 4F The generation of the output frequency drift curve due to temperature is not described in detail.

[0030] Next, the control device 110 selects the lowest slope curve from the plurality of temperature versus output frequency drift curves to generate an optimal temperature compensation resistance value corresponding to the lowest slope curve. Figures 4A to 4H The temperature versus output frequency drift curve with the lowest slope is selected from a total of 8 sets of temperature versus output frequency drift curves, and the interpolated temperature compensation resistor corresponding to the temperature versus output frequency drift curve with the lowest slope is used as the optimal temperature compensation resistor value. There are at least three ways to select the lowest slope curve: select the one with the lowest slope between 25 degrees and 125 degrees from the 8 sets of temperature versus output frequency drift curves, select the one with the lowest slope between -40 degrees and 25 degrees from the 8 sets of temperature versus output frequency drift curves, and select the one with the lowest slope between -40 degrees and 125 degrees from the 8 sets of temperature versus output frequency drift curves. The selection method depends on the actual application. For example, you can select Figure 4E The temperature-to-output frequency drift curve has the lowest slope between 25°C and 125°C. Figure 4H The temperature-to-output frequency drift curve has the lowest slope between -40°C and 25°C. Figure 4D The temperature-to-output frequency drift curve is the one with the lowest slope between -40°C and 125°C. The slope of the curve can be determined using a bisection approximation method or a least squares method, but is not limited thereto.

[0031] In step S360, the control device 110 stores the optimal temperature compensation resistance value into address 4 of the memory 113. In step S370, the die test system 10 ends the frequency test operation.

[0032] In summary, the present application increases the number of temperature compensation resistance values and calibration resistance values by interpolation operation to sequentially generate a plurality of output frequencies at low and high temperatures. A plurality of frequency drift curves are generated, and the optimal temperature compensation resistance value is calculated based on the plurality of frequency drift curves. Since interpolation operation is only required once at low and high temperatures to obtain a plurality of sets of interpolated temperature compensation resistance values and interpolated calibration resistance values for output frequency testing, there is no need to repeatedly perform high and low temperature cycling to collect data, and a large amount of testing time can be saved.

[0033] It will be apparent to those skilled in the art that various modifications and variations can be made to the present application without departing from the spirit or scope of the application. Thus, it is intended that the present application cover the modifications and variations of this application provided they come within the scope of the appended claims and their equivalents.

Claims

1. A bare die testing system, characterized in that: include: a control device for providing a test command to the test device; as well as A test device, comprising a bare die to be tested having a temperature compensation resistor string and a calibration resistor string, wherein the test device performs a frequency test operation according to the test command. The frequency test operation includes: At a first temperature, the test device sequentially adjusts the temperature compensation resistor string to a plurality of temperature compensation resistance values ​​according to the test command, and sequentially adjusts the calibration resistor string to calibrate the output frequency of the die to be tested, so as to generate a plurality of calibration resistance values ​​corresponding to the plurality of temperature compensation resistance values; The control device performs an interpolation operation on the plurality of temperature-compensated resistance values ​​and the plurality of calibration resistance values ​​to generate a plurality of interpolated temperature-compensated resistance values ​​and a plurality of interpolated calibration resistance values; and The testing device performs output frequency testing according to the multiple interpolated temperature compensation resistance values ​​and the multiple interpolated calibration resistance values ​​at a second temperature and a third temperature in sequence to generate multiple output frequencies corresponding to the multiple interpolated temperature compensation resistance values ​​and the multiple interpolated calibration resistance values.

2. The bare die testing system according to claim 1, wherein: The compensation resistor string and the calibration resistor string are variable resistor strings.

3. The bare die testing system according to claim 1, wherein: The multiple temperature compensation resistance values ​​include a default temperature compensation resistance value, a maximum temperature compensation resistance value, and a minimum temperature compensation resistance value.

4. The bare die testing system according to claim 1, wherein: The output frequency calibration is to calibrate the output frequency of the bare crystal to be tested to a reference frequency.

5. The bare die testing system according to claim 1, wherein: The number of the plurality of interpolated temperature-compensated resistance values ​​is greater than the number of the plurality of compensation resistance values, and the number of the plurality of interpolated calibration resistance values ​​is greater than the number of the plurality of calibration resistance values.

6. The bare die testing system according to claim 1, wherein: The second temperature is lower than the first temperature, and the third temperature is higher than the first temperature.

7. The bare die testing system according to claim 1, wherein: The control device generates a plurality of temperature-to-output frequency drift curves based on the first temperature, the second temperature, the third temperature, a reference frequency, and the plurality of output frequencies, and selects a curve with the lowest slope from the plurality of temperature-to-output frequency drift curves to generate an optimal temperature compensation resistance value corresponding to the curve with the lowest slope.

8. A bare die testing method, characterized in that: Applicable to a bare die test system, the bare die test system includes a control device and a test device, the control device is used to provide a test command, the test device includes a bare die to be tested having a temperature compensation resistor string and a calibration resistor string, and performs a frequency test method according to the test command, the frequency test method including: At a first temperature, sequentially adjusting the temperature compensation resistor string to a plurality of temperature compensation resistance values ​​according to the test command, and sequentially adjusting the calibration resistor string to calibrate the output frequency of the die to be tested to generate a plurality of calibration resistance values ​​corresponding to the plurality of temperature compensation resistance values; interpolating the plurality of temperature-compensated resistance values ​​and the plurality of calibration resistance values ​​to generate a plurality of interpolated temperature-compensated resistance values ​​and a plurality of interpolated calibration resistance values; and Output frequency tests are performed sequentially at a second temperature and a third temperature according to the plurality of interpolated temperature compensation resistance values ​​and the plurality of interpolated calibration resistance values ​​to generate a plurality of output frequencies corresponding to the plurality of interpolated temperature compensation resistance values ​​and the plurality of interpolated calibration resistance values.

9. The bare die testing method according to claim 8, wherein: The multiple temperature compensation resistance values ​​include a default temperature compensation resistance value, a maximum temperature compensation resistance value, and a minimum temperature compensation resistance value.

10. The bare die testing method according to claim 9, wherein: The number of the plurality of interpolated temperature-compensated resistance values ​​is greater than the number of the plurality of compensation resistance values, and the number of the plurality of interpolated calibration resistance values ​​is greater than the number of the plurality of calibration resistance values.

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