Display substrate and display device

Abstract

The display substrate and display device provided by the present disclosure include a base substrate having a display area and a frame area. In the frame area: a shift register includes an output transistor, and the first pole of the output transistor is the output end of the shift register; a jumper disk is between the shift register and the display area, and includes a first sub-jumper disk on the same layer as the gate of the output transistor; a common electrode line is between the shift register and the display area, and there is a gap between the common electrode line and the jumper disk; a jumper wire includes first and second sub-jumper wires, the first sub-jumper wire is above the layer where the output transistor is located, and the second sub-jumper wire is arranged on a different layer from the first sub-jumper disk; the first sub-jumper wire overlaps with the first sub-jumper disk, and the second sub-jumper wire does not overlap with the gap, the first sub-jumper wire connects the first sub-jumper disk and the second sub-jumper wire, and the second sub-jumper wire is connected to the first pole of the output transistor.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display substrate and a display device. Background Art

[0002] With the rapid development of display technology, display panels are showing a trend towards high integration and low cost. Gate driver on array (GOA) technology integrates transistors on the display substrate to drive the gate lines row by row via the gate driver circuit. This saves space in the bonding area of ​​the gate integrated circuit (IC) and the wiring space in the fan-out area of ​​the gate lines. This not only reduces production costs in terms of material costs and manufacturing processes, improves production capacity and yield, but also enables the display substrate to achieve a beautiful design with bilateral symmetry and narrow bezels. Summary of the Invention

[0003] The display substrate and display device provided by the present disclosure are specifically described as follows:

[0004] In one aspect, an embodiment of the present disclosure provides a display substrate, comprising:

[0005] A base substrate, the base substrate comprising a display area and a frame area located on at least one side of the display area;

[0006] The shift register is located in the border area, and the shift register includes an output transistor, wherein the first pole of the output transistor is the output end of the shift register;

[0007] A jumper tray is located between the shift register and the display area, the jumper tray includes a first sub-jumper tray, and the first sub-jumper tray is arranged on the same layer as the gate of the output transistor;

[0008] A common electrode wiring is located between the shift register and the display area, with a gap between the common electrode wiring and the jumper tray;

[0009] A jumper wire is located in the border area, and the jumper wire includes a first sub-jumper wire and a second sub-jumper wire, wherein the first sub-jumper wire is located on a side of the layer where the output transistor is located away from the base substrate, and the second sub-jumper wire and the first sub-jumper tray are arranged in different layers; the orthographic projection of the first sub-jumper wire on the base substrate overlaps with the orthographic projection of the first sub-jumper tray on the base substrate, and the orthographic projection of the second sub-jumper wire on the base substrate does not overlap with the orthographic projection of the gap on the base substrate, the first sub-jumper wire connects the first sub-jumper tray and the second sub-jumper wire, and the second sub-jumper wire is connected to the first electrode of the output transistor.

[0010] In some embodiments, the display substrate provided in the embodiments of the present disclosure further includes: a second transparent conductive layer located on the side of the layer where the output transistor is located away from the base substrate, and the first sub-jump wire is located in the second transparent conductive layer.

[0011] In some embodiments, in the above-mentioned display substrate provided in the embodiments of the present disclosure, the jumper wire further includes a third sub-jumper wire, the orthographic projection of the third sub-jumper wire on the base substrate overlaps with the orthographic projection of the first pole of the output transistor on the base substrate, and the third sub-jumper wire connects the second sub-jumper wire and the first pole of the output transistor.

[0012] In some embodiments, in the above-mentioned display substrate provided by the embodiments of the present disclosure, the third sub-jumping line is located in the second transparent conductive layer.

[0013] In some embodiments, the above-mentioned display substrate provided in the embodiment of the present disclosure further includes: a first transparent conductive layer insulated from the second transparent conductive layer, the first transparent conductive layer being located between the layer where the output transistor is located and the second transparent conductive layer; and the second sub-jumper wire being located in the first transparent conductive layer.

[0014] In some embodiments, in the above-mentioned display substrate provided in the embodiments of the present disclosure, the first transparent conductive layer further includes: a first connecting electrode and a second connecting electrode, wherein the first connecting electrode is connected to the first sub-jumper plate through the first sub-jumper line, and the second connecting electrode is connected to the first pole of the output transistor through the third sub-jumper line, and the first connecting electrode, the second connecting electrode, and the second sub-jumper line are arranged as a whole.

[0015] In some embodiments, in the above-mentioned display substrate provided by the embodiments of the present disclosure, the second sub-jump line is located in the second transparent conductive layer, and the first sub-jump line, the second sub-jump line, and the third sub-jump line are integrally arranged.

[0016] In some embodiments, in the above-mentioned display substrate provided by the embodiments of the present disclosure, the second sub-jumping line is provided in the same layer as the first electrode of the output transistor.

[0017] In some embodiments, in the above-mentioned display substrate provided by the embodiments of the present disclosure, the common electrode wiring is provided on the same layer as the first electrode of the output transistor.

[0018] In some embodiments, in the above-mentioned display substrate provided by the embodiments of the present disclosure, the common electrode wiring is provided in the same layer as the gate of the output transistor.

[0019] In some embodiments, in the above-mentioned display substrate provided in the embodiments of the present disclosure, the jumper tray further includes a second sub-jumper tray, which is arranged on the same layer as the first pole of the output transistor, and the second sub-jumper tray is located on the side of the first sub-jumper tray away from the common electrode routing.

[0020] In some embodiments, in the above-mentioned display substrate provided by the embodiments of the present disclosure, the orthographic projection of the second sub-jumper tray on the base substrate is located within the orthographic projection of the first sub-jumper wire on the base substrate, and the second sub-jumper tray is electrically connected to the first sub-jumper tray through the first sub-jumper wire.

[0021] In some embodiments, in the display substrate provided by the embodiments of the present disclosure, the jumper tray is located between the common electrode trace and the display area, and the common electrode trace includes a first avoidance groove, which is recessed in a direction away from the jumper tray;

[0022] The orthographic projection of the first avoidance groove on the base substrate is a first pattern, the orthographic projection of the jumper tray on the base substrate is a second pattern, and the orthographic projection of the first pattern in the extension direction of the common electrode trace overlaps with the orthographic projection of the second pattern in the extension direction of the common electrode trace.

[0023] In some embodiments, in the above-mentioned display substrate provided by the embodiments of the present disclosure, the orthographic projection of the second pattern in the extension direction of the common electrode trace is located within the orthographic projection of the side of the first pattern adjacent to the second pattern in the extension direction of the common electrode trace.

[0024] In some embodiments, in the display substrate provided by the embodiments of the present disclosure, the common electrode trace includes a first avoidance groove, and the first avoidance groove is recessed in a direction away from the display area;

[0025] The orthographic projection of the jumper tray on the base substrate is located within the orthographic projection of the first avoidance groove on the base substrate.

[0026] In some embodiments, in the above-mentioned display substrate provided by the embodiments of the present disclosure, the width of the first avoidance groove in the direction perpendicular to the extension direction of the common electrode line is less than 1 / 2 of the line width of the common electrode line at the non-avoidance groove.

[0027] In some embodiments, in the above-mentioned display substrate provided in the embodiments of the present disclosure, the first electrode of the output transistor includes a main body portion, the gate of the output transistor includes a coupling portion, and the orthographic projection of the main body portion on the base substrate and the orthographic projection of the coupling portion on the base substrate overlap with each other.

[0028] In some embodiments, in the display substrate provided by the embodiments of the present disclosure, the coupling portion includes a first sub-portion and a second sub-portion integrally provided, wherein the first sub-portion and the second sub-portion extend along the extension direction of the common electrode trace, and the second sub-portion is located on a side of the first sub-portion away from the common electrode trace;

[0029] The orthographic projection of the main portion on the base substrate substantially coincides with the orthographic projection of the second sub-portion on the base substrate.

[0030] In some embodiments, in the above-mentioned display substrate provided by the embodiments of the present disclosure, the first electrode of the output transistor further includes a protrusion, which is integrally provided with the main body, and the protrusion is located on a side of the main body adjacent to the common electrode wiring.

[0031] In some embodiments, the display substrate provided in the embodiments of the present disclosure further includes a second transparent conductive layer located on a side of the layer where the output transistor is located away from the base substrate, and the jumper wire further includes a third sub-jugation wire located in the second transparent conductive layer;

[0032] The first electrode of the output transistor also includes a separation portion, which is located on a side of the protruding portion adjacent to the common electrode wiring, and the orthographic projection of the separation portion on the substrate does not overlap with the orthographic projection of the protruding portion on the substrate, and the separation portion is connected to the protruding portion through the third sub-jumper line.

[0033] In some embodiments, in the display substrate provided by the embodiments of the present disclosure, the first portion includes a second avoidance groove, and the second avoidance groove is recessed in a direction away from the jumper tray;

[0034] The orthographic projection of the protruding portion on the base substrate is located within the orthographic projection of the first sub-portion on the base substrate;

[0035] The orthographic projection of the separation portion on the base substrate is located within the orthographic projection of the second avoidance groove on the base substrate.

[0036] In some embodiments, in the above-mentioned display substrate provided by the embodiments of the present disclosure, the orthographic projection of the main body portion on the base substrate substantially coincides with the orthographic projection of the coupling portion on the base substrate.

[0037] In some embodiments, the display substrate provided in the embodiments of the present disclosure further includes a second transparent conductive layer located on a side of the layer where the output transistor is located away from the base substrate, and the jumper wire further includes a third sub-jugation wire located in the second transparent conductive layer;

[0038] The first electrode of the output transistor further includes a separation portion;

[0039] The main body includes a connection area, which is located on a side of the separation portion away from the common electrode wiring and is arranged adjacent to the separation portion. The orthographic projection of the separation portion on the substrate and the orthographic projection of the connection area on the substrate do not overlap with each other, and the separation portion is connected to the connection area through the third sub-jumper line.

[0040] In some embodiments, in the above-mentioned display substrate provided in the embodiments of the present disclosure, the coupling portion includes a second avoidance groove, which is recessed in a direction away from the jumper disk; the main body portion includes a third avoidance groove, and the orthographic projection of the third avoidance groove on the base substrate roughly coincides with the orthographic projection of the second avoidance groove on the base substrate; the orthographic projection of the separation portion on the base substrate is located within the orthographic projection of the third avoidance groove on the base substrate.

[0041] In some embodiments, in the above-mentioned display substrate provided by the embodiments of the present disclosure, in the extension direction of the common electrode wiring, the length of the main body is greater than the length of the separation portion; in the direction perpendicular to the extension direction of the common electrode wiring, the width of the main body is greater than the width of the separation portion.

[0042] In some embodiments, in the display substrate provided by the embodiments of the present disclosure, the second sub-jump line includes a first line and a second line, wherein the first line is substantially parallel to the common electrode line, and the second line is substantially perpendicular to the common electrode line;

[0043] The first wiring is located on a side of the jumper tray perpendicular to an extending direction of the common electrode wiring. The first wiring connects the first sub-jumper wire and the second wiring. The second wiring connects the first electrode of the output transistor.

[0044] In some embodiments, in the above-mentioned display substrate provided in the embodiment of the present disclosure, the second sub-jumper line also includes a third line, the third line is located on the side of the jumper plate away from the common electrode line, and the third line connects the first line and the first sub-jumper line.

[0045] In some embodiments, in the above-mentioned display substrate provided in the embodiments of the present disclosure, the second sub-jumper line also includes a fourth line, the fourth line and the first line are arranged on the same side of the jumper plate, the angle between the fourth line and the extension direction of the common electrode line is an acute angle, and the fourth line connects the first line and the second line.

[0046] In some embodiments, in the above-mentioned display substrate provided by the embodiments of the present disclosure, the fourth line is a straight line or an arc line.

[0047] In some embodiments, the above-mentioned display substrate provided in the embodiments of the present disclosure further includes a second transparent conductive layer located on the side of the layer where the output transistor is located away from the base substrate, and the jumper wire also includes a third sub-jumper wire located in the second transparent conductive layer; the second routing line is connected to the third sub-jumper wire.

[0048] In some embodiments, in the above-mentioned display substrate provided by the embodiments of the present disclosure, the second sub-jump line further includes a fifth line, the fifth line is substantially parallel to the common electrode line, and the fifth line connects the second line and the third sub-jump line.

[0049] In some embodiments, the display substrate provided in the embodiments of the present disclosure further includes a gate connection line, which is substantially parallel to the first wiring and electrically connected to the first sub-jumper pad.

[0050] On the other hand, an embodiment of the present disclosure provides a display device, including the above-mentioned display substrate provided by an embodiment of the present disclosure.

[0051] In some embodiments, the display device provided in the embodiments of the present disclosure further includes: an opposing substrate and a liquid crystal layer, wherein the opposing substrate is opposite to the display substrate, and the liquid crystal layer is located between the opposing substrate and the display substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] Figure 1 A schematic structural diagram of a display substrate provided in an embodiment of the present disclosure;

[0053] Figure 2 A schematic diagram of a connection between an output transistor and a jumper tray provided in an embodiment of the present disclosure;

[0054] Figure 3Another connection diagram of the output transistor and the jumper tray provided in the embodiment of the present disclosure;

[0055] Figure 4 For the Figure 2 and Figure 3 A cross-sectional view of the line A-A';

[0056] Figure 5 For the Figure 2 and Figure 3 Cross-section of line BB';

[0057] Figure 6 For the Figure 2 and Figure 3 Cross-section of line C-C';

[0058] Figure 7 For the Figure 2 and Figure 3 Cross-section of line D-D';

[0059] Figure 8 Another connection diagram of the output transistor and the jumper tray provided in the embodiment of the present disclosure;

[0060] Figure 9 Another connection diagram of the output transistor and the jumper tray provided in the embodiment of the present disclosure;

[0061] Figure 10 For the Figure 8 Sectional view along line E-E';

[0062] Figure 11 For the Figure 9 Cross-sectional view along line F-F';

[0063] Figure 12 For the Figure 8 and Figure 9 Cross-section along line G-G';

[0064] Figure 13 For the Figure 8 Cross-sectional view along line H-H';

[0065] Figure 14 For the Figure 9 Cross-section along line I-I';

[0066] Figure 15 Another connection diagram of the output transistor and the jumper tray provided in the embodiment of the present disclosure;

[0067] Figure 16 For the Figure 15 Cross-section of the J-J' line;

[0068] Figure 17Another connection diagram of the output transistor and the jumper tray provided in the embodiment of the present disclosure;

[0069] Figure 18 Another connection diagram of the output transistor and the jumper tray provided in the embodiment of the present disclosure;

[0070] Figure 19 For the Figure 17 Cross-section of line K-K';

[0071] Figure 20 For the Figure 18 Cross-sectional view along line L-L';

[0072] Figure 21 For the Figure 17 and Figure 18 Cross-section of the M-M' line;

[0073] Figure 22 For the Figure 18 Cross-section of line N-N';

[0074] Figure 23 A schematic diagram of the projection relationship between the first avoidance groove and the jumper tray provided in an embodiment of the present disclosure;

[0075] Figure 24 Another connection diagram of the output transistor and the jumper tray provided in the embodiment of the present disclosure;

[0076] Figure 25 Another connection diagram of the output transistor and the jumper tray provided in the embodiment of the present disclosure;

[0077] Figure 26 A schematic structural diagram of the first electrode of the output transistor provided in an embodiment of the present disclosure;

[0078] Figure 27 A schematic diagram of another structure of the first electrode of the output transistor provided in an embodiment of the present disclosure;

[0079] Figure 28 Another connection diagram of the output transistor and the jumper tray provided in the embodiment of the present disclosure;

[0080] Figure 29 Another connection diagram of the output transistor and the jumper tray provided in the embodiment of the present disclosure;

[0081] Figure 30 A schematic structural diagram of a display device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0082] To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present disclosure. It should be noted that the sizes and shapes of the figures in the drawings do not reflect the actual scale and are intended only to illustrate the contents of the present disclosure. Throughout, the same or similar reference numerals represent the same or similar elements or elements with the same or similar functions.

[0083] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning understood by persons of ordinary skill in the field to which the present disclosure belongs. The words "first", "second" and similar terms used in this disclosure and the claims do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects preceding the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Inside", "outside", "upper", "lower" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0084] The gate drive circuit in the related art includes a plurality of shift registers arranged in cascade, and each shift register is electrically connected to a gate line corresponding to a jumper tray, and the jumper tray is located between the shift register and the gate line. And because a common electrode line is usually set between the shift register and the jumper tray, it is necessary to set a jumper wire across the common electrode line to realize the electrical connection of the jumper tray and the shift register through the jumper wire. However, since the common electrode line and the jumper tray share a gate metal layer, and under the demand of a narrow frame, the distance between the common electrode line and the jumper tray is small, static electricity (ESD) is easily generated between the common electrode line and the jumper tray, and this static electricity can cause the jumper tray to be broken (GO). When the jumper wire (located in the source and drain metal layer) passes through the gap between the common electrode line and the jumper tray, it can be subjected to static electricity and short-circuit (Gout and Com short, GCS) with the common electrode line, resulting in poor display such as horizontal dark lines and horizontal stripes.

[0085] In order to improve the above technical problems existing in the related art, the present disclosure provides a display substrate, such as Figures 1 to 7 As shown, including:

[0086] A base substrate (Glass) 101, the base substrate 101 including a display area AA and a frame area BB located on at least one side of the display area AA;

[0087] A shift register (GOA) is located in the border area BB. The shift register (GOA) includes an output transistor 102. A first electrode 1021 of the output transistor 102 is an output terminal (GOUT) of the shift register (GOA).

[0088] The jumper tray 103 is located between the shift register (GOA) and the display area AA. The jumper tray 103 includes a first sub-jumper tray 1031 . The first sub-jumper tray 1031 is provided on the same layer as the gate 1022 of the output transistor 102 .

[0089] The common electrode trace 104 is located between the shift register (GOA) and the display area AA. There is a gap S between the common electrode trace 104 and the jumper tray 103. The gap S is a static electricity prone area.

[0090] The jumper 105 is located in the border area BB. The jumper 105 includes a first sub-jumper 1051 and a second sub-jumper 1052, wherein the first sub-jumper 1051 is located on the side of the layer where the output transistor 102 is located away from the base substrate 101, and the second sub-jumper 1052 is arranged on a different layer from the first sub-jumper tray 1031; the orthographic projection of the first sub-jumper 1051 on the base substrate 101 overlaps with the orthographic projection of the first sub-jumper tray 1031 on the base substrate 101, and the orthographic projection of the second sub-jumper 1052 on the base substrate 101 does not overlap with the orthographic projection of the above-mentioned gap S on the base substrate 101. The first sub-jumper 1051 connects the first sub-jumper tray 1031 and the second sub-jumper 1052, and the second sub-jumper 1052 is connected to the first electrode 1021 of the output transistor 102.

[0091] In the above-mentioned display substrate provided in the embodiment of the present disclosure, by overlapping the first sub-jumper line 1051 and the first sub-jumper tray 1031, the orthographic projection of the second sub-jumper line 1052 on the base substrate 101 and the orthographic projection of the above-mentioned gap S on the base substrate 101 do not overlap with each other, so that the jumper line 105 including the first sub-jumper line 1051 and the second sub-jumper line 1052 bypasses the gap S between the common electrode line 104 and the jumper tray 103, thereby avoiding the jumper line 105 from being short-circuited with the common electrode line 104 due to static electricity, thereby improving the display quality.

[0092] It should be noted that, in the present disclosure, "arranged in the same layer" and "located in the layer" all refer to a layer structure formed by using the same film-forming process to form a film layer for producing a specific pattern, and then using the same mask through a single patterning process. That is, one patterning process corresponds to one mask (also known as a photomask). Depending on the specific pattern, one patterning process may include multiple exposure, development, or etching processes, and the specific patterns in the formed layer structure may be continuous or discontinuous, and these specific patterns may be at the same height or have the same thickness, or at different heights or have different thicknesses.

[0093] Optionally, the output transistor 102 provided in the embodiment of the present disclosure may be a thin film transistor (TFT) or a metal oxide semiconductor field effect transistor (MOS), which is not limited here. In a specific implementation, the first electrode 1021 of the output transistor 102 may be a source or a drain. The output transistor 102 may be a P-type transistor or an N-type transistor. In a specific implementation, the voltage difference V between the gate and the source of the P-type transistor is gs Its threshold voltage V th Satisfaction relationship V gs <V th When it is turned on, and when the relationship V gs ≥V th When the N-type transistor is turned off; the voltage difference V between its gate and its source gs Its threshold voltage V th Satisfaction relationship V gs >V th When it is turned on, and when the relationship V gs ≤V th In addition, the active layer of the output transistor 102 may be an amorphous silicon (a-Si) active layer, a polycrystalline silicon (P-Si) active layer, or an oxide (IGZO) active layer, which is not limited here.

[0094] In some embodiments, in the above-mentioned display substrate provided in the embodiments of the present disclosure, as Figures 8 to 12 As shown, the device may further include: a second transparent conductive layer (2ITO) located on the side of the layer where the output transistor 102 is located, away from the base substrate 101, and a first sub-jumper 1051 located on the second transparent conductive layer (2ITO). The first sub-jumper 1051 located on the second transparent conductive layer (2ITO) can be used to electrically connect the first electrode 1021 of the output transistor 102 to the first sub-jumper pad 1031 located on the layer (Gate) where the gate 1022 of the output transistor 102 is located, thereby avoiding the need for a separate masking process (GI mask) on the gate insulating layer (GI) 106.

[0095] In some embodiments, in the above-mentioned display substrate provided in the embodiments of the present disclosure, as Figures 1 to 7 As shown, the jumper 105 may further include a third sub-jumper 1053, the orthographic projection of the third sub-jumper 1053 on the base substrate 101 overlaps with the orthographic projection of the first electrode 1021 of the output transistor 102 on the base substrate 101, and the third sub-jumper 1053 connects the second sub-jumper 1052 and the first electrode 1021 of the output transistor 102, so that the jumper 105 bypasses the gap S between the common electrode trace 104 and the jumper tray 103, thereby preventing the jumper 105 from being short-circuited with the common electrode trace 104 due to static electricity, thereby improving display quality.

[0096] In some embodiments, in the above-mentioned display substrate provided in the embodiments of the present disclosure, as Figures 8 to 12 As shown, the third sub-jump line 1053 may be located on the second transparent conductive layer (2ITO) to avoid performing a separate mask process on the gate insulating layer 106 .

[0097] Continue to see Figures 8 to 12 It can be seen that the above-mentioned display substrate provided by the embodiment of the present disclosure may also include: a first transparent conductive layer (1ITO) insulated from the second transparent conductive layer (2ITO), and the first transparent conductive layer (1ITO) is located between the layer where the output transistor 102 is located and the second transparent conductive layer (2ITO); a first insulating layer (PVX1) 107 and a flat layer (Organic) 108 are provided between the source and drain metal layer (i.e., the layer where the first electrode 1021 of the output transistor 102 is located, SD) and the first transparent conductive layer (1ITO), and a second insulating layer (PVX2) 109 is provided between the first transparent conductive layer (1ITO) and the second transparent conductive layer (2ITO). The first sub-jumper line 1051 can be electrically connected to the first sub-jumper pad 1031 via at least one first via extending through the second insulating layer 109, the planar layer 108, the first insulating layer 107, and the gate insulating layer 106. The third sub-jumper line 1053 can be electrically connected to the first electrode 1021 of the output transistor 102 via at least one second via extending through the second insulating layer 109, the planar layer 108, and the first insulating layer 107. Furthermore, when there are multiple first vias, the contact resistance between the first sub-jumper line 1051 and the first sub-jumper pad 1031 can be effectively reduced. Optionally, the multiple first vias can be arranged in a row. Similarly, when there are multiple second vias, the contact resistance between the third sub-jumper line 1053 and the first electrode 1021 of the output transistor 102 can be effectively reduced. Optionally, the multiple second vias can be arranged in a row.

[0098] In some embodiments, in the above-mentioned display substrate provided in the embodiments of the present disclosure, as Figure 8 、 Figure 9 、 Figure 13 and Figure 14 As shown, the second sub-jugation line 1052 can be located in the first transparent conductive layer (1ITO). The jumper line 105 in the related art is usually located in the source and drain metal layer, and the electrical connection between the jumper line 105 and the jumper pad 103 is achieved by adding a via hole penetrating the gate insulating layer 106. Usually, one of the first transparent conductive layer (1ITO) and the second transparent conductive layer (2ITO) is used as the layer where the pixel electrode is located, and the other is used as the layer where the common electrode is located. When the first transparent conductive layer (1ITO) is used as the layer where the pixel electrode is located, the pixel electrode needs to be electrically connected to the first pole 1021 of the switching transistor through a via hole penetrating the first insulating layer 107 and the flat layer 108. When the second transparent conductive layer (2ITO) is used as the layer where the pixel electrode is located, the pixel electrode needs to be electrically connected to the switching transistor through a via hole penetrating the first insulating layer 107, the flat layer 108, and the second insulating layer 109. Specifically, when the first transparent conductive layer (1ITO) is used as the pixel electrode, a via hole penetrating the planar layer 108 and the first insulating layer 107 can be simultaneously fabricated, and then the pixel electrode of the first transparent conductive layer (1ITO) can be fabricated to achieve electrical connection between the pixel electrode and the switching transistor. When the second transparent conductive layer (2ITO) is used as the pixel electrode, a via hole can be first fabricated in the planar layer 108, followed by the common electrode of the first transparent conductive layer (1ITO). Then, holes can be drilled in the first insulating layer 107 and the second insulating layer 108 at positions corresponding to the via holes in the planar layer 108, and finally, the pixel electrode of the second transparent conductive layer (2ITO) can be fabricated to achieve electrical connection between the pixel electrode and the switching transistor. However, the mask plate of the planar layer 108 used to form the above-mentioned via holes electrically connecting the pixel electrodes, as well as the mask plates (VIA masks) of the first insulating layer 107 and the second insulating layer 108, can introduce static electricity and may break down the gate insulating layer 106, resulting in a short circuit between the jumper line 105 of the source-drain metal layer in the related art and the common electrode trace 104 of the gate metal layer (i.e., the layer where the gate electrode 1022 of the output transistor 102 is located), resulting in poor display. Because the first transparent conductive layer (1ITO) is formed after the via hole formation process of the planar layer 108, the second sub-jugation line 1052 located in the first transparent conductive layer (1ITO) in the present disclosure is not affected by the static electricity introduced by the mask plate used to form the via hole of the planar layer 108, thereby effectively preventing the second sub-jugation line 1052 from shorting with the common electrode trace 104.

[0099] In some embodiments, in the above-mentioned display substrate provided in the embodiments of the present disclosure, as Figures 8 to 12As shown, the first transparent conductive layer (1ITO) may further include: a first connecting electrode 110 and a second connecting electrode 111, wherein the first connecting electrode 110 is connected to the first sub-jumper tray 1031 through the first sub-jumper wire 1051, and the second connecting electrode 111 is connected to the first pole 1021 of the output transistor 102 through the third sub-jumper wire 1053. The first connecting electrode 110, the second connecting electrode 111, and the second sub-jumper wire 1052 are integrally arranged, so that the first sub-jumper tray 1031 is electrically connected to the first pole 1021 of the output transistor 102 through the first sub-jumper wire 1051, the first connecting electrode 110, the second sub-jumper wire 1052, the second connecting electrode 111, and the third sub-jumper wire 1053 in sequence.

[0100] Specifically, if Figures 8 to 12 As shown, the first sub-jump line 1051 can be electrically connected to the first connection electrode 110 via at least one third via hole penetrating the second insulating layer 109, and the third sub-jump line 1053 can be electrically connected to the second connection electrode 111 via at least one fourth via hole penetrating the second insulating layer 109. Furthermore, when there are multiple third via holes, the contact resistance between the first sub-jump line 1051 and the first connection electrode 110 can be effectively reduced. Optionally, the multiple third via holes can be formed in a row. Similarly, when there are multiple fourth via holes, the contact resistance between the third sub-jump line 1053 and the second connection electrode 111 can be effectively reduced. Optionally, the multiple fourth via holes can be formed in a row.

[0101] In some embodiments, in the above-mentioned display substrate provided in the embodiments of the present disclosure, as Figures 15 to 22 As shown, the second sub-jump line 1052 can be located in the second transparent conductive layer (2ITO), and the first sub-jump line 1051, the second sub-jump line 1052, and the third sub-jump line 1053 are integrally provided. Since the second transparent conductive layer (2ITO) is formed after the above-mentioned process of fabricating the via holes electrically connected to the pixel electrodes, the second sub-jump line 1052 located in the second transparent conductive layer (2ITO) in the present disclosure is not affected by static electricity introduced by the mask plate of the planar layer 108 used to fabricate the above-mentioned via holes electrically connected to the pixel electrodes, and the mask plates (VIA mask) of the first insulating layer 107 and the second insulating layer 108, thereby effectively preventing the second sub-jump line 1052 from shorting with the common electrode trace 104.

[0102] In some embodiments, in the above-mentioned display substrate provided in the embodiments of the present disclosure, as Figures 2 to 4As shown, the second sub-jumper line 1052 can be disposed on the same layer as the first electrode 1021 of the output transistor 102. Because the second sub-jumper line 1052 bypasses the gap S between the common electrode trace 104 and the first sub-jumper pad 1031, where static electricity is easily generated, the second sub-jumper line 1052 is not affected by static electricity in the gap S. Therefore, the second sub-jumper line 1052 can be disposed on the same layer as the first electrode 1021 of the output transistor 102 (i.e., the source-drain metal layer).

[0103] In some embodiments, in the above-mentioned display substrate provided in the embodiments of the present disclosure, as Figure 9 、 Figure 14 、 Figure 18 and Figure 22 As shown, the common electrode trace 104 can be arranged in the same layer as the first electrode 1021 of the output transistor 102. Because the common electrode trace 104 and the jumper tray 103 in the related art are both located in the gate metal layer (i.e., the layer where the gate 1022 of the output transistor 102 is located), and the distance between them is relatively close, static electricity is easily generated between them. In the present disclosure, by arranging the common electrode trace 104 in the layer where the first electrode 1021 of the output transistor 102 is located (i.e., the source-drain metal layer), the common electrode trace 104 and the first sub-jumper tray 1031 located in the gate metal layer are arranged in different layers, thereby preventing the generation of static electricity.

[0104] In some embodiments, in the above-mentioned display substrate provided in the embodiments of the present disclosure, as Figures 2 to 4 、 Figure 8 、 Figure 13 、 Figure 15 and Figure 16 As shown, the common electrode trace 104 is disposed on the same layer as the gate 1022 of the output transistor 102. Because the second sub-jumper line 1052 bypasses the gap S between the common electrode trace 104 and the first sub-jumper pad 1031, which is prone to static electricity generation, even if the common electrode trace 104 and the gate 1022 of the output transistor 102 are disposed on the same layer, the second sub-jumper line 1052 is not affected by static electricity in the gap S. Furthermore, disposing the common electrode trace 104 and the gate 1022 of the output transistor 102 on the same layer eliminates the need to change the related art process for manufacturing the common electrode trace 104, thus maintaining excellent compatibility.

[0105] In some embodiments, in the above-mentioned display substrate provided in the embodiments of the present disclosure, as Figure 2 、 Figure 3 and Figure 15As shown, the jumper tray 103 may further include a second sub-jumper tray 1032, which is disposed on the same layer as the first electrode 1021 of the output transistor 102, and the second sub-jumper tray 1032 is located on a side of the first sub-jumper tray 1031 away from the common electrode trace 104. Since the side of the first sub-jumper tray 1031 adjacent to the common electrode trace 104 is located at a gap S where static electricity is prone to occur, by disposing the second sub-jumper tray 1032 on a side of the first sub-jumper tray 1031 away from the common electrode trace 104, the static electricity prone area is effectively avoided. The second sub-jumper tray 1032, which is on the same layer as the first electrode 1021 of the output transistor 102, will not be affected by static electricity, thereby preventing the second sub-jumper tray 1032 from short-circuiting with the common electrode trace 104, thereby having no impact on product display.

[0106] In some embodiments, in the above-mentioned display substrate provided in the embodiments of the present disclosure, as Figure 2 、 Figure 3 and Figure 15 As shown, the orthographic projection of the second sub-jumper tray 1032 on the base substrate 101 is located within the orthographic projection of the first sub-jumper wire 1051 on the base substrate 101, and the second sub-jumper tray 1032 is electrically connected to the first sub-jumper tray 1031 via the first sub-jumper wire 1051. Specifically, the first sub-jumper wire 1051 can be electrically connected to the second sub-jumper tray 1032 via at least one fifth via hole that penetrates the second insulating layer 109, the planar layer 108, and the first insulating layer 107. When there are multiple fifth via holes, the contact resistance between the first sub-jumper wire 1051 and the second sub-jumper tray 1032 can be effectively reduced. Optionally, the multiple fifth via holes can form a row. Optionally, when the first sub-jumper wire 1051 is electrically connected to the first sub-jumper tray 1031 via a row of first via holes, the first via hole and the fifth via hole form two rows of via holes.

[0107] In some embodiments, in the above-mentioned display substrate provided in the embodiments of the present disclosure, as Figure 23As shown, the jumper tray 103 is located between the common electrode trace 104 and the display area AA. The common electrode trace 104 includes a first avoidance groove F1, which is recessed away from the jumper tray 103 to avoid the gap S, where static electricity is likely to occur. Optionally, the first avoidance groove F1 is located on the side of the common electrode trace 104 near the output transistor 102 and recessed toward the jumper tray 103. The orthographic projection of the first avoidance groove F1 on the base substrate 101 is a first pattern U, and the orthographic projection of the jumper tray 103 on the base substrate 101 is a second pattern V. Moreover, the orthographic projection of the first pattern U in the extension direction Y of the common electrode trace 104 overlaps with the orthographic projection of the second pattern V in the extension direction Y of the common electrode trace 104. Since the common electrode line 104 and the jumper tray 103 are close to each other, static electricity is easily generated between them. By setting the first avoidance groove F1 on the common electrode line 104, the distance between the common electrode line 104 and the jumper tray 103 is increased, thereby reducing the probability of static electricity generation. Optionally, the shape of the first pattern U can be Figure 23 The trapezoid shown in , may also be other shapes (such as rectangle, etc.), which is not specifically limited here.

[0108] In some embodiments, in the above-mentioned display substrate provided in the embodiments of the present disclosure, as Figure 23 As shown, in order to minimize the probability of static electricity generation, the orthographic projection of the first pattern U in the extension direction Y of the common electrode trace 104 can be made to completely cover the orthographic projection of the second pattern V in the extension direction Y of the common electrode trace 104. Specifically, the orthographic projection of the second pattern V in the extension direction Y of the common electrode trace 104 can be located within the orthographic projection of the first pattern U on the side adjacent to the second pattern V (i.e., the right bottom side of the trapezoid shown in the figure) in the extension direction Y of the common electrode trace 104; the orthographic projection of the second pattern V in the extension direction Y of the common electrode trace 104 can be located within the orthographic projection of the first pattern U on the side away from the second pattern V (i.e., the left bottom side of the trapezoid shown in the figure) in the extension direction Y of the common electrode trace 104, or it can just coincide with the orthographic projection of the side away from the second pattern V (i.e., the left bottom side of the trapezoid shown in the figure) in the extension direction Y of the common electrode trace 104, or completely cover the orthographic projection of the first pattern U on the side away from the second pattern V (i.e., the left bottom side of the trapezoid shown in the figure) in the extension direction Y of the common electrode trace 104.

[0109] In some embodiments, in the above-mentioned display substrate provided in the embodiments of the present disclosure, as Figure 24As shown, the common electrode trace 104 includes a first avoidance groove F1 that is recessed away from the display area AA. The orthographic projection of the jumper tray 103 on the base substrate 101 at least partially overlaps with the orthographic projection of the first avoidance groove F1 on the base substrate 101. Furthermore, the orthographic projection of the jumper tray 103 on the base substrate 101 is located within the orthographic projection of the first avoidance groove F1 on the base substrate 101. This arrangement not only reduces the probability of static electricity being generated between the common electrode trace 104 and the jumper tray 103, but also enables a narrower bezel design.

[0110] In some embodiments, the second sub-jump line 1052 bypasses the first avoidance groove F1 , that is, the orthographic projection of the second sub-jump line 1052 on the base substrate 101 does not overlap with the orthographic projection of the first avoidance groove F1 on the base substrate 101 .

[0111] In some embodiments, in the above-mentioned display substrate provided in the embodiments of the present disclosure, as Figure 23 and Figure 24 As shown, the width d1 of the first avoidance groove F1 in the direction X perpendicular to the extension direction Y of the common electrode line 104 is less than 1 / 2 of the line width d2 of the common electrode line 104 at the non-avoidance groove position. This can effectively reduce the risk of static electricity generation and effectively prevent the common electrode line 104 from being broken.

[0112] Optionally, in order to take into account the relatively small overall resistance of the common electrode trace 104 and the relatively large distance between the common electrode trace 104 and the jumper disk 103, the width d1 of the first avoidance groove F1 can be designed to account for 5% to 30% of the line width d2 of the common electrode trace 104 at the non-avoidance groove. For example, the line width d2 of the common electrode trace 104 at the non-avoidance groove can be 153 μm, the width d1 of the first avoidance groove F1 is 41 μm, and the width d1 of the first avoidance groove F1 accounts for 27% of the line width d2 of the common electrode trace 104 at the non-avoidance groove; the line width d2 of the common electrode trace 104 at the non-avoidance groove can be 103 μm, the width d1 of the first avoidance groove F1 The width d1 of the first avoidance groove F1 is 31 μm, and the width d1 of the first avoidance groove F1 accounts for 30% of the line width d2 of the common electrode trace 104 at the non-avoidance groove; the line width d2 of the common electrode trace 104 at the non-avoidance groove can be 213 μm, and the width d1 of the first avoidance groove F1 is 14 μm, and the width d1 of the first avoidance groove F1 accounts for 7% of the line width d2 of the common electrode trace 104 at the non-avoidance groove; the line width d2 of the common electrode trace 104 at the non-avoidance groove can be 154 μm, and the width d1 of the first avoidance groove F1 is 22 μm, and the width d1 of the first avoidance groove F1 accounts for 14% of the line width d2 of the common electrode trace 104 at the non-avoidance groove.

[0113] In addition, if Figure 3 、 Figure 9 and Figure 18As shown, if the main body width of the common electrode trace 104 (equivalent to the line width d2 of the common electrode trace 104 at the non-avoidance groove) is less than or equal to 50μm, the common electrode trace 104 is not grooved. Because the groove width of the black matrix (BM) at the corresponding position is 10μm to 30μm, the common electrode trace 104 is required to block light instead of grooves. Considering the deviation (margin) caused by factors such as the manufacturing process, it is necessary to ensure that the common electrode trace 104 is at least 50μm to block light and avoid light leakage.

[0114] In some embodiments, in the above-mentioned display substrate provided in the embodiments of the present disclosure, as Figure 2 、 Figure 3 、 Figure 8 、 Figure 9 、 Figure 15 、 Figure 17 、 Figure 18 、 Figure 24 and Figure 25 As shown, the first electrode 1021 of the output transistor 102 may include a main body portion 21a, and the gate 1022 of the output transistor 102 includes a coupling portion 22'. Due to manufacturing process limitations, the orthographic projection of the main body portion 21 on the substrate 101 and the orthographic projection of the coupling portion 22' on the substrate 101 overlap with each other.

[0115] In some embodiments, in the above-mentioned display substrate provided in the embodiments of the present disclosure, as Figure 2 、 Figure 3 、 Figure 8 、 Figure 9 、 Figure 15 、 Figure 17 and Figure 18 As shown, the coupling portion 22' may include an integrally arranged first section 22a and a second section 22b, wherein the first section 22a and the second section 22b extend along the extension direction Y of the common electrode trace 104, and the second section 22b is located on the side of the first section 22a away from the common electrode trace 104; the orthographic projection of the main body portion 21a on the base substrate 101 may roughly coincide with the orthographic projection of the second section 22b on the base substrate 101, so that the pattern of the main body portion 21a is relatively simple (for example, it may be a rectangle as shown in the figure), which is conducive to the manufacture of the output transistor 102.

[0116] It should be noted that in the embodiments provided in the present disclosure, due to the limitations of process conditions or the influence of other factors such as measurement, the "rough overlap" may be exactly overlapped, or there may be some deviations (for example, a deviation of ±2μm). Therefore, as long as the "rough overlap" relationship between related features meets the error allowance, it falls within the scope of protection of the present disclosure.

[0117] In some embodiments, in the above-mentioned display substrate provided in the embodiments of the present disclosure, as Figure 2 、 Figure 3 、 Figure 8 、 Figure 15 and Figure 17 As shown, the first electrode 1021 of the output transistor 102 may further include a protrusion 21b, which is integrally provided with the main body 21a and is located on a side of the main body 21a adjacent to the common electrode trace 104. The provision of the protrusion 21b reduces the distance between the first electrode 1021 of the output transistor 102 and the jumper tray 103. This allows the use of a shorter second sub-jumper wire 1052 to achieve electrical connection between the first electrode 1021 of the output transistor 102 and the jumper tray 103, thereby reducing the resistance of the second sub-jumper wire 1052 and facilitating reduced transmission path loss of the scan signal provided by the output transistor 102.

[0118] In some embodiments, in the above-mentioned display substrate provided in the embodiments of the present disclosure, as Figure 2 、 Figure 3 and Figure 15 As shown, the jumper 103 further includes a third sub-jugator 1053 located on the second transparent conductive layer (2ITO). The first electrode 1021 of the output transistor 102 may further include a separator 21c. The separator 21c is located on a side of the protruding portion 21b adjacent to the common electrode trace 104. The orthographic projection of the separator 21c on the base substrate 101 does not overlap with the orthographic projection of the protruding portion 21b on the base substrate 101. The separator 21c is connected to the protruding portion 21b via the third sub-jugator 1053. The provision of the separator 21c further reduces the distance between the first electrode 1021 of the output transistor 102 and the jumper tray 103. This allows the use of a shorter second sub-jugator 1052 to achieve electrical connection between the first electrode 1021 of the output transistor 102 and the jumper tray 103, thereby reducing the resistance of the second sub-jugator 1052 and thereby reducing the loss of the scanning signal provided by the output transistor 102 in the transmission path.

[0119] Furthermore, the provision of the separation portion 21 c prevents static electricity accumulated on the first electrode 1021 of the output transistor 102 from being conducted between the first electrode 1021 and the common electrode trace 104, or between the common electrode trace 104 and the jumper tray 103, during the display substrate manufacturing process. Furthermore, because the first electrode 1021 of the output transistor 102 is designed to be separated, and the separation portion 21 c is connected only during the final step of forming the second transparent conductive layer (2ITO) on the display substrate, in other words, the first electrode 1021 is disconnected during the steps prior to the formation of the second transparent conductive layer (2ITO). Therefore, even if a significant amount of static electricity accumulates on the first electrode 1021, it will not be conducted between the first electrode 1021 and the common electrode trace 104, or between the common electrode trace 104 and the jumper tray 103, due to the distance between the first electrode 1021 and the common electrode trace 104.

[0120] In some embodiments, in the above-mentioned display substrate provided in the embodiments of the present disclosure, as Figure 2 、 Figure 3 and Figure 15 As shown, the first section 22a includes a second avoidance groove F2, which is recessed in a direction away from the jumper disk 103; the orthographic projection of the protruding portion 21b on the base substrate 101 is located within the orthographic projection of the first section 22a on the base substrate 101; the orthographic projection of the separating portion 21c on the base substrate 101 is located within the orthographic projection of the second avoidance groove F2 on the base substrate 101; wherein, the second avoidance groove F2 is provided in the region where the separating portion 21c is located, thereby avoiding the separation portion 21c and the gate 1022 of the output transistor 102 from generating coupling capacitance and interfering with each other, and retaining the pattern of the gate 1022 in the region where the main body 21a and the protruding portion 21b are located, which can effectively avoid the gate 1022 from breaking. In addition, the presence of the second avoidance groove F2 effectively increases the distance between the gate 1022 of the output transistor 102 and the common electrode wiring 104, thereby preventing static electricity from being generated therebetween. This not only prevents the gate 1022 of the output transistor 102 and the first electrode 1021 from being short-circuited at the location of the separation portion 21a, but also prevents a short-circuit from occurring between the second sub-jumper wire 1052 and the common electrode wiring 104. Optionally, the shape of the second avoidance groove F2 can be Figure 2 、 Figure 3 and Figure 15 The rectangle shown may also be other shapes, which are not specifically limited here.

[0121] In some embodiments, in the above-mentioned display substrate provided in the embodiments of the present disclosure, as Figure 24 and Figure 25 As shown, the orthographic projection of the main body portion 21 a on the base substrate 101 can roughly coincide with the orthographic projection of the coupling portion 22 ′ on the base substrate 101 , that is, the two coincide exactly, or are within the allowable range of process errors.

[0122] In some embodiments, in the above-mentioned display substrate provided in the embodiments of the present disclosure, as Figure 25 As shown, the jumper 103 further includes a third sub-jugation line 1053 located on the second transparent conductive layer (2ITO). The first electrode 1021 of the output transistor 102 further includes a separator 21c. The main body 21a includes a connection region Q. The connection region Q is located on a side of the separator 21c away from the common electrode trace 104 and is adjacent to the separator 21c. The orthographic projection of the separator 21c on the base substrate 101 does not overlap with the orthographic projection of the connection region Q on the base substrate 101. The separator 21c is connected to the connection region Q via the third sub-jugation line 1053. As described above, the provision of the separator 21c helps reduce the loss of the scanning signal provided by the output transistor 102 during the transmission path and effectively prevents static electricity accumulated on the first electrode 1021 of the output transistor 102 from being transferred between the first electrode 1021 and the common electrode trace 104, and between the common electrode trace 104 and the jumper tray 103.

[0123] In some embodiments, in the above-mentioned display substrate provided in the embodiments of the present disclosure, as Figure 25 As shown, the coupling portion 22' includes a second avoidance groove F2, which is recessed away from the jumper tray 103. The main body 21a includes a third avoidance groove F3, the orthographic projection of which on the substrate 101 substantially overlaps with the orthographic projection of the second avoidance groove F2 on the substrate 101, and the two overlap exactly or within the allowable range of process errors. The separation portion 21c is located within the third avoidance groove F3. As described above, the presence of the second avoidance groove F2 effectively increases the distance between the gate 1022 of the output transistor 102 and the common electrode trace 104, thereby preventing the generation of static electricity. This not only prevents a short circuit between the gate 1022 of the output transistor 102 and the first electrode 1021 at the location of the separation portion 21a, but also prevents a short circuit between the second sub-jumper line 1052 and the common electrode trace 104. In addition, the third avoidance groove F3 and the second avoidance groove F2 are roughly overlapped in their orthographic projections, and the separation portion 21a is arranged in the third avoidance groove F3, which can reduce the coupling capacitance between the first electrode 1021 and the gate 1022 of the output transistor 102 to a certain extent, thereby improving the performance of the transistor.

[0124] Optionally, the orthographic projection of the first avoidance groove F1 on the base substrate 101 is a first pattern, the orthographic projection of the third avoidance groove F3 on the base substrate 101 is a third pattern, and the orthographic projection of the second avoidance groove F2 on the base substrate 101 is a fourth pattern, and the orthographic projection of the first pattern on the extension direction Y of the common electrode trace 104 overlaps with the orthographic projection of the third pattern / fourth pattern on the extension direction Y of the common electrode trace 104.

[0125] In some embodiments, in the above-mentioned display substrate provided in the embodiments of the present disclosure, as Figure 26 and Figure 27 As shown, in the extension direction Y of the common electrode trace 104, the length L1 of the main portion 21a is greater than the length L2 of the separating portion 21c; and in the direction X perpendicular to the extension direction Y of the common electrode trace 104, the width W1 of the main portion 21a is greater than the width W2 of the separating portion 21c. This arrangement not only facilitates the connection of the separating portion 21c to the main portion 21a via the third sub-jumper 1053, but also reduces the space occupied by the first electrode 1021 of the output transistor 102, facilitating a narrow frame design.

[0126] Alternatively, as Figure 26 As shown, to facilitate the connection of the separation portion 21c to the protrusion 21b via the third sub-jumper line 1053, in the extension direction Y of the common electrode trace 104, the length L3 of the protrusion 21b can be approximately equal to the length L2 of the separation portion 21c, that is, the length L3 of the protrusion 21b can be equal to the length L2 of the separation portion 21c, or the difference between the length L3 of the protrusion 21b and the length L2 of the separation portion 21c is within the allowable range of errors caused by measurement or manufacturing processes, for example, the difference between the length L3 of the protrusion 21b and the length L2 of the separation portion 21c can be less than or equal to 5% of the length L2 of the separation portion 21c. In some embodiments, the width W3 of the protrusion 21b is less than the width W1 of the main portion 21a, and the width W3 of the protrusion 21b can be the same as or different from the width W2 of the separation portion 21c, which is not limited here.

[0127] In some embodiments, the length L2 of the separating portion 21c may be 25% to 30% of the length L1 of the main portion 21a, and the width W2 of the separating portion 21c may be 10% to 15% of the width W1 of the main portion 21a. For example, if the length L1 of the main portion 21a is 196 μm and the width W1 is 150 μm, and the length L2 of the separating portion 21c and the length L3 of the protrusion 21b are both 50 μm, and the width W2 of the separating portion 21c is 17 μm, then the length L2 of the separating portion 21c is 26% of the length L1 of the main portion 21a, and the width W2 of the separating portion 21c is 11% of the width W1 of the main portion 21a. For example, the length L1 of the main body 21a is 262 μm, and the width W1 is 121 μm; the length L2 of the separation portion 21c and the length L3 of the protrusion 21b are both 68 μm, and the width W2 of the separation portion 21c is 15 μm. At this time, the length L2 of the separation portion 21c is 26% of the length L1 of the main body 21a, and the width W2 of the separation portion 21c is 12% of the width W1 of the main body 21a.

[0128] In some embodiments, in the above-mentioned display substrate provided in the embodiments of the present disclosure, as Figure 2 、 Figure 3 、 Figure 8 、 Figure 9 、 Figure 15 、 Figure 17 、 Figure 18 、 Figure 23 、 Figure 24 、 Figure 25 、 Figure 28 and Figure 29 As shown, the second sub-jumper line 1052 may include a first line 52a and a second line 52b, wherein the first line 52a is substantially parallel to the common electrode line 104 (i.e., exactly parallel, or within the allowable error range, for example, the angle is less than or equal to 5°), and the second line 52b is substantially perpendicular to the common electrode line 104 (i.e., exactly perpendicular, or within the allowable error range, for example, the deviation from the 90° angle is less than or equal to 5°). In other words, the first line 52a extends along the extension direction Y of the common electrode line 104, and the second line 52b extends along the perpendicular direction X to the extension direction Y of the common electrode line 104. The first line 52a is located on the jumper tray 103. On one side of the direction X perpendicular to the extension direction Y of the common electrode trace 104 (for example, the lower side shown in the figure, of course it can also be the upper side shown in the figure), the first trace 52a connects the first sub-jumper line 1051 and the second trace 52b, and the second trace 52b connects the first pole 1021 of the output transistor 102, so that the second sub-jumper line 1052 is wound from the upper side or the lower side of the jumper disk 103 to be electrically connected to the first pole 1021 of the output transistor 102, thereby avoiding the second sub-jumper line 1052 from being affected by static electricity that may be generated at the gap S between the common electrode trace 104 and the first sub-jumper disk 1031 (i.e., the left side of the first sub-jumper disk 1031).

[0129] In some embodiments, in the above-mentioned display substrate provided in the embodiments of the present disclosure, as Figure 24 and Figure 29 As shown, the second sub-jumper line 1052 may also include a third line 52c, which is located on the side of the jumper tray 103 away from the common electrode line 104. The third line 52c connects the first line 52a and the first sub-jumper line 1051. In this case, the second sub-jumper line 1052 is wound from the right side of the jumper tray 103 to be electrically connected to the first electrode 1021 of the output transistor 102, thereby preventing the second sub-jumper line 1052 from being affected by static electricity that may be generated between the common electrode line 104 and the first sub-jumper tray 1031 (i.e., the left side of the first sub-jumper tray 1031). In addition, as shown in FIG. Figure 28 As shown, for ease of manufacturing, the third wiring 52 c may extend along a direction X perpendicular to the extending direction Y of the common electrode wiring 104 .

[0130] In some embodiments, in the above-mentioned display substrate provided in the embodiments of the present disclosure, as Figure 2 、 Figure 3 、 Figure 8 、 Figure 9 、 Figure 15 、 Figure 17 、 Figure 18 、 Figure 23 、 Figure 25 and Figure 29 As shown, in order to better bypass the gap S that is prone to static electricity, the second sub-jumper line 1052 can also include a fourth line 52d. The fourth line 52d and the first line 52a are arranged on the same side of the jumper tray 103 (for example, both are on the lower side of the jumper tray 103). The angle between the fourth line 52d and the extension direction of the common electrode line 104 is an acute angle (which can be 30° to -60°, preferably 45°). The fourth line 52d connects the first line 52a and the second line 52b. Optionally, the fourth line 52d can be a straight line or an arc, which is not limited here.

[0131] In some embodiments, in the above-mentioned display substrate provided in the embodiments of the present disclosure, as Figure 8 、 Figure 9 、 Figure 17 and Figure 18 As shown, the second sub-jumper line 1052 may further include a fifth line 52e. The fifth line 52e is approximately parallel to the common electrode line 104 (i.e., exactly parallel, or within an allowable error range, for example, with an angle of less than or equal to 5°). The fifth line 52e connects the second line 52b and the third sub-jumper line 1053. The fifth line 52e can further increase the distance between the second sub-jumper line 1052 and the gap S, which is prone to static electricity generation, thereby further preventing a short circuit between the second sub-jumper line 1052 and the common electrode line 104 due to static electricity. Optionally, the fifth line 52e is located on the side of the output transistor 102 close to the common electrode line 104 and forms an acute angle with the common electrode line 104 (which can be 30° to 60°, preferably 45°). The fifth line 52e can be a straight line or an arc. Furthermore, a sixth line may be included, which is approximately perpendicular to the common electrode line 104 (i.e., exactly parallel, or within the allowable error range, for example, the angle is less than or equal to 5°), and connects the fifth line 52e and the first electrode 1021 of the output transistor 102.

[0132] In some embodiments, in the above-mentioned display substrate provided in the embodiments of the present disclosure, as Figure 2 、 Figure 3 、 Figure 8 、 Figure 9 、 Figure 15 、 Figure 17 、 Figure 18 、 Figure 23 、 Figure 25 、 Figure 28 and Figure 29 As shown, a gate connection line 112 may be further included. The gate connection line 112 may be substantially parallel to the first wiring 52a (i.e., exactly parallel, or within an allowable error range, for example, an angle of less than or equal to 5°), and the gate connection line 112 is electrically connected to the first sub-jumper pad 1031. Optionally, the gate connection line 112 may be located at the layer where the gate 1022 of the output transistor 102 is located, and connected between the first sub-jumper pad 1031 and the gate line, so as to transmit the scanning signal to the gate line through the gate connection line 112, wherein the gate line may extend in a direction X perpendicular to the extension direction Y of the common electrode wiring 104.

[0133] It should be noted that in the present disclosure, the second sub-jumper line 1052 can not only adopt the wiring method described above, but also can be flexibly set according to the actual wiring space during specific implementation, as long as the gap S between the common electrode trace 104 and the first sub-jumper plate 1031 can be avoided. No specific limitation is made here.

[0134] Based on the same inventive concept, the present disclosure provides a display device, such as Figure 30 As shown, it includes the display substrate 001 provided in the embodiment of the present disclosure. Since the principle of solving the problem of the display device is similar to the principle of solving the problem of the display substrate, the implementation of the display device provided in the embodiment of the present disclosure can refer to the implementation of the display substrate provided in the embodiment of the present disclosure, and the repeated parts will not be repeated.

[0135] In some embodiments, in the above-mentioned display device provided by the embodiments of the present disclosure, as Figure 30 As shown, the display device may further include: an opposing substrate 002 and a liquid crystal layer 003, wherein the opposing substrate 002 is disposed opposite the display substrate 001, and the liquid crystal layer 003 is located between the opposing substrate 002 and the display substrate 001. In some embodiments, the liquid crystal layer 003 may be confined within the space enclosed by the opposing substrate 002 and the display substrate 001 by a sealing adhesive.

[0136] In some embodiments, in the above-mentioned display device provided by the embodiments of the present disclosure, the first transparent conductive layer (1ITO) and the second transparent conductive layer (2ITO) can both be arranged on the display substrate 001, in which case the display device is an advanced dimension switch (ADS) type liquid crystal display device; or, the first transparent conductive layer (1ITO) and the second transparent conductive layer (2ITO) can also be respectively arranged on the display substrate 001 and the counter substrate 002, in which case the display device is a twisted nematic (TN) type liquid crystal display device.

[0137] In some embodiments, the display device provided in the embodiments of the present disclosure may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, a smart watch, a fitness wristband, a personal digital assistant, or the like. The display device includes, but is not limited to, components such as a radio frequency unit, a network module, an audio output & input unit, a sensor, a display unit, a user input unit, an interface unit, a memory, a processor, and a power supply. In addition, it will be understood by those skilled in the art that the above structure does not constitute a limitation on the display device provided in the embodiments of the present disclosure. In other words, the display device provided in the embodiments of the present disclosure may include more or fewer of the above components, or a combination of certain components, or a different arrangement of components.

[0138] Obviously, those skilled in the art may make various changes and modifications to the embodiments of the present disclosure without departing from the spirit and scope of the embodiments of the present disclosure. Thus, if such changes and modifications of the embodiments of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is intended to include such changes and modifications.

Claims

1. A display substrate, wherein: include: A base substrate, the base substrate comprising a display area and a frame area located on at least one side of the display area; A shift register is located in the frame area, the shift register includes an output transistor, and a first pole of the output transistor is an output end of the shift register; A jumper tray is located between the common electrode wiring and the display area. The jumper tray includes a first sub-jumper tray, and the first sub-jumper tray is arranged on the same layer as the gate of the output transistor; A common electrode trace is located between the shift register and the display area, with a gap between the common electrode trace and the jumper tray; the common electrode trace includes a first avoidance groove, the first avoidance groove is recessed in a direction away from the jumper tray; the orthographic projection of the first avoidance groove on the base substrate is a first pattern, the orthographic projection of the jumper tray on the base substrate is a second pattern, and the orthographic projection of the first pattern in the extension direction of the common electrode trace and the orthographic projection of the second pattern in the extension direction of the common electrode trace overlap with each other; A jumper wire is located in the border area, and the jumper wire includes a first sub-jumper wire and a second sub-jumper wire, wherein the first sub-jumper wire is located on a side of the layer where the output transistor is located away from the base substrate, and the second sub-jumper wire and the first sub-jumper tray are arranged in different layers; the orthographic projection of the first sub-jumper wire on the base substrate overlaps with the orthographic projection of the first sub-jumper tray on the base substrate, and the orthographic projection of the second sub-jumper wire on the base substrate does not overlap with the orthographic projection of the gap on the base substrate, the first sub-jumper wire connects the first sub-jumper tray and the second sub-jumper wire, and the second sub-jumper wire is connected to the first electrode of the output transistor.

2. The display substrate according to claim 1, wherein: Also includes: A second transparent conductive layer is located on a side of the layer where the output transistor is located away from the base substrate, and the first sub-jump wire is located in the second transparent conductive layer.

3. The display substrate according to claim 2, wherein: The jumper line further includes a third sub-jumper line, an orthographic projection of the third sub-jumper line on the substrate overlaps with an orthographic projection of the first electrode of the output transistor on the substrate, and the third sub-jumper line connects the second sub-jumper line and the first electrode of the output transistor. The display substrate according to claim 3 , wherein the third sub-jump line is located in the second transparent conductive layer.

5. The display substrate according to claim 3 or 4, wherein: Also includes: a first transparent conductive layer insulated from the second transparent conductive layer, the first transparent conductive layer being located between the layer where the output transistor is located and the second transparent conductive layer; The second sub-jumping line is located on the first transparent conductive layer.

6. The display substrate according to claim 5, wherein: The first transparent conductive layer also includes: a first connecting electrode and a second connecting electrode, wherein the first connecting electrode is connected to the first sub-jumper plate through the first sub-jumper line, and the second connecting electrode is connected to the first electrode of the output transistor through the third sub-jumper line, and the first connecting electrode, the second connecting electrode, and the second sub-jumper line are arranged as a whole.

7. The display substrate according to claim 3 or 4, wherein: The second sub-jumping line is located in the second transparent conductive layer, and the first sub-jumping line, the second sub-jumping line, and the third sub-jumping line are integrally arranged.

8. The display substrate according to any one of claims 1 to 4, wherein: The second sub-jumping line is arranged on the same layer as the first electrode of the output transistor.

9. The display substrate according to claim 6, wherein: The common electrode wiring is arranged on the same layer as the first electrode of the output transistor.

10. The display substrate according to claim 6, wherein: The common electrode wiring is arranged on the same layer as the gate of the output transistor.

11. The display substrate according to claim 10, wherein: The jumper tray further includes a second sub-jumper tray, which is arranged on the same layer as the first electrode of the output transistor and is located on a side of the first sub-jumper tray away from the common electrode wiring.

12. The display substrate according to claim 11, wherein: The orthographic projection of the second sub-jump tray on the base substrate is located within the orthographic projection of the first sub-jump wire on the base substrate, and the second sub-jump tray is electrically connected to the first sub-jump tray through the first sub-jump wire.

13. The display substrate according to claim 1, wherein: The orthographic projection of the second pattern in the extending direction of the common electrode line is located within the orthographic projection of a side of the first pattern adjacent to the second pattern in the extending direction of the common electrode line.

14. The display substrate according to any one of claims 1 to 4, 6, 9 to 10, and 13, wherein: The common electrode wiring includes a first avoidance groove, and the first avoidance groove is recessed in a direction away from the display area; The orthographic projection of the jumper tray on the base substrate is located within the orthographic projection of the first avoidance groove on the base substrate.

15. The display substrate according to claim 1, wherein The width of the first avoidance groove in a direction perpendicular to the extension direction of the common electrode line is less than 1 / 2 of the line width of the common electrode line at a position other than the avoidance groove.

16. The display substrate according to any one of claims 1 to 4, 6, 9 to 10, and 13, wherein: The first electrode of the output transistor includes a main body portion, the gate of the output transistor includes a coupling portion, and an orthographic projection of the main body portion on the base substrate overlaps with an orthographic projection of the coupling portion on the base substrate.

17. The display substrate according to claim 16, wherein: The coupling portion includes a first sub-portion and a second sub-portion integrally provided, wherein the first sub-portion and the second sub-portion extend along the extension direction of the common electrode wiring, and the second sub-portion is located on a side of the first sub-portion away from the common electrode wiring; The orthographic projection of the main portion on the base substrate substantially coincides with the orthographic projection of the second sub-portion on the base substrate.

18. The display substrate according to claim 17, wherein: The first electrode of the output transistor further includes a protruding portion, which is integrally provided with the main body, and is located on a side of the main body adjacent to the common electrode wiring.

19. The display substrate according to claim 18, wherein: It also includes a second transparent conductive layer located on a side of the layer where the output transistor is located away from the substrate, and the jumper wire further includes a third sub-jumper wire located on the second transparent conductive layer; The first electrode of the output transistor also includes a separation portion, which is located on a side of the protruding portion adjacent to the common electrode wiring, and the orthographic projection of the separation portion on the substrate does not overlap with the orthographic projection of the protruding portion on the substrate, and the separation portion is connected to the protruding portion through the third sub-jumper line.

20. The display substrate according to claim 19, wherein The first subsection includes a second avoidance groove, and the second avoidance groove is recessed in a direction away from the jumper tray; The orthographic projection of the protruding portion on the base substrate is located within the orthographic projection of the first sub-portion on the base substrate; The orthographic projection of the separation portion on the base substrate is located within the orthographic projection of the second avoidance groove on the base substrate.

21. The display substrate according to claim 16, wherein An orthographic projection of the main body portion on the base substrate substantially coincides with an orthographic projection of the coupling portion on the base substrate.

22. The display substrate according to claim 21, wherein It also includes a second transparent conductive layer located on a side of the layer where the output transistor is located away from the substrate, and the jumper wire further includes a third sub-jumper wire located on the second transparent conductive layer; The first electrode of the output transistor further includes a separation portion; The main body includes a connection area, which is located on a side of the separation portion away from the common electrode wiring and is arranged adjacent to the separation portion. The orthographic projection of the separation portion on the substrate and the orthographic projection of the connection area on the substrate do not overlap with each other, and the separation portion is connected to the connection area through the third sub-jumper line.

23. The display substrate according to claim 22, wherein: The coupling portion includes a second avoidance groove, which is recessed in a direction away from the jumper tray; the main body portion includes a third avoidance groove, and the orthographic projection of the third avoidance groove on the base substrate substantially coincides with the orthographic projection of the second avoidance groove on the base substrate; The orthographic projection of the separation portion on the base substrate is located within the orthographic projection of the third avoidance groove on the base substrate.

24. The display substrate according to claim 19, 20, 22 or 23, wherein: In the extension direction of the common electrode line, the length of the main body is greater than the length of the separation part; in the direction perpendicular to the extension direction of the common electrode line, the width of the main body is greater than the width of the separation part.

25. The display substrate according to any one of claims 1 to 4, 6, 9 to 10, and 17 to 23, wherein: The second sub-jump line includes a first line and a second line, wherein the first line is substantially parallel to the common electrode line, and the second line is substantially perpendicular to the common electrode line; The first wiring is located on a side of the jumper tray perpendicular to an extending direction of the common electrode wiring. The first wiring connects the first sub-jumper wire and the second wiring. The second wiring connects the first electrode of the output transistor.

26. The display substrate according to claim 25, wherein: The second sub-jumper line further includes a third line, the third line is located on a side of the jumper plate away from the common electrode line, and the third line connects the first line and the first sub-jumper line.

27. The display substrate according to claim 26, wherein: The second sub-jumper line also includes a fourth line, which is arranged on the same side of the jumper tray as the first line. The angle between the fourth line and the extension direction of the common electrode line is an acute angle, and the fourth line connects the first line and the second line.

28. The display substrate according to claim 27, wherein: The fourth line is a straight line or an arc.

29. The display substrate according to claim 25, wherein: It also includes a second transparent conductive layer located on the side of the layer where the output transistor is located away from the substrate. The jumper line also includes a third sub-jumper line located in the second transparent conductive layer; the second routing line is connected to the third sub-jumper line.

30. The display substrate according to claim 29, wherein The second sub-jumping line further includes a fifth line, which is substantially parallel to the common electrode line and connects the second line and the third sub-jumping line.

31. The display substrate according to any one of claims 1 to 4, 6, 9 to 10, 17 to 23, and 26 to 30, wherein: It also includes a gate connection line, which is substantially parallel to the first wiring and electrically connected to the first sub-jumper pad.

32. A display device, wherein: The display substrate comprises the display substrate according to any one of claims 1 to 31.

33. The display device according to claim 32, wherein: Also includes: An opposite substrate and a liquid crystal layer, wherein the opposite substrate is opposite to the display substrate, and the liquid crystal layer is located between the opposite substrate and the display substrate.

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