Low-dropout voltage regulator

Abstract

The application discloses a low-dropout voltage regulator. The low-dropout voltage regulator comprises a differential amplifier circuit, a self-stabilized second-stage amplifier circuit, an output circuit and a frequency compensation circuit. The differential amplifier circuit is electrically connected with the self-stabilized second-stage amplifier circuit. The self-stabilized second-stage amplifier circuit is electrically connected with the output circuit. The frequency compensation circuit is arranged between an output end of the self-stabilized second-stage amplifier circuit, a second end of an output switch component of the output circuit and a third end of the output switch component of the output circuit.

Description

Technical Field

[0001] This invention relates to a low-dropout voltage regulator circuit, and more particularly to a low-dropout voltage regulator circuit with a simple structure. Background Technology

[0002] Traditional low-dropout voltage regulator circuits mostly require external compensation capacitors with large impedance values ​​or complex circuits.

[0003] How to provide a low-dropout voltage regulator circuit with a simple circuit structure to overcome the above-mentioned defects has become one of the important issues that this project aims to solve. Summary of the Invention

[0004] The technical problem to be solved by this invention is to provide a low-dropout voltage regulator circuit that addresses the shortcomings of existing technologies. The circuit comprises: a differential amplifier circuit including an output terminal and a feedback terminal; and a self-stabilizing second-stage amplifier circuit including an input terminal and an output terminal. The output terminal of the differential amplifier circuit is electrically connected to the input terminal of the self-stabilizing second-stage amplifier circuit. The second-stage amplifier circuit includes a first amplifying transistor assembly and a second amplifying transistor assembly. The first amplifying transistor assembly includes a first terminal, a second terminal, and a third terminal. The second amplifying transistor assembly also includes a first terminal, a second terminal, and a third terminal. The first terminal of the first amplifying transistor assembly is electrically connected to an input voltage, and the second terminal of the first amplifying transistor assembly is electrically connected to the second terminal of the second amplifying transistor assembly, thereby forming the input terminal of the second-stage amplifier circuit. The output circuit includes an output transistor assembly and a feedback circuit. The output transistor assembly includes a first terminal, a second terminal, and a third terminal. The first terminal of the output transistor assembly is electrically connected to the input voltage. The second terminal of the output transistor assembly is electrically connected to the output terminal of the second-stage amplifier circuit. The third terminal of the output transistor assembly is electrically connected to the feedback circuit, which is connected to the feedback terminal of the differential amplifier circuit. A frequency compensation circuit is disposed between the output terminal of the second-stage amplifier circuit, the second terminal of the output transistor assembly, and the third terminal of the output transistor assembly.

[0005] Preferably, the frequency compensation circuit includes a first compensation impedance and a first compensation capacitor, the first compensation impedance being connected in series with the first compensation capacitor, the value of the first compensation impedance being between 200 ohms and 30K ohms, and the value of the first compensation capacitor being between 4 picofarads and 50 picofarads.

[0006] Preferably, the frequency compensation circuit includes a first compensation impedance, a first compensation capacitor, a second compensation impedance, and a second compensation capacitor. The first compensation impedance is connected in series with the first compensation capacitor, the second compensation impedance is connected in parallel with the second compensation capacitor, and the first compensation capacitor is connected in series with the second compensation impedance and the second compensation capacitor.

[0007] Preferably, the frequency compensation circuit includes a compensation transistor assembly and a third compensation capacitor. The compensation transistor assembly includes a first terminal, a second terminal, and a third terminal. The first terminal of the compensation transistor assembly is electrically connected to the output terminal of the second-stage amplifier circuit and the second terminal of the output transistor assembly. The second terminal of the compensation transistor assembly is electrically connected to the third terminal of the compensation transistor assembly and the third compensation capacitor.

[0008] Preferably, the third terminal of the second amplifying transistor assembly of the second-stage amplifier circuit is electrically connected to a ground potential.

[0009] Preferably, the second-stage amplifier circuit further includes a third amplifying transistor assembly, the third amplifying transistor assembly including a first terminal, a second terminal and a third terminal, the first terminal of the third amplifying transistor assembly being electrically connected to the third terminal of the second amplifying transistor assembly and the second terminal of the third amplifying transistor assembly, and the third terminal of the third amplifying transistor assembly being electrically connected to a ground potential.

[0010] Preferably, the first amplifying transistor assembly includes a first channel width, the second amplifying transistor assembly includes a second channel width, the first channel width is 1 / 2 to 1 / 15 of the second channel width, and the third amplifying transistor assembly includes a third channel width, the third channel width being more than twice the first channel width.

[0011] Preferably, the differential amplifier circuit includes a current source, a first differential transistor assembly, a second differential transistor assembly, a third differential transistor assembly, and a fourth differential transistor assembly. The first differential transistor assembly includes a first terminal, a second terminal, and a third terminal; the second differential transistor assembly includes a first terminal, a second terminal, and a third terminal; the third differential transistor assembly includes a first terminal, a second terminal, and a third terminal; and the fourth differential transistor assembly includes a first terminal, a second terminal, and a third terminal. The current source is electrically connected to the first terminal of the first differential transistor assembly and the first terminal of the third differential transistor assembly. The second terminal of the first differential transistor assembly is connected to a reference voltage. The third terminal of the second differential transistor assembly is electrically connected to the first terminal of the second differential transistor assembly, the first terminal of the second differential transistor assembly is electrically connected to the second terminal of the second differential transistor assembly, the second terminal of the second differential transistor assembly is electrically connected to the second terminal of the fourth differential transistor assembly, the third terminal of the second differential transistor assembly is electrically connected to a ground potential, the second terminal of the third differential transistor assembly is the feedback terminal of the differential amplifier circuit and is electrically connected to the feedback circuit, the third terminal of the third differential transistor assembly is electrically connected to the first terminal of the fourth differential transistor assembly and the input terminal of the second stage amplifier circuit, and the third terminal of the fourth differential transistor assembly is electrically connected to the ground potential.

[0012] Preferably, the feedback circuit includes a first feedback impedance and a second feedback impedance, the first feedback impedance being connected in series with the second feedback impedance, the first feedback impedance and the second feedback impedance being a resistor or a metal-oxide-semiconductor field-effect transistor connected in the form of a diode, the first differential transistor assembly and the third differential transistor assembly being a P-type metal-oxide-semiconductor field-effect transistor, and the second differential transistor assembly and the fourth differential transistor assembly being an N-type metal-oxide-semiconductor field-effect transistor.

[0013] Preferably, the first amplifying transistor assembly is a P-type metal-oxide-semiconductor field-effect transistor, the second amplifying transistor assembly is an N-type metal-oxide-semiconductor field-effect transistor, and the amplifying circuit composed of the differential amplifying circuit and the second-stage amplifying circuit is self-stabilizing, and no Miller compensation circuit is required between the differential amplifying circuit and the second-stage amplifying circuit.

[0014] One of the advantages of this invention is that the low-dropout voltage regulator circuit provided by this invention not only has a simple circuit structure, but also has a very small internal capacitance, is self-stabilizing, and does not require an external compensation capacitor. Furthermore, the low-dropout voltage regulator circuit of this invention also has a wide operating voltage range and a very small ripple voltage.

[0015] To further understand the features and technical content of the present invention, please refer to the following detailed description and drawings of the present invention. However, the drawings provided are for reference and illustration only and are not intended to limit the present invention. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of the low-dropout voltage regulator circuit of the first embodiment of the present invention.

[0017] Figure 2 This is a schematic diagram of a low-dropout voltage regulator circuit according to a second embodiment of the present invention.

[0018] Figure 3 This is a schematic diagram of a low-dropout voltage regulator circuit according to the third embodiment of the present invention.

[0019] Figure 4 This is a schematic diagram of a low-dropout voltage regulator circuit according to the fourth embodiment of the present invention.

[0020] Figure 5 This is a schematic diagram of a low-dropout voltage regulator circuit according to the fifth embodiment of the present invention.

[0021] Figure 6 This is a schematic diagram of a low-dropout voltage regulator circuit according to the sixth embodiment of the present invention.

[0022] Figure 7 This is a schematic diagram of the output voltage of the low-dropout voltage regulator circuit of the present invention.

[0023] Figure 8 This is a schematic diagram of the phase and gain of the low-dropout voltage regulator circuit of the present invention. Detailed Implementation

[0024] The following specific embodiments illustrate the implementation of the "low dropout voltage regulator circuit" disclosed in this invention. Those skilled in the art can understand the advantages and effects of this invention from the content disclosed in this specification. This invention can be implemented or applied through other different specific embodiments, and various details in this specification can also be modified and changed based on different viewpoints and applications without departing from the concept of this invention. Furthermore, the accompanying drawings of this invention are for simple illustrative purposes only and are not depictions of actual dimensions, as stated in advance. The following embodiments will further describe the relevant technical content of this invention in detail, but the disclosed content is not intended to limit the scope of protection of this invention. In addition, the term "or" used herein may, depending on the actual situation, include any combination of any one or more of the associated listed items.

[0025] [First Embodiment]

[0026] Please see Figure 1 , Figure 1 This is a schematic diagram of the low-dropout voltage regulator circuit of the first embodiment of the present invention.

[0027] This embodiment provides a low-dropout voltage regulator circuit S1, which includes a differential amplifier circuit 1, a self-stabilizing second-stage amplifier circuit 2, an output circuit 3, and a frequency compensation circuit 4.

[0028] The differential amplifier circuit 1 includes an output terminal 11 and a feedback terminal 12.

[0029] The second-stage amplifier circuit 2 includes an input terminal 21 and an output terminal 22. The output terminal 11 of the differential amplifier circuit 1 is electrically connected to the input terminal 21 of the second-stage amplifier circuit 2. The second-stage amplifier circuit 2 includes a first amplifying transistor assembly M1 and a second amplifying transistor assembly M2. In this embodiment, the first amplifying transistor assembly M1 is a P-type metal-oxide-semiconductor field-effect transistor (P-MOSFET). The second amplifying transistor assembly M2 is an N-type metal-oxide-semiconductor field-effect transistor (N-MOSFET). The first amplifying transistor assembly M1 includes a first terminal, a second terminal, and a third terminal. The second amplifying transistor assembly M2 includes a first terminal, a second terminal, and a third terminal. The first terminal of the first amplifying transistor assembly M1 is electrically connected to an input voltage VDD. The second terminal of the first amplifying transistor assembly M1 is electrically connected to the second terminal of the second amplifying transistor assembly M2 to form the input terminal 21 of the second-stage amplifier circuit 2 and is connected to the output terminal 11 of the differential amplifier circuit 1. The third terminal of the first amplifying transistor assembly M1 is connected to the first terminal of the second amplifying transistor assembly M2 to form the output terminal 22 of the second-stage amplifier circuit 2. In this embodiment, the first terminal of the first amplifying transistor component M1 is a source terminal. The second terminal of the first amplifying transistor component M1 is a gate terminal. The third terminal of the first amplifying transistor component M1 is a drain terminal. The first terminal of the second amplifying transistor component M2 is a drain terminal. The second terminal of the second amplifying transistor component M2 is a gate terminal. The third terminal of the second amplifying transistor component M2 is a source terminal. In this embodiment, the second-stage amplifying circuit 2 is a self-stabilizing second-stage amplifying circuit. Furthermore, in general low-dropout voltage regulator circuits, a Miller compensation circuit is provided between the differential pair and the second-stage amplifying circuit. However, in this embodiment, the amplifying circuit composed of the differential pair and the second-stage amplifying circuit is self-stabilizing. That is, in this embodiment, a Miller compensation circuit is not required between the differential pair 1 and the second-stage amplifying circuit 2.

[0030] The output circuit 3 includes an output transistor assembly 31 and a feedback circuit 32. The output transistor assembly 31 includes a first terminal, a second terminal, and a third terminal. The first terminal of the output transistor assembly 31 is electrically connected to the input voltage VDD. The second terminal of the output transistor assembly 31 is electrically connected to the output terminal 22 of the second-stage amplifier circuit 2. In this embodiment, the output circuit 3 can be connected to a load to provide output voltage and output current. In this embodiment, the output transistor assembly 31 is a P-type metal-oxide-semiconductor field-effect transistor (P-MOSFET). The first terminal of the output transistor assembly 31 is a source terminal. The second terminal of the output transistor assembly 31 is a gate terminal. The third terminal of the output transistor assembly 31 is a drain terminal.

[0031] The third terminal of the output transistor assembly 31 is electrically connected to the feedback circuit 32. The feedback circuit 32 is connected to the feedback terminal 12 of the differential amplifier circuit 1.

[0032] The frequency compensation circuit 4 is disposed between the output terminal 22 of the second-stage amplifier circuit 2, the second terminal of the output transistor assembly 31, and the third terminal of the output transistor assembly 31. That is, the frequency compensation circuit 4 is disposed between the second-stage amplifier circuit 2 and the output circuit 3. In addition, the output terminal 11 of the differential amplifier circuit 1 is directly electrically connected to the second terminal of the first amplifying transistor assembly M1 and the second terminal of the second amplifying transistor assembly M2 of the second-stage amplifier circuit 2.

[0033] The frequency compensation circuit 4 includes a first compensation impedance R1 and a first compensation capacitor C1. The first compensation impedance R1 is connected in series with the first compensation capacitor C1. In this embodiment, the resistance value of the first compensation impedance R1 is between 200 ohms and 30K ohms. The capacitance value of the first compensation capacitor C1 is between 4pF (picofarads) and 50pF (picofarads).

[0034] In this embodiment, the third terminal of the second amplifying transistor component M2 of the second-stage amplifying circuit 2 is electrically connected to a ground potential.

[0035] The differential amplifier circuit 1 includes a current source CS, a first differential transistor assembly DM1, a second differential transistor assembly DM2, a third differential transistor assembly DM3, and a fourth differential transistor assembly DM4. In this embodiment, the first differential transistor assembly DM1 and the third differential transistor assembly DM3 are P-type metal-oxide-semiconductor field-effect transistors (P-MOSFETs). The second differential transistor assembly DM2 and the fourth differential transistor assembly DM4 are N-type metal-oxide-semiconductor field-effect transistors (N-MOSFETs).

[0036] The first differential transistor assembly DM1 includes a first terminal, a second terminal, and a third terminal. The second differential transistor assembly DM2 includes a first terminal, a second terminal, and a third terminal. The third differential transistor assembly DM3 includes a first terminal, a second terminal, and a third terminal. The fourth differential transistor assembly DM4 includes a first terminal, a second terminal, and a third terminal.

[0037] The first terminal of the first differential transistor component DM1 and the third differential transistor component DM3 is a source terminal. The second terminal of the first differential transistor component DM1 and the third differential transistor component DM3 is a gate terminal. The third terminal of the first differential transistor component DM1 and the third differential transistor component DM3 is a drain terminal.

[0038] The first terminals of the second differential transistor assembly DM2 and the fourth differential transistor assembly DM4 are both drain terminals. The second terminals of the second differential transistor assembly DM2 and the fourth differential transistor assembly DM4 are both gate terminals. The third terminals of the second differential transistor assembly DM2 and the fourth differential transistor assembly DM4 are both source terminals.

[0039] The current source CS is electrically connected to the first terminal of the first differential transistor assembly DM1 and the first terminal of the third differential transistor assembly DM3. The second terminal of the first differential transistor assembly DM1 is connected to a reference voltage (Vref), which is typically generated using a bandgap reference circuit. The third terminal of the first differential transistor assembly DM1 is electrically connected to the first terminal of the second differential transistor assembly DM2. The first terminal of the second differential transistor assembly DM2 is electrically connected to the second terminal of the second differential transistor assembly DM2. The second terminal of the second differential transistor assembly DM2 is electrically connected to the second terminal of the fourth differential transistor assembly DM4. The third terminal of the second differential transistor assembly DM2 is electrically connected to a ground potential. The second terminal of the third differential transistor assembly DM3 is the feedback terminal 12 of the differential amplifier circuit 1. The feedback terminal 12 is electrically connected to the feedback circuit 32. The third terminal of the third differential transistor assembly DM3 is electrically connected to the first terminal of the fourth differential transistor assembly DM4 and the input terminal 21 of the second-stage amplifier circuit 2. The third terminal of the fourth differential transistor assembly DM4 is electrically connected to a ground potential.

[0040] The feedback circuit 32 includes a first feedback impedance 321 and a second feedback impedance 322. The first feedback impedance 321 is connected in series with the second feedback impedance 322. The connection point between the first feedback impedance 321 and the second feedback impedance 322 is connected to the feedback terminal 12 of the differential amplifier circuit 1.

[0041] The first amplifying transistor assembly M1 includes a first channel width, and the second amplifying transistor assembly M2 includes a second channel width, wherein the first channel width is 1 / 2 to 1 / 15 of the second channel width.

[0042] In this embodiment, the change in the output voltage of the output circuit 3 is amplified by the differential amplifier circuit 1 and provided to the second-stage amplifier circuit 2. The second-stage amplifier circuit 2 effectively provides the voltage to the output circuit 3, which can effectively reduce the ripple voltage.

[0043] [Second Embodiment]

[0044] Please see Figure 2 , Figure 2 This is a schematic diagram of a low-dropout voltage regulator circuit according to a second embodiment of the present invention.

[0045] In this embodiment, the low-dropout voltage regulator circuit S2 is similar to the low-dropout voltage regulator circuit S1 in the first embodiment. The main difference is that the frequency compensation circuit 4' includes a first compensation impedance R1, a first compensation capacitor C1, a second compensation impedance R2, and a second compensation capacitor C2. The first compensation impedance R1 is connected in series with the first compensation capacitor C1. The second compensation impedance R2 is connected in parallel with the second compensation capacitor C2. The first compensation capacitor C1 is connected in series with the second compensation impedance R2 and the second compensation capacitor C2.

[0046] [Third Embodiment]

[0047] Please see Figure 3 , Figure 3 This is a schematic diagram of a low-dropout voltage regulator circuit according to the third embodiment of the present invention.

[0048] In this embodiment, the low-dropout voltage regulator circuit S3 is similar to the low-dropout voltage regulator circuit S1 in the first embodiment. The main difference is that the frequency compensation circuit 4" includes a compensation transistor assembly 41 and a third compensation capacitor C3. The compensation transistor assembly 41 includes a first terminal, a second terminal, and a third terminal. The first terminal of the compensation transistor assembly 41 is electrically connected to the output terminal 22 of the second-stage amplifier circuit 2 and the second terminal of the output transistor assembly 31. The second terminal of the compensation transistor assembly 41 is electrically connected to the third terminal of the compensation transistor assembly 41 and the third compensation capacitor C3. In this embodiment, the compensation transistor assembly 41 is a P-type metal-oxide field-effect transistor (P-MOSFET). The first terminal of the compensation transistor assembly 41 is a source terminal. The second terminal of the compensation transistor assembly 41 is a gate terminal. The third terminal of the compensation transistor assembly 41 is a drain terminal.

[0049] Furthermore, in this embodiment, the feedback impedance of the feedback circuit 32 can also be replaced by the first feedback transistor assembly 323 and the second feedback transistor assembly 324. The first feedback transistor assembly 323 and the second feedback transistor assembly 324 are both P-type metal-oxide field-effect transistors (P-MOSFETs).

[0050] [Fourth Embodiment]

[0051] Please see Figure 4 , Figure 4 This is a schematic diagram of a low-dropout voltage regulator circuit according to the fourth embodiment of the present invention.

[0052] In this embodiment, the low-dropout voltage regulator circuit S4 is similar to the low-dropout voltage regulator circuit S1 in the first embodiment. The main difference is that the second-stage amplifier circuit 2' further includes a third amplifying transistor component M3. The third amplifying transistor component M3 includes a first terminal, a second terminal, and a third terminal. The first terminal of the third amplifying transistor component M3 is electrically connected to the third terminal of the second amplifying transistor component M2 and the second terminal of the third amplifying transistor component M3. The third terminal of the third amplifying transistor component M3 is electrically connected to a ground potential. In this embodiment, the third amplifying transistor component M3 is an N-type metal-oxide field-effect transistor (N-MOSFET). The first terminal of the third amplifying transistor component M3 is a drain terminal. The second terminal of the third amplifying transistor component M3 is a gate terminal. The third terminal of the third amplifying transistor component M3 is a source terminal.

[0053] In this embodiment, the first amplifying transistor assembly M1 includes a first channel width. The second amplifying transistor assembly M2 includes a second channel width. The first channel width of the first amplifying transistor assembly M1 is 1 / 2 to 1 / 15 of the second channel width of the second amplifying transistor assembly M2.

[0054] In addition, the third amplifying transistor assembly M3 includes a third channel width, which is more than twice the first channel width of the first amplifying transistor assembly M1.

[0055] [Fifth Embodiment]

[0056] Please see Figure 5 , Figure 5 This is a schematic diagram of a low-dropout voltage regulator circuit according to the fifth embodiment of the present invention.

[0057] In this embodiment, the low-dropout voltage regulator circuit S5 is similar to the low-dropout voltage regulator circuit S2 in the first embodiment. The main difference is that the second-stage amplifier circuit 2' further includes a third amplifying transistor component M3. The third amplifying transistor component M3 includes a first terminal, a second terminal, and a third terminal. The first terminal of the third amplifying transistor component M3 is electrically connected to the third terminal of the second amplifying transistor component M2 and the second terminal of the third amplifying transistor component M3. The third terminal of the third amplifying transistor component M3 is electrically connected to a ground potential. In this embodiment, the third amplifying transistor component M3 is an N-type metal-oxide-semiconductor field-effect transistor (N-MOSFET).

[0058] In this embodiment, the first amplifying transistor assembly M1 includes a first channel width. The second amplifying transistor assembly M2 includes a second channel width. The first channel width of the first amplifying transistor assembly M1 is 1 / 2 to 1 / 15 of the second channel width of the second amplifying transistor assembly M2.

[0059] In addition, the third amplifying transistor assembly M3 includes a third channel width, which is more than twice the first channel width of the first amplifying transistor assembly M1.

[0060] [Sixth Embodiment]

[0061] Please see Figure 6 , Figure 6 This is a schematic diagram of a low-dropout voltage regulator circuit according to the sixth embodiment of the present invention.

[0062] In this embodiment, the low-dropout voltage regulator circuit S6 is similar to the low-dropout voltage regulator circuit S3 in the first embodiment. The main difference is that the second-stage amplifier circuit 2' further includes a third amplifying transistor component M3. The third amplifying transistor component M3 includes a first terminal, a second terminal, and a third terminal. The first terminal of the third amplifying transistor component M3 is electrically connected to the third terminal of the second amplifying transistor component M2 and the second terminal of the third amplifying transistor component M3. The third terminal of the third amplifying transistor component M3 is electrically connected to a ground potential.

[0063] In this embodiment, the first amplifying transistor assembly M1 includes a first channel width. The second amplifying transistor assembly M2 includes a second channel width. The first channel width of the first amplifying transistor assembly M1 is 1 / 2 to 1 / 15 of the second channel width of the second amplifying transistor assembly M2.

[0064] In addition, the third amplifying transistor assembly M3 includes a third channel width, which is more than twice the first channel width of the first amplifying transistor assembly M1.

[0065] Furthermore, in this embodiment, the feedback impedance of the feedback circuit 32 in the output circuit 3' of the first embodiment and the fourth embodiment can be replaced by the first feedback transistor assembly 323 and the second feedback transistor assembly 324. That is, as Figure 3 as well as Figure 6 In this configuration, the first feedback impedance 31 and the second feedback impedance 32 can be replaced by transistor components. That is, the first feedback impedance R1 and the first feedback impedance R2 can be a resistor or a metal-oxide-semiconductor field-effect transistor (diode-connected MOSFET) connected in the form of a diode.

[0066] Please see Figure 7 as well as Figure 8 , Figure 7 This is a schematic diagram of the output voltage of the low-dropout voltage regulator circuit of the present invention. Figure 8 This is a schematic diagram of the phase and gain of the low-dropout voltage regulator circuit of the present invention.

[0067] Figure 7 This is a schematic diagram of the output voltage of the low-dropout voltage regulator circuit of the present invention. The ripple voltage of the output voltage can be below 10mV. Figure 8 This is a schematic diagram of the phase and gain of the low-dropout voltage regulator circuit of this invention. Its phase margin is 57 degrees. The linear regulation (LNR) is 0.16mV / V. The power supply rejection ratio is -71dB. The power efficiency is 83%.

[0068] [Beneficial Effects of the Examples]

[0069] One of the advantages of this invention is that the low-dropout voltage regulator circuit provided by this invention not only has a simple circuit structure, but also has a very small internal capacitance, is self-stabilizing, and does not require an external compensation capacitor. Furthermore, the low-dropout voltage regulator circuit of this invention also has a wide operating voltage range and a very small ripple voltage.

[0070] The content disclosed above is only a preferred and feasible embodiment of the present invention, and is not intended to limit the claims of the present invention. Therefore, all equivalent technical changes made based on the content of the present invention specification and drawings are included within the scope of the claims of the present invention.

Claims

1. A low-dropout voltage regulator circuit, characterized in that, include: A differential amplifier circuit includes an output terminal and a feedback terminal; A self-stabilizing second-stage amplifier circuit includes an input terminal and an output terminal. The output terminal of the differential amplifier circuit is electrically connected to the input terminal of the self-stabilizing second-stage amplifier circuit. The second-stage amplifier circuit includes a first amplifying transistor assembly and a second amplifying transistor assembly. The first amplifying transistor assembly includes a first terminal, a second terminal, and a third terminal. The second amplifying transistor assembly includes a first terminal, a second terminal, and a third terminal. The first terminal of the first amplifying transistor assembly is electrically connected to an input voltage. The second terminal of the first amplifying transistor assembly is electrically connected to the second terminal of the second amplifying transistor assembly to form the input terminal of the second-stage amplifier circuit and connected to the output terminal of the differential amplifier circuit. The third terminal of the first amplifying transistor assembly is connected to the first terminal of the second amplifying transistor assembly to form the output terminal of the self-stabilizing second-stage amplifier circuit. An output circuit includes an output transistor assembly and a feedback circuit. The output transistor assembly includes a first terminal, a second terminal, and a third terminal. The first terminal of the output transistor assembly is electrically connected to the input voltage. The second terminal of the output transistor assembly is electrically connected to the output terminal of the second-stage amplifier circuit. The third terminal of the output transistor assembly is electrically connected to the feedback circuit. The feedback circuit is connected to the feedback terminal of the differential amplifier circuit. as well as A frequency compensation circuit is disposed between the output terminal of the second-stage amplifier circuit, the second terminal of the output transistor assembly, and the third terminal of the output transistor assembly. Wherein, the first amplifying transistor component is a P-type metal-oxide-semiconductor field-effect transistor, the second amplifying transistor component is an N-type metal-oxide-semiconductor field-effect transistor, the first terminal of the first amplifying transistor component is a source terminal, the second terminal of the first amplifying transistor component is a gate terminal, the third terminal of the first amplifying transistor component is a drain terminal, the first terminal of the second amplifying transistor component is a drain terminal, the second terminal of the second amplifying transistor component is a gate terminal, and the third terminal of the second amplifying transistor component is a source terminal.

2. The low-dropout voltage regulator circuit as described in claim 1, characterized in that, The frequency compensation circuit includes a first compensation impedance and a first compensation capacitor. The first compensation impedance is connected in series with the first compensation capacitor. The value of the first compensation impedance is between 200 ohms and 30K ohms, and the value of the first compensation capacitor is between 4 picofarads and 50 picofarads.

3. The low-dropout voltage regulator circuit as described in claim 1, characterized in that, The frequency compensation circuit includes a first compensation impedance, a first compensation capacitor, a second compensation impedance, and a second compensation capacitor. The first compensation impedance is connected in series with the first compensation capacitor, the second compensation impedance is connected in parallel with the second compensation capacitor, and the first compensation capacitor is connected in series with the second compensation impedance and the second compensation capacitor.

4. The low-dropout voltage regulator circuit as described in claim 1, characterized in that, The frequency compensation circuit includes a compensation transistor assembly and a third compensation capacitor. The compensation transistor assembly includes a first terminal, a second terminal, and a third terminal. The first terminal of the compensation transistor assembly is electrically connected to the output terminal of the second-stage amplifier circuit and the second terminal of the output transistor assembly. The second terminal of the compensation transistor assembly is electrically connected to the third terminal of the compensation transistor assembly and the third compensation capacitor.

5. The low-dropout voltage regulator circuit as described in claim 1, characterized in that, The third terminal of the second amplifying transistor assembly in the second-stage amplifier circuit is electrically connected to a ground potential.

6. The low-dropout voltage regulator circuit as described in claim 1, characterized in that, The second-stage amplifier circuit further includes a third amplifying transistor assembly, which includes a first terminal, a second terminal, and a third terminal. The first terminal of the third amplifying transistor assembly is electrically connected to the third terminal of the second amplifying transistor assembly and the second terminal of the third amplifying transistor assembly, and the third terminal of the third amplifying transistor assembly is electrically connected to a ground potential.

7. The low-dropout voltage regulator circuit as described in claim 6, characterized in that, The first amplifying transistor assembly includes a first channel width, the second amplifying transistor assembly includes a second channel width, the first channel width is 1 / 2 to 1 / 15 of the second channel width, and the third amplifying transistor assembly includes a third channel width, the third channel width being more than twice the first channel width.

8. The low-dropout voltage regulator circuit as described in claim 1, characterized in that, The differential amplifier circuit includes a current source, a first differential transistor assembly, a second differential transistor assembly, a third differential transistor assembly, and a fourth differential transistor assembly. The first differential transistor assembly includes a first terminal, a second terminal, and a third terminal. The second differential transistor assembly includes a first terminal, a second terminal, and a third terminal. The third differential transistor assembly includes a first terminal, a second terminal, and a third terminal. The fourth differential transistor assembly includes a first terminal, a second terminal, and a third terminal. The current source is electrically connected to the first terminal of the first differential transistor assembly and the first terminal of the third differential transistor assembly. The second terminal of the first differential transistor assembly is connected to a reference voltage. The third terminal is electrically connected to the first terminal of the second differential transistor assembly, the first terminal of the second differential transistor assembly is electrically connected to the second terminal of the second differential transistor assembly, the second terminal of the second differential transistor assembly is electrically connected to the second terminal of the fourth differential transistor assembly, the third terminal of the second differential transistor assembly is electrically connected to a ground potential, the second terminal of the third differential transistor assembly is the feedback terminal of the differential amplifier circuit and is electrically connected to the feedback circuit, the third terminal of the third differential transistor assembly is electrically connected to the first terminal of the fourth differential transistor assembly and the input terminal of the second stage amplifier circuit, and the third terminal of the fourth differential transistor assembly is electrically connected to the ground potential.

9. The low-dropout voltage regulator circuit as described in claim 8, characterized in that, The feedback circuit includes a first feedback impedance and a second feedback impedance, the first feedback impedance being connected in series with the second feedback impedance, the first feedback impedance and the second feedback impedance being a resistor or a metal-oxide-semiconductor field-effect transistor connected in the form of a diode, the first differential transistor assembly and the third differential transistor assembly being a P-type metal-oxide-semiconductor field-effect transistor, and the second differential transistor assembly and the fourth differential transistor assembly being an N-type metal-oxide-semiconductor field-effect transistor.

10. The low-dropout voltage regulator circuit as described in claim 1, characterized in that, The amplifier circuit composed of the differential amplifier circuit and the second-stage amplifier circuit is self-stabilizing, and no compensation circuit is required between the differential amplifier circuit and the second-stage amplifier circuit.

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