Vector instruction processing method, apparatus, and readable storage medium based on RISC-V instruction set

Abstract

This invention discloses a vector instruction processing method, apparatus, and readable storage medium based on the RISC-V instruction set. The invention executes a configuration instruction and obtains its configuration parameters. Based on a tag index, the obtained configuration parameters are updated in the file entry corresponding to the configuration instruction. Simultaneously, the destination register in the file entry is set to a ready state, and the destination register of the configuration instruction is set as the first source register of the vector instruction corresponding to the configuration instruction. In response to the first source register and other source registers of the vector instruction being in a ready state, the configuration parameters in the file entry are obtained based on the tag index carried in the vector instruction. The vector instruction is then executed. This method ensures that even when vector instructions are executed out of order, the configuration parameters Vtype and Vl of the corresponding configuration instruction are accurately obtained based on the tag index, guaranteeing the accuracy of the processing results when the vector processor processes vector instructions.

Description

Technical Field

[0001] This invention relates to the field of computer technology, and more specifically to a vector instruction processing method, apparatus, and readable storage medium based on the RISC-V instruction set. Background Technology

[0002] The fifth-generation Reduced Instruction Set Computer (RISC-V) combines the advantages of x86 and ARM instruction sets. RISC-V features simple instructions, fewer instruction lines, smaller code size, and lower power consumption. As a result, RISC-V is being used more and more widely.

[0003] RISC-V includes an existing basic instruction set and an extended instruction set. The basic instruction set includes RV32I, RV32E, RV64I, and RV128I, while the extended instruction set includes M, A, F, D, C, and V extensions. The V extension is the vector extension instruction set (RISC-V Vector). RISC-V is implemented through a Vector processor. The vector extension instruction set includes configuration (Vset) instructions and vector instructions. The Vset instruction configures the Vtype and Vl parameters required for the execution of the Vector instruction. The execution of each Vector instruction depends on the configuration result of its corresponding Vset instruction.

[0004] In existing technologies, Vector instructions are executed sequentially, meaning they can only be executed when it is determined that a Vector instruction must be committed. However, during sequential execution, the next Vector instruction cannot be executed until the previous one has completed. This results in long waiting times for Vector instructions that do not depend on the results of preceding Vector instructions, impacting the performance of the Vector processor. Therefore, Vector instructions that do not depend on the results of preceding Vector instructions can be executed earlier to improve the performance of the Vector processor. However, when Vector instructions are executed out of order, their corresponding Vset instructions may also be executed out of order. In this case, the configuration parameters Vtype and Vl obtained by the Vector instructions after the Vset instruction may be incorrect, and may be configuration parameters from other Vset instructions.

[0005] In summary, ensuring accurate acquisition of the configuration parameters Vtype and Vl of the corresponding Vset instruction when Vector instructions are executed out of order is a problem that needs to be solved. Summary of the Invention

[0006] In view of this, embodiments of the present invention provide a vector instruction processing method, apparatus and readable storage medium based on the RISC-V instruction set, which can ensure that the configuration parameters Vtype and Vl of the corresponding Vset instruction are accurately obtained when the Vector instruction is executed out of order, thus ensuring the accuracy of the Vector processor processing results.

[0007] In a first aspect, embodiments of the present invention provide a vector instruction processing method based on the RISC-V instruction set, the method comprising:

[0008] Execute a configuration instruction to obtain configuration parameters for the configuration instruction, wherein the configuration instruction carries a tag index; update the obtained configuration parameters to the file entry corresponding to the configuration instruction according to the tag index, and simultaneously set the destination register in the file entry to a ready state, wherein the destination register of the configuration instruction is set to the first source register of the vector instruction corresponding to the configuration instruction; in response to the first source register and other source registers of the vector instruction being in a ready state, obtain the configuration parameters in the file entry according to the tag index carried in the vector instruction, wherein the tag index carried in the vector instruction is the same as the tag index carried in the configuration instruction; execute the vector instruction.

[0009] Optionally, the file entry also includes a validity indicator. After updating the obtained configuration parameters to the file entry corresponding to the configuration instruction according to the tag index, the method further includes:

[0010] The validity indicator in the file entry is marked as valid, wherein the validity indicator is used to indicate whether the configuration parameter in the file entry is valid.

[0011] Optionally, the method further includes:

[0012] Retrieve instruction data;

[0013] During the decoding phase, in response to the instruction data being the configuration instruction, a corresponding file entry is allocated for the configuration instruction in the configuration cache, and a tag index is generated;

[0014] Add the tag index to the configuration instruction.

[0015] Optionally, the method further includes:

[0016] Write the destination register of the configuration instruction into the file entry, and mark the validity indication in the file entry as invalid.

[0017] Optionally, the method further includes:

[0018] Write the file entry corresponding to the configuration instruction to the end of the configuration cache.

[0019] Optionally, the method further includes:

[0020] During the decoding phase, in response to the instruction data being the vector instruction, the file entry is retrieved from the end of the configuration cache;

[0021] In response to the validity indication in the file entry being marked as invalid, the first source register in the file entry is added to the source register list of the vector instruction;

[0022] Add the tag index from the file entry to the vector instruction.

[0023] Optionally, the method further includes:

[0024] Rename the vector instructions and configuration instructions after the decoding stage;

[0025] After the renaming is completed, the vector instructions and the configuration instructions are written into the reorder cache (ROB), and the vector instructions and the configuration instructions are distributed to different instruction slots according to different instruction types.

[0026] Optionally, the method further includes:

[0027] In response to any configuration instruction being moved to the head of the reorder cache ROB, the file entry corresponding to the configuration instruction preceding that configuration instruction is deleted from the configuration cache.

[0028] Optionally, the method further includes:

[0029] In response to receiving a clear command, determine the clear point corresponding to the clear command;

[0030] Delete the file entries in the configuration cache that precede the clear point.

[0031] Optionally, the configuration parameters include a vector data type register and a vector element length.

[0032] Optionally, the method further includes:

[0033] In response to executing the vector instruction, the file entry corresponding to the configuration instruction is found based on the tag index carried in the vector instruction;

[0034] In response to the validity indicator being marked as valid in the file entry, the configuration parameters in the file entry are retrieved;

[0035] The vector instruction is executed according to the configuration parameters.

[0036] Secondly, embodiments of the present invention provide a vector instruction processing apparatus based on the RISC-V instruction set, the apparatus comprising:

[0037] The first execution unit is configured to execute configuration instructions and obtain configuration parameters of the configuration instructions, wherein the configuration instructions carry a tag index;

[0038] The setting unit is used to update the obtained configuration parameters to the file entry corresponding to the configuration instruction according to the tag index, and at the same time set the destination register in the file entry to a ready state, wherein the destination register of the configuration instruction is set to the first source register of the vector instruction corresponding to the configuration instruction;

[0039] The processing unit, in response to the first source register and other source registers of the vector instruction being in a ready state, is used to obtain the configuration parameters in the file entry according to the tag index carried in the vector instruction, wherein the tag index carried in the vector instruction is the same as the tag index carried in the configuration instruction;

[0040] The second execution unit is used to execute the vector instructions.

[0041] Optionally, the file entry also includes a validity indicator. After updating the obtained configuration parameters to the file entry corresponding to the configuration instruction according to the tag index, the processing unit is further configured to:

[0042] The validity indicator in the file entry is marked as valid, wherein the validity indicator is used to indicate whether the configuration parameter in the file entry is valid.

[0043] Optionally, the device may also include:

[0044] The acquisition unit is used to acquire instruction data;

[0045] The processing unit is further configured to, during the decoding stage, in response to the instruction data being the configuration instruction, allocate a corresponding file entry for the configuration instruction in the configuration cache and generate a tag index;

[0046] The processing unit is further configured to add the tag index to the configuration instruction.

[0047] Optionally, the processing unit is further configured to:

[0048] Write the destination register of the configuration instruction into the file entry, and mark the validity indication in the file entry as invalid.

[0049] Optionally, the device may also include:

[0050] The writing unit is used to write the file entry corresponding to the configuration instruction to the end of the configuration cache.

[0051] Optionally, the acquisition unit is further configured to:

[0052] During the decoding phase, in response to the instruction data being the vector instruction, the file entry is retrieved from the end of the configuration cache;

[0053] The processing unit is further configured to: in response to the validity indication in the file entry being marked as invalid, add the first source register in the file entry to the source register list of the vector instruction.

[0054] Optionally, the processing unit is further configured to:

[0055] Add the tag index from the file entry to the vector instruction.

[0056] Optionally, the device may also include:

[0057] The renaming unit is used to rename the vector instructions and the configuration instructions after the decoding stage;

[0058] The processing unit is further configured to, after completing the renaming, write the vector instruction and the configuration instruction into the reorder cache (ROB), and distribute the vector instruction and the configuration instruction to different instruction slots according to different instruction types.

[0059] Optionally, the device may also include:

[0060] The deletion unit, in response to any configuration instruction moving to the head of the reorder cache ROB, is used to delete the file entry corresponding to the configuration instruction preceding the any configuration instruction in the configuration cache.

[0061] Optionally, the receiving unit is further configured to:

[0062] In response to receiving a clear command, determine the clear point corresponding to the clear command;

[0063] The deletion unit is further configured to delete file entries in the configuration cache prior to the clear point.

[0064] Optionally, the configuration parameters include a vector data type register and a vector element length.

[0065] Optionally, the device may also include:

[0066] The lookup unit, in response to executing the vector instruction, is used to look up the file entry corresponding to the configuration instruction based on the tag index carried in the vector instruction;

[0067] The acquisition unit is further configured to acquire the configuration parameters in the file entry in response to the validity indicator mark being valid in the file entry;

[0068] The second execution unit is further configured to execute the vector instructions according to the configuration parameters.

[0069] Thirdly, embodiments of the present invention provide computer program instructions that, when executed by a processor, implement the method as described in the first aspect or any one of the possible methods described in the first aspect.

[0070] Fourthly, embodiments of the present invention provide a computer-readable storage medium having storage thereon.

[0071] The computer program instructions, when executed by a processor, implement the method as described in the first aspect or any one of the possibilities of the first aspect.

[0072] Fifthly, embodiments of the present invention provide a chip including a memory and a processing core, the memory being used to store one or more computer program instructions, wherein the one or more computer program instructions are executed by the processing core to implement the method as described in the first aspect or any one of the possible methods of the first aspect.

[0073] Sixthly, embodiments of the present invention provide a board card, the board card including the chip described in the fifth aspect.

[0074] In a seventh aspect, embodiments of the present invention provide a server, the server including the board from the sixth aspect.

[0075] This invention, through the execution of a configuration instruction, obtains the configuration parameters of that instruction, wherein the configuration instruction carries a tag index. The obtained configuration parameters are then updated in the file entry corresponding to the configuration instruction based on the tag index, and the destination register in the file entry is set to a ready state. The destination register of the configuration instruction is set as the first source register of the vector instruction corresponding to the configuration instruction. In response to the first source register and other source registers of the vector instruction being in a ready state, the configuration parameters in the file entry are obtained based on the tag index carried in the vector instruction, wherein the tag index carried in the vector instruction is the same as the tag index carried in the configuration instruction. The vector instruction is then executed. This method ensures that even when vector instructions are executed out of order, the configuration parameters Vtype and Vl of the corresponding configuration Vset instruction are accurately obtained based on the tag index, guaranteeing the accuracy of the processing results when the vector processor processes vector instructions. Attached Figure Description

[0076] The above and other objects, features and advantages of the present invention will become clearer from the following description of embodiments of the invention with reference to the accompanying drawings, in which:

[0077] Figure 1 This is a flowchart of a vector instruction processing method based on the RISC-V instruction set according to an embodiment of the present invention;

[0078] Figure 2 This is a schematic diagram of a configuration information structure according to an embodiment of the present invention;

[0079] Figure 3 This is a schematic diagram of a register list corresponding to a vector instruction in an embodiment of the present invention;

[0080] Figure 4 This is a flowchart of another vector instruction processing method based on the RISC-V instruction set according to an embodiment of the present invention;

[0081] Figure 5 This is a flowchart of another vector instruction processing method based on the RISC-V instruction set according to an embodiment of the present invention;

[0082] Figure 6 This is a schematic diagram of the processing flow of configuration instructions and vector instructions according to an embodiment of the present invention;

[0083] Figure 7 This is a flowchart of a vector instruction processing method based on the RISC-V instruction set according to an embodiment of the present invention;

[0084] Figure 8 This is a schematic diagram of a vector instruction processing device based on the RISC-V instruction set according to an embodiment of the present invention. Detailed Implementation

[0085] The present invention is described below based on embodiments, but the invention is not limited to these embodiments. In the detailed description of the invention below, certain specific details are described in detail. Those skilled in the art will fully understand the invention even without these details. To avoid obscuring the essence of the invention, well-known methods, processes, flows, elements, and circuits are not described in detail.

[0086] Furthermore, those skilled in the art should understand that the accompanying drawings provided herein are for illustrative purposes only and are not necessarily drawn to scale.

[0087] Unless the context explicitly requires it, words such as "including" or "contains" throughout the application should be interpreted as including rather than exclusive or exhaustive; that is, meaning "including but not limited to".

[0088] In the description disclosed in this invention, it should be understood that the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance. Furthermore, in the description disclosed in this invention, unless otherwise stated, "a plurality of" means two or more.

[0089] In the prior art, RISC-V (Reduced Instruction Set Computer-Five) includes a basic instruction set and extended instruction sets. The basic instruction set includes RV32I, RV32E, RV64I, and RV128I, while the extended instruction set includes M, A, F, D, C, and V extensions. Taking the V extension as an example, the V extension is the vector extension instruction set (RISC-VVector). RISC-V is implemented through a Vector processor. The vector extension instruction set includes the Vset instruction and the Vector instruction. The Vset instruction configures the Vtype and Vl parameters required for the execution of the Vector instruction. The execution of each Vector instruction depends on its corresponding V. The configuration result of the `set` instruction is subject to sequential execution. Each Vector instruction depends on the nearest `Vset` instruction. After `Vset` completes, it writes the results `Vtype` and `Vl` to registers. Vector instructions can then directly read these registers to obtain the correct configuration parameters `Vtype` and `Vl`. Furthermore, because Vector instructions execute sequentially—meaning they can only be executed when they are determined to be committed—meaning they are only sent to the Vector processor for execution if they are located at the head of the Reorder Buffer (ROB). Therefore, in sequential execution, the next Vector instruction must wait for the previous one to complete. This results in long wait times for Vector instructions that do not depend on the results of previous instructions, impacting Vector processor performance. Therefore, Vector instructions that do not depend on the results of previous instructions can be executed earlier to improve Vector processor performance. However, when Vector instructions are executed out of order, their corresponding configuration Vset instructions may also be executed out of order. In this case, the configuration parameters Vtype and Vl obtained by the Vector instructions after the configuration Vset instructions may be incorrect, and may be configuration parameters of other configuration Vset instructions. Since the execution of Vector instructions depends on their corresponding Vset instructions, how to ensure that the configuration parameters Vtype and Vl of the corresponding Vset instructions are accurately obtained when Vector instructions are executed out of order is a problem that needs to be solved.

[0090] In this embodiment of the invention, to solve the above problems, a vector instruction processing method based on the RISC-V instruction set is proposed, specifically as follows: Figure 1 As shown, Figure 1 This is a flowchart of a vector instruction processing method based on the RISC-V instruction set according to an embodiment of the present invention, specifically including:

[0091] Step S100: Execute the configuration instruction and obtain the configuration parameters of the configuration instruction, wherein the configuration instruction carries a tag index.

[0092] Specifically, the configuration parameters are vector data type register (Vtype) and vector element length (Vl), where Vtype is used to interpret the default type of the vector register file content.

[0093] In this embodiment of the invention, the tag index is a unique index generated for the configuration instruction during the decoding stage; and during the decoding stage, each configuration instruction is assigned a corresponding file entry in the configuration cache, wherein the file entry includes configuration information such as... Figure 2 Specifically, the configuration parameters include the tag index, the destination register rd, Vtype, Vl, and the validity indicator. The validity indicator indicates whether the configuration parameters are valid. If the validity indicator is marked as valid, it means that the configuration instruction has been executed and the Vtype and Vl in the file entry have been updated. Furthermore, it indicates that the Vector instruction corresponding to the configuration instruction can obtain valid Vtype and Vl.

[0094] In one possible implementation, since the tag index is added to the configuration instruction during the decoding stage, the corresponding file entry in the configuration cache can be found based on the tag index when the configuration instruction is executed.

[0095] In one possible implementation, the configuration command can be vsetvli, vsetvl, or vsetvli. In this embodiment of the invention, vsetvli can be selected as an example.

[0096] Step S101: Update the obtained configuration parameters to the file entry corresponding to the configuration instruction according to the tag index, and set the destination register in the file entry to the ready state, wherein the destination register of the configuration instruction is set to the first source register of the vector instruction corresponding to the configuration instruction.

[0097] Specifically, after finding the corresponding file entry in the configuration cache based on the tag index, the configuration parameters Vtype and Vl generated according to the configuration instructions are updated to the corresponding positions in the file entry. In one possible implementation, the validity indicator in the file entry is marked as valid. For example, the validity indicator is represented by false or true; valid can be represented as true, and invalid can be represented as false.

[0098] Furthermore, after the configuration parameters are updated, the destination register rd is set to the ready state.

[0099] Since the destination register (rd) of the configuration instruction has been added to the source register list of its corresponding vector instruction, the destination register in the file entry is set to the ready state, indicating that the first source register is ready. For example, if vector instruction A originally has 3 source registers, during the decoding stage, the destination register of the configuration instruction B corresponding to vector instruction A can be added to the source register list of that vector instruction, that is, added to the list as the 4th source register (without overwriting any existing source registers). When the state of the destination register of configuration instruction B is ready, the state of the 4th source register of vector instruction A is also ready.

[0100] In one possible implementation, the first source register is one of multiple registers corresponding to a vector instruction. For example, suppose the register list corresponding to the vector instruction includes four registers. Figure 3 As shown, it includes a destination register rd1, a second source register rs1, a third source register rs2, and a first source register rs3. The destination register of the configuration instruction is the first source register in the vector instruction corresponding to the configuration instruction. When the destination register rd of the configuration instruction is set to the ready state, that is, the first source register rs3 is in the ready state. Specifically, setting the ready state is also called the wake-up mechanism.

[0101] Step S102: In response to the first source register and the other source registers of the vector instruction being in a ready state, the configuration parameters in the file entry are obtained according to the tag index carried in the vector instruction, wherein the tag index carried in the vector instruction is the same as the tag index carried in the configuration instruction.

[0102] Specifically, when all registers corresponding to the vector instruction are in a ready state, it means that the vector instruction is ready to be executed. When executing the vector instruction, configuration parameters need to be obtained. Therefore, the configuration parameters with true validity in the corresponding file entry need to be searched in the configuration cache according to the tag index carried in the vector instruction.

[0103] Step S103: Execute the vector instruction.

[0104] Specifically, when the vector instruction is executed, it needs to parse the register group Lmul and the element bit width Sew from the configuration parameter Vtype; and determine the number of elements to be updated by the Vector instruction from the configuration parameter Vl.

[0105] In this embodiment of the invention, it can be ensured that even when vector instructions are executed out of order, the configuration parameters Vtype and Vl of the corresponding configuration Vset instruction can be accurately obtained based on the label index, thus ensuring the accuracy of the processing results when the vector processor processes vector instructions and is not affected by out-of-order execution.

[0106] In one possible implementation, prior to step S100, the method further includes other steps, specifically as follows: Figure 4 As shown, Figure 4 This is a flowchart of a vector instruction processing method based on the RISC-V instruction set according to an embodiment of the present invention, specifically including:

[0107] Step S104: Obtain instruction data.

[0108] In one possible implementation, instruction data is retrieved from the instruction cache. The instruction data can be a configuration instruction or a vector instruction, and this embodiment of the invention does not limit the specific type of instruction.

[0109] Step S105: In the decoding stage, in response to the instruction data being the configuration instruction, a corresponding file entry is allocated for the configuration instruction in the configuration cache, and a tag index is generated.

[0110] Specifically, the generated unique tag index is written into the file entry. At the same time, the destination register of the configuration instruction is written into the file entry, the destination register is set to an inactive state, and the validity indicator in the file entry is marked as invalid. At this time, the positions of the configuration parameters Vtype and Vl in the file entry are empty.

[0111] Step S106: Add the tag index to the configuration instruction.

[0112] In one possible implementation, the purpose of adding the tag index to the configuration instruction is that after the configuration instruction is executed, the generated configuration parameters can be updated to the corresponding file entries based on the tag index.

[0113] In one possible implementation, after step S106, the method further includes other steps, specifically as follows: Figure 5 As shown, Figure 5This is a flowchart of a vector instruction processing method based on the RISC-V instruction set according to an embodiment of the present invention, specifically including:

[0114] Step S107: Write the file entry corresponding to the configuration instruction to the end of the configuration cache.

[0115] Specifically, the configuration cache includes multiple file entries, and the file entry for each configuration instruction is written to the configuration cache in the order of decoding.

[0116] Step S108: In the decoding stage, in response to the instruction data being the vector instruction, the file entry is obtained from the end of the configuration cache.

[0117] Specifically, retrieving the file entry from the tail of the configuration cache ensures that the file entry obtained by the vector instruction corresponds to the configuration information of the nearest configuration instruction. The nearest configuration instruction is the configuration instruction to which this vector instruction belongs. Therefore, the file entry of the configuration instruction at the tail is closest to the currently decoded vector instruction, and the information in this tail file entry is the information to be added by the currently decoded vector instruction.

[0118] Step S109: In response to the validity indication in the file entry being marked as invalid, the first source register in the file entry is added to the source register list of the vector instruction. By adding the first source register in the file entry to the source register list of the vector instruction, the destination register of the configuration instruction is set as the first source register of the vector instruction corresponding to the configuration instruction.

[0119] Specifically, if the validity indicator in the file entry is marked as invalid, it means that the configuration instruction corresponding to the file entry has not yet been executed.

[0120] In one possible implementation, if the validity indicator in the file entry is marked as valid, it means that the configuration instruction corresponding to the file entry has been executed, and there is no need to add the first source register in the file entry to the source register list of the vector instruction.

[0121] Step S110: Add the tag index from the file entry to the vector instruction.

[0122] In one possible implementation, adding the tag index from the file entry to the vector instruction aims to find the configuration parameters in the corresponding file entry based on the tag index when executing the vector instruction, ensuring that incorrect configuration parameters are not used and guaranteeing the accuracy of the vector processor when processing vector instructions.

[0123] In one possible implementation, after the decoding stage, the method further includes: renaming the vector instructions and the configuration instructions after the decoding stage; after the renaming is completed, writing the vector instructions and the configuration instructions into the reordering cache (ROB), and distributing the vector instructions and the configuration instructions to different instruction slots according to different instruction types.

[0124] Optionally, the writing order when renaming the vector instructions and the configuration instructions and writing them into the reorder cache (ROB) is only for recording the vector instructions and the configuration instructions, and does not affect the execution order, nor does it represent the execution order.

[0125] Optionally, the vector instructions and the configuration instructions are distributed to different instruction slots according to different instruction types. For example, the configuration instruction vsetvli, vector instruction 1, and vector instruction 2 are distributed to different instruction slots. After the registers corresponding to the configuration instruction vsetvli, vector instruction 1, and vector instruction 2 are all in a ready state, they can be sent to the execution unit for execution. If vector instruction 1 and vector instruction 2 have no dependency, the two vector instructions can also be executed simultaneously. This embodiment of the invention does not limit this.

[0126] In one possible implementation, the method further includes: in response to any configuration instruction moving to the head of the reorder cache ROB, deleting the file entry corresponding to the configuration instruction preceding the any configuration instruction in the configuration cache.

[0127] Specifically, deleting completed file entries can clear unnecessary cache usage in the configuration cache.

[0128] In one possible implementation, the method further includes: in response to receiving a clear instruction, determining the clear point corresponding to the clear instruction; and deleting the file entries in the configuration cache preceding the clear point.

[0129] In one possible implementation, the method further includes: in response to executing the vector instruction, searching for a file entry corresponding to the configuration instruction based on the tag index carried in the vector instruction; in response to the validity indicator in the file entry being marked as valid, obtaining the configuration parameters in the file entry; and executing the vector instruction based on the configuration parameters.

[0130] In this embodiment of the invention, the configuration instructions and the vector instructions can be considered to be processed on the same pipeline, including the following stages: Fetch Stage, Decode Stage, Rename Stage, Dispatch Stage, Issue Stage, Execute Stage, Write-back Stage, and Commit Stage. The Fetch Stage, Decode Stage, Rename Stage, and Commit Stage are executed sequentially, while the other stages can be executed out of order. In this embodiment, we mainly focus on the Decode Stage, Issue Stage, Execute Stage, and Commit Stage, specifically as follows... Figure 6 As shown.

[0131] In the Figure 6 In the decoding stage, the configuration instruction Vestvil, vector instruction Vector1, and vector instruction Vector2 need to be decoded. The following describes the processing steps... Figure 6 A detailed explanation is provided, and the specific processing steps are shown in the flowchart below. Figure 7 As shown, the details are as follows:

[0132] Step S700: Obtain instruction data.

[0133] Step S701: In the decoding stage, in response to the instruction data being a configuration instruction, a corresponding file entry is allocated for the configuration instruction in the configuration cache, and a tag index is generated. At the same time, the destination register in the file entry is set to an unexecuted state.

[0134] Specifically, during the decoding stage, the configuration instruction Vestvil corresponds to the destination register rd, register rs, and vtypei (the bit width of each vector element); the vector instruction Vector1 corresponds to the destination register rd1, the first source register rs3, the second source register rs1, and the third source register rs2; the vector instruction Vector2 corresponds to the destination register rd1, the first source register rs3, the second source register rs1, and the third source register rs2. In this embodiment of the invention, the register lists corresponding to the vector instructions Vector1 and Vector2 can be the same or different, and this embodiment of the invention does not limit them.

[0135] like Figure 6 The state of the destination register rd corresponding to the configuration instruction Vestvil is the same as that of the first source register rs3 corresponding to the vector instructions Vector1 and Vector2.

[0136] Step S702: Write the file entry corresponding to the configuration instruction to the end of the configuration cache, and at the same time, add the tag index to the configuration instruction.

[0137] Specifically, the configuration cache includes file entries including configuration information config1 and configuration information config2, and the configuration information config3 generated by the configuration command Vestvil is written to the end of the configuration cache.

[0138] In this embodiment of the invention, each configuration information includes a tag index (tag), a destination register (rd), a Vtype, a Vl, and a validity indicator (valid).

[0139] Step S703: In response to the instruction data being the vector instruction, obtain the configuration information of the file entry from the end of the configuration cache.

[0140] Step S704: In response to the validity indication in the file entry being marked as invalid, the first source register in the file entry is added to the source register list of the vector instruction.

[0141] Step S705: Add the tag index to the vector instruction.

[0142] Step S706: Rename the vector instructions and configuration instructions after the decoding stage.

[0143] Step S707: After the renaming is completed, the vector instruction and the configuration instruction are written into the reorder cache (ROB).

[0144] Step S708: Distribute the vector instructions and the configuration instructions to different instruction slots according to different instruction types.

[0145] Specifically, the configuration command Vestvil, the vector command Vector1, and the vector command Vector2 are distributed to different command slots.

[0146] Step S709: Execute the configuration command and obtain the configuration parameters of the configuration command.

[0147] Step S710: Update the configuration parameters in the file entry corresponding to the configuration instruction according to the tag index, and set the destination register in the file entry to the ready state.

[0148] Specifically, after the configuration instructions are completed, the wake-up mechanism will be triggered to wake up the first source register.

[0149] Step S711: Set the first source register to the ready state.

[0150] Step S712: In response to the first source register and the other source registers of the vector instruction being in a ready state, the configuration parameters are obtained according to the tag index carried in the vector instruction.

[0151] Step S713: Execute the vector instruction.

[0152] Step S714: In response to any configuration instruction moving to the head of the reorder cache ROB, delete the file entry corresponding to the configuration instruction preceding the configuration instruction in the configuration cache.

[0153] Specifically, the reorder cache ROB includes multiple vector instructions and configuration instructions in sequence. Assuming that config1 in the configuration cache corresponds to Vest1, when the header of the reorder cache ROB is Vest2, it means that Vest1 has been completed. Therefore, config1 in the configuration cache is deleted.

[0154] In one possible implementation, during the decoding stage, the destination register of the configuration instruction may not be added to the source register list of the vector instruction; instead, the tag index of the configuration instruction can be written into its corresponding vector instruction. After the configuration instruction is executed, the generated configuration parameters vtype and vl are updated to the file entry corresponding to the configuration instruction using the tag index, and the validity indicator in the file entry corresponding to the configuration instruction is marked as valid. During the distribution stage, the ability of the vector instruction to be emitted is actively detected. Specifically, the configuration information corresponding to the configuration instruction in the configuration cache is obtained based on the tag index in the vector instruction. If the validity indicator corresponding to the configuration instruction is detected as valid, the vector instruction is sent to the execution unit, the configuration parameters are obtained from the configuration cache, and the vector instruction is executed. If the validity indicator corresponding to the configuration instruction is detected as invalid, the emission of the vector instruction is blocked, and the detection is repeated.

[0155] The above embodiments and Figure 7 The difference between the specific embodiments is that, Figure 7 The latter uses a wake-up mechanism to wake up the execution of vector instructions, without requiring the dispatch phase to actively detect whether the vector instructions can be executed. These are two different processing methods, and this embodiment of the invention does not limit them.

[0156] Figure 8 This is a schematic diagram of a vector instruction processing device based on the RISC-V instruction set according to an embodiment of the present invention. Figure 8 As shown, the device in this embodiment includes a first execution unit 801, a setting unit 802, a processing unit 803, and a second execution unit 804.

[0157] The first execution unit 801 is configured to execute a configuration instruction and obtain configuration parameters of the configuration instruction, wherein the configuration instruction carries a tag index; the setting unit 802 is configured to update the obtained configuration parameters to the file entry corresponding to the configuration instruction according to the tag index, and simultaneously set the destination register in the file entry to a ready state, wherein the destination register of the configuration instruction is set to the first source register of the vector instruction corresponding to the configuration instruction; the processing unit 803, in response to the first source register and other source registers of the vector instruction being in a ready state, is configured to obtain the configuration parameters in the file entry according to the tag index carried in the vector instruction, wherein the tag index carried in the vector instruction is the same as the tag index carried in the configuration instruction; and the second execution unit 804 is configured to execute the vector instruction.

[0158] Optionally, the file entry also includes a validity indicator. After updating the obtained configuration parameters to the file entry corresponding to the configuration instruction according to the tag index, the method further includes:

[0159] The validity indicator in the file entry is marked as valid, wherein the validity indicator is used to indicate whether the configuration parameter in the file entry is valid.

[0160] Optionally, the device may also include:

[0161] The acquisition unit is used to acquire instruction data;

[0162] The processing unit is further configured to, during the decoding stage, in response to the instruction data being the configuration instruction, allocate a corresponding file entry for the configuration instruction in the configuration cache and generate a tag index;

[0163] The processing unit is further configured to add the tag index to the configuration instruction.

[0164] Optionally, the processing unit is further configured to:

[0165] Write the destination register of the configuration instruction into the file entry, and mark the validity indication in the file entry as invalid.

[0166] Optionally, the device may also include:

[0167] The writing unit is used to write the file entry corresponding to the configuration instruction to the end of the configuration cache.

[0168] Optionally, the acquisition unit is further configured to:

[0169] During the decoding phase, in response to the instruction data being the vector instruction, the file entry is retrieved from the end of the configuration cache;

[0170] The processing unit is further configured to: in response to the validity indication in the file entry being marked as invalid, add the first source register in the file entry to the source register list of the vector instruction;

[0171] Add the tag index from the file entry to the vector instruction.

[0172] Optionally, the device may also include:

[0173] The renaming unit is used to rename the vector instructions and the configuration instructions after the decoding stage;

[0174] The processing unit is further configured to, after completing the renaming, write the vector instruction and the configuration instruction into the reorder cache (ROB), and distribute the vector instruction and the configuration instruction to different instruction slots according to different instruction types.

[0175] Optionally, the device may also include:

[0176] The deletion unit, in response to any configuration instruction moving to the head of the reorder cache ROB, is used to delete the file entry corresponding to the configuration instruction preceding the any configuration instruction in the configuration cache.

[0177] Optionally, the receiving unit is further configured to:

[0178] In response to receiving a clear command, determine the clear point corresponding to the clear command;

[0179] The deletion unit is further configured to delete file entries in the configuration cache prior to the clear point.

[0180] Optionally, the configuration parameters include a vector data type register and a vector element length.

[0181] Optionally, the device may also include:

[0182] The lookup unit, in response to executing the vector instruction, is used to look up the file entry corresponding to the configuration instruction based on the tag index carried in the vector instruction;

[0183] The acquisition unit is further configured to acquire the configuration parameters in the file entry in response to the validity indicator mark being valid in the file entry;

[0184] The second execution unit is further configured to execute the vector instructions according to the configuration parameters.

[0185] In this embodiment of the invention, a computer program instruction is also provided, which, when executed by a processor, implements the method described in any one of the above embodiments.

[0186] In this embodiment of the invention, a computer-readable storage medium is also provided, on which computer program instructions are stored, which, when executed by a processor, implement the method described in any one of the above embodiments.

[0187] This invention provides a chip including a memory and a processing core. The memory is used to store one or more computer program instructions, wherein the one or more computer program instructions are executed by the processing core to implement the method described in any of the above embodiments.

[0188] This invention provides a board card that includes the chip.

[0189] This invention provides a server, which includes the aforementioned board.

[0190] As those skilled in the art will recognize, various aspects of the embodiments of the present invention can be implemented as a system, method, or computer program product. Therefore, various aspects of the embodiments of the present invention can take the form of a completely hardware implementation, a completely software implementation (including firmware, resident software, microcode, etc.), or an implementation combining software and hardware aspects, which may generally be referred to herein as a "circuit," "module," or "system." Furthermore, various aspects of the embodiments of the present invention can take the form of a computer program product implemented in one or more computer-readable media having computer-readable program code implemented thereon.

[0191] Any combination of one or more computer-readable media can be used. A computer-readable medium can be a computer-readable signal medium or a computer-readable storage medium. A computer-readable storage medium can be, for example, (but not limited to) an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or apparatus, or any suitable combination thereof. More specific examples (not an exhaustive list) of computer-readable storage media will include: an electrical connection having one or more wires, a portable computer floppy disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable optical disc read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In the context of embodiments of the present invention, a computer-readable storage medium can be any tangible medium capable of containing or storing a program used by or in conjunction with an instruction execution system, device, or apparatus.

[0192] Computer-readable signal media may include propagated data signals having computer-readable program code implemented therein, such as in baseband or as part of a carrier wave. Such propagated signals may take any of a variety of forms, including, but not limited to, electromagnetic, optical, or any suitable combination thereof. A computer-readable signal medium may be any computer-readable medium that is not a computer-readable storage medium and can communicate, propagate, or transmit a program used by or in conjunction with an instruction execution system, device, or apparatus.

[0193] Program code implemented on a computer-readable medium may be transmitted using any suitable medium, including but not limited to wireless, wired, fiber optic cable, RF, or any suitable combination thereof.

[0194] Computer program code for performing operations relating to various aspects of embodiments of the present invention can be written in any combination of one or more programming languages, including: object-oriented programming languages ​​such as Java, Smalltalk, C++, etc.; and conventional procedural programming languages ​​such as the "C" programming language or similar programming languages. The program code can be executed as a standalone software package entirely on the user's computer, partially on the user's computer, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter case, the remote computer can be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computer (e.g., via the Internet provided by an Internet service provider).

[0195] The flowchart illustrations and / or block diagrams of the methods, apparatus (systems), and computer program products according to embodiments of the present invention describe various aspects of the embodiments of the present invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus to produce a machine such that the instructions (executed via the processor of the computer or other programmable data processing apparatus) create means for implementing the functions / actions specified in the flowchart and / or block diagram blocks or blocks.

[0196] These computer program instructions may also be stored in a computer-readable medium that can direct a computer, other programmable data processing apparatus or other means to operate in a particular manner, such that the instructions stored in the computer-readable medium produce an article of writing that includes instructions that implement the functions / actions specified in flowchart and / or block diagram blocks or blocks.

[0197] Computer program instructions may also be loaded onto a computer, other programmable data processing apparatus or other device to cause a series of operable steps to be performed on the computer, other programmable apparatus or other device to produce a computer-implemented process, such that the instructions, which execute on the computer or other programmable apparatus, provide for implementing the functions / actions specified in flowchart and / or block diagram blocks or blocks.

[0198] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. For those skilled in the art, the present invention can be modified and varied in various ways. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principle of the present invention should be included within the scope of protection of the present invention.

Claims

1. A vector instruction processing method based on the RISC-V instruction set, characterized in that, The method includes: Execute the configuration command and obtain the configuration parameters of the configuration command, wherein the configuration command carries a tag index; The configuration parameters obtained according to the tag index are updated to the file entry corresponding to the configuration instruction, and the destination register in the file entry is set to the ready state. The destination register of the configuration instruction is set to the first source register of the vector instruction corresponding to the configuration instruction. In response to the first source register and the other source registers of the vector instruction being in a ready state, the configuration parameters in the file entry are obtained according to the tag index carried in the vector instruction, wherein the tag index carried in the vector instruction is the same as the tag index carried in the configuration instruction; Execute the vector instruction.

2. The method as described in claim 1, characterized in that, The file entry also includes a validity indicator. After updating the obtained configuration parameters to the file entry corresponding to the configuration instruction according to the tag index, the method further includes: The validity indicator in the file entry is marked as valid, wherein the validity indicator is used to indicate whether the configuration parameter in the file entry is valid.

3. The method as described in claim 1, characterized in that, The method also includes: Retrieve instruction data; During the decoding phase, in response to the instruction data being the configuration instruction, a corresponding file entry is allocated for the configuration instruction in the configuration cache, and a tag index is generated; Add the tag index to the configuration instruction.

4. The method as described in claim 3, characterized in that, The method also includes: Write the destination register of the configuration instruction into the file entry, and mark the validity indication in the file entry as invalid.

5. The method as described in claim 4, characterized in that, The method also includes: Write the file entry corresponding to the configuration instruction to the end of the configuration cache.

6. The method as described in claim 5, characterized in that, The method also includes: During the decoding phase, in response to the instruction data being the vector instruction, the file entry is retrieved from the end of the configuration cache; In response to the validity indication in the file entry being marked as invalid, the first source register in the file entry is added to the source register list of the vector instruction; Add the tag index from the file entry to the vector instruction.

7. The method as described in claim 3, characterized in that, The method also includes: Rename the vector instructions and configuration instructions after the decoding stage; After the renaming is completed, the vector instructions and the configuration instructions are written into the reorder cache (ROB), and the vector instructions and the configuration instructions are distributed to different instruction slots according to different instruction types.

8. A vector instruction processing device based on the RISC-V instruction set, characterized in that, The device includes: The first execution unit is configured to execute configuration instructions and obtain configuration parameters of the configuration instructions, wherein the configuration instructions carry a tag index; The setting unit is used to update the obtained configuration parameters to the file entry corresponding to the configuration instruction according to the tag index, and at the same time set the destination register in the file entry to a ready state, wherein the destination register of the configuration instruction is set to the first source register of the vector instruction corresponding to the configuration instruction; The processing unit, in response to the first source register and other source registers of the vector instruction being in a ready state, is used to obtain the configuration parameters in the file entry according to the tag index carried in the vector instruction, wherein the tag index carried in the vector instruction is the same as the tag index carried in the configuration instruction; The second execution unit is used to execute the vector instructions.

9. A computer program instruction, characterized in that, The computer program instructions, when executed by a processor, implement the method as described in any one of claims 1-7.

10. A computer-readable storage medium storing computer program instructions thereon, characterized in that, The computer program instructions, when executed by a processor, implement the method as described in any one of claims 1-7.

Images