A system on chip, circuit control method and device
By introducing a reset control unit and synchronization circuit into the system-on-a-chip, combined with a clock gating circuit, the high complexity of the reset control scheme and the timing convergence problem are solved, achieving simplified design and improved stability.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- TENCENT TECHNOLOGY (SHENZHEN) CO LTD
- Filing Date
- 2021-12-31
- Publication Date
- 2026-07-24
AI Technical Summary
Existing system-on-a-chip (SoC) reset control schemes are highly complex and it is difficult to guarantee the timing convergence of reset signals, resulting in high pressure on back-end layout and routing and potential congestion.
A unified reset signal is generated by a reset control unit, and the synchronous processing and gating control of each IP unit are realized by combining a reset synchronization circuit and a clock gating circuit, which simplifies the design and ensures timing convergence.
It effectively simplifies the reset circuit design, ensures the timing convergence of the reset signal, and improves the operational stability of IP units in the system-on-a-chip.
Smart Images
Figure CN116415535B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of electronic circuit technology, and in particular to a system-on-a-chip, circuit control method and device. Background Technology
[0002] System-on-a-chip (SoC) devices are typically composed of interconnected intellectual property (IP) units, such as a system-on-a-chip (SoC). For these SoCs, existing chip reset solutions integrate all reset control functions into a single reset control unit within the chip. However, for IP units comprising multiple circuit units, each circuit unit needs to implement independent reset control logic. Therefore, the reset control unit must provide reset signals to each circuit unit within that IP unit separately. This significantly increases the design complexity of the reset control unit and the number of ports connecting the reset control unit and the IP unit. Furthermore, to avoid uncertain operating states of the IP unit, the recovery time and removal time of the reset signal must be converged. This is typically achieved by designing corresponding circuits in the back-end implementation within the IP unit to ensure timing convergence of the reset signal, placing enormous pressure on back-end layout and routing, and potentially causing congestion. Therefore, simplifying the design of the reset circuit and effectively ensuring the timing convergence of the reset signal has become an urgent problem to be solved. Summary of the Invention
[0003] This application provides a system-on-a-chip, circuit control method, and apparatus that can effectively simplify the design of the reset circuit and ensure the timing convergence of the reset signal.
[0004] In a first aspect, embodiments of this application provide a system-on-a-chip (SoC) comprising a reset control unit and at least one intellectual property (IP) unit. Each IP unit includes a reset synchronization circuit and a clock gating circuit. The reset control unit is connected to each IP unit, wherein:
[0005] The reset control unit is used to generate a reset signal for each IP unit.
[0006] The reset synchronization circuit is used to synchronize the reset signal according to the clock signal of each IP unit to obtain a synchronized reset signal. The synchronized reset signal is used to reset at least one circuit unit included in each IP unit.
[0007] The reset control unit is further configured to generate a gating signal for each IP unit based on the synchronized reset signal of each IP unit, wherein the gating signal is used to control the clock gating circuit included in each IP unit to enable or disable the clock signal of each IP unit.
[0008] Secondly, embodiments of this application provide a circuit control method applied to a system-on-a-chip (SoC). The SoC includes a reset control unit and at least one intellectual property (IP) unit. Each IP unit includes a reset synchronization circuit and a clock gating circuit. The reset control unit is connected to each IP unit. The method includes:
[0009] The first IP unit calls the reset synchronization circuit to synchronize the reset signal generated by the reset control unit to obtain a synchronized reset signal. The first IP unit is any one of the at least one intellectual property IP unit.
[0010] The first IP unit uses the synchronized reset signal to reset at least one circuit unit included in the first IP unit.
[0011] The first IP unit controls the clock gating circuit to enable or disable the clock signal of the first IP unit according to the gating signal of the first IP unit. The gating signal is generated by the reset control unit according to the synchronized reset signal.
[0012] Thirdly, embodiments of this application provide a circuit control method applied to a system-on-a-chip (SoC). The SoC includes a reset control unit and at least one intellectual property (IP) unit. Each IP unit includes a reset synchronization circuit and a clock gating circuit. The reset control unit is connected to each IP unit. The method includes:
[0013] The reset control unit generates a reset signal for each IP unit, so that each IP unit obtains a synchronized reset signal using the reset synchronization circuit. The synchronized reset signal is used to reset at least one circuit unit included in each IP unit.
[0014] The reset control unit generates a gating signal for each IP unit based on the synchronized reset signal of each IP unit. The gating signal is used to control the clock gating circuit included in each IP unit to enable or disable the clock signal of each IP unit.
[0015] Fourthly, embodiments of this application provide a circuit control device, the device comprising:
[0016] The processing module is used to call the reset synchronization circuit included in the first IP unit to perform synchronization processing on the reset signal generated by the reset control unit to obtain a synchronized reset signal. The first IP unit is any one of at least one intellectual property IP unit.
[0017] A reset module is used to reset at least one circuit unit included in the first IP unit using the synchronized reset signal.
[0018] The control module is used to control the clock gating circuit included in the first IP unit to enable or disable the clock signal of the first IP unit according to the gating signal of the first IP unit. The gating signal is generated by the reset control unit according to the synchronized reset signal.
[0019] Fifthly, embodiments of this application provide a circuit control device, the device comprising:
[0020] The first generation module is used to generate a reset signal for each IP unit in at least one intellectual property IP unit, so that each IP unit obtains a synchronized reset signal using a reset synchronization circuit, and the synchronized reset signal is used to reset at least one circuit unit included in each IP unit.
[0021] The second generation module is used to generate a gating signal for each IP unit based on the synchronized reset signal of each IP unit. The gating signal is used to control the clock gating circuit included in each IP unit to enable or disable the clock signal of each IP unit.
[0022] In a sixth aspect, embodiments of this application provide a computer-readable storage medium storing a computer program, the computer program including program instructions that are executed by a processor to perform the circuit control method as described in the second or third aspect.
[0023] In this embodiment, the system-on-a-chip (SoC) includes a reset control unit and at least one intellectual property (IP) unit. Each IP unit includes a reset synchronization circuit and a clock gating circuit. The reset control unit generates a reset signal for each IP unit. The reset synchronization circuit of each IP unit synchronizes the reset signal according to the clock signal of each IP unit to obtain a synchronized reset signal. The synchronized reset signal can be used to reset at least one circuit unit included in each IP unit. The synchronized reset signal is used as a unified reset control signal for an IP unit, meaning that one reset signal generated by the reset control unit can be used to control the reset of multiple circuit units in the IP unit. In addition, the reset control unit also generates a gating signal for each IP unit according to the synchronized reset signal of each IP unit. The clock gating circuit included in each IP unit enables or disables the clock signal of each IP unit according to the gating signal to ensure the timing convergence requirement of the reset signal during the reset release process. This effectively simplifies the design of the reset circuit, ensures the timing convergence of the reset signal, and improves the stability of the IP unit operation in the SoC. Attached Figure Description
[0024] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0025] Figure 1 This is a schematic diagram of the circuit structure of a system-on-a-chip provided in an embodiment of this application;
[0026] Figure 2a This is a schematic diagram of the circuit structure of another system-on-a-chip provided in an embodiment of this application;
[0027] Figure 2b This is a schematic diagram of the circuit structure of an IP unit provided in an embodiment of this application;
[0028] Figure 2c This is a schematic diagram of the circuit structure of a reset control module provided in an embodiment of this application;
[0029] Figure 2d This is a timing diagram of the operation of the multi-channel signal provided in the embodiments of this application;
[0030] Figure 2e This is a schematic diagram of a reset circuit structure for an IP unit provided in an embodiment of this application;
[0031] Figure 2fThis is a schematic diagram of the circuit structure of another system-on-a-chip provided in the embodiments of this application;
[0032] Figure 3 This is a schematic flowchart of a circuit control method provided in an embodiment of this application;
[0033] Figure 4 This is a schematic flowchart of another circuit control method provided in an embodiment of this application;
[0034] Figure 5 This is a schematic diagram of the structure of a circuit control device provided in an embodiment of this application;
[0035] Figure 6 This is a schematic diagram of another circuit control device provided in an embodiment of this application. Detailed Implementation
[0036] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.
[0037] Please see Figure 1 This is a schematic diagram of the circuit structure of a system-on-a-chip (SoC) provided in an embodiment of this application. The SoC 10 includes a reset control unit 11 and at least one intellectual property (IP) unit 12. Each IP unit 12 includes a reset synchronization circuit 121 and a clock gating circuit 122. The reset control unit 11 is connected to each IP unit 12, wherein:
[0038] The reset control unit 11 is used to generate a reset signal for each IP unit 12.
[0039] The reset synchronization circuit 121 of each IP unit 12 is used to synchronize the reset signal according to the clock signal of each IP unit 12 to obtain a synchronized reset signal. The synchronized reset signal is used to reset at least one circuit unit 123 included in each IP unit 12.
[0040] The reset control unit 11 is also configured to generate a gating signal for each IP unit 12 based on the synchronized reset signal of each IP unit 12. The gating signal is used to control the clock gating circuit 122 included in each IP unit 12 to enable or disable the clock signal of each IP unit 12.
[0041] Specifically, for each IP unit 12, the reset control unit 11 can generate a corresponding reset signal, so that for each IP unit 12, the reset control unit 11 can occupy only one port to transmit the reset signal to each IP unit 12. Each IP unit 12 has its own clock signal required for operation. Different IP units 12 can share the same clock signal; of course, different IP units 12 can also each have their own clock signal, that is, each uses a different clock signal. This application embodiment does not limit this.
[0042] Because synchronous convergence of reset signals must be ensured within the IP unit, the asynchronous reset signal generated by the reset control unit must be synchronized with the IP unit's clock signal before being used within the IP unit. Specifically, the reset synchronization circuit 121 of each IP unit 12 synchronizes the corresponding reset signal based on the clock signal of each IP unit 12, obtaining a synchronized reset signal for each IP unit 12. This synchronized reset signal can be used to reset at least one circuit unit 123 included in each IP unit 12; that is, each IP unit 12 can use its own synchronized reset signal to reset one or more of its own circuit units. For example, if an IP unit 12 includes multiple circuit units such as a top-level circuit unit and functional circuit units, then the IP unit 12 can perform reset control on the top-level circuit unit and each functional circuit unit separately based on the synchronized reset signal. This effectively achieves independent reset control of each circuit unit within the same IP unit and simplifies the design complexity of the reset control unit 11 for reset control.
[0043] Furthermore, to ensure the timing convergence of the reset signal and avoid uncertain operating states of the internal circuits of the IP units, the reset control unit 11 can also generate a gate signal for each IP unit 12 based on the synchronized reset signal of each IP unit 12. For example, the gate signal for each IP unit 12 can be generated based on the changes in the synchronized reset signal of each IP unit 12. The clock gate circuit 122 of each IP unit 12 can be used to enable or disable the clock signal of each IP unit based on the gate signal of each IP unit, so that the recovery time and removal time of the reset signal during the reset release process meet the requirements, thereby ensuring the timing convergence of the reset signal during the reset release process. Specifically, the clock gate circuit 122 can adopt a clock gate circuit design.
[0044] In some feasible implementations, the top-level circuit unit in an IP unit can be understood as the bus design circuit of the entire IP unit, responsible for the bus allocation and layout of the IP unit. Each functional circuit unit can be understood as implementing specific functions based on the bus of the top-level circuit unit.
[0045] In some feasible implementations, the reset synchronization circuit 121 may specifically be a multi-level register, such as a three-level register, to achieve multi-level synchronization of the reset signal.
[0046] In some feasible implementations, the system-on-a-chip described in the embodiments of this application may specifically be a system on a chip (SOC), and the embodiments of this application do not limit this.
[0047] In this embodiment, the reset control unit of the system-on-a-chip (SoC) is used to generate a reset signal for each IP unit. The reset synchronization circuit of each IP unit of the SoC is used to synchronize the reset signal according to the clock signal of each IP unit to obtain a synchronized reset signal. The synchronized reset signal can be used to reset at least one circuit unit included in each IP unit. The synchronized reset signal is used as a unified reset control signal for an IP unit; that is, one reset signal generated by the reset control unit can be used to control the reset of multiple circuit units in the IP unit. In addition, the reset control unit is also used to generate a gating signal for each IP unit according to the synchronized reset signal. The clock gating circuit included in each IP unit enables or disables the clock signal of each IP unit according to the gating signal to ensure the timing convergence requirement of the reset signal during the reset release process. This effectively simplifies the design of the reset circuit, ensures the timing convergence of the reset signal, and improves the stability of the IP unit operation in the SoC.
[0048] In some feasible implementations, the reset control unit 11 is specifically configured to: cause each IP unit 12 to enter a reset state after synchronization of the reset signal of each IP unit 12, and after a first preset time, control the gate signal of each IP unit 12 to a first level to disable the clock signal of each IP unit 12; cause each IP unit 12 to exit the reset state after synchronization of the reset signal of each IP unit 12, and after a second preset time, control the gate signal of each IP unit 12 to a second level to enable the clock signal of each IP unit 12.
[0049] The specific values of the first preset duration and the second preset duration can be flexibly designed according to the requirements of the recovery time and removal time of the reset signal. For example, the first preset duration can be 11 clock cycles or 6 clock cycles. The first preset duration and the second preset duration can be the same or different, but they should both meet the requirements of the recovery time and removal time of the reset signal.
[0050] like Figure 2d As shown, taking an IP unit 12 that is triggered by a falling edge and exits the reset on a rising edge as an example, the actual signals driving the IP unit 12 include a gated clock signal and a reset signal. Specifically, the reset signal refers to the synchronized reset signal. When the IP unit 12 needs to enter the reset state, the reset signal generated by the reset control unit 11 is synchronized by the reset synchronization circuit 121 and pulled low at time a, so the IP unit 12 enters the reset state. Then, at time b, 10 clock cycles after time a, the reset control unit 11 adjusts the gate signal of the IP unit 12 to the first level (such as a high level) to disable the clock signal of the IP unit 12. One clock cycle after time b, the clock is disabled, that is, the gated clock signal is empty (equivalent to cutting off the clock signal). When the IP unit 12 needs to exit the reset state, the reset signal generated by the reset control unit 11 is pulled high at time c after passing through the reset synchronization circuit 121, so the IP unit 12 exits the reset state. At time d, after 10 clock cycles, the reset control unit 11 adjusts the gate signal of the IP unit 12 to the second level (e.g., low level). After another clock cycle, the clock is enabled, meaning the gated clock signal is restored. It can be seen that since the total clock cycle from time c to time d+1 is 11 cycles, the Removal Time and Recovery Time of the reset signal are satisfied, thus ensuring timing convergence of the reset. There is no need to further converge the timing in the back-end implementation, effectively simplifying the design of the reset circuit and ensuring timing convergence of the reset signal.
[0051] In some feasible implementations, the specific structure of the reset control unit 11 can be as follows: Figure 2a As shown, the reset control unit 11 includes a reset signal generation circuit 111 and a gate signal generation module 112, wherein:
[0052] The reset signal generation circuit 111 is used to generate a reset signal for each IP unit 12.
[0053] The gating signal generation module 112 is used to generate a gating signal for each IP unit 12 based on the synchronized reset signal of each IP unit 12.
[0054] Specifically, the gate signal generation module 112 can be a software-controlled register. The gate signal generation module 112 can include registers that match the number of IP units 12. Each register is used to control the generation of the corresponding gate signal for the IP unit 12. For example, by modifying the value of the register, the gate signal can be adjusted to a low level or a high level. Thus, the reset control unit can generate the reset signal and gate signal required by each IP unit using the reset signal generation circuit and the gate signal generation module.
[0055] In some feasible implementations, an IP unit may include multiple circuit units, and each circuit unit can implement independent reset control logic. The IP unit may include a first circuit unit and at least one second circuit unit. The first circuit unit may be a top-level circuit unit, and the second circuit unit may be a functional circuit unit. The reset control of each second circuit unit can be implemented in the first circuit unit, and the timing convergence of the reset signals of each second circuit unit can be guaranteed simultaneously. Taking the first IP unit as an example, the first IP unit can be any one of the at least one intellectual property IP unit mentioned above. Figure 2b As shown, the first IP unit 12 includes a first circuit unit 124 and three second circuit units (second circuit unit 125, second circuit unit 126, and second circuit unit 127). The first IP unit 12 also includes the first circuit unit 124 and clock gating circuits 122 corresponding to each of the second circuit units (second circuit unit 125, second circuit unit 126, and second circuit unit 127). The first circuit unit 124 includes a gating module 1241 and a reset control module 1242 corresponding to each of the second circuit units, wherein:
[0056] The reset control module 1242 corresponding to each second circuit unit is used to generate a reset signal for each second circuit unit according to the reset signal of the first circuit unit 124. The reset signal of each second circuit unit is used to reset each second circuit unit. The reset signal of the first circuit unit 124 is the reset signal after synchronization of the first IP unit 12.
[0057] The gating module 1241 corresponding to each second circuit unit is used to generate a gating signal for each second circuit unit based on the reset signal of each second circuit unit.
[0058] The first IP unit 12 includes a clock gating circuit 122 corresponding to each second circuit unit, which is used to enable or disable the clock signal of each second circuit unit according to the gating signal of each second circuit unit.
[0059] In some feasible implementations, the reset synchronization circuit 121 of the first IP unit 12 is specifically used to synchronize the reset signal of the first IP unit 12 according to the clock signal of the first circuit unit 124 to obtain the reset signal of the first circuit unit 124, and the reset signal of the first circuit unit 124 is used to reset the first circuit unit 124.
[0060] The gate signal generation module 112 of the reset control unit 11 is specifically used to generate a gate signal for the first circuit unit 124 based on the reset signal of the first circuit unit 124.
[0061] The first IP unit 12 includes a clock gate circuit 122 corresponding to the first circuit unit 124, which is used to enable or disable the clock signal of the first circuit unit 124 according to the gate signal of the first circuit unit 124, thereby realizing the effective reset of the first circuit unit and ensuring the timing convergence of the reset signal of the first circuit unit.
[0062] In some feasible implementations, such as Figure 2c As shown, the reset control module 1242 includes a reset register 12421 and a logic processing circuit 12422, wherein:
[0063] The reset register 12421 corresponding to each second circuit unit is used to generate the reset control signal for each second circuit unit.
[0064] The logic processing circuit 12422 corresponding to each second circuit unit is used to process the reset control signal of each second circuit unit and the reset signal of the first circuit unit 124 to generate the reset signal of each second circuit unit. Specifically, the logic processing circuit 12422 can be an AND gate circuit, which can accurately and effectively generate the reset signal required by each second circuit unit by using the reset synchronization circuit of the IP unit (i.e., the reset signal of the first circuit unit).
[0065] In some feasible implementations, the gate module 1241 corresponding to each second circuit unit is specifically used for: causing each second circuit unit to enter a reset state upon receiving a reset signal, and after a third preset time, controlling the gate signal of each second circuit unit to a first level to disable the clock signal of each second circuit unit; causing each second circuit unit to exit the reset state upon receiving a reset signal, and after a fourth preset time, controlling the gate signal of each second circuit unit to a second level to enable the clock signal of each second circuit unit.
[0066] The function of the gating module 1241 is similar to that of the gating signal generation module 112 included in the reset control unit 11. In addition, similar to the design of the first preset duration and the second preset duration, the specific values of the third preset duration and the fourth preset duration can also be flexibly designed according to the requirements of the recovery time and removal time of the reset signal of the corresponding second circuit unit. For example, the third preset duration can be 11 clock cycles or 6 clock cycles. The third preset duration and the fourth preset duration can be the same or different, but they should all meet the requirements of the recovery time and removal time of the reset signal.
[0067] It should be noted that the control methods of the reset control module 1242 and the gate control module 1241 for the reset signal and gate control signal of each second circuit unit can be referred to Figure 2d The corresponding description. Taking the second circuit unit 125 of the first IP unit 12 as an example, assuming that the second circuit unit 125 is triggered by a falling edge and exits the reset on a rising edge, the actual signals driving the second circuit unit 125 include the clock signal of the gated second circuit unit 125 and the reset signal of the second circuit unit 125; when the second circuit unit 125 needs to enter the reset state, the reset control module 1242 corresponding to the second circuit unit 125 pulls the generated reset signal of the second circuit unit 125 low at time a, and the second circuit unit 125 enters the reset state. Then, in 10 clock cycles at time a... At time b, following the initial period, the gating module 1241 corresponding to the second circuit unit 125 adjusts the gating signal of the second circuit unit 125 to the first level (e.g., high level) to disable the clock signal of the second circuit unit 125. After one clock cycle at time b, the clock is disabled, meaning the clock signal of the gated second circuit unit 125 is empty (equivalent to cutting off the clock signal). When the second circuit unit 125 needs to exit the reset state, the reset control module 1242 pulls the generated reset signal of the second circuit unit 125 high at time c, and the second circuit unit 125 exits the reset state. After 10 clock cycles, at time d, the gating module 1241 corresponding to the second circuit unit 125 adjusts the gating signal of the second circuit unit 125 to the second level (e.g., low level). After another clock cycle, the clock is enabled, meaning the clock signal of the gated second circuit unit 125 is restored. As can be seen, since the total clock cycle from time c to time d+1 is 11 cycles, the Removal Time and Recovery Time of the reset signal are already satisfied, thus ensuring the timing convergence of the reset. There is no need to converge the timing in the back-end implementation, which effectively simplifies the design of the reset circuit and ensures the timing convergence of the reset signal.
[0068] In some feasible implementations, the reset control module 1242 and the gating module 1241 can both be software-controlled registers, which can change the level of the reset signal and the gating signal by configuring the value of the register to 0 or 1.
[0069] In some feasible implementations, Figure 1 The IP units shown can be self-developed IP units, whose internal circuit structures can be flexibly designed according to requirements. However, for purchased IP units, their internal designs are usually fixed and cannot be changed arbitrarily. Therefore, a similar design approach can be adopted. For example... Figure 2e As shown, a wrapper structure can be implemented outside the purchased IP unit 13, and the purchased IP unit 13 is instantiated inside the wrapper. Inside the wrapper, a clock gate circuit 122 (such as a clock gate device) is added before the clock signal that originally drives the purchased IP unit 13. Thus, the reset signal is released when the clock is disabled through the reset synchronization circuit 121 and the clock gate circuit 122, so as to ensure the timing convergence of the reset signal of the purchased IP unit.
[0070] It should be noted that if the purchased IP unit cannot be externally wrapped, the corresponding clock gating circuit 122 and reset synchronization circuit 121 can be added to the reset control unit to achieve reset control of the purchased IP unit, such as... Figure 2f As shown, at this time, the clock signal of the purchased IP unit 13 needs to be input to the reset control unit 13 so that the clock gate circuit 122 and the reset synchronization circuit 121 corresponding to the purchased IP unit 13 in the reset control unit 13 can be used.
[0071] In some feasible implementations, a partially distributed reset control scheme can also be adopted. The reset control unit retains some reset circuits that are not easy to implement in the IP unit. At the same time, another part of the reset control is implemented inside the IP unit. Both parts are controlled simultaneously. For example, only a clock gating circuit is added inside the IP unit to ensure the timing convergence of the reset signal, while the corresponding clock gating circuit and reset synchronization circuit are implemented in the reset control unit. This enables a flexible and diverse reset control scheme that can meet the reset requirements of various application scenarios.
[0072] Please see Figure 3This is a flowchart illustrating a circuit control method provided in an embodiment of this application. The method can be applied to a system-on-a-chip (SoC), which includes a reset control unit and at least one intellectual property (IP) unit. Each IP unit includes a reset synchronization circuit and a clock gating circuit. The reset control unit is connected to each IP unit. Specifically, the method may include the following steps:
[0073] 301. The first IP unit calls the reset synchronization circuit to synchronize the reset signal generated by the reset control unit to obtain a synchronized reset signal. The first IP unit is any one of at least one intellectual property IP unit.
[0074] 302. The first IP unit uses the synchronized reset signal to reset at least one circuit unit included in the first IP unit.
[0075] 303. The first IP unit controls the clock gating circuit to enable or disable the clock signal of the first IP unit according to the gating signal of the first IP unit. The gating signal is generated by the reset control unit according to the synchronized reset signal.
[0076] In some feasible implementations, the first IP unit includes a first circuit unit and at least one second circuit unit. The first circuit unit includes a gating module and a reset control module corresponding to each of the at least one second circuit unit. Specific implementations of resetting the at least one circuit unit included in the first IP unit using a synchronized reset signal may include:
[0077] The first IP unit uses the synchronized reset signal as the reset signal of the first circuit unit and resets the first circuit unit using the reset signal of the first circuit unit; it calls the reset control module corresponding to each second circuit unit, generates a reset signal for each second circuit unit based on the reset signal of the first circuit unit, and resets each second circuit unit using the reset signal of each second circuit unit; it calls the gating module corresponding to each second circuit unit, generates a gating signal for each second circuit unit based on the reset signal of each second circuit unit; and it controls the clock gating circuit included in the first IP unit corresponding to each second circuit unit to enable or disable the clock signal of each second circuit unit based on the gating signal of each second circuit unit.
[0078] In some feasible implementations, the reset control module includes a reset register and logic processing circuitry. The first IP unit calls the reset control module corresponding to each second circuit unit. The specific implementation of generating the reset signal for each second circuit unit based on the reset signal of the first circuit unit may include:
[0079] The first IP unit calls the reset register corresponding to each second circuit unit to generate a reset control signal for each second circuit unit; it calls the logic processing circuit corresponding to each second circuit unit to process the reset control signal of each second circuit unit and the reset signal of the first circuit unit to generate a reset signal for each second circuit unit.
[0080] In some feasible implementations, the first IP unit calls the reset synchronization circuit to synchronize the reset signal generated by the reset control unit, and the specific implementation of obtaining the synchronized reset signal may include:
[0081] The first IP unit calls the reset synchronization circuit to synchronize the reset signal generated by the reset control unit according to the clock signal of the first circuit unit, and obtains the reset signal of the first circuit unit; according to the gate signal of the first circuit unit, it controls the clock gate circuit included in the first IP unit corresponding to the first circuit unit to enable or disable the clock signal of the first circuit unit. The gate signal of the first circuit unit is generated by the reset control unit according to the reset signal of the first circuit unit.
[0082] In some feasible implementations, the first IP unit calls the gating module corresponding to each second circuit unit, and the specific implementation of generating the gating signal for each second circuit unit based on the reset signal of each second circuit unit may include...
[0083] The first IP unit, upon receiving a reset signal from each second circuit unit, causes each second circuit unit to enter a reset state. After a third preset time, it invokes the corresponding gating module of each second circuit unit to control the gating signal of each second circuit unit to a first level, thereby disabling the clock signal of each second circuit unit. Upon receiving a reset signal from each second circuit unit, the first IP unit causes each second circuit unit to exit the reset state. After a fourth preset time, it invokes the corresponding gating module of each second circuit unit to control the gating signal of each second circuit unit to a second level, thereby enabling the clock signal of each second circuit unit.
[0084] It should be noted that the specific implementation of each method step in the embodiments of this application can be referred to the relevant description of the above circuit structure embodiments, and will not be repeated here.
[0085] In this embodiment, the first IP unit calls the reset synchronization circuit to synchronize the reset signal generated by the reset control unit to obtain a synchronized reset signal. The synchronized reset signal is then used to reset at least one circuit unit included in the first IP unit. The clock gating circuit can be controlled to enable or disable the clock signal of the first IP unit according to the gating signal of the first IP unit. The gating signal is generated by the reset control unit based on the synchronized reset signal. Thus, the first IP unit can use one reset signal generated by the reset control unit for the reset control of multiple circuit units included in itself. This ensures the timing convergence requirement of the reset signal during the reset release process, reduces the complexity of the IP unit's reset control, and helps improve the stability of the IP unit's operation in the system-on-a-chip.
[0086] Please see Figure 4 This is a flowchart illustrating another circuit control method provided in this application embodiment. This method can be applied to a system-on-a-chip (SoC), which includes a reset control unit and at least one intellectual property (IP) unit. Each IP unit includes a reset synchronization circuit and a clock gating circuit. The reset control unit is connected to each IP unit. Specifically, the method may include the following steps:
[0087] 401. The reset control unit generates a reset signal for each IP unit, such that each IP unit obtains a synchronized reset signal using a reset synchronization circuit, and the synchronized reset signal is used to reset at least one circuit unit included in each IP unit.
[0088] 402. The reset control unit generates a gating signal for each IP unit based on the synchronized reset signal of each IP unit. The gating signal is used to control the clock gating circuit included in each IP unit to enable or disable the clock signal of each IP unit.
[0089] In some feasible implementations, the specific implementation method of the reset control unit generating the gating signal for each IP unit based on the synchronized reset signal of each IP unit may include:
[0090] The reset control unit, after synchronization of each IP unit, sends a reset signal to each IP unit, causing each IP unit to enter a reset state. After a first preset time, it controls the gate signal of each IP unit to a first level to disable the clock signal of each IP unit. After synchronization of each IP unit, the reset signal causes each IP unit to exit the reset state. After a second preset time, it controls the gate signal of each IP unit to a second level to enable the clock signal of each IP unit.
[0091] It should be noted that the specific implementation of each method step in the embodiments of this application can be referred to the relevant description of the above circuit structure embodiments, and will not be repeated here.
[0092] In this embodiment, the reset control unit generates a reset signal for each IP unit, enabling each IP unit to obtain a synchronized reset signal using a reset synchronization circuit. The synchronized reset signal is used to reset at least one circuit unit included in each IP unit. A gate signal for each IP unit is generated based on the synchronized reset signal of each IP unit. The gate signal is used to control the clock gate circuit included in each IP unit to enable or disable the clock signal of each IP unit. The reset control unit only needs to generate one reset signal and one gate signal corresponding to each IP unit, which can ensure the timing convergence requirement of the reset signal during the reset release process, reduce the complexity of the reset control of the IP unit, and help improve the stability of the IP unit operation in the system-on-a-chip.
[0093] In summary, the embodiments of this application provide a distributed reset implementation scheme. On the one hand, by releasing the reset signal when the clock is disabled, the timing requirements of the reset signal during the reset release process can be guaranteed, eliminating the need to converge the Removal Time and Recovery Time of the back-end circuit of the IP unit, greatly reducing the difficulty of timing convergence in the back-end implementation process. On the other hand, if there are independent reset control requirements for multiple levels of circuit units in the IP unit (such as independent reset control of the top-level circuit unit, independent reset control of each functional unit), then by implementing the reset function in a distributed manner within the IP unit, the design complexity of the reset control unit and the number of interconnections between the reset control unit and the IP unit can be reduced, which is beneficial to reducing the coupling between the IP unit and the reset control unit design and improving design efficiency.
[0094] Please see Figure 5 This is a schematic diagram of a circuit control device according to an embodiment of this application. The device includes:
[0095] The processing module 501 is used to call the reset synchronization circuit included in the first IP unit to perform synchronization processing on the reset signal generated by the reset control unit to obtain a synchronized reset signal. The first IP unit is any one of at least one intellectual property IP unit.
[0096] The reset module 502 is used to reset at least one circuit unit included in the first IP unit using the synchronized reset signal.
[0097] The control module 503 is used to control the clock gating circuit included in the first IP unit to enable or disable the clock signal of the first IP unit according to the gating signal of the first IP unit. The gating signal is generated by the reset control unit according to the synchronized reset signal.
[0098] Optionally, the first IP unit includes a first circuit unit and at least one second circuit unit. The first circuit unit includes a gating module and a reset control module corresponding to each of the at least one second circuit unit. The reset module 502 is specifically used for:
[0099] The synchronized reset signal is used as the reset signal of the first circuit unit, and the first circuit unit is reset using the reset signal of the first circuit unit.
[0100] The reset control module corresponding to each second circuit unit is invoked to generate a reset signal for each second circuit unit based on the reset signal of the first circuit unit, and the reset signal of each second circuit unit is used to reset each second circuit unit.
[0101] The gating module corresponding to each second circuit unit is invoked to generate a gating signal for each second circuit unit based on the reset signal of each second circuit unit.
[0102] Based on the gating signal of each second circuit unit, the clock gating circuit of the first IP unit corresponding to each second circuit unit is controlled to enable or disable the clock signal of each second circuit unit.
[0103] Optionally, the reset control module includes a reset register and a logic processing circuit. The reset module 502 is specifically used for:
[0104] The reset control signal for each second circuit unit is generated by calling the reset register corresponding to each second circuit unit.
[0105] The logic processing circuit corresponding to each second circuit unit is invoked to process the reset control signal of each second circuit unit and the reset signal of the first circuit unit to generate the reset signal of each second circuit unit.
[0106] Optionally, the processing module 501 is specifically used for:
[0107] The reset synchronization circuit is invoked to synchronize the reset signal generated by the reset control unit according to the clock signal of the first circuit unit, so as to obtain the reset signal of the first circuit unit.
[0108] Based on the gating signal of the first circuit unit, the clock gating circuit of the first IP unit corresponding to the first circuit unit is controlled to enable or disable the clock signal of the first circuit unit. The gating signal of the first circuit unit is generated by the reset control unit based on the reset signal of the first circuit unit.
[0109] Optionally, the reset module 502 is specifically used for:
[0110] The reset signal of each second circuit unit causes each second circuit unit to enter a reset state, and after a third preset time, the gate control module corresponding to each second circuit unit is called to control the gate control signal of each second circuit unit to the first level, so as to disable the clock signal of each second circuit unit.
[0111] The reset signal of each second circuit unit causes each second circuit unit to exit the reset state, and after a fourth preset time, the gate control module corresponding to each second circuit unit is called to control the gate control signal of each second circuit unit to the second level, so as to enable the clock signal of each second circuit unit.
[0112] It should be noted that the functions of each functional module of the circuit control device in the embodiments of this application can be specifically implemented according to the methods in the above method embodiments. The specific implementation process can be referred to the relevant descriptions in the above method embodiments, which will not be repeated here.
[0113] Please see Figure 6 This is a schematic diagram of another circuit control device according to an embodiment of this application. The device includes:
[0114] The first generation module 601 is used to generate a reset signal for each IP unit in at least one intellectual property IP unit, so that each IP unit obtains a synchronized reset signal using a reset synchronization circuit, and the synchronized reset signal is used to reset at least one circuit unit included in each IP unit.
[0115] The second generation module 602 is used to generate a gating signal for each IP unit based on the synchronized reset signal of each IP unit. The gating signal is used to control the clock gating circuit included in each IP unit to enable or disable the clock signal of each IP unit.
[0116] Optionally, the second generation module 602 is specifically used for:
[0117] The reset signal after synchronization of each IP unit causes each IP unit to enter a reset state, and after a first preset time, the gate signal of each IP unit is controlled to a first level to disable the clock signal of each IP unit.
[0118] The reset signal after synchronization of each IP unit causes each IP unit to exit the reset state, and after a second preset time, the gate signal of each IP unit is controlled to the second level to enable the clock signal of each IP unit.
[0119] It should be noted that the functions of each functional module of the circuit control device in the embodiments of this application can be specifically implemented according to the methods in the above method embodiments. The specific implementation process can be referred to the relevant descriptions in the above method embodiments, which will not be repeated here.
[0120] In some feasible implementations, embodiments of this application also provide an electronic device that includes the system-on-a-chip described in the foregoing embodiments.
[0121] In the above embodiments, the descriptions of each embodiment have their own emphasis. Parts not described in detail in a certain embodiment can be referred to in the relevant descriptions of other embodiments. The technical solutions of this application, in essence, or the parts that contribute to the prior art, or all or part of the technical solutions, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which can be a personal computer, server, or network device, specifically a processor in the computer device) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium may include: a USB flash drive, a portable hard drive, a magnetic disk, an optical disk, a read-only memory (ROM), or a random access memory (RAM), and other media capable of storing program code.
[0122] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.
Claims
1. A system-on-a-chip, characterized in that, The system-on-a-chip includes a reset control unit and at least one intellectual property (IP) unit. Each IP unit includes a reset synchronization circuit and a clock gating circuit. The reset control unit is connected to each IP unit, wherein: The reset control unit is used to generate a reset signal for each IP unit; The reset synchronization circuit is used to synchronize the reset signal according to the clock signal of each IP unit to obtain a synchronized reset signal. The synchronized reset signal is used to reset at least one circuit unit included in each IP unit. The reset control unit is further configured to generate a gating signal for each IP unit based on the synchronized reset signal of each IP unit, wherein the gating signal is used to control the clock gating circuit included in each IP unit to enable or disable the clock signal of each IP unit.
2. The system-on-a-chip according to claim 1, characterized in that, The reset control unit is specifically used for: The reset signal after synchronization of each IP unit causes each IP unit to enter a reset state, and after a first preset time, the gate signal of each IP unit is controlled to a first level to disable the clock signal of each IP unit. The reset signal after synchronization of each IP unit causes each IP unit to exit the reset state, and after a second preset time, the gate signal of each IP unit is controlled to the second level to enable the clock signal of each IP unit.
3. The system-on-a-chip according to claim 1, characterized in that, The clock gating circuit is used to enable or disable the clock signal of each IP unit according to the gating signal of each IP unit.
4. The system-on-a-chip according to any one of claims 1 to 3, characterized in that, The reset control unit includes a reset signal generation circuit and a gate signal generation module, wherein: The reset signal generation circuit is used to generate a reset signal for each IP unit; The gating signal generation module is used to generate a gating signal for each IP unit based on the synchronized reset signal of each IP unit.
5. The system-on-a-chip according to claim 4, characterized in that, The first IP unit in the at least one intellectual property IP unit includes a first circuit unit and at least one second circuit unit. The first IP unit is any one of the at least one intellectual property IP units. The first circuit unit includes a gating module and a reset control module corresponding to each of the at least one second circuit unit, wherein: The reset control module corresponding to each second circuit unit is used to generate a reset signal for each second circuit unit according to the reset signal of the first circuit unit. The reset signal of each second circuit unit is used to reset each second circuit unit. The reset signal of the first circuit unit is the reset signal synchronized with the first IP unit. The gating module corresponding to each second circuit unit is used to generate a gating signal for each second circuit unit based on the reset signal of each second circuit unit; The first IP unit includes a clock gating circuit corresponding to each of the second circuit units, which is used to enable or disable the clock signal of each of the second circuit units according to the gating signal of each of the second circuit units.
6. The system-on-a-chip according to claim 5, characterized in that, The reset synchronization circuit is specifically used to synchronize the reset signal of the first IP unit according to the clock signal of the first circuit unit to obtain the reset signal of the first circuit unit. The reset signal of the first circuit unit is used to reset the first circuit unit. The gate signal generation module is specifically used to generate a gate signal for the first circuit unit based on the reset signal of the first circuit unit. The first IP unit includes a clock gating circuit corresponding to the first circuit unit, which is used to enable or disable the clock signal of the first circuit unit according to the gating signal of the first circuit unit.
7. The system-on-a-chip according to claim 5, characterized in that, The reset control module includes a reset register and logic processing circuitry, wherein: The reset register corresponding to each second circuit unit is used to generate a reset control signal for each second circuit unit; The logic processing circuit corresponding to each second circuit unit is used to process the reset control signal of each second circuit unit and the reset signal of the first circuit unit to generate the reset signal of each second circuit unit.
8. The system-on-a-chip according to claim 5, characterized in that, The gate module corresponding to each second circuit unit is specifically used for: The reset signal of each second circuit unit causes each second circuit unit to enter a reset state, and after a third preset time, the gate signal of each second circuit unit is controlled to a first level to disable the clock signal of each second circuit unit. The reset signal of each second circuit unit causes each second circuit unit to exit the reset state, and after a fourth preset time, the gate signal of each second circuit unit is controlled to the second level to enable the clock signal of each second circuit unit.
9. A circuit control method, characterized in that, The method is applied to a system-on-a-chip (SoC), wherein the SoC includes a reset control unit and at least one intellectual property (IP) unit, each of the at least one IP unit including a reset synchronization circuit and a clock gating circuit, and the reset control unit is connected to each IP unit. The method includes: The first IP unit calls the reset synchronization circuit to synchronize the reset signal generated by the reset control unit to obtain a synchronized reset signal. The first IP unit is any one of the at least one intellectual property IP unit. The first IP unit uses the synchronized reset signal to reset at least one circuit unit included in the first IP unit; The first IP unit controls the clock gating circuit to enable or disable the clock signal of the first IP unit according to the gating signal of the first IP unit. The gating signal is generated by the reset control unit according to the synchronized reset signal.
10. The method according to claim 9, characterized in that, The first IP unit includes a first circuit unit and at least one second circuit unit. The first circuit unit includes a gating module and a reset control module corresponding to each of the at least one second circuit unit. The first IP unit uses the synchronized reset signal to reset at least one circuit unit included in the first IP unit, including: The first IP unit uses the synchronized reset signal as the reset signal of the first circuit unit, and uses the reset signal of the first circuit unit to reset the first circuit unit. The first IP unit calls the reset control module corresponding to each second circuit unit, generates a reset signal for each second circuit unit based on the reset signal of the first circuit unit, and resets each second circuit unit using the reset signal of each second circuit unit. The first IP unit calls the gating module corresponding to each second circuit unit to generate a gating signal for each second circuit unit based on the reset signal of each second circuit unit; The first IP unit controls the clock gating circuit included in the first IP unit, corresponding to each second circuit unit, to enable or disable the clock signal of each second circuit unit according to the gating signal of each second circuit unit.
11. The method according to claim 10, characterized in that, The reset control module includes a reset register and logic processing circuitry. The first IP unit calls the reset control module corresponding to each second circuit unit to generate a reset signal for each second circuit unit based on the reset signal of the first circuit unit, including: The first IP unit calls the reset register corresponding to each second circuit unit to generate a reset control signal for each second circuit unit; The first IP unit calls the logic processing circuit corresponding to each of the second circuit units to process the reset control signal of each of the second circuit units and the reset signal of the first circuit unit to generate the reset signal of each of the second circuit units.
12. The method according to claim 10 or 11, characterized in that, The first IP unit calls the reset synchronization circuit to synchronize the reset signal generated by the reset control unit, obtaining a synchronized reset signal, including: The first IP unit calls the reset synchronization circuit to synchronize the reset signal generated by the reset control unit according to the clock signal of the first circuit unit, so as to obtain the reset signal of the first circuit unit. The first IP unit controls the clock gating circuit corresponding to the first circuit unit, which is included in the first IP unit, to enable or disable the clock signal of the first circuit unit according to the gating signal of the first circuit unit. The gating signal of the first circuit unit is generated by the reset control unit according to the reset signal of the first circuit unit.
13. The method according to claim 10 or 11, characterized in that, The first IP unit calls the gating module corresponding to each of the second circuit units to generate a gating signal for each of the second circuit units based on the reset signal of each second circuit unit, including: The first IP unit causes each second circuit unit to enter a reset state upon receiving a reset signal from the reset signal of each second circuit unit. After a third preset time, the first IP unit calls the gate control module corresponding to each second circuit unit to control the gate control signal of each second circuit unit to a first level, thereby disabling the clock signal of each second circuit unit. The first IP unit causes each second circuit unit to exit the reset state upon receiving a reset signal from the second circuit unit, and after a fourth preset time period, calls the gating module corresponding to each second circuit unit to control the gating signal of each second circuit unit to the second level, so as to enable the clock signal of each second circuit unit.
14. A circuit control method, characterized in that, The method is applied to a system-on-a-chip (SoC), wherein the SoC includes a reset control unit and at least one intellectual property (IP) unit, each of the at least one IP unit including a reset synchronization circuit and a clock gating circuit, and the reset control unit is connected to each IP unit. The method includes: The reset control unit generates a reset signal for each IP unit, so that each IP unit obtains a synchronized reset signal using the reset synchronization circuit. The synchronized reset signal is used to reset at least one circuit unit included in each IP unit. The reset control unit generates a gating signal for each IP unit based on the synchronized reset signal of each IP unit. The gating signal is used to control the clock gating circuit included in each IP unit to enable or disable the clock signal of each IP unit.
15. The method according to claim 14, characterized in that, The reset control unit generates a gating signal for each IP unit based on the synchronized reset signal of each IP unit, including: The reset control unit, upon receiving the reset signal after synchronization of each IP unit, causes each IP unit to enter a reset state. After a first preset time, it controls the gate signal of each IP unit to a first level to disable the clock signal of each IP unit. The reset control unit, upon receiving a reset signal from each IP unit after synchronization, causes each IP unit to exit the reset state. After a second preset time, it controls the gate signal of each IP unit to a second level to enable the clock signal of each IP unit.
16. A circuit control device, characterized in that, The device includes: The processing module is used to call the reset synchronization circuit included in the first IP unit to perform synchronization processing on the reset signal generated by the reset control unit to obtain a synchronized reset signal. The first IP unit is any one of at least one intellectual property IP unit. A reset module is used to reset at least one circuit unit included in the first IP unit using the synchronized reset signal; The control module is used to control the clock gating circuit included in the first IP unit to enable or disable the clock signal of the first IP unit according to the gating signal of the first IP unit. The gating signal is generated by the reset control unit according to the synchronized reset signal.
17. A circuit control device, characterized in that, The device includes: The first generation module is used to generate a reset signal for each IP unit in at least one intellectual property IP unit, so that each IP unit obtains a synchronized reset signal using a reset synchronization circuit, and the synchronized reset signal is used to reset at least one circuit unit included in each IP unit. The second generation module is used to generate a gating signal for each IP unit based on the synchronized reset signal of each IP unit. The gating signal is used to control the clock gating circuit included in each IP unit to enable or disable the clock signal of each IP unit.
18. A computer-readable storage medium, characterized in that, The computer storage medium stores a computer program, the computer program including program instructions, which are executed by a processor to perform the circuit control method as described in any one of claims 9 to 13, or the circuit control method as described in any one of claims 14 to 15.