Control circuit, display device and method for driving a main processor

Abstract

Embodiments of the present disclosure relate to a control circuit, a display apparatus, and a method for driving a main processor. Specifically, a control circuit, a display apparatus, and a method for driving a main processor can be provided, which can reduce power consumption in a transmission / reception circuit connected with an interface by powering off at least one of a source transmission / reception circuit or a sink transmission / reception circuit electrically connected with an auxiliary channel (AUX) during at least a part of a vertical blanking period.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2021-0193481, filed on December 30, 2021, which is incorporated herein by reference for all purposes, as fully set forth herein. Technical Field

[0003] Embodiments of this disclosure relate to control circuitry, display devices, and methods for driving a main processor. Background Technology

[0004] The development of a smart society has led to various needs for displays and the widespread use of various forms of displays, such as liquid crystal displays (LCDs), plasma display panels (PDPs), or organic light-emitting displays (OLEDs).

[0005] The display device may include a display driving circuit for generating and outputting voltages for displaying images, and a timing controller for controlling the operating timing of the display driving circuit.

[0006] The timing controller can be connected to the main processor via a preset interface. The main processor and the timing controller can send or receive commands and data according to the preset interface standard. Summary of the Invention

[0007] Embodiments of this disclosure may provide control circuitry, display devices, and methods for driving a main processor that can reduce power consumption in transmit / receive circuitry connected to an interface.

[0008] Embodiments of this disclosure may provide a control circuit comprising: a main processor including source transmit / receive circuitry; and a timing controller including sink transmit / receive circuitry connected to the main processor via an interface, and generating and outputting image data and control signals, wherein the interface includes a main link and an auxiliary channel, and wherein the main processor de-energizes at least one of the source transmit / receive circuitry or the synchronization transmit / receive circuitry electrically connected to the auxiliary channel during at least a portion of a vertical blank period between different refresh frame cycles.

[0009] Embodiments of this disclosure may provide a display device comprising: a main processor including source transmit / receive circuitry; a timing controller including sink transmit / receive circuitry connected to the main processor via an interface, and generating and outputting image data and control signals; a data drive circuitry controlled by the timing controller for driving timing, and generating and outputting data voltages based on the image data and control signals; a gate drive circuitry controlled by the timing controller, and outputting gate voltages based on control signals; and a display panel having multiple data lines to which data voltages are applied, multiple gate lines to which gate voltages are applied, and multiple sub-pixels electrically connected to the multiple data lines and the multiple gate lines, wherein the interface includes a main link and an auxiliary channel, and wherein the main processor de-energizes at least one of the source transmit / receive circuitry or the synchronous transmit / receive circuitry electrically connected to the auxiliary channel during at least a portion of a vertical blank period between different refresh frame cycles.

[0010] Implementations of this disclosure may provide a method for driving a main processor, the method comprising: the main processor sending pixel packets for generating image data to a timing controller via a main link of an interface; the main processor, including source transmit / receive circuitry electrically connected to an auxiliary channel of the interface, de-energizing the source transmit / receive circuitry after the timing controller receives the pixel packets; the main processor energizing the source transmit / receive circuitry electrically connected to the auxiliary channel; and the main processor sending a link training signal via the main link.

[0011] Embodiments of this disclosure may provide a control circuit including: a main processor including source transmit / receive circuitry; and a timing controller including sink transmit / receive circuitry connected to the main processor via an interface, and generating and outputting image data and control signals, wherein the interface includes a main link and an auxiliary channel, and wherein the main processor de-energizes at least one of the source transmit / receive circuitry and the sink transmit / receive circuitry electrically connected to the main link during at least a portion of a vertical blank period between different refresh frame cycles.

[0012] According to embodiments of this disclosure, control circuitry, display device, and method for driving a main processor can be provided that can reduce power consumption in transmit / receive circuitry connected to an interface. Attached Figure Description

[0013] The above and other objects, features and advantages of this disclosure will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0014] Figure 1 This is a block diagram showing a control circuit and a data drive circuit controlled by the control circuit according to an embodiment of the present disclosure;

[0015] Figure 2 This is a block diagram illustrating the configuration of the main processor according to an embodiment of the present disclosure;

[0016] Figure 3 It shows including Figure 1 A view of the system configuration of the display device for the control circuit;

[0017] Figure 4 This is a view illustrating examples of various refresh frame rates implemented by a display device according to embodiments of the present disclosure;

[0018] Figure 5 This is a view showing the interface between the main processor and the timing controller according to an embodiment of the present disclosure;

[0019] Figure 6 This is a block diagram illustrating the configuration of the phase-locked loop;

[0020] Figure 7 This is a view showing the display timing of a display device according to an embodiment of the present disclosure, and the status of the main link and auxiliary channel according to the display timing;

[0021] Figures 8 to 10 This is a view that exemplarily illustrates the implementation method and operation method of the counter;

[0022] Figure 11 This is a view showing that both the primary link and the secondary channel are disconnected during at least a portion of the vertical blank period; and

[0023] Figure 12 and Figure 13 This is a flowchart illustrating a method for driving a main processor according to an embodiment of the present disclosure. Detailed Implementation

[0024] In the following description of examples or embodiments of the invention, reference will be made to the accompanying drawings, which illustrate specific examples or embodiments that can be implemented, and the same reference numerals and symbols may be used to denote the same or similar parts, even when these parts are shown in different drawings. Furthermore, in the following description of examples or embodiments of the invention, detailed descriptions of well-known functions and parts incorporated herein may be omitted where such descriptions may make the subject matter of some embodiments of the invention quite unclear. Terms such as “comprising,” “having,” “including,” “constituting,” “made of,” and “formed by” as used herein are generally intended to allow for the addition of additional parts, unless these terms are used in conjunction with the term “only.” As used herein, singular forms are intended to include plural forms unless the context clearly indicates otherwise.

[0025] In this document, terms such as “first,” “second,” “A,” “B,” “(A),” or “(B)” may be used to describe elements of the invention. Each of these terms is not intended to define the nature, order, sequence, or number of elements, but is only used to distinguish the corresponding element from other elements.

[0026] When referring to a first element as "connected or coupled to," "in contact with," or "overlapping" with a second element, it should be understood that the first element can not only be "directly connected or coupled to" or "directly contact or overlap" with the second element, but a third element can also be "inserted" between the first and second elements, or the first and second elements can be "connected or coupled," "in contact with," or "overlapping" with each other via a fourth element. Here, the second element can be included in at least one of two or more elements that are "connected or coupled," "in contact with," or "overlapping" with each other.

[0027] When time-related terms such as “after,” “following,” “next,” “before,” etc., are used to describe a process or operation of an element or configuration, or a flow or step in an operation, processing, or manufacturing method, these terms may be used to describe a non-continuous or non-sequential process or operation, unless the terms “directly” or “immediately after” are used together.

[0028] Furthermore, when referring to any size, relative size, etc., it should be assumed that the numerical values ​​or corresponding information of an element or feature (e.g., level, range, etc.) include tolerances or error ranges that may be caused by various factors (e.g., process factors, internal or external influences, noise, etc.), even when no relevant description is specified. In addition, the term "may" fully encompasses all the meanings of the term "able to".

[0029] In the following, various embodiments of the present disclosure are described in detail with reference to the accompanying drawings.

[0030] Figure 1 This is a block diagram showing a control circuit 100 and a display driving circuit 130 controlled by the control circuit 100 according to an embodiment of the present disclosure.

[0031] Reference Figure 1 According to an embodiment of the present disclosure, the control circuit 100 includes a main processor 110 and a timing controller 120 configured to generate and output data voltages for image display.

[0032] The main processor 110 and the timing controller 120 can send and receive converted commands and signals according to preset interface standards.

[0033] The timing controller 120 controls the display driver circuit 130 and allows the display driver circuit 130 to output signals (e.g., data voltage, gate voltage, etc.) for image display to the display panel according to the timing.

[0034] Figure 2 This is a block diagram illustrating the configuration of the main processor 110 according to an embodiment of the present disclosure.

[0035] Reference Figure 2 According to embodiments of the present disclosure, the main processor 110 may include a system memory 210, a central processing unit (CPU) 220, an interrupt controller 230, a transmit / receive circuit 240, a memory controller 250, an image generator 260, and a display controller 270.

[0036] The system memory 210 can store the commands and parameters necessary for the operation of the display driver circuit 130. For example, the CPU 220 can operate using the commands and parameters stored in the system memory 210.

[0037] CPU 220 can control the overall operation of main processor 110. For example, CPU 220 can control the operation of each component, namely system memory 210, interrupt controller 230, transmit / receive circuit 240, memory controller 250, image generator 260, and display controller 270. CPU 220 can request image generator 260 to generate or process images.

[0038] Interrupt controller 230 can control interrupts that occur during the operation of main processor 110. In other words, interrupt controller 230 can receive interrupts from each component, adjust the execution order of each interrupt, and transmit them to CPU 220 to perform the operation corresponding to the corresponding interrupt.

[0039] The transmit / receive circuit 240 can transmit commands, signals, interrupts, and data converted according to various interface standards to / receive commands, signals, interrupts, and data converted according to various interface standards from the timing controller 120. The transmit / receive circuit 240 can provide image data stored in an external memory (not shown) to the display driver circuit 130 (particularly a data driver circuit) via the timing controller 120. In this disclosure, the transmit / receive circuit 240 may simply mean a transmit circuit configured to transmit data, or it may simply mean a receive circuit configured to receive data, or it may also mean a transmit / receive circuit configured to both transmit and receive data.

[0040] The memory controller 250 can control the external memory while sending and receiving data from the external memory connected to the main processor 110. In other words, the memory controller 250 can access the external memory to read, write, and delete image data according to requests from the CPU 220, the image generator 260, or the display controller 270.

[0041] The image generator 260 can generate or process program commands related to graphics processing under the control of the CPU 220. The image generator 260 can be implemented as a graphics engine, a graphics processing unit (GPU), a graphics accelerator, or a 2D processor.

[0042] The display controller 270 can control the operation of the main processor 110 on the aforementioned timing controller 120, or it can control the operation of the timing controller 120 on the main processor 110. For example, the display controller 270 can control the memory controller 250 to output data stored in external memory through the transmit / receive circuit 240. The display controller 270 can control the image generator 260 to output image data generated by the image generator 260 through the transmit / receive circuit 240.

[0043] System bus 280 can be used as a path for data transmission / reception between components by connecting components to main processor 110. System bus 280 may include a small bus for data communication between components.

[0044] The main processor 110 according to embodiments of this disclosure may be a host system or a system-on-a-chip (SoC) device.

[0045] Figure 3 It shows including Figure 1 A view of the system configuration of the control circuit 100 and the display device 300.

[0046] Reference Figure 3 The display device 300 according to embodiments of the present disclosure may include: a main processor 110; a timing controller 120 capable of communicating with the main processor 110; a display driving circuit 130 controlled by the timing controller 120 for timing operation; and a display panel 310, wherein multiple data lines DL and multiple gate lines GL to which voltages output from the display driving circuit 130 are arranged.

[0047] The display driving circuit 130 is a circuit used to drive the display panel 310, and may include a data driving circuit 320 and a gate driving circuit 330.

[0048] The display panel 310 may include a display area AA for displaying images and a non-display area NA for not displaying images. The non-display area NA may be the outer area of ​​the display area AA and may be referred to as a border area. All or part of the non-display area NA may be an area visible from the front surface of the display device 300, or it may be a curved area that is not visible from the front surface of the display device 300.

[0049] The display panel 310 may include a substrate and a plurality of sub-pixels SP disposed on the substrate. The display panel 310 may also include various types of signal lines for driving the plurality of sub-pixels SP.

[0050] The display device 300 according to embodiments of the present disclosure may be a liquid crystal display device or a light-emitting display device in which the display panel 310 itself emits light. When the display device 300 according to embodiments of the present disclosure is a self-emitting display device, each of the plurality of sub-pixels SP may include a light-emitting element.

[0051] For example, the display device 300 according to an embodiment of the present disclosure may be an organic light-emitting diode display in which the light-emitting element is implemented as an organic light-emitting diode (OLED). As another example, the display device 300 according to an embodiment of the present disclosure may be a quantum dot display device in which the light-emitting element is implemented as a quantum dot that is a self-emitting semiconductor crystal.

[0052] For example, various types of signal lines may include multiple data lines DL that transmit data signals (also known as data voltages or image signals) and multiple gate lines GL that transmit gate signals (also known as gate voltages or scan signals).

[0053] The data drive circuit 320 is configured to drive multiple data lines DL and can output data voltage to the multiple data lines DL. The gate drive circuit 330 is configured to drive multiple gate lines GL and can output gate signals to the multiple gate lines GL.

[0054] The timing controller 120 may be a device configured to control the operation of the data drive circuit 320 and the gate drive circuit 330. The timing controller 120 may control the driving timing of multiple data lines DL and the driving timing of multiple gate lines GL.

[0055] The timing controller 120 can supply a data drive control signal DCS to the data drive circuit 320 to control the data drive circuit 320. The timing controller 120 can supply a gate drive control signal GCS to the gate drive circuit 330 to control the gate drive circuit 330.

[0056] The timing controller 120 can receive input image data from the main processor 110 and supply image data DATA to the data driving circuit 320 based on the input image data.

[0057] The timing controller 120 can generate and output one or more synchronization signals to drive the data drive circuit 320 and the gate drive circuit 330 with precise timing.

[0058] For example, timing controller 120 can generate a vertical synchronization signal (also known as a Vsync signal) indicating the start of each frame. Timing controller 120 can generate a horizontal synchronization signal (also known as an Hsync signal) indicating the start of a horizontal line.

[0059] The data drive circuit 320 can supply data voltage to multiple data lines DL according to the drive timing controlled by the timing controller 120.

[0060] The data drive circuit 320 can receive digital image data DATA from the timing controller 120, and can convert the received image data DATA into analog data voltage and output it to multiple data lines DL.

[0061] The gate drive circuit 330 can supply gate signals to multiple gate lines GL according to the timing control of the timing controller 120. The gate drive circuit 330 can receive a first gate voltage corresponding to the on-level voltage and a second gate voltage corresponding to the off-level voltage, as well as various gate drive control signals GCS, generate gate signals, and supply the generated gate signals to the multiple gate lines GL.

[0062] For example, the data drive circuit 320 can be connected to the display panel 310 via tape auto-packing (TAB), or to the bonding pads of the display panel 310 via chip on glass (COG) or chip on panel (COP), or it can be implemented and connected to the display panel 310 via chip on film (COF).

[0063] The gate driving circuit 330 can be connected to the display panel 310 via Tape-on-Board (TAB) method, or to the bonding pads of the self-emitting display panel 310 via COG or Chip-on-Plate (COP) method, or it can be connected to the display panel 310 via COF method. The gate driving circuit 330 can be formed in the non-display area NA of the display panel 310 as a Gate-in-Panel (GIP) type.

[0064] Meanwhile, at least one of the data driving circuit 320 and the gate driving circuit 330 can be disposed in the display area AA of the display panel 310. For example, at least one of the data driving circuit 320 and the gate driving circuit 330 can be disposed so that it does not overlap with the sub-pixel SP or overlaps with all or some of the sub-pixels SP.

[0065] The data driving circuit 320 can be connected to one side (e.g., the top or bottom) of the display panel 310. Depending on the driving scheme or design, the data driving circuit 320 can be connected to both sides (e.g., the top and bottom) of the self-emitting display panel 310, or two or more of the four sides of the self-emitting display panel 310.

[0066] The gate drive circuit 330 can be connected to one side (e.g., the left or right side) of the display panel 310. Depending on the driving scheme or panel design, the gate drive circuit 330 can be connected to both sides (e.g., the left and right sides) of the display panel 310, or two or more of the four sides of the display panel 310.

[0067] The timing controller 120 can be implemented as a separate component from the data drive circuit 320, or the timing controller 120 and the data drive circuit 320 can be integrated into an integrated circuit (IC).

[0068] The timing controller 120 may be a timing controller used in typical display technologies, or it may be a control device or circuit in a control device that can perform other control functions as well as the functions of the timing controller. The timing controller 120 may be implemented as various circuits or electronic components, such as integrated circuits (ICs), field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), or processors.

[0069] The timing controller 120 can be electrically connected to the data drive circuit 320 and the gate drive circuit 330 via a printed circuit board (PCB) or a flexible printed circuit board (FPCB).

[0070] The timing controller 120 can send signals to / receive signals from the data drive circuit 320 according to one or more predetermined interfaces. Interfaces may include, for example, a Low Voltage Differential Signaling (LVDS) interface, an EPI interface, and a Serial Peripheral Interface (SPI).

[0071] To provide touch sensing and image display functions, the display device 300 according to embodiments of the present disclosure may include a touch sensor and a touch sensing circuit that senses the touch sensor to detect whether a touch occurs by a touch object such as a finger or a pen, or the location of the touch.

[0072] The touch sensing circuit may include: a touch driving circuit 360 that drives and senses the touch sensor and generates and outputs touch sensing data; and a touch controller 370 that can use the touch sensing data to detect the occurrence of a touch or the location of the touch.

[0073] A touch sensor may include multiple touch electrodes. A touch sensor may also include multiple touch lines for electrically connecting the multiple touch electrodes and the touch driving circuitry 360°.

[0074] A touch sensor in the form of a touch panel can be located outside the display panel 310, or it can be located inside the display panel 310. When the touch panel in the form of a panel is located outside the display panel 310, the touch panel is referred to as an external type. When the touch sensor is external, the touch panel and the display panel 310 can be manufactured separately, or they can be combined during the assembly process. An external type touch panel may include a touch panel substrate and multiple touch electrodes on the touch panel substrate.

[0075] When the touch sensor is present inside the display panel 310, the touch sensor, as well as signal lines and electrodes related to display driving, can be formed on the substrate during the manufacturing process of the display panel 310.

[0076] The touch driving circuit 360 can supply a touch driving signal to at least one of the plurality of touch electrodes and can sense at least one of the plurality of touch electrodes to generate touch sensing data.

[0077] Touch sensing circuits can perform touch sensing in self-capacitance sensing schemes or mutual capacitance sensing schemes.

[0078] The touch driving circuit 360 and touch controller 370 included in the touch sensing circuit can be implemented as separate devices or as a single device. The touch driving circuit 360 and data driving circuit 320 can be implemented as separate devices or as a single device.

[0079] The display device 300 may also include a power supply circuit for supplying various types of power to the data driving circuit 320 and / or the touch sensing circuit.

[0080] The display device 300 according to the embodiments of this disclosure may be a mobile terminal, such as a smartphone or tablet computer, or a monitor or television (TV) of various sizes, but is not limited thereto, and may be a display device of various types and sizes capable of displaying information or images.

[0081] Figure 4 This is a view illustrating examples of various refresh frame rates implemented by a display device according to embodiments of the present disclosure.

[0082] Reference Figure 4 The display device according to embodiments of this disclosure can achieve various refresh frame rates by changing the ratio of refresh frames to skip frames based on the vertical synchronization signal. For example, refresh frames and skip frames can be initiated based on the rising edge or falling edge of the vertical synchronization signal.

[0083] A refresh frame can refer to the frame period during which the data driving circuit 320 outputs data voltages at various levels based on the brightness of the sub-pixels. During the refresh frame period, data voltages at various levels can be applied to each sub-pixel according to the brightness of the image displayed by the corresponding sub-pixel.

[0084] The capacitors included in the sub-pixel are charged with the data voltage applied to the sub-pixel during the refresh frame cycle. Therefore, the corresponding sub-pixel can emit light during one frame cycle.

[0085] The skip frame is distinguished from the refresh frame when data voltages of various levels are applied to each sub-pixel. During the skip frame period, a preset level of data voltage can be applied to multiple sub-pixels.

[0086] Therefore, when displaying a static image in the display area for an extended period of time, the image can be displayed at a low refresh rate. This reduces power consumption in the data drive circuitry.

[0087] Reference Figure 4 If all frames are refreshed based on a vertical sync signal with a frequency of 120Hz, then the refresh rate is 120Hz. In other words, when the refresh rate equals the frequency of the vertical sync signal, there may be no skipped frames. A higher refresh rate may be desirable when displaying video content.

[0088] Therefore, the time interval between refresh frames is likely to be approximately 8.3ms (1 / 120 of a second).

[0089] After a refresh frame ends, one or more skip frames can be initiated.

[0090] Reference Figure 4 Based on a vertical synchronization signal with a frequency of 120Hz, four skip frames are initiated consecutively after one refresh frame is completed. Therefore, the refresh frame rate is 24Hz. The time interval between refresh frames is approximately 41.7ms (1 / 24 second).

[0091] The frame refresh rate can be controlled by the aforementioned main processor 110. For example, refer to... Figure 1 Based on the refresh frame rate set by the main processor 110, the main processor 110 sends pixel packets for generating image data to the timing controller 120 every frame or intermittently, enabling various refresh frame rates to be achieved.

[0092] Figure 5 This is a view showing the interface 510 between the main processor 110 and the timing controller 120 according to an embodiment of the present disclosure.

[0093] Reference Figure 5 Interface 510 may be a display port that includes a main link (also known as MAIN or MAIN LINK), an auxiliary channel AUX, and a hot-plug detector (HPD) signal line (hereinafter referred to as "HPD").

[0094] The main link MAIN of the display port is a channel used to send image data from the main processor 110 to the timing controller 120. The main link MAIN is a channel with high bandwidth and short call time, and it is a simplex channel used to send data from the main processor 110 to the timing controller 120.

[0095] The AUX auxiliary channel of the display port is a half-duplex bidirectional channel used for link management and device control.

[0096] HPD is used to indicate the connection status between the main processor 110 and the timing controller 120.

[0097] The transmitted data can be converted into 8B / 10B code or Manchester code, and can be transmitted from the source transmit / receive circuit 520 and the sink transmit / receive circuit 530 to the interface 510.

[0098] The source transmit / receive circuit 520 and the sink transmit / receive circuit 530 may include one or more transmitters for transmitting data and one or more receivers for receiving data. The source transmit / receive circuit 520 and the sink transmit / receive circuit 530 constitute the physical layer.

[0099] Reference Figure 5 The main processor 110 and the timing controller 120 include timing generators 540 and 550, respectively.

[0100] The timing generator 540 included in the main processor 110 can be a device that generates a timing signal for synchronizing signals received from the timing controller 120. The timing generator 550 included in the timing controller 120 can be a device that generates a timing signal for synchronizing signals received from the main processor 110.

[0101] The timing generators 540 and 550 can be used as clock generators to generate clock signals.

[0102] The main processor 110 and the timing controller 120 can be synchronized with each other via timing generators 540 and 550.

[0103] Figure 6 This is a block diagram showing the configuration of the phase-locked loop (PLL) 600.

[0104] Figure 5 The aforementioned timing generators 540 and 550 may include a phase-locked loop 600.

[0105] The phase-locked loop 600 may include a phase frequency detector 601, a charge pump 602, a low-pass filter 603, a voltage-controlled oscillator (VCO) 604, and a partitioning circuit 605.

[0106] Reference Figure 6 The phase frequency detector 601 receives a reference frequency FreqRef input to input terminal 606 of the phase-locked loop 600 and a feedback signal input from the divider circuit 605. The phase frequency detector 601 generates a pulse based on the phase difference between the two input signals and outputs the pulse. The pulse output from the phase frequency detector 601 is input to the charge pump 602.

[0107] The output of charge pump 602 is connected to the input of voltage-controlled oscillator 604 via low-pass filter 603. The output terminal 607 of voltage-controlled oscillator 604 is connected to the input terminal of divider circuit 605.

[0108] The phase frequency detector 601 can be configured to compare the output of the dividing circuit 605 with the reference frequency Freq Ref and generate a pulse proportional to the phase difference between the comparison signals.

[0109] For example, the phase frequency detector 601 can be implemented by adding the outputs of two analog multipliers. Alternatively, the phase frequency detector 601 can be implemented by a combination of XOR gates, flip-flops, or digital logic gates.

[0110] The charge pump 602 can be configured to charge and discharge a capacitor based on the output of the phase frequency detector 601. The phase frequency detector 601 can provide two output signals (referred to as "up" and "down"). Each of the two output signals can be a signal for charging the capacitor or a signal for discharging the capacitor. Therefore, the voltage across the capacitor is proportional to the phase difference between the pulse input to the input terminal 606 of the phase-locked loop 600 and the pulse input from the dividing circuit 605.

[0111] The charge pump 602 can supply current to the capacitor via, for example, a p-channel MOSFET, and can discharge current from the capacitor via an n-channel MOSFET.

[0112] The phase-locked loop 600 may also include a low-pass filter 603 configured to remove high-frequency harmonic components output from the phase frequency detector 601. The low-pass filter 603 can be implemented as a passive filter configured by connecting a resistor and a capacitor in series. The low-pass filter 603 can also be implemented as an active filter. In this case, the low-pass filter 603 may include an amplifier, such as an operational amplifier (also called an "op-amp"), and a feedback path including resistors and capacitors.

[0113] The cutoff frequency of the low-pass filter 603 can be preset to determine the "capture range" of the phase-locked loop 600 operation.

[0114] The voltage-controlled oscillator 604 can be configured to output a frequency that depends on the output of the charge pump 602, which is filtered in the low-pass filter 603.

[0115] The voltage-controlled oscillator 604 can be implemented as a harmonic oscillator or a relaxation oscillator. The variable current used to charge and discharge the capacitor of the charge pump 602 can alter the frequency of the voltage-controlled oscillator 604. Therefore, the output of the voltage-controlled oscillator 604 depends on the output of the charge pump 602.

[0116] Reference Figure 6 The dividing circuit 605 can be configured to divide the signal output from the output terminal 607 of the voltage-controlled oscillator 604 into preset values. Accordingly, the frequency divided into preset values ​​can be input to the phase-frequency detector 601. Therefore, a frequency different from the frequency of the signal input to the input terminal 606 can be output to the output terminal 607.

[0117] A signal of a preset frequency is input to input terminal 606. For example, a crystal oscillator, RC oscillator, or LC oscillator can be used as a component for outputting a signal of the preset frequency.

[0118] The preset frequency needs to be within the frequency range of the phase-locked loop 600 operation. The operating range of the phase-locked loop 600 can be referred to as the "capture range".

[0119] When the preset frequency is higher than the frequency of the signal output from the dividing circuit 605, the phase frequency detector 601 can send a signal to the charge pump 602 to charge the capacitor included in the charge pump 602. When the preset frequency is lower than the frequency of the signal output from the dividing circuit 605, the phase frequency detector 601 can send a signal to the charge pump 602 to remove the charge from the capacitor included in the charge pump 602.

[0120] Alternatively, when the preset frequency is higher than the frequency of the signal output from the dividing circuit 605, the phase frequency detector 601 can send a signal to the charge pump 602 to remove charge from the capacitor included in the charge pump 602. When the preset frequency is lower than the frequency of the signal output from the dividing circuit 605, the phase frequency detector 601 can send a signal to the charge pump 602 to charge the capacitor included in the charge pump 602.

[0121] The signal output from charge pump 602 is filtered by low-pass filter 603, and the filtered signal is input to voltage-controlled oscillator 604. Voltage-controlled oscillator 604 can generate and output a signal with a frequency corresponding to the filtered signal.

[0122] When the frequency and phase of the signal input to the input terminal 606 of the phase-locked loop 600 are the same as the frequency and phase of the signal output from the output terminal 607 of the phase-locked loop 600, the phase-locked loop 600 is indicated as "locked".

[0123] When the frequency or phase of the signal input to the input terminal 606 of the phase-locked loop 600 is different from the frequency or phase of the signal output from the output terminal 607 of the phase-locked loop 600 (i.e., when the phase-locked loop 600 is not locked), the frequency or phase of the signal output from the output terminal 607 can be compensated through the above feedback process.

[0124] Figure 7 This is a view showing the display timing of a display device according to an embodiment of the present disclosure, and the status of the main link (MAIN LINK) and the auxiliary channel (AUX) according to the display timing.

[0125] Reference Figure 7 The display timing of the display device according to the embodiments of the present disclosure may include an active period and a vertical blank period.

[0126] Figure 7 The effective time period ACTIVE corresponds to the time period when the main processor sends the pixel packet PXL PACKET for image display to the timing controller via the main link MAIN LINK.

[0127] In addition to the image data used to actually display the image, the PXL PACKET may also include information such as the number of pixels (or subpixels) arranged in horizontal rows, the total number of rows in an image frame, the width of the horizontal sync signal, and the width of the vertical sync signal.

[0128] in other words, Figure 7The effective time period ACTIVE can correspond to the time period during which the data voltage used for image display is applied to multiple data lines in the refresh frame cycle described above (the time period between t0 and t1 and the time period after t7).

[0129] Reference Figure 7 The display timing can also include dummy image periods before and after the valid ACTIVE period (DUMMY VIDEO). Figure 7 (Time periods t1 to t2 and t6 to t7).

[0130] The DUMMY VIDEO period is not the period when image data for image display is input to the display area. For example, when dummy gate lines that are not electrically connected to subpixels are further arranged in the non-display area of ​​the display panel, gate signals can be output to the dummy gate lines during the DUMMY VIDEO period.

[0131] Therefore, it is possible to indirectly identify whether the gate signal is input to the gate line in the display area of ​​the display panel at the appropriate timing by detecting the output timing of the gate signal input to the dummy gate line.

[0132] During the dummy image period (DUMMY VIDEO), the main link (MAIN LINK) can transmit either vertical front dummy data (VFD) or vertical back dummy data (VBD).

[0133] In some cases, during a portion of the vertical blank period (VBLANK), the gate signal can be input to a dummy gate line. In this case, the dummy image period (DUMMY VIDEO) can be omitted.

[0134] Therefore, the time period when the main link transmits vertical front dummy data (VFD) or vertical back dummy data (VBD) signals can overlap with the vertical blank time period (VBLANK).

[0135] Reference Figure 7 In periods that do not overlap with the active period, there exists a vertical blank period (VBLANK). The vertical blank period (VBLANK) can include the skip frame period of the refresh frame and the vertical blank period itself. Therefore, the length of the vertical blank period (VBLANK) can exceed the length of one frame period (e.g., approximately 8.3ms based on 120Hz).

[0136] When the period of transmitting the vertical leading edge (VFD) data on the main link ends (the period from t1 to t2), the main link enters the period of transmitting the vertical leading edge (VFP) signal (the period from t2 to t3). When the period of transmitting the vertical trailing edge (VBP) signal on the main link ends (the period from t5 to t6), the main link enters the period of transmitting the vertical trailing edge (VBD) data (the period from t6 to t7).

[0137] During the period when the main link transmits the vertical leading edge (VFP) signal (time period t2 to t3), or during the period when the main link transmits the vertical trailing edge (VBP) signal (time period t5 to t6), the main processor can send the pixel packet (PXLPACKET) and other data to the timing controller via the main link.

[0138] For example, the main processor can send timing data for performing touch sensing functions to the timing controller via the main link. The timing controller can receive the timing data for performing touch sensing functions, generate a touch synchronization signal (e.g., a Tsync signal) and output it to the touch controller described above.

[0139] Alternatively, the main processor can send data for adjusting screen brightness to the timing controller via the main link. Therefore, even without receiving new image data, the timing controller can adjust the brightness of sub-pixels based on settings derived from the received data.

[0140] Reference Figure 7 During the period between the time when the transmission of the vertical leading edge (VFP) signal via the main link ends (corresponding to t3) and the time when the transmission of the vertical trailing edge (VBP) signal is initiated (corresponding to t5) (corresponding to the period t3 to t5), the transmitting / receiving circuits (e.g., source transmitting / receiving circuits and / or sink transmitting / receiving circuits) connected to the main link can be de-energized.

[0141] Reference Figure 5 and Figure 7 Power consumption can be reduced by de-energizing the transmit / receive circuits 520 and 530 connected to the main link (MAIN LINK) during at least a portion of the corresponding time period (time period t3 to t5).

[0142] From the perspective of the main link, the power-off state of the source transmit / receive circuit 520 and / or the sink transmit / receive circuit 530 connected to the main link can be defined as the link OFF state. The link OFF state is also referred to as the "sleep" state.

[0143] Conversely, from the perspective of the main link, the power-on state of the source transmit / receive circuit 520 and the sink transmit / receive circuit 530 connected to the main link can be defined as the "link connected" state.

[0144] When the main processor sends the valid synchronization signal 710 to the timing controller through the auxiliary channel AUX, the disconnection state of the main link MAIN LINK can be terminated.

[0145] Therefore, although the main link (MAIN LINK) is in a disconnected state, the source transmit / receive circuit 520 and the sink transmit / receive circuit 530 connected to the auxiliary channel (AUX) can be in a powered-on state. Thus, although the main link (MAIN LINK) is in a "disconnected" state, the auxiliary channel (AUX) can be in a "connected" state.

[0146] Reference Figure 7 At time t4, the effective synchronization signal 710 is sent from the main processor to the timing controller through the auxiliary channel AUX, and the link disconnection state of the main link MAIN LINK is terminated.

[0147] If the main link (MAIN LINK) is disconnected, then the link training signal (LINK TRAINING) will be initiated via the main link (MAIN LINK).

[0148] The LINK TRAINING signal can include clock recovery parameters. The timing controller can receive the clock recovery parameters and recover the clock that caused the error through the phase-locked loop 600 described above (see reference). Figure 6 ).

[0149] The LINK TRAINING signal can include one or more symbol-locked patterns. After the clock recovery parameters have been transmitted, the symbol-locked patterns can be sent via the main link. The timing controller can receive the symbol-locked patterns and synchronize with the main processor.

[0150] Therefore, when the main processor finishes sending the LINK TRAINING signal, the main processor and the timing controller synchronize at time (time t5).

[0151] After the main processor finishes sending the LINK TRAINING signal, the main link (MAIN LINK) can transmit the vertical trailing edge signal (VBP) and the vertical trailing dummy data (VBD).

[0152] Reference Figure 7 During the period when the main link (MAIN LINK) is in the "link disconnected" state, the auxiliary channel (AUX) is in the "link connected" state. Since the main processor should transmit a valid synchronization signal 710 through the auxiliary channel (AUX) to end the main link's disconnected state, it may be difficult to keep the auxiliary channel (AUX) in the disconnected state.

[0153] According to embodiments of this disclosure, both the main link (MAIN LINK) and the auxiliary channel (AUX) can be switched to a link disconnect state based on the number of pulses of the clock signal CLK.

[0154] Reference Figure 7 Based on the number of pulses of the clock signal CLK corresponding to the time period (t3 to t4) when the main link (MAIN LINK) is in a link-disconnected state, both the main link (MAIN LINK) and the auxiliary channel (AUX) can remain in a link-disconnected state. The clock signal CLK can be a signal output from the timing generators 540 and 550 mentioned above (see...). Figure 5 ).

[0155] The main processor and / or timing controller according to embodiments of this disclosure may further include a counter (COUNTER) for counting the number of pulses of the clock signal CLK.

[0156] The counter (COUNTER) receives the clock signal CLK and detects the rising or falling edge of the CLK pulses to count the number of pulses. The number of clock signal CLK pulses counted by the counter (COUNTER) during a predetermined time period corresponds to the length of the corresponding time period.

[0157] Therefore, the number of pulses calculated by the counter can be used to replace the length of the main link disconnection period.

[0158] The counter included in the main processor can output the calculated number of pulses to the main processor. The counter included in the timing controller can output the calculated number of pulses to the timing controller.

[0159] The following is for reference Figure 5 and Figure 7A method is described for adjusting the time period when the main processor 110 de-energizes the transmit / receive circuits 520 and 530 connected to the main link MAIN LINK and the transmit / receive circuits 520 and 530 connected to the auxiliary channel AUX.

[0160] According to an embodiment of the present invention, the main processor 110 may include a memory (not shown). The value of the length of the vertical blank period VBLAND according to the refresh frame rate may be pre-stored in the memory.

[0161] The memory storing the length of the vertical blank period BBLAND can be memory included in the main processor 110 or external memory connected to the main processor 110. When the memory is included in the main processor 110, the display controller 270 may include the memory.

[0162] Based on the refresh frame rate information of the image data transmitted via the main link, the main processor 110 de-energizes the transmit / receive circuit 520 connected to the main link at time t3.

[0163] Therefore, the source transmit / receive circuit 520 connected to the main link (MAIN LINK) can be powered off.

[0164] The main processor 110 can power off the source transmit / receive circuit 520 connected to the auxiliary channel AUX at time t3.

[0165] The source transmit / receive circuit 520 and the sink transmit / receive circuit 530 connected to the auxiliary channel AUX can be designed to be connected to the same power supply. Since the source transmit / receive circuit 520 and the sink transmit / receive circuit 530 connected to the auxiliary channel AUX are connected to the same power supply, they can be powered off simultaneously. Therefore, the power consumption reduction effect can be further enhanced.

[0166] Therefore, at time t3, both the main link (MAIN LINK) and the auxiliary channel (AUX) can be switched to the "link disconnected" state.

[0167] The counter COUNTER counts the number of pulses starting from time t3 based on the clock signal CLK and outputs the count result.

[0168] The main processor 110 compares the output value of the counter COUNTER with the pre-stored length of the vertical blank period BVBLANK. When the output value of the counter COUNTER equals the pre-stored length of the vertical blank period BVBLANK, the main processor 110 powers on the source transmit / receive circuit 520 connected to the main link MAIN LINK, and also powers on the source transmit / receive circuit 520 and the sink transmit / receive circuit 530 connected to the auxiliary channel AUX. In other words, based on the value output by the counter COUNTER at time t4, the main processor 110 can switch the main link MAIN LINK and the auxiliary channel AUX from a "link disconnected" state to a "link connected" state.

[0169] If both the main link (MAIN LINK) and the auxiliary channel (AUX) switch from a "link disconnected" state to a "link connected" state, the main processor 110 sends a link training signal (LINK TRAINING) to the timing controller 120 via the main link (MAIN LINK). The timing controller 120 can receive the link training signal (LINK TRAINING) and execute a process for synchronization with the main processor 110.

[0170] The main processor 110 can initialize the output value of the counter COUNTER after time t4.

[0171] According to an embodiment of the present invention, the main processor 110 may include a memory (not shown), and the value of the length of the vertical blank period VBLAND according to the refresh frame rate may not be pre-stored in the memory. In this case, the value stored in the memory can be updated based on the value output from the counter COUNTER.

[0172] For example, during the first vertical blank period VBLANK, where the refresh frame rate is not maintained but changed, the main link (MAIN LINK) can be in a "link disconnected" state, and the auxiliary channel (AUX) can remain in a "link connected" state while the main link (MAIN LINK) is in a "link disconnected" state.

[0173] The counter COUNTER counts the number of pulses of the clock signal CLK starting from time t3. When the main processor 110 sends the valid synchronization signal 710 to the auxiliary channel AUX (i.e., the period from t3 to t4), the counter COUNTER counts the number of pulses of the clock signal CLK from time t3 to time t4.

[0174] The counter COUNTER can output the number of clock signal CLK pulses counted during the time period from t3 to t4, and the main processor 110 can store the output value of the counter COUNTER in memory.

[0175] During the vertical blank period VBLANK, which maintains the refresh frame rate, both the main link (MAIN LINK) and the auxiliary channel (AUX) can be in a "link disconnected" state.

[0176] The main processor 110 can receive the value output from the counter COUNTER starting from time t3. The main processor 110 can compare the value stored in memory with the value output from the counter COUNTER. When the two compared values ​​become equal, the main processor 110 can switch the status of the main link MAIN LINK and the auxiliary channel AUX from the "link disconnected" state to the "link connected" state.

[0177] Therefore, both the main link (MAIN LINK) and the auxiliary channel (AUX) can be in a "link disconnected" state for at least a portion of the vertical blank period (VBLANK). This reduces power consumption.

[0178] Reference Figure 7 During the period before time t3 and after time t4, the counter COUNTER may or may not count the number of pulses of the clock signal CLK (it doesn't matter).

[0179] Figures 8 to 10 This is an exemplary view showing an implementation method and operation method of the counter 800.

[0180] Reference Figure 8 Counter 800 can be configured to receive clock signal CLK and count the number of pulses of the input signal. Figure 8 The counter 800 is only used for implementation Figure 7 Examples of counters (COUNTER) are provided, but this is not an exception.

[0181] Reference Figure 8 The counter 800 may include two or more flip-flops 810, 820, 830 and 840. For example, the counter 800 may include a first flip-flop 810, a second flip-flop 820, a third flip-flop 830 and a fourth flip-flop 840.

[0182] The clock signal CLK is input to the input terminal of the first flip-flop 810. The output terminal of the first flip-flop 810 is connected to the input terminal of the second flip-flop 820. The output terminal of the second flip-flop 820 is connected to the input terminal of the third flip-flop 830. The output terminal of the third flip-flop 830 is connected to the input terminal of the fourth flip-flop 840.

[0183] The output value Q0 of the first flip-flop 810 is input to the input terminal of the second flip-flop 820. The output value Q1 of the second flip-flop 820 is input to the input terminal of the third flip-flop 830. The output value Q2 of the third flip-flop 830 is input to the input terminal of the fourth flip-flop 840. The output value of the fourth flip-flop 840 is Q3.

[0184] Each of the first flip-flops 810 through the fourth flip-flop 840 detects the rising or falling edge of a pulse. When the rising or falling edge of the pulse is detected, the phase of the output value is changed. Each of the first flip-flops 810 through the fourth flip-flop 840 can be implemented as a conventional JK flip-flop.

[0185] Figure 9 It shows Figure 8 A diagram illustrating the principle of how the counter 800 counts the number of pulses of the clock signal CLK.

[0186] Reference Figure 8 and Figure 9 The first flip-flop 810 through the fourth flip-flop 840 can detect the falling edge of the input pulse. For example, when the logic value of the clock signal CLK input to the first flip-flop 810 changes from 1 to 0, the logic value of the output value Q0 of the first flip-flop 810 changes. Therefore, the value of Q0 changes from 0 to 1, or from 1 to 0.

[0187] Therefore, the frequency of the output signal of each of the first flip-flops 810 to the fourth flip-flop 840 is half the frequency of the input signal.

[0188] Therefore, the output values ​​Q0 of the first flip-flop 810, Q1 of the second flip-flop 820, Q2 of the third flip-flop 830, and Q3 of the fourth flip-flop 840 can be used to represent the number of pulses of the clock signal CLK as a binary number.

[0189] Therefore, the counter 800, which includes N flip-flops, can count the number of pulses of the clock signal CLK up to 2^N.

[0190] Reference Figure 9 If the values ​​of Q0, Q1, Q2, and Q3 are 0, 0, 0, and 0 respectively, the number of pulses is counted as 0. If the values ​​of Q0, Q1, Q2, and Q3 are 1, 0, 0, and 0 respectively, the number of pulses is counted as 1. If the values ​​of Q0, Q1, Q2, and Q3 are 1, 1, 1, and 1 respectively, the number of pulses is counted as 15.

[0191] Therefore, the first flip-flop 810 to the fourth flip-flop 840 can be used to configure a counter 800 capable of counting the number of 16 pulses.

[0192] Figure 10 yes Figure 8 The truth table for counter 800.

[0193] Reference Figure 10 Q0 corresponds to the first digit of the binary number, Q1 corresponds to the second digit of the binary number, Q2 corresponds to the third digit of the binary number, and Q3 corresponds to the fourth digit of the binary number.

[0194] When the number of counting pulses increases by 1, the value of Q0 increases by 1. After the values ​​of Q0, Q1, Q2, and Q3 have all become 1, if the value of Q0 increases by 1, then Q0, Q1, Q2, and Q3 all return to 0.

[0195] Therefore, the logic values ​​of Q0, Q1, Q2, and Q3 can be used to detect up to 16 clock signal pulses during a predetermined time period.

[0196] Figures 8 to 10 Only the implementation is shown. Figure 7 This is an example of a counter (COUNTER), but not limited to it. Considering, for example, the length of the link OFF period between the main link and auxiliary channels, and the frequency of the clock signal CLK used as a reference, design changes can be made such that the maximum number of pulses the counter can count is altered (e.g., it can be changed by...). Figure 8 The maximum number of pulses detected by the counter 800 shown is 16.

[0197] Figure 11 This is a view showing that both the main link (MAIN LINK) and the auxiliary channel (AUX) are disconnected during at least a portion of the vertical blank period (VBLANK).

[0198] Reference Figure 11 The main link (MAIN LINK) can be disconnected during time period t3 to t4. The auxiliary channel (AUX) can also be disconnected during time period t3 to t4. In some cases, the auxiliary channel (AUX) can be disconnected for at least a portion of time period t3 to t4, and can be connected for the remaining portion of time period.

[0199] Reference Figure 11 At the time when the LINK TRAINING signal is sent to the MAIN LINK, a preset constant voltage level can be applied to the AUX channel. In other words, the effective synchronization signal 710 (refer to...) Figure 7The voltage level can be applied to the auxiliary channel AUX instead of the auxiliary channel AUX. Although the effective synchronization signal 710 is not transmitted through the auxiliary channel AUX, the link training signal LINK TRAINING can be transmitted through the main link MAIN LINK.

[0200] The length of the time period (the length of time period t3 to t4) when the main link and the auxiliary channel AUX are in a link disconnected state can be replaced by the number of pulses of the CLK signal.

[0201] The above counter COUNTER (refer to) Figure 7 It can count the number of pulses of the clock signal CLK starting from time t3.

[0202] The main processor adjusts the length of the time period when the main link (MAIN LINK) and auxiliary channel (AUX) are disconnected based on the refresh frame rate. The main processor can also adjust the time period length based on the number of pulses calculated by the counter (COUNTER).

[0203] The clock signal CLK that the counter COUNTER uses to count the number of its pulses can, for example, be a signal with the same frequency as the horizontal synchronization signal (also known as the Hsync signal) generated and output by the timing controller.

[0204] Therefore, the main processor according to the embodiments of this disclosure can control the transmit / receive circuit 240 (see reference). Figure 2 The time period when both the main link (MAIN LINK) and the auxiliary channel (AUX) are disconnected.

[0205] Figure 12 This is a flowchart illustrating a method 1200 for driving a main processor according to an embodiment of the present disclosure.

[0206] Reference Figure 12 The flowchart begins (1210). The beginning of the flowchart can correspond to the step in which the main processor sends pixel packets used to generate image data to the timing controller via the main link.

[0207] If the display enters a vertical blank period (VBLANK) at a specific time, the main processor can send signals (1220) via the main link to generate, for example, touch signals. The signals sent via the main link during the vertical blank period (VBLANK) can be signals other than image data.

[0208] The main processor can power off the transmit / receive circuits (e.g., the source transmit / receive circuits), causing the main link MAINLINK and the auxiliary channel AUX to be switched to a link-disconnected state during the vertical blank period VBLAND (1230).

[0209] The main processor counts the number of clock signal pulses (1240) after the main link (MAIN LINK) and auxiliary channel (AUX) are switched to the link disconnect state. The counter included in the main processor can count the number of clock signal pulses.

[0210] If the number of clock signal pulses calculated by the counter is equal to the number of clock signal pulses corresponding to the preset length of the link disconnection period, the main processor will power on the transmit / receive circuits connected to the main link MAIN LINK and the auxiliary channel AUX (1250). Therefore, the main link MAIN LINK and the auxiliary channel AUX are switched to the link-on state.

[0211] The main processor sends the link training signal (LINK TRAINING) to the timing controller (1260) via the main link (MAIN LINK). The timing controller synchronizes with the main processor based on the received link training signal.

[0212] During the active period, the main processor sends pixel packets for image display to the timing controller (1270) via MAIN LINK.

[0213] Then, the end of the flowchart (1280) is defined.

[0214] Therefore, in the method for driving the main processor according to the embodiments of this disclosure, the training signal is sent via MAIN LINK even when the valid synchronization signal indicating the start of the valid time period is not sent via the auxiliary channel.

[0215] Therefore, when the main link (MAIN LINK) is disconnected, the auxiliary channel (AUX) may also be disconnected. In other words, power consumption can be reduced by powering off the transmit / receive circuitry connected to the auxiliary channel (AUX).

[0216] Figure 13 This is a flowchart illustrating a method 1300 for driving a main processor according to an embodiment of the present disclosure.

[0217] Reference Figure 13 The flowchart begins (1310). The beginning of the flowchart can correspond to the step in which the main processor sends pixel packets used to generate image data to the timing controller via the main link.

[0218] If the display enters a vertical blank period (VBLANK), the main processor can send a timing signal (1315) via the main link (MAIN LINK) to generate, for example, a touch signal.

[0219] During the period when the display timing is a vertical blank period (VBLANK), the main processor can power off the transmit / receive circuits (e.g., source transmit / receive circuits) connected to the main link (MAIN LINK) (1320). Therefore, the main link (MAIN LINK) can be in a link disconnected state.

[0220] After powering down the transmit / receive circuitry connected to the main link, the main processor counts the number of pulses of the clock signal CLK (1325). A counter included in the main processor can count the number of pulses of the clock signal.

[0221] The main processor sends the active synchronization signal ACTIVE SYNC, indicating the start of the active period, to the timing controller (1330) via the auxiliary channel AUX. The main processor stores the number of clock signal pulses counted by a counter in its memory up to the time when the active synchronization signal ACTIVE SYNC is output to the auxiliary channel AUX.

[0222] During the effective period VACTIVE, the main processor sends the pixel packets used to generate image data to the timing controller (1335) via MAIN LINK.

[0223] After the effective period VACTIVE ends, the display timer enters the vertical blank period VBLAND (1340). The main processor can send timing signals for generating, for example, touch signals via the main link MAIN LINK.

[0224] The main processor de-energizes the transmit / receive circuits electrically connected to the main link (MAIN LINK) and also de-energizes the transmit / receive circuits electrically connected to the auxiliary channel (AUX) (1345). Therefore, the main link and auxiliary channel enter a link disconnect state.

[0225] The main processor counts the number of pulses of the clock signal CLK (1350). The counter included in the main processor can count the number of pulses of the clock signal.

[0226] If the number of pulses counted by the counter equals the number of clock signal pulses stored in memory, the main processor will power on the transmit / receive circuits connected to the main link (MAIN LINK) and the transmit / receive circuits connected to the auxiliary channel (AUX) (1355). Therefore, the main link (MAIN LINK) and the auxiliary channel (AUX) are switched to the link-on state. The main processor can then send the link training signal to the timing controller via the main link. Thus, the main processor and the timing controller are synchronized.

[0227] The display shows that the timer enters the valid period, and the main processor sends pixel packets (1360) through the main link (MAIN LINK).

[0228] Define the end of the flowchart (1365).

[0229] Therefore, even when the length of the vertical blank period is not pre-stored in memory at each refresh frame rate, the length of the vertical blank period can be detected, and the transmit / receive circuit connected to the auxiliary channel can be powered off.

[0230] Therefore, the power consumption of the main processor and timing controller can be reduced.

[0231] The following is a brief description of the above-described embodiments of the present disclosure.

[0232] Embodiments of this disclosure may provide a control circuit 100, comprising: a main processor 110 including a source transmit / receive circuit 520; and a timing controller 120 including a synchronous transmit / receive circuit 530 connected to the main processor 110 via an interface 510, and generating and outputting image data DATA and control signals DCS or GCS, wherein the interface 510 includes a main link (MAIN LINK) and an auxiliary channel (AUX), and wherein the main processor 110 de-energizes at least one of the source transmit / receive circuit 520 or the synchronous transmit / receive circuit 530 electrically connected to the auxiliary channel (AUX) during at least a portion of the vertical blank period (VBLANK) between different refresh frame cycles.

[0233] Embodiments of this disclosure may provide a control circuit 100, wherein the main processor 110 includes: a timing generator 540 for generating and outputting a clock signal CLK; and a counter 800 configured to detect the pulse edge of the clock signal CLK.

[0234] Embodiments of this disclosure may provide a control circuit 100, wherein if a preset number of pulse edges of the clock signal CLK are detected, the main processor 110 will electrically connect to the source transmit / receive circuit 520 of the auxiliary channel AUX to power on.

[0235] Embodiments of this disclosure may provide a control circuit 100, wherein a counter 800 detects the falling edge or rising edge of a clock signal CLK.

[0236] Embodiments of this disclosure may provide a control circuit 100, wherein a timing controller 120 generates and outputs a horizontal synchronization signal indicating the start of a horizontal line in an indicator frame, and wherein a clock signal CLK output by a timing generator 540 has the same frequency as the horizontal synchronization signal.

[0237] Embodiments of this disclosure may provide a control circuit 100, wherein a main processor 110 detects the length of a period when the source transmit / receive circuit 520 electrically connected to the main link MAIN LINK is in a power-off state, and wherein the main processor 110 controls the length of the period when the source transmit / receive circuit 520 electrically connected to the auxiliary channel AUX is powered off based on the detected length of the period.

[0238] Embodiments of this disclosure may provide a control circuit 100 in which the period during which the source transmit / receive circuit 520, electrically connected to the auxiliary channel AUX, is de-energized varies according to the length of the vertical blank period VBLANK.

[0239] Embodiments of this disclosure may provide a control circuit 100, wherein a main processor 110 controls the length of the period when the source transmit / receive circuit 520 electrically connected to the auxiliary channel AUX is de-energized, according to the length of the vertical blank period VBLANK.

[0240] Embodiments of this disclosure may provide a control circuit 100, wherein a source transmit / receive circuit 520 and a synchronization transmit / receive circuit 530 electrically connected to an auxiliary channel AUX are connected to a single power supply.

[0241] Embodiments of this disclosure may provide a control circuit 100, wherein a main processor 110 controls the on / off timing of a single power supply.

[0242] Embodiments of this disclosure may provide a control circuit 100, wherein a counter 800 includes a flip-flop (e.g., a first flip-flop 810) that receives a clock signal CLK.

[0243] Embodiments of this disclosure may provide a control circuit 100 in which a preset level of constant voltage is applied to the auxiliary channel AUX at a time (e.g., time t4) when the main processor 110 sends a link training signal LINK TRAINING to the timing controller 120 via the main link MAIN LINK for synchronization between the main processor 110 and the timing controller 120.

[0244] Embodiments of this disclosure may provide a display device 300, comprising: a main processor 110 including a source transmitting / receiving circuit 520; a timing controller 120 including a sink transmitting / receiving circuit 530 connected to the main processor 110 via an interface 510, and generating and outputting image data DATA and control signals DCS or GCS; a data driving circuit 320 controlled by the timing controller 120 for driving timing, and generating and outputting a data voltage based on the image data DATA and control signals DCS or GCS; a gate driving circuit 330 controlled by the timing controller 120, and outputting a gate voltage based on the control signals DCS or GCS; and a display panel 310 having multiple data lines DL to which data voltage is applied, multiple gate lines GL to which gate voltage is applied, and multiple sub-pixels SP electrically connected to the multiple data lines DL and the multiple gate lines GL, wherein the interface 510 includes a main link MAIN. The LINK and the auxiliary channel AUX, and wherein, during at least a portion of the vertical blank period BVBLANK between different refresh frame cycles, the main processor 110 will de-energize at least one of the source transmit / receive circuits 520 or the synchronous transmit / receive circuits 530 that are electrically connected to the auxiliary channel AUX.

[0245] Embodiments of this disclosure may provide a display device 300, wherein a timing controller 120 generates and outputs a vertical synchronization signal defining a plurality of frame periods, wherein a main processor 110 transmits a pixel packet PXL PACKET to the timing controller 120 via a main link during a refresh frame period between the plurality of frame periods, and wherein the main processor 110 de-energizes at least one of a source transmit / receive circuit 520 or a synchronization transmit / receive circuit 530 electrically connected to an auxiliary channel AUX during a skip frame period other than the refresh frame period between the plurality of frame periods.

[0246] Embodiments of this disclosure may provide a method 1200 or 1300 for driving a main processor 110, the method 1200 or 1300 comprising: the main processor 110 sending a pixel packet PXL PACKET for generating image data DATA to a timing controller 120 (1210 or 1310) via a main link MAIN LINK of interface 510; the main processor 110, including a source transmit / receive circuit 520 electrically connected to an auxiliary channel AUX of interface 510, de-energizing the source transmit / receive circuit 520 after the timing controller 120 receives the pixel packet PXL PACKET (1230 or 1345); the main processor 110 energizing the source transmit / receive circuit 520 electrically connected to the auxiliary channel AUX (1250 or 1345); and the main processor 110 sending a link training signal LINK TRAINING via the main link MAINLINK (1260 or 1355).

[0247] Implementations of this disclosure may provide method 1200 or 1300, which further includes counting pulses of a clock signal CLK generated and output by the main processor 110 by a counter 800 included in the main processor 110 (1240, 1325 or 1350).

[0248] Implementations of this disclosure may provide a method 1300 in which, while the source transmit / receive circuit 520 electrically connected to the auxiliary channel AUX is in a de-energized state, a counter 800 counts pulses of the clock signal CLK (1240 or 1350).

[0249] Implementations of this disclosure may provide a method 1300 in which, while the source transmit / receive circuit 520 electrically connected to the auxiliary channel AUX is energized, a counter 800 counts pulses of the clock signal CLK (1325).

[0250] The foregoing description has been presented to enable those skilled in the art to make and use the technical concepts of the invention, and has been provided in the context of a particular application and its requirements. Various modifications, additions, and substitutions to the described embodiments will readily become apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments and applications without departing from the spirit and scope of the invention. The foregoing description and figures provide examples of the technical concepts of the invention for illustrative purposes only. That is, the disclosed embodiments are intended to illustrate the scope of the technical concepts of the invention. Therefore, the scope of the invention is not limited to the illustrated embodiments, but should have the widest scope consistent with the claims. The scope of protection of the invention should be interpreted based on the appended claims, and all technical concepts within the scope of their equivalents should be interpreted as being included within the scope of the invention.

Claims

1. A control circuit, comprising: The main processor includes the source transmitting / receiving circuitry; as well as A timing controller includes a receiver / transmitter circuit connected to the main processor via an interface, and generates and outputs image data and control signals. The interface includes a main link and an auxiliary channel. During at least a portion of the vertical blank periods between different refresh frame cycles, the main processor de-energizes at least one of the source transmit / receive circuit and the sink transmit / receive circuit electrically connected to the auxiliary channel, and Specifically, the main processor will de-energize at least one of the source transmit / receive circuit and the sink transmit / receive circuit, which are electrically connected to the auxiliary channel, during skip frame periods other than the refresh frame period between multiple frame periods.

2. The control circuit according to claim 1, wherein, The main processor includes: A timing generator that generates and outputs clock signals; and A counter configured to detect the pulse edge of the clock signal.

3. The control circuit according to claim 2, wherein, If a preset number of pulse edges of the clock signal are detected, the main processor will electrically connect to the source transmit / receive circuit of the auxiliary channel to power on.

4. The control circuit according to claim 2, wherein, The counter detects the falling edge or rising edge of the clock signal.

5. The control circuit according to claim 2, wherein, The timing controller generates and outputs a horizontal synchronization signal indicating the start of a horizontal line in the frame, and The clock signal output by the timing generator has the same frequency as the horizontal synchronization signal.

6. The control circuit according to claim 1, wherein, The main processor detects the length of the time period during which the source transmitting / receiving circuit electrically connected to the main link is in a power-off state, and The main processor controls the length of the time period when the source transmitting / receiving circuit electrically connected to the auxiliary channel is powered off, based on the detected length of the time period.

7. The control circuit according to claim 1, wherein, The time period during which the source transmitting / receiving circuit electrically connected to the auxiliary channel is de-energized varies depending on the length of the vertical blank period.

8. The control circuit according to claim 1, wherein, The main processor controls the process so that the length of the period when the source transmitting / receiving circuit electrically connected to the auxiliary channel is de-energized is changed according to the length of the vertical blank period.

9. The control circuit according to claim 1, wherein, The source transmit / receive circuit and the sink transmit / receive circuit, which are electrically connected to the auxiliary channel, are connected to a single power supply.

10. The control circuit according to claim 9, wherein, The main processor controls the on / off timing of the individual power supply.

11. The control circuit according to claim 2, wherein, The counter includes a trigger that receives the clock signal.

12. The control circuit according to claim 1, wherein, At the time when the main processor sends a link training signal for synchronization between the main processor and the timing controller to the timing controller via the main link, a preset level of constant voltage is applied to the auxiliary channel.

13. A display device, comprising: The main processor includes the source transmitting / receiving circuitry; A timing controller includes a receiver / receiver circuit connected to the main processor via an interface, and generates and outputs image data and control signals; A data driving circuit, controlled by the timing controller for driving timing, and generating and outputting data voltage based on the image data and the control signal; A gate drive circuit, which is controlled by the timing controller, and outputs a gate voltage based on the control signal; as well as A display panel having multiple data lines to which the data voltage is applied, multiple gate lines to which the gate voltage is applied, and multiple sub-pixels electrically connected to the multiple data lines and the multiple gate lines. The interface includes a main link and an auxiliary channel. During at least a portion of the vertical blank periods between different refresh frame cycles, the main processor de-energizes at least one of the source transmit / receive circuit and the sink transmit / receive circuit electrically connected to the auxiliary channel, and Specifically, the main processor will de-energize at least one of the source transmit / receive circuit and the sink transmit / receive circuit, which are electrically connected to the auxiliary channel, during skip frame periods other than the refresh frame period between multiple frame periods.

14. The display device according to claim 13, wherein, The timing controller generates and outputs a vertical synchronization signal that defines the multiple frame periods, and The main processor sends pixel packets to the timing controller via the main link during the refresh frame period between the multiple frame periods.

15. A method for driving a main processor, the method comprising: The main processor sends the pixel packets used to generate image data to the timing controller through the main link of the interface; The main processor, which includes a source transmit / receive circuit electrically connected to an auxiliary channel of the interface, de-energizes the source transmit / receive circuit after the timing controller receives the pixel packet; The main processor powers on the source transmitting / receiving circuit, which is electrically connected to the auxiliary channel; as well as The main processor sends the link training signal through the main link. Specifically, the main processor will power off the source transmit / receive circuit electrically connected to the auxiliary channel during skip frame periods other than the refresh frame period between multiple frame periods.

16. The method of claim 15, further comprising: The main processor includes a counter that counts the pulses of the clock signal generated and output by the main processor.

17. The method according to claim 16, wherein, While the source transmitting / receiving circuit electrically connected to the auxiliary channel is in a de-energized state, the counter performs the counting of pulses of the clock signal.

18. The method according to claim 16, wherein, While the source transmitting / receiving circuit electrically connected to the auxiliary channel is powered on, the counter counts the pulses of the clock signal.

19. A control circuit, comprising: The main processor includes the source transmitting / receiving circuitry; as well as A timing controller includes a receiver / transmitter circuit connected to the main processor via an interface, and generates and outputs image data and control signals. The interface includes a main link and an auxiliary channel. Specifically, during at least a portion of the vertical blank periods between different refresh frame cycles, the main processor will de-energize at least one of the source transmit / receive circuit and the sink transmit / receive circuit, which are electrically connected to the main link. Specifically, the main processor will de-energize at least one of the source transmit / receive circuit and the sink transmit / receive circuit, which are electrically connected to the main link, during skip frame periods other than the refresh frame period between multiple frame periods.

20. The control circuit according to claim 19, wherein, When the main processor sends a valid synchronization signal indicating the start of the valid time period to the timing controller via the auxiliary channel, the power-off state of the main link ends, and During the effective time period, the main processor sends pixel packets for image display to the timing controller via the main link.

21. The control circuit according to claim 20, wherein, The main processor detects the length of the time period from the start of the power failure state of the main link to the time when the main processor sends the valid synchronization signal.

22. The control circuit according to claim 21, wherein, The main processor includes: A timing generator that generates and outputs clock signals; and A counter is configured to count the number of pulse edges of a clock signal from the start of the power-off state of the main link until the main processor sends the valid synchronization signal.

23. The control circuit according to claim 21, wherein, The main processor will de-energize at least one of the source transmit / receive circuits and the sink transmit / receive circuits electrically connected to the main link during at least a portion of the vertical blank period, and will also de-energize at least one of the source transmit / receive circuits and the sink transmit / receive circuits electrically connected to the auxiliary channel.

24. The control circuit according to claim 23, wherein, The main processor controls the length of the time period during which the main link and the auxiliary channel are in a power-off state based on the length of the time period from the start of the power-off state of the main link to the time period during which the main processor sends the valid synchronization signal.

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