Systems and methods for sub-pixel rendering and display driver

Abstract

The present disclosure relates to a method for driving a display panel, a display driver, a display apparatus, and an image processing circuit, and more particularly to sub-pixel rendering. A method for driving a display panel according to an aspect of the present application includes determining an input-side squared gray value of a pixel of input image data by taking a square of an input gray value, wherein the taking of the square of the input gray value includes taking a square of a first input gray value of the input gray value and taking a square of a second input gray value of the input gray value, calculating a first processed gray value from the first squared input gray value and the second squared input gray value, generating output image data by independently performing correction on the input-side squared gray value based on a correction value, and driving the display panel based on the output image data.

Description

[0001] This application is a divisional application of Chinese Patent Application No. 201810029832.4.

[0002] Cross Reference To Related Applications

[0003] This application claims priority to Japanese Patent Application No. 2017-003271 filed on January 12, 2017, and Japanese Patent Application No. 2017-004528 filed on January 13, 2017, the disclosures of which are incorporated herein by reference. TECHNICAL FIELD

[0004] The present disclosure relates to a display driver, a display device, and an image processing circuit, and more particularly to sub-pixel rendering. BACKGROUND

[0005] Sub-pixel rendering is a technique for displaying an image at a higher resolution than the original resolution of a display device (e.g., an OLED (Organic Light Emitting Diode) display panel and an LCD (Liquid Crystal Display) panel) by performing image data processing on image data of an original image. Hereinafter, an image data process for implementing sub-pixel rendering can be referred to as a sub-pixel rendering process. The sub-pixel rendering process involves generating image data for driving M pixels of a display device from image data associated with N pixels of an original image, where N and M are natural numbers satisfying N > M.

[0006] The sub-pixel rendering process is implemented in accordance with a gamma characteristic of the display device. The following is described for a case where image data for driving one pixel of the display device is generated from image data associated with two pixels of an original image by the sub-pixel rendering process, while a gray value of each sub-pixel is represented by eight bits in the image data of the original image and the image data for driving the pixels of the display device. When the gray values of R sub-pixels of the first and second pixels are described as "255" and "0", respectively, in the image data of the original image and the gray value of the R sub-pixel of the corresponding pixel of the display device is calculated by simply averaging the gray values of the R sub-pixels of the first and second pixels in the sub-pixel rendering process, the result is a gray value of "127.5". When the R sub-pixel of the corresponding pixel of the display device is driven with the gray value of "127.5", the luminance of the R sub-pixel becomes 22% for a gamma value γ of 2.2; however, in one embodiment, the R sub-pixel of the corresponding pixel of the display device is driven so that the luminance of the R sub-pixel becomes 50%, because a gray value of "255" corresponds to a luminance of 100% and a gray value of "0" corresponds to a luminance of 0%. When the gamma value γ of the display device is 2.2, the gray value of the R sub-pixel of the corresponding pixel of the display device is calculated as "186" in the sub-pixel rendering process.

[0007] Accordingly, the sub-pixel rendering process generally includes performing a gamma conversion (i.e., calculating a γth power of a gray scale value of the image data) on the gray scale value described in the image data of the original image, calculating image data associated with the M pixels of the display device based on the image data obtained by the gamma conversion, and then performing a gamma inverse conversion (i.e., calculating a 1 / γth power of a gray scale value of the image data).

[0008] Such a sub-pixel rendering process can cause an increase in circuit size. The gamma conversion and the gamma inverse conversion involve a calculation of a power. As is widely known to those skilled in the art, a circuit that performs a calculation of a power has a large circuit size. For example, the gamma conversion or the gamma inverse conversion is performed using a LUT (Look-Up Table); however, the use of the LUT to implement the gamma conversion or the gamma inverse conversion increases the circuit size.

[0009] Accordingly, there is a technical need to reduce the circuit size of a circuit that performs a sub-pixel rendering process. SUMMARY

[0010] In one embodiment, a display driver includes a sub-pixel rendering circuit configured to generate output image data describing output gray scale values as gray scale values of sub-pixels of M corresponding pixels of an output image corresponding to N pixels of an input image from input image data describing input gray scale values as gray scale values of sub-pixels of the N pixels of the input image, N being an integer of 2 or more and M being an integer satisfying 1≤M

[0011] In another embodiment, an image processing circuit includes a sub-pixel rendering circuit configured to generate output image data describing output gray scale values associated with M corresponding pixels of an output image corresponding to N pixels of an input image from input image data describing input gray scale values associated with the N pixels of the input image, N being an integer of 2 or more and M being an integer satisfying 1≤M

[0012] In yet another embodiment, a display apparatus includes a display panel and a display driver that drives the display panel. The display driver includes a subpixel rendering circuit configured to generate output image data that describes output grayscale values associated with M corresponding pixels of an output image that correspond to N pixels of an input image from input image data that describes input grayscale values associated with the N pixels of the input image, N being an integer of 2 or more and M being an integer that satisfies 1 < M < N, and a driving circuit configured to drive the display panel in response to the output image data. The subpixel rendering circuit is configured to calculate input-side squared grayscale values that are squares of the input grayscale values of the respective N pixels of the input image, calculate correction values associated with the M corresponding pixels from correction parameters determined in response to a gamma value set to the display driver and the input grayscale values, and generate the output image data by processing the input-side squared grayscale values based on the correction values.

[0013] In yet another embodiment, a display driver for driving a display panel includes a subpixel rendering circuit configured to perform a subpixel rendering process on first image data to generate second image data, an octachrome halftone circuit configured to perform an octachrome halftone process on the second image data to generate third image data that describes a grayscale value of each of R, G, and B subpixels of each pixel with one bit, and a driving circuit configured to drive the display panel in response to the third image data. The octachrome halftone circuit includes a storage circuit configured to store a dither table and configured to generate the third image data by performing a dither process on the second image data using dither values selected from elements of the dither table. A frequency distribution of values of the elements of the dither table is non-uniform.

[0014] In yet another embodiment, a display apparatus includes a display panel and a display driver. The display driver includes a subpixel rendering circuit configured to perform a subpixel rendering process on first image data to generate second image data, an octachrome halftone circuit configured to perform an octachrome halftone process on the second image data to generate third image data that describes a grayscale value of each of R, G, and B subpixels of each pixel with one bit, and a driving circuit configured to drive the display panel in response to the third image data. The octachrome halftone circuit includes a storage circuit configured to store a dither table and configured to generate the third image data by performing a dither process on the second image data using dither values selected from elements of the dither table when generating the third image data associated with a pixel of interest of the display panel. A frequency distribution of values of the elements of the dither table is non-uniform. BRIEF DESCRIPTION OF DRAWINGS

[0015] Figure 1A is a block diagram showing a configuration of a display apparatus according to one or more embodiments;

[0016] Figure 1B FIG. 1 is a conceptual diagram illustrating a configuration of a pixel according to one or more embodiments;

[0017] Figure 1C FIG. 2 is a block diagram illustrating a configuration of a display driver according to one or more embodiments;

[0018] Figure 2 FIG. 3 is a block diagram illustrating a configuration of a sub-pixel rendering circuit according to one or more embodiments;

[0019] Figure 3 FIG. 4 is a conceptual diagram illustrating a correspondence between pixels according to one or more embodiments;

[0020] Figure 4 FIG. 5 is a conceptual diagram illustrating a method of calculating a gray value according to one or more embodiments;

[0021] Figure 5 FIG. 6 is a table illustrating a correspondence between a gamma value γ and a correction parameter a according to one or more embodiments;

[0022] Figure 6 FIG. 7 is a conceptual diagram illustrating a correspondence between pixels according to one or more embodiments;

[0023] Figure 7 FIG. 8 is a conceptual diagram illustrating a method of calculating a gray value according to one or more embodiments;

[0024] Figure 8 FIG. 9 is a block diagram illustrating a configuration of a display driver according to one or more embodiments;

[0025] Figure 9 FIG. 10 illustrates one example of a dithering table according to one or more embodiments;

[0026] Figure 10 FIG. 11 illustrates a gamma characteristic of a dithering process according to one or more embodiments;

[0027] Figure 11 FIG. 12 is a block diagram illustrating a configuration of an eight- color halftone circuit according to one or more embodiments;

[0028] Figure 12 FIG. 13 illustrates one example of a dithering table according to one or more embodiments; and

[0029] Figure 13 FIG. 14 illustrates one example of a dithering table according to one or more embodiments. Figure 14 FIG. 15 schematically illustrates one example of a sub-pixel rendering process and an eight-color halftone process performed in an image processing circuit according to one or more embodiments. DETAILED DESCRIPTION

[0030] A description will now be given of embodiments of the disclosure with reference to the accompanying drawings. Figure 1Ais a block diagram showing a configuration of a display device 10 in one embodiment. The display device 10 includes a display panel 1 and a display driver 2. An OLED (organic light emitting diode) display panel or a liquid crystal display panel can be used as the display panel 1.

[0031] The display panel 1 includes gate lines 4, data lines 5, pixel circuits 6, and gate line drive circuits 7. Each pixel circuit 6 is provided at an intersection of a gate line 4 and a data line 5, and is configured to display one of red, green, and blue colors. A pixel circuit 6 displaying red is used as an R sub-pixel. Similarly, a pixel circuit 6 displaying green is used as a G sub-pixel, and a pixel circuit 6 displaying blue is used as a B sub-pixel. When an OLED display panel is used as the display panel 1, in one embodiment, a pixel circuit 6 displaying red can include a light emitting element emitting red light, a pixel circuit 6 displaying green can include a light emitting element emitting green light, and a pixel circuit 6 displaying blue can include a light emitting element emitting blue light.

[0032] As shown in Figure 1B , each pixel 8 of the display panel 1 includes one R sub-pixel, one G sub-pixel, and one B sub-pixel. Figure 1B In one embodiment, the R sub-pixel (pixel circuit 6 displaying red) is indicated by reference numeral 6R. Similarly, the G sub-pixel (pixel circuit 6 displaying green) is indicated by reference numeral 6G, and the B sub-pixel (pixel circuit 6 displaying blue) is indicated by reference numeral 6B.

[0033] Referring also to Figure 1A , the gate line drive circuits 7 drive the gate lines 4 in response to gate control signals 31 received from the display driver 2. In this embodiment, a pair of gate line drive circuits 7 is provided. One of the gate line drive circuits 7 drives odd-numbered gate lines 4, and the other drives even-numbered gate lines 4. In this embodiment, the gate line drive circuits 7 are integrated on the display panel 1 by using a GIP (Gate on Panel) technique. Such gate line drive circuits 7 can be referred to as GIP circuits.

[0034] The display driver 2 drives the display panel 1 in response to image data 32 and control data 33 received from a host 3, so as to display an image on the display panel 1. The image data 32 describes a gray scale value of each sub-pixel of each pixel of an image to be displayed (or an original image). The control data 33 includes commands and parameters for controlling the display driver 2. An application processor, a CPU (Central Processing Unit), a DSP (Digital Signal Processor), or the like can be used as the host 3.

[0035] Figure 1C is a block diagram showing a configuration of the display driver 2 in one embodiment. The display driver 2 includes an interface control circuit 11, an image processing circuit 12, a latch circuit 13, a gray scale voltage generator circuit 14, a data line drive circuit 15, and a register 16.

[0036] The interface control circuit 11 operates as follows. First, the interface control circuit 11 forwards the image data 32 received from the host 3 to the image processing circuit 12. The interface control circuit 11 also stores various parameters contained in the control data 33 into the register 16, and controls the corresponding circuit of the display driver 2 in response to the command contained in the control data 33.

[0037] The image processing circuit 12 performs the intended image data process on the image data 32 received from the interface control circuit 11 to generate the display data 34 for driving the display panel 1. As described later, in one embodiment, the image data process performed in the image processing circuit 12 includes a sub-pixel rendering process. Details of the sub-pixel rendering process performed in the image processing circuit 12 will be described later. The image data process performed in the image processing circuit 12 can include processes other than the sub-pixel rendering process (e.g. color adjustment).

[0038] The latch circuit 13 latches the display data 34 from the image processing circuit 12, and forwards the latched display data 34 to the data line drive circuit 15.

[0039] The gray scale voltage generator circuit 14 generates a set of gray scale voltages corresponding to the allowable values of the gray scale values described in the display data 34, respectively.

[0040] The data line drive circuit 15 drives the corresponding data line 5 with the gray scale voltage corresponding to the value of the display data 34. In one embodiment, the data line drive circuit 15 selects one of the gray scale voltages received from the gray scale voltage generator circuit 14 corresponding to the value of the display data 34, and drives the corresponding data line 5 to the selected gray scale voltage.

[0041] The register 16 stores various control parameters used to control the operation of the display driver 2. The register 16 is configured to be rewritable from outside of the display driver 2, e.g. from the host 3. The control parameters stored in the register 16 include a correction parameter a used to control the sub-pixel rendering process performed in the image processing circuit 12. The content and technical implication of the correction parameter a will be described later in one embodiment.

[0042] Figure 2 is a block diagram showing the configuration of the circuit performing the sub-pixel rendering process in the image processing circuit 12. Hereinafter, the circuit performing the sub-pixel rendering process is referred to as the sub-pixel rendering circuit 20. The sub-pixel rendering circuit 20 is configured to perform the sub-pixel rendering process on the input image data D IN to generate the output image data D OUT . Hereinafter, the image corresponding to the input image data D IN is referred to as the input image, and the image corresponding to the output image data is referred to as the output image. The input image data DIN The input image data D IN The input image data D OUT The input image data D OUT The input image data D

[0043] The input image data D IN may be the image data 32 supplied from the interface control circuit 11 to the image processing circuit 12. Alternatively, image data obtained by performing the intended image data processing on the image data 32 can be used as the input image data D IN The output image data D OUT may be used as the display data 34 supplied to the data line drive circuit 15. Alternatively, image data obtained by performing the intended image data processing on the output image data D OUT may be used as the display data 34, and supplied to the data line drive circuit 15.

[0044] In this embodiment, the sub-pixel rendering circuit 20 includes a square calculation circuit 21, a sub-pixel rendering calculation circuit 22, a square root calculation circuit 23, a correction value calculation circuit 24, and an adder circuit 25.

[0045] The square calculation circuit 21 calculates the square of the input grayscale value of each sub-pixel of each pixel of the input image. The value of the square of the input grayscale value can be referred to as an input-side square grayscale value.

[0046] The sub-pixel rendering calculation circuit 22 calculates the square grayscale value of the SPR processing (sub-pixel rendering processing) for each sub-pixel of each pixel of the output image from the input-side square grayscale value calculated for each sub-pixel of each pixel of the input image. The square grayscale value of the SPR processing approximately corresponds to the square of the grayscale value of each sub-pixel of each pixel of the output image. However, it should be noted that, as will be understood from the following description, the square root of the square grayscale value of the SPR processing calculated for each sub-pixel of each pixel of the output image cannot be used as the grayscale value of each sub-pixel of each pixel of the output image. The square grayscale value of the SPR processing for a sub-pixel of a particular color (e.g., red, green, or blue) of a particular pixel of the output image is calculated from the input-side square grayscale value calculated for a sub-pixel of the particular color of the pixel of the input image corresponding to the particular pixel of the output image.

[0047] The square root calculating circuit 23 calculates a square root (i.e., 1 / 2 power) of the square gray value of the SPR processing calculated for each subpixel of each pixel of the output image.

[0048] The correction value calculating circuit 24 calculates a correction value ΔD for each subpixel of each pixel of the output image. The correction parameter α stored in the register 16 is used to calculate the correction value ΔD. The calculated correction value ΔD is supplied to the adder circuit 25.

[0049] The adder circuit 25 adds the correction value ΔD calculated for each subpixel of each pixel of the output image to the square root of the square gray value of the SPR processing calculated for each subpixel of each pixel of the output image. The output of the adder circuit 25 is the output image data D OUT OUT The gray value of a particular subpixel of a particular pixel of the output image described above is calculated as a sum of the square root of the square gray value of the SPR processing calculated for the particular subpixel and the correction value ΔD calculated for the particular subpixel.

[0050] As described above, a conventional subpixel rendering process includes a gamma conversion, an arithmetic process of image data, and a gamma inverse conversion. The gamma conversion includes a calculation of γ power, and the gamma inverse conversion includes a calculation of 1 / γ power, where γ is a gamma value. As described above, the circuit size of a circuit that performs the gamma conversion or the gamma inverse conversion is large.

[0051] The subpixel rendering circuit 20 of this embodiment is configured so that a square calculation (e.g., a calculation that results in a square) is performed instead of the gamma conversion, and a square root calculation (e.g., a calculation that results in a square root) is performed instead of the gamma inverse conversion, and an error caused by these calculations is compensated for by adding the correction value ΔD. The square calculation and the square root calculation can be implemented by a circuit having a smaller circuit size than a circuit that calculates a power. Although the square calculation and the square root calculation are used instead of the gamma conversion and the gamma inverse conversion can cause an error, this error can be compensated for by adding the correction value ΔD. Accordingly, the configuration of the subpixel rendering circuit 20 of this embodiment is effective in reducing the circuit size.

[0052] Hereinafter, the operation of the subpixel rendering circuit 20 that generates the output image data D OUT will be described for the case where the ratio of the number of pixels of the input image to the number of pixels of the output image is 3:2. In other embodiments, other ratios can be used.

[0053] Figure 3 The correspondence between the pixels of the input image and the pixels of the output image for the case where the ratio of the number of pixels of the input image to the number of pixels of the output image is 3:2 is schematically shown. Figure 3 ​The image shown is an example where the output image data D is associated with 720 pixels arranged horizontally. OUT The input image data D is associated with 1080 pixels arranged horizontally. IN To calculate.

[0054] exist Figure 3 During the subpixel rendering process shown, the output image data D OUT Calculated based on two pixel units in the output image, these two pixels are adjacent along the horizontal direction (the direction in which the raster lines extend). The output image data D associated with two adjacent pixels in the output image... OUT Input image data D associated with four pixels of the input image IN To calculate. In one embodiment, the output image data D associated with the pixel Pout#(2k) of the output image. OUT The input image data D is associated with the pixels Pin#(3k-1), Pin#(3k), and Pin(3k+1) of the input image. IN To calculate, and associate the output image data D with the pixel Pout#(2k+1) of the output image. OUT The input image data D is associated with the pixels Pin#(3k+1) and Pin(3k+2) of the input image. IN To calculate, in one embodiment, k is an integer equal to or greater than zero.

[0055] For the case where k is zero, that is, for the output image data D associated with the leftmost pixel Pout#0 of the output image OUT The calculation assumes that pixel Pin#0 of the input image is located at the leftmost position along the horizontal direction, and pixel Pin#(-1) does not exist. To address this issue, the output image data D associated with pixel Pout#0 of the output image is... OUT By using the input image data D associated with pixel Pin#1 IN Instead of the input image data D associated with pixel Pin#(-1) IN To calculate. In other words, the output image data D associated with pixel Pout#0 of the output image. OUT Input image data D associated with pixels Pin#1, Pin#0, Pin#1, and Pin#2 of the input image IN To calculate. And in this case, the output image data D associated with the two pixels Pout#0 and #1 of the output image. OUT This can actually be understood as the input image data D associated with four pixels Pin#1, Pin#0, Pin#1, and Pin#2 of the input image. IN To calculate.

[0056] In various embodiments, the subpixel rendering process performed by the subpixel rendering circuit 20 includes processing input image data D associated with four pixels Pin#(3k-1), Pin#(3k), Pin#(3k+1), and Pin#(3k+2). IN To calculate the output image data D associated with two pixels Pout#(2k) and Pout#(2k+1). OUT For example, the output image data D of two pixels Pout#2 and Pout#3 of the output image. OUT In this subpixel rendering process, it is calculated from four pixels of the input image: Pin#2, Pin#3, Pin#4, and Pin#5. In various embodiments, for the case where k=0, the input image data D associated with pixel Pin#1 is... IN Used to replace the input image data D associated with pixel Pin#(-1) IN .

[0057] In one or more embodiments, the input image data D associated with four pixels Pin#(3k-1), Pin#(3k), Pin#(3k+1), and Pin#(3k+2) of the input image IN The input image data D can be referred to as D respectively. IN0 D IN1 D IN2 and D IN3 Input image data D IN0 Describe the gray values ​​R0, G0, and B0 of the R sub-pixel, G sub-pixel, and B sub-pixel of pixel Pin#(3k-1), and the input image data D. IN1 Describe the grayscale values ​​R1 of the R sub-pixel, G1 of the G sub-pixel, and B1 of the B sub-pixel of pixel Pin# (3k). Similarly, the input image data D IN2 Describe the gray values ​​R2 of the R sub-pixel, G2 of the G sub-pixel, and B2 of the B sub-pixel of pixel Pin#(3k+1), and the input image data D. IN3 The grayscale values ​​R3 of the R sub-pixel, G3 of the G sub-pixel, and B3 of the B sub-pixel describe pixel Pin#(3k+2). In various embodiments, the input image data D INi The grayscale value R of the R sub-pixel described in [the text] i The grayscale value of the G sub-pixel G i And the grayscale value B of sub-pixels B i These can be referred to as the input grayscale value R. i G i and B i , where i is an integer from zero to three.

[0058] In some embodiments, the output image data D OUT may be referred to as output image data D OUT0 and D OUT1 may be referred to as output image data D OUT0 OUT1 may be referred to as output image data D OUTj may be referred to as output image data D j may be referred to as output image data D j may be referred to as output image data D j may be referred to as output image data D j may be referred to as output image data D j may be referred to as output image data D j may be referred to as output image data D

[0059] Figure 4 An example method of calculating the output luminance values NewR0and NewR1(i.e., the luminance values NewR0and NewR1of the R sub-pixels of the pixels Pout#(2k) and Pout#(2k+1) of the output image) is schematically shown. The output luminance values NewR0and NewR1are calculated as follows.

[0060] The input-side squared luminance values R0 2 , R1 2 , R2 2 , and R3 2 , which are squares of the input luminance values R0, R1, R2, and R3(i.e., the luminance values R0, R1, R2, and R3of the R sub-pixels of the pixels Pin#(3k-1), Pin#(3k), Pin#(3k+1), and Pin#(3k+2) of the input image), are calculated by the squaring calculation circuit 21.

[0061] The squared luminance values R SUB0 2 , and R SUB1 2 The input-side squared luminance values R0 2 , R1 2 , R2 2 , and R3​2 The square gray value R of the SPR-processed R subpixel of the output image is calculated by the square root calculation circuit 23. SUB0 2 The square gray value R of the SPR-processed R subpixel of the output image is calculated by the square root calculation circuit 23. SUB1 2 The square gray value R of the SPR-processed R subpixel of the output image is calculated by the square root calculation circuit 23.

[0062]

[0063] Further, the square gray value R of the SPR-processed R subpixel of the output image pixels Pout#(2k) and Pout#(2k+1) is calculated by the square root calculation circuit 23. SUB0 2 The square gray value R of the SPR-processed R subpixel of the output image is calculated by the square root calculation circuit 23. SUB1 2 The square root R of the square gray value R of the SPR-processed R subpixel of the output image is calculated by the square root calculation circuit 23. SUB0 The square root R of the square gray value R of the SPR-processed R subpixel of the output image is calculated by the square root calculation circuit 23. SUB1 The square root R of the square gray value R of the SPR-processed R subpixel of the output image is calculated by the square root calculation circuit 23.

[0064] Further, in some embodiments, the correction value calculation circuit 24 calculates the correction values AR0 and AR1 of the respective R subpixels of the output image pixels Pout#(2k) and Pout#(2k+1) in accordance with the following expressions (2a) and (2b):

[0065]

[0066] The correction parameter a used in the expressions (2a) and (2b) is stored in the register 16, and the correction value calculation circuit 24 calculates the correction values AR0 and AR1 using the correction parameter a received from the register 16. The correction parameter a is calculated in accordance with the following expression (3a):

[0067]

[0068] where γ is the gamma value of the display panel 1 (the gamma value set to the display driver 2), and MAX is the allowable maximum value of the gray value of each subpixel of each pixel in the input image data D IN and the output image data D OUT In some embodiments, when the input image data D IN and the output image data D OUT each describe the gray value of each subpixel of each pixel using eight bits, the following expression holds:

[0069] MAX = 255 (= 2 8 -1).

[0070] In this case, the expression (3a) can be rewritten as the following expression (3b):

[0071]

[0072] In this case, the expression (3a) can be rewritten as the following expression (3b):Figure 5 is a table showing the correspondence between the gamma value γ and the correction parameter α calculated according to the above expression (3b). Figure 5 The correction parameter α shown is calculated as a seven-digit numerical value, and is obtained by rounding off the α calculated according to expression (3b) to an integer. When the gamma value γ of the display panel 1 is 2.2, for example, the correction parameter α stored in the register 16 is set to 44.

[0073] The adder circuit 25 calculates the output gray values NewR0 and NewR1 (i.e., the gray values NewR0 and NewR1 of the R sub-pixels of the pixels Pout#(2k) and Pout#(2k+1), respectively) by adding the correction values ΔR0 and ΔR1 to the square roots R SUB0 and R SUB1 of the R sub-pixels of the pixels Pout#(2k) and Pout#(2k+1), respectively. In other words, the adder circuit 25 calculates the output gray values NewR0 and NewR1 according to the following expressions (4a) and (4b):

[0074] NewR0 = R SUB0 + ΔR0, and... (4a)

[0075] NewR1 = R SUB1 + ΔR1.... (4b)

[0076] According to the above calculation, the output gray values NewR0 and NewR1 are calculated as a result as a whole of the sub-pixel rendering circuit 20 according to the following expressions (5a) and (5b):

[0077]

[0078] In each of the embodiments, the calculation of the output gray values NewR0 and NewR1 according to expressions (5a) and (5b) allows to obtain gray values that are close to the gray values obtained by strictly performing the sub-pixel rendering process based on the gamma conversion and the inverse gamma conversion.

[0079] In one or more embodiments, when the sub-pixel rendering process is strictly performed using the gamma conversion and the inverse gamma conversion, the output gray values NewR0 and NewR1 of the R sub-pixels of the pixels Pout#(2k) and Pout#(2k+1) of the output image are calculated according to the following expressions (6a) and (6b):

[0080]

[0081] When γ is approximately equal to 2, the following approximate expressions (7a) and (7b) hold:

[0082]

[0083] The right-hand sides of expressions (5a) and (5b) can be obtained by substituting R0, R1, R2, and R3 into A, B, C, and D of the right-hand sides of expressions (7a) and (7b), respectively. This implies that the approximate calculation can be implemented with sufficient accuracy by calculating the output gray values NewR0 and NewR1 according to expressions (5a) and (5b). According to the inventor's study, for a gamma value γ of from 2.0 to 3.0, the sufficient accuracy can be achieved by calculating the output gray values NewR0 and NewR1 according to expressions (5a) and (5b) with seven-bit correction parameters α.

[0084] Expressions (8a) and (8b) are calculation examples for the case where the gamma value γ of the display panel 1 is 2.2. When the gamma value γ is 2.2, the correction parameters α are set to "44" as by Figure 5 It is understood that when the input gray values R0, R1, R2, and R3 are "255", "0", "255", and "0", respectively, the output gray values NewR0 and NewR1 are calculated as follows:

[0085]

[0086] The calculated output gray values NewR0 and NewR1 are equal to the values obtained by strictly performing the sub-pixel rendering process by using the gamma conversion and the gamma inverse conversion.

[0087] When the gamma value γ is 2.0, the correction parameters α calculated according to expressions (3a) or (3b) are infinite. In this case, in one embodiment, the correction values ΔR0 and ΔR1 can be calculated to be zero by the correction value calculation circuit 24. To implement this operation, the display driver 2 can be configured so that a flag asserted when the gamma value γ is 2.0 is prepared in the register 16, and the correction value calculation circuit 24 is configured to unconditionally set the correction values ΔR0 and ΔR1 to zero when the flag is asserted.

[0088] The gray values NewG0 and NewG1 of the G sub-pixels and the gray values NewB0 and NewB1 of the B sub-pixels of the output image pixels Pout#(2k) and Pout#(2k+1) are calculated in a similar manner.

[0089] In one embodiment, the input-side squared gray values G0 2 , G1 2 , G2 2 , and G3 2 (which are squares of the gray values G0, G1, G2, and G3 of the G sub-pixels of the input image pixels Pin#(3k-1), Pin#(3k), Pin#(3k+1), and Pin#(3k+2)) and the input-side squared gray values B02 B1 2 B2 2 and B3 2 (The squares of the gray values ​​B0, B1, B2 and B3 of the B sub-pixels) are calculated by the square calculation circuit 21.

[0090] The squared gray values ​​G of the sub-pixels of pixels Pout#(2k) and Pout#(2k+1) in the output image are obtained by SPR processing. SUB0 2 and G SUB1 2 The sub-pixel rendering calculation circuit 22 further calculates the squared gray value G0 from the input side. 2 G1 2 G2 2 and G3 2 To calculate, and the squared gray value B of the SPR processing of sub-pixel B. SUB0 2 and B SUB1 2 Square grayscale value B0 from the input side 2 B1 2 B2 2 and B3 2 To calculate the squared gray value G processed by SPR. SUB0 2 G SUB1 2 B SUB0 2 and B SUB1 2 Calculate according to the following formulas (9a), (9b), (10a) and (10b):

[0091]

[0092] Furthermore, the squared gray values ​​G of the G sub-pixels of the output image's pixels Pout#(2k) and Pout#(2k+1) are processed by SPR. SUB0 2 and G SUB1 2 The square root of G SUB0 and G SUB1 And the squared gray value B of the SPR processing of sub-pixel B SUB0 2 and B SUB1 2 The square root of B SUB0 and B SUB1 The square root is calculated using the square root calculation circuit 23.

[0093] Further, in some embodiments, the correction value calculation circuit 24 calculates the correction values AG0and AG1of the respective G sub-pixels of the pixels Pout#(2k) and Pout#(2k+1) of the output image in accordance with the following equations (11a) and (11b), and calculates the correction values AB0and AB1of the respective B sub-pixels in accordance with the following equations (12a) and (12b):

[0094]

[0095] The adder circuit 25 calculates the gray scale values NewG0and NewG1of the G sub-pixels of the pixels Pout#(2k) and Pout#(2k+1) of the output image by adding the correction values AG0and AG1to the square roots G SUB0 and G SUB1 calculated for the G sub-pixels of the pixels Pout#(2k) and Pout#(2k+1) of the output image, respectively. Similarly, the adder circuit 25 also calculates the gray scale values NewB0and NewB1of the B sub-pixels of the pixels Pout#(2k) and Pout#(2k+1) of the output image by adding the correction values AB0and AB1to the square roots B SUB0 and B SUB1 calculated for the B sub-pixels of the pixels Pout#(2k) and Pout#(2k+1) of the output image, respectively.

[0096] In other words, the adder circuit 25 calculates the gray scale values NewG0and NewG1of the G sub-pixels and the gray scale values NewB0and NewB1of the B sub-pixels of the pixels Pout#(2k) and Pout#(2k+1) of the output image in accordance with the following equations (13a), (13b), (14a) and (14b):

[0097] NewG0= G SUB0 + AG0,... (13a)

[0098] NewG1= G SUB1 + AG1,... (13b)

[0099] NewB0= B SUB0 + AB0, and... (14a)

[0100] NewB1= B SUB1 + AB1.... (14b)

[0101] According to the above calculation, the gray scale values NewGo and NewGi of the G sub-pixels and the gray scale values NewBo and NewBi of the B sub-pixels of the output image pixels Pout#(2k) and Pout#(2k+1) are calculated as a result of the whole of the sub-pixel rendering circuit 20 as follows by expressions (15a), (15b), (16a) and (16b):

[0102]

[0103] In each embodiment, the calculation of the gray scale values NewGo and NewGi of the G sub-pixels and the gray scale values NewBo and NewBi of the B sub-pixels of the pixels Pout#(2k) and Pout#(2k+1) according to expressions (15a), (15b) and (16a) and (16b) realizes a sufficiently accurate approximation calculation.

[0104] As described above, the sub-pixel rendering circuit 20 of the present embodiment is configured to perform a square calculation instead of a gamma conversion and to perform a square root calculation instead of a gamma inverse conversion, while compensating for errors caused by such operations by adding a correction value. This configuration of the sub-pixel rendering circuit 20 of the present embodiment effectively reduces the circuit size thereof.

[0105] In one embodiment, the sub-pixel rendering circuit 20 of the present embodiment also provides the advantage that the gamma value γ can be easily modified by modifying the correction parameter α stored in the register 16. When the register 16 is writable from the host 3, the host 3 can access the register 16 to modify the correction parameter α stored in the register 16. For example, as understood from the above description, the gamma value γ used in the sub-pixel rendering circuit 20 can be modified from 2.2 to 2.1 by accessing the register 16 from the host 3 and modifying the correction parameter α stored in the register 16 from 44 to 85. Figure 5

[0106] While the above embodiment describes a configuration in which the output image data D OUT is calculated from the input image data D IN associated with four pixels of the input image, the sub-pixel rendering process can generally be realized according to a process similar to the case in which the output image data D OUT is calculated from the input image data D IN associated with M pixels of the output image, N being an integer of 2 or more and M being an integer satisfying 1≤M

[0107] Figure 6 The correspondence between the pixels of the input image and the pixels of the output image in the sub-pixel rendering process is schematically shown for the case in which the ratio of the number of pixels of the input image to the number of pixels of the output image is 2:1.​Figure 6 An example is shown in which output image data D OUT from input image data D IN associated with three pixels of the input image is calculated.

[0108] In Figure 6 the subpixel rendering process shown, output image data D OUT from input image data D IN associated with three pixels of the input image is calculated. In one embodiment, output image data D OUT associated with a pixel Pout#k of the output image is calculated from input image data D IN associated with pixels Pin#(2k-l), Pin#(2k), and Pin(2k+l) of the input image, where k is an integer equal to or greater than zero.

[0109] For the case where k is zero, i.e., for the calculation of output image data D OUT associated with the leftmost pixel Pout#0 of the output image, pixel Pin#0 of the input image is located at the leftmost side in the horizontal direction, and pixel Pin#(-l) does not exist. In various embodiments, to solve this problem, output image data D OUT associated with pixel Pout#0 of the output image is calculated by using input image data D IN associated with pixel Pin#l instead of input image data D IN associated with pixel Pin#(-l). In other words, output image data D OUT associated with pixel Pout#0 of the output image is calculated from input image data D IN associated with pixels Pin#l, Pin#0, and Pin#l of the input image. Also in this case, output image data D OUT associated with pixel Pout#0 of the output image can actually be understood to be calculated from input image data D IN associated with three pixels Pin#l, Pin#0, and Pin#l of the input image.

[0110] Figure 7 A method of calculating a gray value NewR (output gray value NewR) of an R subpixel of a pixel Pout#k of the output image is schematically shown. The output gray value NewR can be calculated as follows.

[0111] Input-side square gray values R0 2 , Rl 2 , and R2 2The square of the gray value R0, R1, and R2 (input gray values R0, R1, and R2) of the R sub-pixel of the pixel Pin#(2k-l), Pin#(2k), and Pin#(2k+1) of the input image is calculated by the square calculating circuit 21.

[0112] The square root R of the square gray value R of the SPR processing of the R sub-pixel of the pixel Pout#k of the output image SUB 2 is then calculated from the input side square gray values R0 2 , R1 2 , and R2 2 by the sub-pixel rendering calculating circuit 22. The square gray value R SUB 2 of the SPR processing is calculated in accordance with the following equation (17):

[0113]

[0114] Further, the square root R SUB 2 of the square gray value R SUB of the SPR processing of the R sub-pixel of the pixel Pout#k of the output image is calculated by the square root calculating circuit 23.

[0115] Meanwhile, the correction value calculating circuit 24 calculates the correction value AR in accordance with the following equation (18):

[0116]

[0117] The correction parameter a in the expression (18) is stored in the register 16, and the correction value calculating circuit 24 uses the correction parameter a received from the register 16 to calculate the correction value AR.

[0118] The adder circuit 25 calculates the output gray value NewR (i.e., the gray value NewR of the R sub-pixel of the pixel Pout#k) by adding the square root R SUB calculated for the R sub-pixel of the pixel Pout#k of the output image to the correction value AR. In other words, the adder circuit 25 calculates the output gray value NewR in accordance with the following equation (19):

[0119] NewR = R SUB + AR... (19)

[0120] According to the above calculation, the output gray value NewR is calculated as a result of the entire sub-pixel rendering circuit 20 in accordance with the following equation (20):

[0121]

[0122] The grayscale values ​​NewG and NewB of the G sub-pixel and B sub-pixel of pixel Pout#k are calculated in a similar manner. Those skilled in the art will readily understand from the above discussion that the grayscale values ​​NewR, NewG, and NewB of the R sub-pixel and G sub-pixel of pixel Pout#k are calculated in this way to achieve a sufficiently accurate approximation.

[0123] In one embodiment, such as Figure 8 As shown, the display driver 2A can be configured to perform an eight-color halftone process and a subpixel rendering process. The "eight-color halftone process" mentioned herein refers to the process of converting image data associated with the original image into image data in which the number of permissible colors for each pixel is eight, that is, the number of permissible gray levels for each of the R, G, and B subpixels of each pixel is two. When performing an eight-color halftone process on image data associated with a specific pixel, the resulting image data is generated as three-bit data (the "on" or "off" state of each of the R, G, and B subpixels of the specified pixel). Here, "on" a subpixel means driving the subpixel with a gray level voltage corresponding to the maximum permissible gray level, while "off" a subpixel means driving the subpixel with a gray level voltage corresponding to the minimum permissible gray level.

[0124] As shown, the display driver 2A includes an interface control circuit 41, an image processing circuit 42, a grayscale voltage generator circuit 43, a data line driving circuit 44, a timing control circuit 45, and a panel interface circuit 46.

[0125] In various embodiments, the interface control circuit 41 forwards image data 32 received from the host 3 to the image processing circuit 42. Additionally, the interface control circuit 41 controls the corresponding circuitry of the display driver 2 in response to control parameters and commands contained in the control data 33. The image processing circuit 42 generates display data 34 by performing image data processing on the image data 32 received from the interface control circuit 41, which is used to drive the display panel 1. The grayscale voltage generator circuit 43 generates grayscale voltages V0 to V1 corresponding to the allowable values ​​of the grayscale values ​​described in the display data 34. M The data line driving circuit 44 uses a grayscale voltage corresponding to the grayscale value described in the display data 34 to drive the corresponding data line 5. In one embodiment, the data line driving circuit 44 receives grayscale voltages V0 to V from the grayscale voltage generator circuit 43. MAmong the gray scale voltages, the gray scale voltage corresponding to the gray scale value described in the display data 34 is selected for the corresponding data line 5, and the corresponding data line 5 is driven to the selected gray scale voltage. The timing control circuit 45 performs timing control of the corresponding circuits of the display driver 2 in response to the control signal received from the interface control circuit 41. The panel interface circuit 46 supplies the gate control signal 31 to the gate line drive circuit 7 of the display panel 1, thereby controlling the gate line drive circuit 7.

[0126] In this embodiment, the gray scale voltage generator circuit 43 is configured to stop generating the gray scale voltages corresponding to the intermediate gray scale values (i.e., the gray scale voltages other than the gray scale voltages corresponding to the allowable maximum and minimum gray scale values). From the gray scale voltages V0 to V M Among the gray scale voltages, the gray scale voltage V0 corresponds to the allowable minimum gray scale value, and the gray scale voltage V M corresponds to the allowable maximum gray scale value. Accordingly, the gray scale voltages V1 to V M-1 correspond to the intermediate gray scale values, respectively. In response to the instruction of the gray scale voltage control signal supplied from the interface control circuit 41, the gray scale voltage generator circuit 43 stops generating the gray scale voltages V1 to V M-1 corresponding to the intermediate gray scale values.

[0127] In one or more embodiments, the gamma characteristic of the data line drive circuit 44 depends on the distribution of the voltage levels of the gray scale voltages V0 to V M supplied from the gray scale voltage generator circuit 43. In order to set the data line drive circuit 44 to the intended gamma characteristic, the distribution of the voltage levels of the gray scale voltages V0 to V M is determined in accordance with the intended gamma characteristic. The gray scale voltages V0 to V M generated by the gray scale voltage generator circuit 43 are controlled by the gray scale voltage control signal supplied from the interface control circuit 41.

[0128] The gamma characteristic of the entire display driver 2 is determined as the superposition of the gamma characteristic of the image processing performed in the image processing circuit 42 and the gamma characteristic of the data line drive circuit 44. In order to display an image with appropriate luminance, the gamma characteristic of the entire display driver 2 can be set to match the gamma characteristic of the display panel 1.

[0129] In this embodiment, the image processing circuit 42 is configured to perform a sub-pixel rendering process and an eight-color halftone process. More specifically, in this embodiment, the image processing circuit 42 includes a sub-pixel rendering circuit 47, an eight-color halftone circuit 48, and a selector 49.

[0130] The sub-pixel rendering circuit 47 performs a sub-pixel rendering process on the image data 32 received from the interface control circuit 41 to generate SPR-processed image data 35, and supplies the generated SPR-processed image data 35 to the eight- shade halftone circuit 48 and the selector 49. Hereinafter, an image corresponding to the SPR-processed image data can be referred to as an SPR-processed image. The sub-pixel rendering circuit 47 also supplies the address indicating the position of each pixel in the SPR-processed image to the eight-shade halftone circuit 48. When the SPR-processed image data 35 associated with a certain pixel is supplied to the eight-shade halftone circuit 48, the sub-pixel rendering circuit 47 supplies the address of the pixel to the eight-shade halftone circuit 48 in synchronization with the supply of the SPR-processed image data 35.

[0131] In one embodiment, the sub-pixel rendering circuit 47 can be configured similarly to the sub-pixel rendering circuit 20 shown in FIG. 2. In this case, the sub-pixel rendering circuit 47 can perform the sub-pixel rendering process as described above. In alternative embodiments, the sub-pixel rendering circuit 47 can perform a different sub-pixel rendering process. Figure 2

[0132] The eight-shade halftone circuit 48 generates binary image data 36 by performing an eight-shade halftone process on the SPR-processed image data 35.

[0133] The selector 49 selects one of the SPR-processed image data 35 received from the sub-pixel rendering circuit 47 and the binary image data 36 received from the eight-shade halftone circuit 48, and supplies the selected image data as display data 34 to the data line drive circuit 44. The data line drive circuit 44 drives the display panel 1 in response to the display data 34 received from the selector 49.

[0134] In one or more embodiments, when the image processing circuit 42 is caused to perform the eight-shade halftone process, the interface control circuit 41 supplies an image processing control signal to the image processing circuit 42 to instruct the performance of the eight-shade halftone process. The selector 49 selects the binary image data 36 in response to the image processing control signal. In addition, the interface control circuit 41 supplies a gray-scale voltage control signal to the gray-scale voltage generator circuit 43 to instruct the stop of the generation of the gray-scale voltages VI to V M-1 corresponding to the intermediate gray-scale values. The gray-scale voltage generator circuit 43 stops the generation of the gray-scale voltages VI to V M-1 corresponding to the intermediate gray-scale values in response to the gray-scale voltage control signal. This allows the reduction of the power consumption of the gray-scale voltage generator circuit 43. Note that in some embodiments, the generation of the gray-scale voltages VO and V M-1 corresponding to the allowable minimum and maximum gray-scale values, respectively, is continued even when the generation of the gray-scale voltages VI to V M corresponding to the intermediate gray-scale values is stopped.​

[0135] Although Figure 8 While Figure 8 While

[0136] In some embodiments, implementing an octachrome halftoning process for multi- gray scale image data can be to determine whether each sub-pixel is to be "turned on" or "turned off" according to the most significant bit of the data indicative of the gray scale value of the sub-pixel; note that the SPR-processed image data 35 is a kind of multi-gray scale image data. By "turning on" each sub-pixel of the pixel of interest when the most significant bit of the data indicative of the gray scale value of the sub-pixel is "1" and "turning off" each sub-pixel when the most significant bit of the data indicative of the gray scale value of the sub-pixel is "0", it is possible to display an image in which the number of allowable colors of each pixel is eight. However, this octachrome halftoning process largely degrades image quality because spatial variations of gray scale values in the image cannot be sufficiently represented.

[0137] The octachrome halftoning process can be understood as a color reduction process that reduces the number of added bits. Therefore, a dithering process, which is one of color reduction processes that is said to effectively suppress degradation of image quality, can be a potential octachrome halftoning process. Performing a dithering process allows spatial variations of gray scale values in the image to be represented, and thus reduces degradation of image quality. In some embodiments, a dithering process is implemented by adding a dithering value determined in a random manner to image data and then clipping one or more low bits. The term "random" referred to herein means that the probability that a dithering value takes a corresponding allowable value is the same. For example, an octachrome halftoning process for image data that employs eight bits to represent the gray scale value of each sub-pixel can be implemented by adding an eight-bit dithering value to the image data of each sub-pixel (note that the resulting value is nine bits) and extracting the most significant bit (i.e., clipping eight low bits).

[0138] In various embodiments, generation of a dithering value used in a dithering process is implemented by reading out a dithering value from a dithering table that describes allowable dithering values as elements in response to the address of the pixel of interest. Figure 9 One example of a dithering table that includes 16 x 16 elements and describes eight-bit dithering values as corresponding elements is shown. Figure 9The illustrated dither table includes 256 elements, and the dither values described in the respective elements are set to different values from zero to 255. In other words, Figure 9 The illustrated dither table is determined so that the number of elements each of which takes a value from zero to 255 is one. For example, the dither value can be selected from the 256 elements of the illustrated dither table in response to the four low-order bits of the X address and the four low-order bits of the Y address, where the X address is an address indicating a position in the horizontal direction (the direction in which the gate lines extend) of the display panel 1, and the Y address is an address indicating a position in the vertical direction (the direction in which the data lines extend) of the display panel 1. Figure 9 The dither value is selected from the 256 elements of the illustrated dither table to generate a random dither value, where the X address is an address indicating a position in the horizontal direction (the direction in which the gate lines extend) of the display panel 1, and the Y address is an address indicating a position in the vertical direction (the direction in which the data lines extend) of the display panel 1.

[0139] It should be noted that when an image is displayed in response to the image data obtained by the eight-color halftone process, the gamma characteristics of the data line drive circuit 44 are set using the distribution of voltage levels of the gray scale voltages V0 to V M The gamma characteristics of the data line drive circuit 44 do not work because the displayed image includes only the sub-pixels of the maximum gray scale value and the minimum value allowed. When the eight-color halftone process is performed, the gray scale voltages V1 to V M-1 corresponding to the intermediate gray scale values are not used, and thus the setting of the gray scale voltages V1 to V M-1 has no effect on the gamma characteristics of the data line drive circuit 44.

[0140] It should also be noted that when the eight-color halftone process is implemented by the dither process using the dither values determined in a random manner, this eight-color halftone process is equivalent to image processing with a gamma value γ of 1. Figure 10 The gamma characteristics of the eight-color halftone process implemented by the dither process using the dither values determined in a random manner are shown, where the gray scale value of each sub-pixel is represented using an eight-bit value (from zero to 255). Figure 10 In this figure, the solid line indicates the gamma characteristics of the eight-color halftone process implemented by the dither process using the dither values determined in a random manner, and the dashed line indicates the gamma characteristics of a gamma value of 2.2.

[0141] When dithering is performed on the image data associated with a certain subpixel using a dither value determined in a random manner, the probability that the subpixel is "on" increases in proportion to the gray scale value specified for the image data associated with the subpixel. When the gray scale value specified for a certain subpixel is "0", the probability that the subpixel is "on" is 0%, whereas when the gray scale value is "255", the probability is 100%. For a gray scale value of "128", the subpixel is "off for dither values of zero to 127, and "on" for dither values of 128 to 255. In other words, for a gray scale value of "128", the subpixel is "on" with a probability of 50% and "off with a probability of 50%. Accordingly, the effective brightness level of the subpixel in the displayed image is 50% of the maximum brightness level allowed. As described thus far, the probability that the subpixel is "on" increases in proportion to the gray scale value specified for the subpixel, and the effective brightness level of the subpixel in the displayed image also increases in proportion to the gray scale value specified for the subpixel. This implies that the gamma value of the dithering process using dither values determined in a random manner is 1.

[0142] Accordingly, the eight- color halftoning process implemented by the dithering process using dither values determined in a random manner can cause a mismatch between the gamma characteristics of the entire display driver 2 and the gamma characteristics of the display panel 1, and cause the brightness level of each subpixel to be unable to be properly represented in the displayed image, but the eight-color halftoning process is able to represent spatial variations in the gray scale values in the displayed image.

[0143] The eight-color halftoning circuit 48 of this embodiment is configured to perform an eight-color halftoning process based on a dithering process while solving this problem. A description of the configuration and operation of the eight-color halftoning circuit 48 in this embodiment is given below.

[0144] Figure 11 is a block diagram showing the eight-color halftoning circuit 48. In this embodiment, the eight-color halftoning circuit 48, which is configured to perform a dithering process using dither values, includes a LUT (Look-Up Table) circuit 51 and an adder circuit 52.

[0145] The LUT circuit 51 is a storage circuit that stores a dither table 53. The LUT circuit 51 selects a dither value D DITHER from an element of the dither table 53 in response to the X address and the Y address of the pixel of interest provided from the subpixel rendering circuit 47, and provides the selected dither value D DITHER to the adder circuit 52. Figure 11In the diagram, the X and Y addresses are indicated by the legend "(X,Y)". Here, the X address of the pixel of interest indicates the position in the SPR-processed image (the image corresponding to the SPR-processed image data 35) along the horizontal direction (the direction corresponding to the direction in which the raster lines extend in the display panel 1), and the Y address indicates the position in the SPR-processed image along the vertical direction (the direction corresponding to the direction in which the data lines extend in the display panel 1). When the grayscale values ​​D of the R, G, and B sub-pixels of each pixel... SPR R D SPR G and D SPR B When describing the image data 35 processed by SPR using m bits (for m being an integer of 2 or higher), each element of the jitter table 53 has an m-bit value, and the jitter value D DITHER It also has m-bit values. In this case, the number of elements in the jitter table 53 is 2. m .

[0146] The grayscale values ​​D of the R, G, and B sub-pixels of each pixel. SPR R D SPR G and D SPR B In this embodiment, which uses eight bits of the image data 35 processed by SPR to describe the dithering, each element of the dithering table 53 takes an eight-bit value selected from "0" to "255". The dithering table 53 has 16 rows and 16 columns of elements. However, it should be noted that, as described later, in one embodiment, two or more elements may take... Figure 11 The same value in the dither table 53 of the eight-color halftone circuit 48 shown. In this embodiment where the dither table 53 has 16 rows and 16 columns of elements, the LUT circuit 51 selects the dither value D from the 256 elements of the dither table 53 in response to the four low bits of the X address and the four low bits of the Y address of the pixel of interest. DITHER .

[0147] Adder circuit 52 receives SPR-processed image data 35 from sub-pixel rendering circuit 47 and adds the dither value provided by LUT circuit 51 to the grayscale value of each sub-pixel of each pixel described in the SPR-processed image data 35. In one embodiment, for the R, G, and B sub-pixels of the pixel of interest described in the SPR-processed image data 35, adder circuit 52 calculates the sum SUM according to the following equations (21a) to (21c). R SUM G and SUM B :

[0148] SUM R =DSPR R +D DITHER ,... (21a)

[0149] SUM G =D SPR G +D DITHER , and... (21b)

[0150] SUM B =D SPR B +D DITHER ,... (21c)

[0151] where D SPR R is the gray value of the R sub-pixel of the pixel of interest described in the SPR-processed image data 35, D SPR G is the gray value of the G sub-pixel of the pixel of interest, and D SPR B is the gray value of the B sub-pixel of the pixel of interest. The most significant bits of the sums SUM R , SUM G , and SUM B are output as the binary image data 36. It should be noted that each of the sums SUM R , SUM G , and SUM B is a nine-bit value in this embodiment, where each of the gray values D SPR R , D SPR G , and D SPR B of the R, G, and B sub-pixels described in the SPR-processed image data 35 is an eight-bit value, and the dithering value D DITHER is also an eight-bit value. The binary image data 36 takes one bit to indicate whether each of the R, G, and B sub-pixels of each pixel is "on" or "off, and the bits D BN R , D BN G , and D BN B of the binary image data 36, which respectively correspond to the R, G, and B sub-pixels of the pixel of interest, can be expressed by the following equations (22a) to (22c):

[0152] D BN R = MSB [SUM R ],... (22a)

[0153] D BNG =MSB[SUM G ], and…(22b)

[0154] D BN B =MSB[SUM B ]. …(22c)

[0155] exist Figure 11 In the illustrated eight-color halftone circuit 48, the frequency distribution of the values ​​of the elements in the dithering table 53 is specifically designed to provide the gamma characteristic of the desired gamma value for the eight-color halftone circuit 48. It is possible to achieve various gamma characteristics in a dithering process by appropriately designing the frequency distribution of the dithering table used in the dithering process. In this specification, the frequency distribution of the values ​​of the elements in the dithering table represents the distribution of the number N(p) of elements having a value p. Generally, the dithering table used in the dithering process is determined such that the number of elements taking each permissible value is one, i.e., for any q, N(p) = 1. Figure 9 This illustrates a 16-row-16-column jitter table, and how it is used. Figure 9 The dithering process of the dithering table shown has a gamma characteristic of 1 as described above. In contrast, the use of a dithering table where the frequency distribution is non-uniform (i.e., the number N(p) of elements with a value of p depends on p) allows for various image processing steps to be performed according to the dithering process. Note that there are values ​​from zero to 2. m For integers p1 and p2 of -1, when the frequency distribution is not uniform, the number of elements N(p1) and N(p2) taking the values ​​p1 and p2 are different in the jitter table.

[0156] The following is an example in which an eight-color halftone process based on dithering is performed using an m-bit dithering value D. DITHER Image data 35 processed by SPR (which describes the gray values ​​D of R, G, and B sub-pixels) SPR R D SPR G and D SPR B To execute. 36 bits of binary image data (B) BN k Calculate the sum D SPR k +D DITHER The most significant bit, where k is any one of "R", "G", and "B". In this case, when the values ​​of the elements of dithering table 53 are determined such that the grayscale value D for each sub-pixel is... SPR k Any permissible value p, jitter table 53 2 m The element q has a value equal to or greater than 2. mthe effective luminance level of the subpixel in the display image becomes (q / 2 m ) times the maximum allowable luminance level. In some embodiments, it is possible to realize the gamma characteristic of the gamma value γ by defining q according to the following equation (23):

[0157]

[0158] where floor(x) is a floor function which gives the largest integer less than or equal to x. The addition of the value 0.5 and the floor function floor(x) is introduced only to provide rounding to an integer. The rounding can be realized in different ways.

[0159] When m is 8 and the gray value D SPR k of a certain subpixel is 186, the luminance level of the subpixel is set to 0.5 (= 128 / 256) times the maximum allowable luminance level to realize the gamma characteristic of the gamma value of 2.2. In this case, the desired luminance level can be realized for the subpixel by defining p as 186 and q as 128, and designing the dither table 53 such that 128 of the 256 elements of the dither table 53 have a value equal to or greater than 70.

[0160] Figure 12 An example of the value of the corresponding element of the dither table 53 for m being eight when the eight-color halftone process of the gamma characteristic of the gamma value γ of 2.2 is performed is shown. Figure 12 The dither table 53 shown is determined such that q of the 2 m SPR k of the dither table 53 is defined according to the following equation (24) for each of the allowable values p of the gray value D m of a certain subpixel:

[0161]

[0162] More specifically, Figure 12 The dither table 53 shown is obtained by performing a conversion on the dither table shown in FIG. 8 according to the following equation (25): Figure 9

[0163] where α(i,j) is the value of the element in the i-th row and j-th column of the dither table shown in FIG. 8, β(i,j) is the value of the element in the i-th row and j-th column of the dither table 53 shown in FIG. 7, and floor(x) is a floor function which gives the largest integer equal to or less than x.

[0164] Figure 9 Figure 12 Figure 12 ​​​​The use of the illustrated dither table 53 allows Figure 11 The illustrated eight-color halftoning circuit 48 performs the dithering process of the gamma value γ of 2.2.

[0165] In some embodiments, the gray scale value D of each sub-pixel described in the SPR-processed image data 35 SPR k is an m-bit value and the dither value is also an m-bit value, the dither table 53 (which implements the dithering process of the gamma value γ) can be generated by the following process:

[0166] (1) A first dither table is generated by a conventional method in which the number of elements taken from each allowable value is one (i.e., N(p) = 1 for any q). Note that the first dither table has 2 m elements; and

[0167] (2) The first dither table thus generated is converted according to the following equation (26):

[0168]

[0169] where α(i,j) is the value of the element in the i-th row and j-th column of the first dither table, and β(i,j) is the value of the element in the i-th row and j-th column of the second dither table obtained by this conversion.

[0170] Figure 13 and Figure 14 An example of the sub-pixel rendering process and the eight-color halftoning process performed in the image processing circuit 42 in this embodiment is schematically shown. In Figure 13 and Figure 14 the illustrated example, the image data 32 corresponds to an original image in which the gray scale values D of its respective sub-pixels (R sub-pixels, G sub-pixels, and B sub-pixels) SPR k all equal to pixels that are allowed the minimum gray scale value "0", and the gray scale values D of its respective sub-pixels (R sub-pixels, G sub-pixels, and B sub-pixels) SPR k all equal to pixels that are allowed the maximum gray scale value "255" are alternately arranged. In the sub-pixel rendering process in the sub-pixel rendering circuit 47, the gray scale value of each sub-pixel of the pixels of the SPR-processed image data 35 is calculated from the gray scale values of the respective sub-pixels of the two adjacent pixels in the original image so that the luminance level is averaged. Thus, the gray scale value of each sub-pixel of the pixels of the SPR-processed image data 35 is calculated to be "186" in one example.

[0171] The eight-color halftone process is then performed on the image data 35 processed by the SPR by the eight-color halftone circuit 48. In the eight-color halftone circuit 48, the eight-color halftone process is performed using a gamma characteristic with a gamma value of 2.2. As described above, when the grayscale value D of each sub-pixel... SPR k In the image data 35 processed by SPR, described as 186, the luminance level of each subpixel has a gamma characteristic of 50% (≈128 / 255) for a gamma value of 2.2.

[0172] In this embodiment, the LUT circuit 51 from Figure 12 Select the jitter value D to be provided to adder circuit 52 from the elements of jitter table 53 shown. DITHER As mentioned above, Figure 12 The values ​​of the corresponding elements in the jitter table 53 shown are determined from the frequency distribution (which achieves a gamma value of 2.2 gamma characteristics). The adder circuit 52 will take the jitter value D received from the LUT circuit 51... DITHER With the grayscale value D of each sub-pixel SPR k Add them together and calculate the sum SUM. k Bit D associated with the sub-pixel of color k in binary image data 36. BN k Determined as the sum SUM k The most significant bit.

[0173] The following describes the grayscale value D of each sub-pixel in image data 35, where the above process is performed on pixels arranged in 16 rows and 16 columns for SPR processing. SPR k The situation to be executed. When using Figure 12 The dithering table 53 shown shows the grayscale value D of each sub-pixel. SPR k When it is "186", bit D BN k The 128 values ​​relative to 16×16 pixels are calculated as "1". This is because when the jitter value D... DITHER from Figure 12 When selecting elements from the jitter table 53 shown, the sum SUM k The most significant bit is "1" relative to the 128 bits of a 16×16 pixel. Correspondingly, each sub-pixel of color k is "on" in the 128 bits of the 16×16 pixel. This implies that the effective luminance level of each sub-pixel of color k is 50% of the maximum permissible luminance level in the displayed image. Accordingly, the eight-color halftone process of this embodiment implements a gamma characteristic of 2.2, appropriately representing the luminance level of each pixel in the displayed image.

[0174] As described above, this embodiment provides image data processing techniques that implement both a sub-pixel rendering process and an eight-shade halftoning process. The eight-shade halftoning of this embodiment allows for a spatial variation in the gray scale values in a displayed image, and appropriately represents the luminance levels of the individual pixels in the displayed image.

[0175] While the above describes a particular embodiment of the present disclosure, those skilled in the art will appreciate that the techniques of the present disclosure can be practiced with various modifications.

Claims

1. A method for driving a display panel, comprising: The input-side squared gray value of the pixel in the input image data is determined by taking the square of the input gray value, wherein taking the square of the input gray value includes taking the square of the first input gray value and taking the square of the second input gray value. The first processed gray value is calculated based on the first squared input gray value and the second squared input gray value; Output image data is generated by independently performing corrections on the squared gray values ​​of the input side based on the correction values; and The display panel is driven based on the output image data.

2. The method as described in claim 1, wherein, Taking the square of the input grayscale value includes taking the square of the third input grayscale value, and further calculating the first processed grayscale value based on the third squared input grayscale value.

3. The method as described in claim 2, wherein, Taking the square of the input grayscale value further includes taking the square of a fourth input grayscale value, and the method further includes: The second processed gray value is calculated based on the third squared input gray value and the fourth squared input gray value.

4. The method of claim 1, further comprising: The correction value is determined based on the correction parameters and the input grayscale value.

5. The method of claim 4, wherein, Determining the correction value includes: A first correction value is determined based on a combination of a first input gray value, a second input gray value, and a third input gray value, as well as correction parameters. This first correction value is associated with a first pixel of the display panel.

6. The method of claim 5, wherein, Determining the correction value also includes: A second correction value is determined based on a combination of a third and a fourth input grayscale value and a correction parameter, and the second correction value is associated with a second pixel of the display panel.

7. The method of claim 6, wherein, The first input grayscale value corresponds to the first pixel, the second input grayscale value corresponds to the second pixel, the third input grayscale value corresponds to the third pixel, and the fourth input grayscale value corresponds to the fourth pixel.

8. A display driver, comprising: The subpixel rendering (SPR) circuit is configured as follows: The input-side squared gray value of the pixel in the input image data is determined by taking the square of the input gray value, wherein taking the square of the input gray value includes taking the square of the first input gray value and taking the square of the second input gray value. The first processed gray value is calculated based on the first squared input gray value and the second squared input gray value; Output image data is generated by independently performing corrections on the squared gray values ​​of the input side based on the correction values; and A driver circuit configured to drive the display panel based on the output image data.

9. The display driver as claimed in claim 8, wherein, Taking the square of the input grayscale value includes taking the square of the third input grayscale value, and the SPR circuit is further configured as follows: The first processed gray value is also calculated based on the third squared input gray value.

10. The display driver as claimed in claim 9, wherein, Taking the square of the input grayscale value also includes taking the square of a fourth input grayscale value, and the SPR circuit is further configured as follows: The second processed gray value is calculated based on the third squared input gray value and the fourth squared input gray value.

11. The display driver as claimed in claim 8, wherein, The SPR circuit is also configured to determine the correction value based on the correction parameters and the input grayscale value.

12. The display driver of claim 11, wherein, Determining the correction value includes: A first correction value is determined based on a combination of a first input gray value, a second input gray value, and a third input gray value, as well as correction parameters. This first correction value is associated with a first pixel of the display panel.

13. The display driver of claim 12, wherein, Determining the correction value also includes: A second correction value is determined based on a combination of a third and a fourth input grayscale value and a correction parameter, and the second correction value is associated with a second pixel of the display panel.

14. The display driver as claimed in claim 13, wherein, The first input grayscale value corresponds to the first pixel, the second input grayscale value corresponds to the second pixel, the third input grayscale value corresponds to the third pixel, and the fourth input grayscale value corresponds to the fourth pixel.

15. A display device, comprising: Display panel; as well as Display driver, configured as follows: The input-side squared gray value of the pixel in the input image data is determined by taking the square of the input gray value, wherein taking the square of the input gray value includes taking the square of the first input gray value and taking the square of the second input gray value. The first processed gray value is calculated based on the first squared input gray value and the second squared input gray value; Output image data is generated by independently performing corrections on the squared gray values ​​of the input side based on the correction values; and The display panel is driven based on the output image data.

16. The display device as claimed in claim 15, wherein, Taking the square of the input grayscale value includes taking the square of a third input grayscale value, and the display driver is further configured as follows: The first processed gray value is also calculated based on the third squared input gray value.

17. The display device as claimed in claim 16, wherein, Taking the square of the input grayscale value also includes taking the square of a fourth input grayscale value, and the display driver is further configured to: The second processed gray value is calculated based on the third squared input gray value and the fourth squared input gray value.

18. The display device as claimed in claim 15, wherein, The display driver is also configured to determine the correction value based on the correction parameters and the input grayscale value.

19. The display device as claimed in claim 18, wherein, Determining the correction value includes: A first correction value is determined based on a combination of a first input gray value, a second input gray value, and a third input gray value, as well as correction parameters. This first correction value is associated with a first pixel of the display panel.

20. The display device as claimed in claim 19, wherein, Determining the correction value also includes: A second correction value is determined based on a combination of a third and a fourth input grayscale value and a correction parameter, and the second correction value is associated with a second pixel of the display panel.

Images