Dual gate structure, field oxide structure, and method of manufacturing semiconductor devices

Abstract

The application relates to a double-gate structure, a field oxygen structure and a manufacturing method of a semiconductor device, and the manufacturing method of the double-gate structure comprises the following steps: obtaining a wafer formed with a first gate dielectric layer and a second gate dielectric layer; forming a gate material layer on the first and second gate dielectric layers; forming a photoresist anti-reflection layer on the gate material layer; coating photoresist on the photoresist anti-reflection layer, exposing by using a polysilicon gate photoetching plate, developing the photoresist, then etching the photoresist anti-reflection layer and the gate material layer, forming a first gate on the first gate dielectric layer and a second gate on the second gate dielectric layer, and the first gate dielectric layer extends from the bottom of the first gate on both sides; removing the photoresist, then dry etching the first gate dielectric layer extending from the bottom of the first gate, and the photoresist anti-reflection layer is used as a blocking layer of the dry etching. The application uses the photoresist anti-reflection layer as an etching blocking layer, removes the excess first gate dielectric layer extending out of the first gate by dry etching, and ensures that the device does not break the trench.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and in particular to a method for manufacturing a dual-gate structure, a method for manufacturing a field oxide structure, and a method for manufacturing a semiconductor device. Background Technology

[0002] With the continuous development of integrated circuit technology, the integration density of process platforms is becoming increasingly higher, and integrating high-voltage processes on low-voltage process platforms is becoming more and more common. In the Dual Gate (DG) process, an exemplary fabrication method is to first grow a thick gate oxide, then photolithographically etch a thin gate region, re-grow the thin gate oxide, and finally deposit polysilicon. Due to the overlay error during the thick gate photolithography and polysilicon photolithography operations, the thick gate oxide needs to extend beyond the polysilicon by a certain size to ensure that the polysilicon does not exceed the edge of the thick gate oxide. During subsequent source / drain implantation, the thick gate oxide extending beyond the polysilicon will block the source / drain implantation. If the thick gate oxide is thin, the impact on source / drain implantation is small and can almost be ignored. However, if the thick gate oxide is too thick, most of the source / drain implantation will be blocked, leading to a broken trench in the device. Summary of the Invention

[0003] Therefore, it is necessary to provide a method for manufacturing a dual-gate structure in which the source-drain injection of the device is not blocked by an extra injection blocking layer.

[0004] A method for manufacturing a dual-gate structure includes: acquiring a wafer, wherein a first gate dielectric layer and a second gate dielectric layer are formed on a substrate, the thickness of the second gate dielectric layer being less than that of the first gate dielectric layer; forming a gate material layer on the first gate dielectric layer and the second gate dielectric layer; forming a photolithographic anti-reflection layer on the gate material layer; coating photoresist on the photolithographic anti-reflection layer; exposing and developing the photoresist using a polysilicon gate photomask; then etching the photolithographic anti-reflection layer and the gate material layer to form a first gate on the first gate dielectric layer and a second gate on the second gate dielectric layer; wherein the width of the first gate dielectric layer is greater than the width of the first gate and both sides of the first gate dielectric layer extend from the bottom of the first gate; removing the photoresist; then dry etching the first gate dielectric layer extending from the bottom of the first gate, the photolithographic anti-reflection layer serving as a barrier layer for the dry etching; controlling the etching conditions so that the photolithographic anti-reflection layer is not completely etched before the extended first gate dielectric layer is completely etched; and performing source / drain implantation on both sides of the first gate.

[0005] The above-mentioned method for manufacturing a dual-gate structure utilizes a photolithographic anti-reflection layer as an etching barrier layer and dry etching to remove excess first gate dielectric layer extending beyond the first gate, thereby ensuring that source and drain injection are not blocked by excess first gate dielectric layer and ensuring that the device does not experience trench breakage.

[0006] In one embodiment, the photolithographic antireflective layer is made of silicon oxynitride.

[0007] In one embodiment, both the first gate dielectric layer and the second gate dielectric layer are gate oxide layers.

[0008] In one embodiment, the gate material layer is made of polycrystalline silicon.

[0009] In one embodiment, the step of obtaining a wafer includes: forming a first dielectric layer in a first region on the substrate; forming a second dielectric layer on the substrate and the first dielectric layer; wherein the first dielectric layer in the first region and the second dielectric layer in the first region together serve as the first gate dielectric layer, and the second dielectric layer outside the first region serves as the second gate dielectric layer.

[0010] In one embodiment, the dry etching employs a mechanism for monitoring the etching endpoint.

[0011] In one embodiment, the dry etching process monitors the etching endpoint by monitoring changes in the etching rate curve.

[0012] In one embodiment, the first gate is the gate of a high-voltage device, and the second gate is the gate of a low-voltage device.

[0013] It is also necessary to provide a method for manufacturing field oxygen structures.

[0014] A method for manufacturing a field oxide structure includes: obtaining a wafer, wherein a field oxide layer and a gate dielectric layer are formed on a substrate, the thickness of the gate dielectric layer being less than that of the field oxide layer; forming a gate material layer on the field oxide layer and the gate dielectric layer; forming a photolithographic anti-reflection layer on the gate material layer; coating photoresist on the photolithographic anti-reflection layer; exposing and developing the photoresist using a polysilicon gate photomask; and then etching the photolithographic anti-reflection layer and the gate material layer to obtain a gate layer, wherein one side of the gate layer extends from the edge of the field oxide layer to the gate dielectric layer, and the other side is shorter than the field oxide layer, thereby causing the field oxide layer to extend from the bottom of the other side of the gate layer; removing the photoresist; and then dry etching the field oxide layer extending from the bottom of the other side of the gate layer, wherein the photolithographic anti-reflection layer serves as a barrier layer for the dry etching; controlling the etching conditions so that the photolithographic anti-reflection layer is not completely etched before the extended field oxide layer is completely etched; and performing source / drain implantation into the substrate.

[0015] The above-mentioned method for manufacturing field oxide structures utilizes a photolithographic anti-reflection layer as an etching barrier layer and dry etching to remove excess field oxide layers extending beyond the gate layer, thereby ensuring that source and drain injection are not blocked by excess field oxide layers and ensuring that the device does not experience trench breakage.

[0016] In one embodiment, the step of obtaining a wafer includes: forming a first oxide layer on the substrate; removing the first oxide layer in a second region; forming a gate dielectric layer in the second region, wherein the gate dielectric layer formed simultaneously on the first oxide layer and the first oxide layer together serve as the field oxide layer.

[0017] In one embodiment, the photolithographic antireflective layer is made of silicon oxynitride.

[0018] In one embodiment, the gate material layer is made of polycrystalline silicon.

[0019] In one embodiment, the dry etching employs a mechanism for monitoring the etching endpoint.

[0020] In one embodiment, the dry etching process monitors the etching endpoint by monitoring changes in the etching rate curve.

[0021] It is also necessary to provide a method for manufacturing a semiconductor device, applied in the BCD process, including the method for manufacturing a dual-gate structure as described in any of the foregoing embodiments, and / or the method for manufacturing a field oxide structure as described in any of the foregoing embodiments. Attached Figure Description

[0022] To better describe and illustrate embodiments and / or examples of the inventions disclosed herein, reference may be made to one or more accompanying drawings. Additional details or examples used to describe the drawings should not be considered as limiting the scope of any of the disclosed inventions, the currently described embodiments and / or examples, or the best mode of these inventions as currently understood.

[0023] Figure 1 This is a flowchart of a method for manufacturing a dual-gate structure in one embodiment;

[0024] Figures 2a to 2e Is adopted Figure 1 A schematic cross-sectional view of the wafer at each step in one embodiment of the method for fabricating a dual-gate structure.

[0025] Figure 3 This is one embodiment Figure 2a A flowchart illustrating the formation method of the structure shown;

[0026] Figure 4 This is a flowchart of a method for manufacturing a field oxygen structure in one embodiment;

[0027] Figures 5a to 5e Is adopted Figure 4 A schematic cross-sectional view of a wafer at each step in one embodiment of the method for fabricating a field oxygen structure.

[0028] Figure 6 This is one embodiment Figure 5aA flowchart illustrating the method for forming the structure shown. Detailed Implementation

[0029] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Preferred embodiments of the invention are shown in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0030] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0031] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this invention, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.

[0032] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “under” the other element or feature will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0033] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0034] Embodiments of the invention are described herein with reference to cross-sectional views that serve as schematic diagrams of ideal embodiments (and intermediate structures). Thus, variations in the shape shown can be anticipated due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing processes. For example, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, the buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes are not intended to show the actual shapes of the regions of the device and are not intended to limit the scope of the invention.

[0035] The semiconductor terminology used in this article is the technical terminology commonly used by those skilled in the art. For example, for P-type and N-type impurities, in order to distinguish the doping concentration, P+ type represents heavily doped P-type, P type represents moderately doped P-type, P- type represents lightly doped P-type, N+ type represents heavily doped N-type, N type represents moderately doped N-type, and N- type represents lightly doped N-type.

[0036] In BCD (Bipolar CMOS DMOS) processes with a critical dimension (CD) of 0.18 micrometers, thicker field oxide or gate oxide is added during the process to achieve higher device breakdown voltage and lower on-resistance, or to provide devices with different gate voltages. After polysilicon etching, the introduction of thick field oxide and thick gate oxide can cause some of the field oxide and thick gate oxide to protrude beyond the polysilicon, affecting source / drain injection and potentially causing device trench breakage. To address this issue, two exemplary solutions are introduced here. The first method is to add a photomask to etch the thick gate oxide or thick field oxide protruding beyond the polysilicon. That is, after completing the polysilicon etching, an additional photolithography step is added to expose the gate oxide or field oxide region protruding beyond the polysilicon and then etch it to remove the excess oxide layer. The second method is to precisely control the overlay error between the thick gate oxide or thick field oxide and the polysilicon, controlling the size of the thick gate oxide or thick field oxide protruding beyond the polysilicon within a certain process tolerance, while increasing the source / drain injection energy to ensure normal conduction. Of the two solutions mentioned above, adding a photomask will significantly increase the process cost; while the overlay error control solution will significantly increase the process difficulty, and the process fluctuations of the production line will be significantly reflected in the device, resulting in a small device window. At the same time, due to the adjustment of the source-drain injection scheme, the integration of high-voltage processes on the original low-voltage process will be limited, and the process scalability will be reduced.

[0037] Figure 1 This is a flowchart of a method for manufacturing a dual-gate structure according to an embodiment of this application, including the following steps:

[0038] S110, Obtain a wafer on which a first gate dielectric layer and a second gate dielectric layer are formed on a substrate.

[0039] See Figure 2a A first gate dielectric layer 222 is formed in a portion of the substrate 210, and a second gate dielectric layer 224 is formed in a portion of the substrate 210. The thickness of the first gate dielectric layer 222 is greater than the thickness of the second gate dielectric layer 224. In one embodiment of this application, the first gate dielectric layer 222 is a thick gate oxide, and the second gate dielectric layer 224 is a thin gate oxide.

[0040] In one embodiment of this application, the substrate 210 is a semiconductor substrate, and its material can be undoped single-crystal silicon, doped single-crystal silicon, silicon-on-insulator (SOI), silicon-on-insulator stacked (SSOI), silicon-on-insulator stacked (S-SiGeOI), silicon-on-insulator (SiGeOI), and germanium-on-insulator (GeOI), etc., or it can be at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, or other III / V compound semiconductors. Figure 2aIn the illustrated embodiment, the substrate 210 is made of monocrystalline silicon. Isolation structures such as STI (shallow trench isolation) can also be formed on the substrate 210.

[0041] In one embodiment of this application, the first gate dielectric layer 222 and the second gate dielectric layer 224 may comprise conventional dielectric materials such as silicon oxides, nitrides, and oxynitrides having a dielectric constant from about 4 to about 20 (measured in vacuum). Alternatively, the first gate dielectric layer 222 and the second gate dielectric layer 224 may comprise dielectric materials with generally higher dielectric constants, ranging from about 20 to at least about 100. Such higher dielectric constant dielectric materials may include, but are not limited to, hafnium oxide, hafnium silicate, titanium oxide, barium strontium titanate (BSTs), and lead zirconate titanate (PZTs).

[0042] S120, a gate material layer is formed on the first gate dielectric layer and the second gate dielectric layer.

[0043] See Figure 2b In one embodiment of this application, the gate material layer 230 is made of polysilicon; in other embodiments, metals, metal nitrides, metal silicides or similar compounds may also be used as the material of the gate material layer 230.

[0044] In one embodiment of this application, the gate material layer 230 can be formed using chemical vapor deposition (CVD), such as low-temperature chemical vapor deposition (LTCVD), low-pressure chemical vapor deposition (LPCVD), thermally accelerated chemical vapor deposition (LTCVD), and plasma chemical vapor deposition (PECVD). Alternatively, methods such as sputtering and physical vapor deposition (PVD) can be used. The thickness of the gate material layer 230 can be adjusted according to the device dimensions and is not specifically limited herein.

[0045] S130, a photolithographic anti-reflection layer is formed on the gate material layer.

[0046] In one embodiment of this application, the material of the photolithographic antireflective layer 232 is silicon oxynitride.

[0047] S140, photolithography and etching of the anti-reflection layer and gate material layer.

[0048] Photoresist was coated onto the anti-reflective layer 232, exposed to the photoresist using a polysilicon gate photomask, and then developed using a developer. The resulting photoresist pattern is shown below. Figure 2c As shown, the photolithographic anti-reflection layer 232 and the gate material layer 230 are then etched to form the first gate 231 on the first gate dielectric layer 222, and the second gate is formed on the second gate dielectric layer 224. Figure 2d and Figure 2eThe second gate is not shown. In one embodiment of this application, the first gate is the gate of a high-voltage device, and the second gate is the gate of a low-voltage device. To avoid overlay errors causing the first gate 231 to extend beyond the first gate dielectric layer 222, the polysilicon gate photomask pattern is designed so that the width of the first gate 231 is smaller than the width of the first gate dielectric layer 222, and the photomask pattern of the first gate 231 is located inside the first gate dielectric layer 222 on both sides during photolithography alignment. See also Figure 2d ,exist Figure 2d In the embodiment shown, the width of the first gate dielectric layer 222 is greater than the width of the first gate 231, and both sides of the first gate dielectric layer 222 extend from the bottom of the first gate 231.

[0049] S150, remove the photoresist, and then dry etch to remove the first gate dielectric layer extending from the bottom of the first gate.

[0050] The photoresist 240 is removed, and then the first gate dielectric layer 222 and the second gate dielectric layer 224 are dry-etched, that is, the first gate dielectric layer 222 extending from the bottom of the first gate 231 is dry-etched, and the photolithographic anti-reflection layer 232 serves as a barrier layer for dry etching. By controlling the etching conditions, the photolithographic anti-reflection layer 232 is not completely etched before the first gate dielectric layer 222 extending from the bottom of the first gate 231 is completely etched.

[0051] In one embodiment of this application, the excess first gate dielectric layer 222 is etched by utilizing the difference in etching selectivity between the material of the photolithographic anti-reflection layer 232 and the first gate dielectric layer 222 and the substrate 210. To ensure that this step does not etch the first gate 231 and the substrate 210, the thickness of the photolithographic anti-reflection layer 232 formed in step S130 and the dry etching process in step S150 are specifically adjusted. The adjustment of the etching process may include adjustments to factors such as gas source, plasma, etching equipment capability, and etching mechanism. The adjustment of the etching gas may include adjustments to the gas type, concentration, mixing ratio, and usage time. The adjustment of the plasma may include adjustments to the coil, radio frequency power (RF power), and temperature. The adjustment of the equipment capability may include adjustments to factors such as viscosity coefficient and equipment environment.

[0052] In one embodiment of this application, the etching selectivity ratio of SiON in the anti-reflection layer 232 to silicon dioxide in the first gate dielectric layer 222 during dry etching in step S150 is between 1:1 and 1:2, ensuring that the first gate dielectric layer 222 is completely etched even before SiON is fully etched. The gas ratio used is crucial for adjusting the etching selectivity ratio. In one embodiment of this application, the gas source for dry etching in step S150 includes O2, CF4, C4F8, CHF3, etc., and the etching is performed in stages for 10 to 90 seconds.

[0053] In one embodiment of this application, the etching is monitored using an end-point monitoring mechanism. The end-point is monitored by tracking changes in the etching rate curve. This ensures that the first gate dielectric layer 222 and the second gate dielectric layer 224, which are not covered by the first gate 231, are thoroughly etched, while the photolithographic anti-reflection layer 232 is also thoroughly etched, and the substrate 210, the first gate 231, and the second gate are not over-etched. See also... Figure 2d and Figure 2e This application does not require additional high-precision overlay etching of the first gate 231 and the first gate dielectric layer 222. The self-aligned etching of the first gate dielectric layer 222 can be completed by ordinary etching, and the boundary of the etched first gate dielectric layer 222 is automatically aligned with the boundary of the first gate 231.

[0054] S160, source and drain injections are performed on both sides of the first gate.

[0055] Doped ions are implanted on both sides of the first gate 231 to form source and drain regions. Since the portion of the first gate dielectric layer 222 extending beyond the bottom of the first gate 231 has been removed in step S150, the source and drain implantation is not blocked by the excess first gate dielectric layer 222, and the source and drain implantation can be fully implanted into the substrate 210, thereby ensuring that the device does not experience trench breakage.

[0056] See Figure 3 In one embodiment of this application, Figure 2a The structure shown can be formed in the following ways:

[0057] S102, a first dielectric layer is formed in a first region on the substrate.

[0058] In one embodiment of this application, a first dielectric layer can be grown on substrate 210 by thermal oxidation process, and the first dielectric layer outside the first region of the substrate can be removed by photolithography and etching, leaving only the first dielectric layer in the first region.

[0059] In another embodiment of this application, a mask layer is formed on substrate 210, the mask layer is photolithographically and etched to expose the substrate in a first region, and the mask layer is removed after a first dielectric layer is grown on the exposed substrate in the first region.

[0060] S104, a second dielectric layer is formed on the substrate and the first dielectric layer.

[0061] The first dielectric layer and the second dielectric layer of the first region together serve as the first gate dielectric layer 222, and the second dielectric layer outside the first region serves as the second gate dielectric layer 224.

[0062] The second dielectric layer can be grown on the substrate 210 and the first dielectric layer by a thermal oxidation process.

[0063] Based on the same inventive concept, this application further provides a method for manufacturing a field oxygen structure. Figure 4 This is a flowchart of a method for manufacturing a field oxygen structure in one embodiment, including the following steps:

[0064] S410, to obtain a wafer on a substrate having a field oxide layer and a gate dielectric layer formed thereon.

[0065] See Figure 5a A field oxide layer 522 is formed in a portion of the substrate 510, and a gate dielectric layer 524 is formed in a portion of the substrate 510. The thickness of the field oxide layer 522 is greater than the thickness of the gate dielectric layer 524. In one embodiment of this application, the gate dielectric layer 524 is a gate oxide layer.

[0066] In one embodiment of this application, the substrate 510 is a semiconductor substrate, and its material can be undoped single-crystal silicon, doped single-crystal silicon, silicon-on-insulator (SOI), silicon-on-insulator stacked (SSOI), silicon-on-insulator stacked (S-SiGeOI), silicon-on-insulator (SiGeOI), and germanium-on-insulator (GeOI), etc., or it can be at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, or other III / V compound semiconductors. Figure 5a In the illustrated embodiment, the substrate 510 is made of monocrystalline silicon. Isolation structures such as STI (shallow trench isolation) can also be formed on the substrate 510.

[0067] In one embodiment of this application, the field oxide layer 522 and the gate dielectric layer 524 may comprise conventional dielectric materials such as silicon oxides, nitrides, and oxynitrides having a dielectric constant from about 4 to about 20 (measured in vacuum). Alternatively, the field oxide layer 522 and the gate dielectric layer 524 may comprise dielectric materials with generally higher dielectric constants, ranging from about 20 to at least about 100. Such higher dielectric constant dielectric materials may include, but are not limited to, hafnium oxide, hafnium silicate, titanium oxide, barium strontium titanate (BSTs), and lead zirconate titanate (PZTs).

[0068] S420 forms a gate material layer on the field oxide layer and the gate dielectric layer.

[0069] See Figure 5b In one embodiment of this application, the gate material layer 530 is made of polysilicon; in other embodiments, metals, metal nitrides, metal silicides or similar compounds may also be used as the material of the gate material layer 530.

[0070] In one embodiment of this application, the gate material layer 530 can be formed using chemical vapor deposition (CVD), such as low-temperature chemical vapor deposition (LTCVD), low-pressure chemical vapor deposition (LPCVD), thermally accelerated chemical vapor deposition (LTCVD), and plasma chemical vapor deposition (PECVD). Alternatively, methods such as sputtering and physical vapor deposition (PVD) can be used. The thickness of the gate material layer 530 can be adjusted according to the device dimensions and is not specifically limited herein.

[0071] S430, a photolithographic anti-reflection layer is formed on the gate material layer.

[0072] In one embodiment of this application, the material of the photolithographic antireflective layer 532 is silicon oxynitride.

[0073] S440, photolithography and etching of the anti-reflective layer and gate material layer.

[0074] Photoresist was coated onto the anti-reflective layer 532, exposed to the photoresist using a polysilicon gate photomask, and then developed using a developer. The resulting photoresist pattern is shown below. Figure 5c As shown, the photolithographic anti-reflection layer 532 and the gate material layer 530 are then etched to obtain the gate layer 531. The first side of the gate layer 531 (i.e. Figure 5d The left side of the gate layer 531 extends from the edge of the field oxide layer 522 onto the gate dielectric layer 524. To avoid overlay errors causing damage to the second side of the gate layer 531 (i.e., the left side of the gate layer 531), Figure 5d The right side of the gate layer 531 extends beyond the field oxide layer 522; therefore, the polysilicon gate photomask pattern is designed so that the second side of the photomask pattern of the gate layer 531 is located inside the field oxide layer 522 during photolithography alignment. See also... Figure 5d ,exist Figure 5d In the illustrated embodiment, the field oxide layer 522 extends from the bottom of the second side of the gate layer 531.

[0075] S450, remove the photoresist, and then dry etch to remove the field oxide layer extending from the bottom of the second side of the gate layer.

[0076] The photoresist 540 is removed, and then the field oxide layer 522 and the gate dielectric layer 524 are dry-etched, specifically, the field oxide layer 522 extending from the bottom of the gate layer 531 is dry-etched, with the photolithographic anti-reflection layer 532 acting as a barrier layer for dry etching. By controlling the etching conditions, the photolithographic anti-reflection layer 532 is prevented from being completely etched before the field oxide layer 522 extending from the bottom of the gate layer 531 is completely etched.

[0077] In one embodiment of this application, the etching of excess gate dielectric layer 522 is completed by utilizing the difference in etching selectivity between the material of photolithographic antireflective layer 532 and the gate dielectric layer 522 and substrate 510. To ensure that this step does not etch into gate layer 531 and substrate 510, the thickness of photolithographic antireflective layer 532 formed in step S430 and the dry etching process in step S450 are specifically adjusted. Adjustments to the etching process may include adjustments to factors such as gas source, plasma, etching equipment capability, and etching mechanism. Adjustments to the etching gas may include adjustments to gas type, concentration, mixing ratio, and usage time. Adjustments to the plasma may include adjustments to coil, RF power, and temperature. Adjustments to equipment capability may include adjustments to factors such as viscosity coefficient and equipment environment.

[0078] In one embodiment of this application, the etching selectivity ratio of SiON in the antireflective layer 532 to silicon dioxide in the field oxide layer 522 during dry etching in step S450 is between 1:1 and 1:2, ensuring that the field oxide layer 522 is completely etched even before SiON is fully etched. The gas ratio used is crucial for modulating the selectivity ratio. In one embodiment of this application, the gas source for dry etching in step S450 includes O2, CF4, C4F8, CHF3, etc., and the etching is performed in stages for 10–90 seconds.

[0079] In one embodiment of this application, the etching is monitored using an end-point monitoring mechanism. The end-point is monitored by tracking changes in the etching rate curve. This ensures that the field oxide layer 522 not covered by the gate layer 531 and the gate dielectric layer 524 not covered by the gate layer 531 are thoroughly etched, while also thoroughly etching the photolithographic anti-reflection layer 532, and preventing over-etching of the substrate 510 and the gate layer 531. See also... Figure 5d and Figure 5e This application does not require the additional high-precision overlay of the gate layer 531 and the field oxide layer 522. The self-aligned etching of the field oxide layer 522 can be completed by ordinary etching, and the boundary of the etched field oxide layer 522 is automatically aligned with the boundary of the gate layer 531.

[0080] S460 performs source / drain implantation into the substrate.

[0081] Since the portion of the field oxide layer 522 extending beyond the bottom of the gate layer 531 has been removed in step S450, the source / drain injection will not be blocked by the excess field oxide layer 522, thereby ensuring that the device does not experience trench breakage.

[0082] See Figure 6 In one embodiment of this application, Figure 5a The structure shown can be formed in the following ways:

[0083] S402, a first oxide layer is formed on the substrate.

[0084] In one embodiment of this application, a first oxide layer can be grown on substrate 510 by a thermal oxidation process.

[0085] S404 removes the first oxide layer in the second region.

[0086] Excess first oxide layer is removed by photolithography and etching, leaving only the first oxide layer in the required areas.

[0087] S406, a gate dielectric layer is formed in the second region.

[0088] A gate dielectric layer 524 can be grown in the second region on the substrate 510 by a thermal oxidation process, and a gate dielectric layer 524 is also grown on the first oxide layer. The first oxide layer and the gate dielectric layer 524 on the first oxide layer together serve as the field oxide layer 522.

[0089] The aforementioned manufacturing methods for the dual-gate structure and the field-oxygen structure can be applied to the BCD process. That is, the BCD process can include the steps in the manufacturing method for the dual-gate structure and / or the steps in the manufacturing method for the field-oxygen structure. Compared to the two exemplary solutions, the aforementioned manufacturing methods for the dual-gate structure and the field-oxygen structure can reduce costs, simplify process control, and provide effective compatibility and scalability for integrating low-voltage and high-voltage processes in the BCD process, thus enhancing the overall competitiveness of the process platform.

[0090] It should be understood that although the steps in the flowchart of this application are shown sequentially as indicated by the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowchart of this application may include multiple steps or multiple stages, which are not necessarily completed at the same time, but may be executed at different times, and the execution order of these steps or stages is not necessarily sequential, but may be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0091] In the description of this specification, references to terms such as "some embodiments," "other embodiments," and "ideal embodiments" indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0092] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0093] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. A method for manufacturing a dual-gate structure, comprising: A wafer is obtained, wherein a first gate dielectric layer and a second gate dielectric layer are formed on a substrate, and the thickness of the second gate dielectric layer is less than that of the first gate dielectric layer; A gate material layer is formed on the first gate dielectric layer and the second gate dielectric layer; A photolithographic anti-reflection layer is formed on the gate material layer; Photoresist is coated on the photolithographic anti-reflection layer, exposed and developed using a polysilicon gate photomask, and then the photolithographic anti-reflection layer and the gate material layer are etched to form a first gate on the first gate dielectric layer and a second gate on the second gate dielectric layer; the width of the first gate dielectric layer is greater than the width of the first gate and both sides of the first gate dielectric layer extend from the bottom of the first gate. The photoresist is removed, and then the first gate dielectric layer extending from the bottom of the first gate is dry etched, with the photolithographic anti-reflection layer serving as a barrier layer for the dry etching; the etching conditions are controlled so that the photolithographic anti-reflection layer is not completely etched before the extended first gate dielectric layer is completely etched. Source and drain injections are performed on both sides of the first gate.

2. The manufacturing method of the dual-gate structure according to claim 1, characterized in that, The photolithographic antireflective layer is made of silicon oxynitride.

3. The manufacturing method of the dual-gate structure according to claim 1, characterized in that, Both the first gate dielectric layer and the second gate dielectric layer are gate oxide layers.

4. The manufacturing method of the dual-gate structure according to claim 1, characterized in that, The gate material layer is made of polycrystalline silicon.

5. The method for manufacturing a dual-grid structure according to claim 1, characterized in that, The steps for obtaining the wafer include: A first dielectric layer is formed in a first region on the substrate; A second dielectric layer is formed on the substrate and the first dielectric layer; Wherein, the first dielectric layer of the first region and the second dielectric layer of the first region together serve as the first gate dielectric layer, and the second dielectric layer outside the first region serves as the second gate dielectric layer.

6. A method for manufacturing a field oxygen structure, comprising: Obtain a wafer having a field oxide layer and a gate dielectric layer formed on a substrate, wherein the thickness of the gate dielectric layer is less than that of the field oxide layer; A gate material layer is formed on the field oxide layer and the gate dielectric layer; A photolithographic anti-reflection layer is formed on the gate material layer; Photoresist is coated on the photolithographic anti-reflection layer, exposed and developed using a polysilicon gate photomask, and then the photolithographic anti-reflection layer and the gate material layer are etched to obtain a gate layer. One side of the gate layer extends from the edge of the field oxide layer to the gate dielectric layer, and the other side is shorter than the field oxide layer, so that the field oxide layer extends from the bottom of the other side of the gate layer. The photoresist is removed, and then the field oxide layer extending from the bottom of the other side of the gate layer is dry etched, with the photolithographic anti-reflection layer serving as a barrier layer for the dry etching; the photolithographic anti-reflection layer is not completely etched before the extended field oxide layer is completely etched by controlling the etching conditions. Source / drain implantation is performed into the substrate.

7. The method for manufacturing a field oxygen structure according to claim 6, characterized in that, The steps for obtaining the wafer include: A first oxide layer is formed on the substrate; Remove the first oxide layer in the second region; A gate dielectric layer is formed in the second region, and the gate dielectric layer formed simultaneously on the first oxide layer together with the first oxide layer serves as the field oxide layer.

8. The method for manufacturing a field oxygen structure according to claim 6, characterized in that, The photolithographic antireflective layer is made of silicon oxynitride.

9. The method for manufacturing a field oxygen structure according to claim 6, characterized in that, The gate material layer is made of polycrystalline silicon.

10. A method for manufacturing a semiconductor device, applied in a BCD process, characterized in that, The method includes the steps of the manufacturing method of the dual-gate structure according to any one of claims 1-5, and / or the steps of the manufacturing method of the field oxygen structure according to any one of claims 6-9.

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