Image sensor readout circuit, image sensor and method of operation thereof

Abstract

The application discloses an image sensor readout circuit, an image sensor and a working method thereof, and belongs to the field of sensors. An amplifier circuit amplifies and inverts a low-gain image signal and a low-gain reset signal to output an inverted low-gain amplified image signal and an inverted low-gain amplified reset signal. A switch selection circuit sequentially outputs a high-gain reset signal and a high-gain image signal according to a first control signal, and sequentially outputs the inverted low-gain amplified image signal and the inverted low-gain amplified reset signal according to a second control signal. An analog-to-digital conversion circuit quantizes the high-gain reset signal and the high-gain image signal to obtain high-gain effective image signal quantization values, and quantizes the inverted low-gain amplified image signal and the inverted low-gain amplified reset signal to obtain low-gain effective image signal quantization values. The application realizes a high dynamic range of the image sensor, saves hardware cost, reduces the volume and improves the readout speed.

Description

Technical Field

[0001] This application belongs to the field of sensors, and in particular relates to an image sensor readout circuit, an image sensor, and a method for operating the same. Background Technology

[0002] High dynamic range is required in image sensor applications to capture information from both bright and dark scenes. Common methods to improve dynamic range include increasing the full-well charge capacity and multi-frame image synthesis. Dual Conversion Gain (DCG) modifies the conversion gain by changing the size of the integrating capacitor. A small capacitor is used to increase conversion gain in low-light conditions, while a large capacitor is used to decrease conversion gain in high-light conditions to provide high dynamic range. For example... Figure 1 As shown, the image sensor readout circuit in DCG mode uses two comparators to read out the low-conversion-gain output signal and the high-conversion-gain output signal of a single pixel, respectively. A single pixel sequentially outputs a high-gain image signal and a low-gain image signal in one readout cycle. Therefore, two counters are needed to quantize the signals. During one quantization cycle, a single comparator circuit and a single counter are not working for half a cycle. Therefore, the related image sensor readout circuit suffers from slow readout speed, high cost, and large size. Summary of the Invention

[0003] The purpose of this application is to provide an image sensor readout circuit, an image sensor, and a method for operating the same, in order to solve the shortcomings of existing image sensor readout circuits, such as slow readout speed, high cost, and large size.

[0004] This application provides an image sensor readout circuit, including:

[0005] An amplifier circuit is connected to the pixel circuit of the image sensor. The pixel circuit is configured to sequentially output a high-gain reset signal, a high-gain image signal, a low-gain image signal, and a low-gain reset signal. The amplifier circuit is configured to amplify and invert the low-gain image signal and the low-gain reset signal to output an inverted low-gain amplified image signal and an inverted low-gain amplified reset signal.

[0006] A switch selection circuit, connected to the pixel circuit and the amplifier circuit, is configured to sequentially receive the high-gain reset signal, the high-gain image signal, the inverted low-gain amplified image signal, and the inverted low-gain amplified reset signal, and sequentially output the high-gain reset signal and the high-gain image signal according to a first control signal, and sequentially output the inverted low-gain amplified image signal and the inverted low-gain amplified reset signal according to a second control signal;

[0007] An analog-to-digital converter circuit, connected to the switch selection circuit, is configured to quantize the high-gain reset signal and the high-gain image signal to obtain the quantized value of the effective image signal under high gain, and to quantize the inverted low-gain amplified image signal and the inverted low-gain amplified reset signal to obtain the quantized value of the effective image signal under low gain.

[0008] This application also provides an image sensor, including:

[0009] The pixel circuit is configured to sequentially output a high-gain reset signal, a high-gain image signal, a low-gain image signal, and a low-gain reset signal; and

[0010] The image sensor readout circuit described above.

[0011] This application also provides an electronic device including the image sensor described above.

[0012] This application also provides a method for operating an image sensor readout circuit, including:

[0013] Input a first control signal to cause the switch selection circuit to output the high-gain reset signal and the high-gain image signal in sequence, and cause the analog-to-digital conversion circuit to quantize the high-gain reset signal and the high-gain image signal to obtain the quantized value of the effective image signal under high gain;

[0014] A second control signal is input so that the switch selection circuit sequentially outputs the inverted low-gain amplified image signal and the inverted low-gain amplified reset signal; and the analog-to-digital conversion circuit quantizes the inverted low-gain amplified image signal and the inverted low-gain amplified reset signal to obtain the quantized value of the effective image signal under low gain.

[0015] The beneficial effects of this invention compared to existing technologies are as follows: Since the low-gain image signal is processed using an amplifier circuit, a single analog-to-digital converter (ADC) can quantize both the low-gain and high-gain image signals output from a single pixel. This achieves a high dynamic range for the image sensor while saving hardware costs and reducing size. Furthermore, the ADC eliminates waiting time during quantization, improving the image signal readout speed. Attached Figure Description

[0016] To more clearly illustrate the technical inventions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 A schematic diagram of a readout circuit for an image sensor in a related technology;

[0018] Figure 2 This is a schematic diagram of the structure of an image sensor readout circuit provided in an embodiment of this application;

[0019] Figure 3 This is a schematic diagram of an analog-to-digital conversion circuit in an image sensor readout circuit according to an embodiment of this application;

[0020] Figure 4 An example circuit diagram of an image sensor readout circuit provided in an embodiment of this application;

[0021] Figure 5 yes Figure 4 The timing diagram of the image sensor readout circuit is shown. Detailed Implementation

[0022] To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.

[0023] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0024] It should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0025] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0026] Figure 2A schematic diagram of the image sensor readout circuit provided in Embodiment 1 of this application is shown. For ease of explanation, only the parts relevant to this embodiment are shown, and are described in detail below:

[0027] The image sensor readout circuit described above includes an amplifier circuit 12, a switch selection circuit 13, and an analog-to-digital conversion circuit 14.

[0028] The pixel circuit 11 is configured to sequentially output a high-gain image signal and a low-gain image signal.

[0029] Amplifier circuit 12 is connected to pixel circuit 11 of image sensor. Pixel circuit 11 is configured to output high-gain reset signal, high-gain image signal, low-gain image signal and low-gain reset signal in sequence. Amplifier circuit 12 is configured to amplify and invert the low-gain image signal and low-gain reset signal to output inverted low-gain amplified image signal and inverted low-gain amplified reset signal.

[0030] The switch selection circuit 13 is connected to the pixel circuit 11 and the amplifier circuit 12. It is configured to sequentially receive a high-gain reset signal, a high-gain image signal, an inverted low-gain amplified image signal, and an inverted low-gain amplified reset signal. It sequentially outputs the high-gain reset signal and the high-gain image signal according to the first control signal, and sequentially outputs the inverted low-gain amplified image signal and the inverted low-gain amplified reset signal according to the second control signal.

[0031] The analog-to-digital converter circuit 14 is connected to the switch selection circuit 13 and is configured to quantize the high-gain reset signal and the high-gain image signal to obtain the quantized value of the effective image signal under high gain, and to quantize the inverted low-gain amplified image signal and the inverted low-gain amplified reset signal to obtain the quantized value of the effective image signal under low gain.

[0032] Here, high-gain image signal refers to the image signal under high conversion gain; low-gain image signal refers to the image signal under low conversion gain. High-gain reset signal refers to the reset signal under high conversion gain; low-gain reset signal refers to the reset signal under low conversion gain. The effective image signal quantization value under high gain refers to the difference between the high-gain reset signal and the high-gain image signal; the effective image signal quantization value under low gain refers to the difference between the low-gain reset signal and the low-gain image signal.

[0033] The high-gain image signal and the low-gain image signal are acquired through the same exposure.

[0034] By combining a high-gain reset signal to quantize a high-gain image signal and a low-gain reset signal to quantize a low-gain image signal, the quantization accuracy is improved.

[0035] like Figure 3As shown, the analog-to-digital converter circuit 14 includes a comparator circuit 141, a counter 142, and a memory 143 connected in sequence;

[0036] The comparator circuit 141 includes a comparator with a ramp voltage connected to its non-inverting input and a switch selection circuit 13 connected to its inverting input.

[0037] In a specific implementation, when the analog-to-digital converter 14 quantizes the high-gain reset signal, the comparator circuit 141 is configured to compare the ramp voltage and the high-gain reset signal and output a first comparison signal; the counter 142 is configured to count down when the first comparison signal is received, and record the first counting result when the state of the first comparison signal flips (e.g., from high level to low level, or from low level to high level). In one specific embodiment, when the first comparison signal is 0, the counter stops counting and records the first counting result.

[0038] In a specific implementation, when the analog-to-digital converter circuit 14 quantizes the high-gain image signal, the comparator circuit 141 is configured to compare the ramp voltage and the high-gain image signal and output a second comparison signal; the counter 142 is configured to count upwards from the first counting result when the second comparison signal is received, and output the second counting result when the state of the second comparison signal flips. The second counting result is the difference between the quantization result of the high-gain reset signal and the quantization result of the high-gain image signal; the memory 143 is configured to store the second counting result and use the second counting result as the quantization value of the effective image signal under high gain.

[0039] In a specific implementation, when the analog-to-digital converter circuit 14 quantizes the inverted low-gain amplified image signal, the comparator circuit 141 is configured to compare the ramp voltage and the inverted low-gain amplified image signal and output a third comparison signal; the counter 142 is configured to count down when the third comparison signal is received, and record the third counting result when the state of the third comparison signal flips.

[0040] In a specific implementation, when the analog-to-digital converter circuit 14 quantizes the inverted low-gain amplified reset signal, the comparator circuit 141 is configured to compare the ramp voltage and the inverted low-gain amplified reset signal and output a fourth comparison signal; the counter 142 is configured to start counting upwards from the third counting result when the fourth comparison signal is received, and output the fourth counting result when the state of the fourth comparison signal flips. The fourth counting result is the difference between the quantization result of the inverted low-gain amplified image signal and the quantization result of the inverted low-gain amplified reset signal; the memory 143 is configured to store the fourth counting result and use the fourth counting result as the quantization value of the effective image signal under low gain.

[0041] The comparison circuit 141, counter 142 and memory 143 connected in sequence above realize the quantization processing of low-gain amplified image signals and high-gain image signals, and realize the quantization dual-conversion gain mode of a single analog-to-digital converter circuit 14. While achieving the high dynamic range of the image sensor, the cost is reduced and the size is reduced.

[0042] As an example and not a limitation, the reference voltage is adjustable.

[0043] The gain of the circuit in low conversion gain mode can be further improved by adjusting the reference voltage.

[0044] As an example rather than a limitation, the slope of the ramp voltage is adjustable.

[0045] During the quantization process of the output of pixel circuit 11, the slopes of its low conversion gain downslope voltage and high conversion gain downslope voltage can be set to be different, thus further improving the circuit gain and thereby further increasing the dynamic range of the image sensor.

[0046] This application also provides an image sensor, including the image sensor readout circuit described above.

[0047] This invention also provides a method for operating an image sensor readout circuit, including steps 101 to 102.

[0048] Step 101: Step A: Input the first control signal so that the switch selection circuit outputs the high-gain reset signal and the high-gain image signal in sequence, and causes the analog-to-digital converter circuit 14 to quantize the high-gain reset signal and the high-gain image signal to obtain the quantized value of the effective image signal under high gain.

[0049] Step 102: Input the second control signal so that the switch selection circuit outputs the inverted low-gain amplified image signal and the inverted low-gain amplified reset signal in sequence; and make the analog-to-digital converter circuit 14 quantize the inverted low-gain amplified image signal and the inverted low-gain amplified reset signal to obtain the quantized value of the effective image signal under low gain.

[0050] When the analog-to-digital conversion circuit 14 includes a comparator circuit 141, a counter 142, and a memory 143, step 100 includes steps A1, B1, A2, B2, and C2.

[0051] Step A1: Comparison circuit 141 compares the ramp voltage and the high-gain reset signal, and outputs the first comparison signal;

[0052] Step B1: When the counter 142 receives the first comparison signal, it counts down, and when the state of the first comparison signal flips, it records the first counting result.

[0053] Step A2: Comparison circuit 141 compares the ramp voltage and the high-gain image signal and outputs a second comparison signal;

[0054] Step B2: When the second comparison signal is received, the counter 142 starts counting upward from the first counting result, and when the state of the second comparison signal flips, it outputs the second counting result, which is the difference between the high-gain reset signal and the quantization result of the high-gain image signal.

[0055] Step C2: The memory 143 is configured to store the second counting result and use the second counting result as the effective image signal quantization value under high gain.

[0056] When the analog-to-digital conversion circuit 14 includes a comparator circuit 141, a counter 142, and a memory 143, step 102 includes steps A3, B3, A4, B4, and C4.

[0057] Step A3: Comparison circuit 141 compares the inverted low-gain amplified image signal with the ramp voltage and outputs a third comparison signal;

[0058] Step B3: When the counter 142 receives the third comparison signal, it counts down, and when the state of the third comparison signal flips, it records the third count result.

[0059] Step A4: Comparison circuit 141 compares the inverted low-gain amplified reset signal with the ramp voltage and outputs the fourth comparison signal;

[0060] Step B4: Counter 142 is configured to start counting upwards from the third counting result when the fourth comparison signal is received, and to output the fourth counting result when the state of the fourth comparison signal flips. The fourth counting result is the difference between the quantization result of the inverted low-gain amplified image signal and the inverted low-gain amplified reset signal.

[0061] Step C4: Memory 143 is configured to store the fourth counting result and use the fourth counting result as the effective image signal quantization value under low gain.

[0062] When the analog-to-digital conversion circuit 14 includes a comparator circuit 141, a counter 142, and a memory 143, step 99 is included before the analog-to-digital conversion circuit quantizes the high-gain reset signal and before the analog-to-digital conversion circuit quantizes the inverted low-gain amplified image signal.

[0063] Step 99: Clear the comparator circuit 141.

[0064] Figure 4An example circuit structure of an image sensor readout circuit provided in an embodiment of the present invention is shown. For ease of explanation, only the parts related to the embodiment of the present invention are shown, and are described in detail below:

[0065] Pixel circuit 11 includes a reset transistor RST, a dual-conversion gain transistor DCG, a transmission transistor TX, a source follower transistor SF, a row selection transistor RS, a photoelectric conversion element PD, and a dual-conversion gain capacitor Cdcg.

[0066] The drain of the reset transistor RST and the drain of the source follower transistor SF are connected to the first power supply PIXVDD. The source of the reset transistor RST is connected to the first terminal of the dual conversion gain capacitor Cdcg and the drain of the dual conversion gain transistor DCG. The source of the dual conversion gain transistor DCG, the gate of the source follower transistor SF, and the source of the transmission transistor TX are connected to the floating diffusion point FD. The drain of the transmission transistor TX is connected to the negative terminal of the photoelectric conversion element PD. The source of the source follower transistor SF is connected to the drain of the row selection transistor RS. The source of the row selection transistor RS serves as the output terminal of the pixel circuit 11 to output a high-gain image signal, a low-gain image signal, a high-gain reset signal, and a low-gain reset signal. The gate of the reset transistor RST is connected to the reset signal rst. The gate of the dual conversion gain transistor DCG is connected to the conversion gain control signal dcg. The gate of the row selection transistor RS is connected to the row selection signal rowsel. The gate of the transmission transistor TX is connected to the control signal tx. The second terminal of the dual conversion gain capacitor Cdcg is connected to the second power supply VC. The positive terminal of the photoelectric conversion element PD is connected to the power supply ground.

[0067] The comparator circuit 141 includes a comparator U1, a first capacitor C1, a second capacitor C2, a first reset switch cmp_az1, and a second reset switch cmp_az2.

[0068] The non-inverting input terminal of comparator U1 and the first terminal of the first reset switch cmp_az1 are connected to the first terminal of the first capacitor C1; the second terminal of the first capacitor C1 is connected to the ramp voltage; the inverting input terminal Vinn of comparator U1 and the first terminal of the second reset switch cmp_az2 are connected to the first terminal of the second capacitor C2; the second terminal of the second capacitor C2 serves as the input terminal of the comparator circuit 141 and is connected to the switch selection circuit 13 to sequentially receive the high-gain reset signal, the high-gain image signal, the inverted low-gain amplified image signal, and the inverted low-gain amplified reset signal; the first non-inverting output terminal Vop of comparator U1 is connected to the second terminal of the first reset switch cmp_az1, the first inverting output terminal Von of comparator U1 is connected to the second terminal of the second reset switch cmp_az2, and the output terminal Vout of comparator U1 serves as the output terminal of the comparator circuit 141 and is connected to the counter 142 to output the first comparison signal, the second comparison signal, the third comparison signal, and the fourth comparison signal.

[0069] By setting the first reset switch cmp_az1 and the second reset switch cmp_az2, the comparator U1 is reset in a timely manner, which improves the accuracy of the comparator circuit 141.

[0070] The first capacitor is a variable capacitor. Adjusting the variable capacitor can further improve the circuit gain.

[0071] The switch selection circuit 13 includes a selection switch, clamp_en.

[0072] The first input terminal of the selector switch clamp_en is used as the first input terminal of the switch selection circuit 13 and connected to the amplifier circuit 12 to sequentially receive the inverted low-gain amplified image signal and the inverted low-gain amplified reset signal; the second input terminal of the selector switch clamp_en is used as the second input terminal of the switch selection circuit 13 and connected to the pixel circuit 11 to sequentially receive the high-gain reset signal and the high-gain image signal; the output terminal of the selector switch clamp_en is used as the output terminal of the switch selection circuit 13 and connected to the analog-to-digital converter circuit 14 to sequentially output the high-gain reset signal, the high-gain image signal, the inverted low-gain amplified image signal, and the inverted low-gain amplified reset signal.

[0073] The switch selection circuit 13 is simple and reliable.

[0074] The amplifier circuit 12 includes amplifier U2, third capacitor C3, fourth capacitor C4, fifth capacitor C5, third reset switch cmp_az3, and fourth reset switch cmp_az4.

[0075] The non-inverting input terminal Vinp of amplifier U2 and the first terminal of the third reset switch cmp_az3 are connected to the first terminal of the third capacitor C3, and the second terminal of the third capacitor C3 is connected to the reference voltage. The inverting input terminal Vinn of amplifier U2, the first terminal of the fourth reset switch cmp_az4, and the first terminal of the fifth capacitor C5 are connected to the first terminal of the fourth capacitor C4. The second terminal of the fourth capacitor C4 serves as the input terminal of amplifier circuit 12, and is connected to pixel circuit 11 and switch selection circuit 13 to receive low-gain image signals and low-gain reset signals. The second terminal of the third reset switch cmp_az is connected to the first non-inverting output terminal Vop of amplifier U2, and the second terminal of the fourth reset switch cmp_az4 is connected to the first inverting output terminal Von of amplifier U2. The second terminal of the fifth capacitor C5 and the output terminal Vout of amplifier U2 together serve as the output terminal of amplifier circuit 12 to output the inverted low-gain amplified image signal and the inverted low-gain amplified reset signal.

[0076] The third and fifth capacitors are adjustable, and adjusting the capacitors can further improve the circuit gain.

[0077] By setting the third reset switch cmp_az3 and the fourth reset switch cmp_az4, amplifier U2 is reset in a timely manner, improving the accuracy of amplifier circuit 12. By connecting the low-gain image signal and the low-gain reset signal to the inverting input terminal Vinn of amplifier U2, the low-gain image signal and the low-gain reset signal are amplified and inverted.

[0078] The following is based on the working principle. Figure 4 Further explanation is provided below:

[0079] Figure 5 yes Figure 4 The timing diagram of the image sensor readout circuit is shown.

[0080] At time t0, the row selection signal rowsel is set to high level, the row selection transistor RS is turned on, and the selection switch colamp_en connects the output terminal pixout of pixel circuit 11 to the inverting input terminal Vinn of comparator U1.

[0081] At time t1, the first reset switch cmp_az1 and the second reset switch cmp_az2 are turned on, the non-inverting input terminal Vinp of comparator U1 and the first-stage non-inverting output terminal Vop of comparator U1 are shorted together, and the inverting input terminal Vinn of comparator U1 and the first-stage inverting output terminal Von of comparator U1 are shorted together, and comparator U1 begins to reset.

[0082] At time t2, the reset signal rst is set to low level; at time t3, the conversion gain control signal dcg is set to low level, the dual conversion gain transistor DCG is turned off, and a high-gain reset signal is obtained.

[0083] At time t4, the first reset switch cmp_az1 and the second reset switch cmp_az2 are disconnected.

[0084] At time t5, the ramp voltage Vramp begins to decrease, and counter 142 begins to count downwards. The ramp voltage Vramp is coupled to the non-inverting input Vinp of comparator U1 through a capacitor, and the high-gain reset signal pixout is coupled to the inverting input Vinn of the comparator through a capacitor. When the high-gain reset signal pixout and the ramp voltage Vramp overlap, the output of comparator U1 flips, and counter 142 stops counting, obtaining the quantized result of the high-gain reset signal (the first counting result).

[0085] At time t6, the high-gain reset signal quantization ends, and the ramp voltage Vramp returns to the reference state.

[0086] Between t7 and t8, the control signal tx is set to a high level, the transmission transistor TX is turned on, and the output terminal pixout of the pixel circuit 11 outputs a high-gain image signal.

[0087] At time t9, the ramp voltage begins to decrease, and counter 142 begins to count upwards. The ramp voltage Vramp is coupled to the non-inverting input Vinp of comparator U1 through a capacitor, and the high-gain image signal pixout is coupled to the inverting input Vinn of the comparator through a capacitor. When the high-gain image signal pixout and the ramp voltage Vramp overlap, the comparator output flips, and counter 142 stops counting, obtaining the difference between the high-gain image signal and the high-gain reset signal, which is the quantized value of the effective image signal under high gain.

[0088] At time t10, the high-gain image signal quantization ends, and the ramp voltage Vramp begins to return to the reference state.

[0089] At time t11, the selector switch colamp_en connects the output of amplifier U2 to the inverting input Vinn of comparator U1.

[0090] At time t12, the conversion gain control signal dcg is set to high level, and the dual conversion gain transistor DCG is turned on.

[0091] Between t13 and t14, the control signal tx is set to a high level, the transmission transistor TX is turned on, and the output terminal pixout of the pixel circuit 11 outputs a low-gain image signal.

[0092] At time t15, the first reset switch cmp_az1 and the second reset switch cmp_az2 are turned on, the third reset switch cmp_az3 and the fourth reset switch cmp_az4 are turned on, and amplifier U2 and comparator U1 begin to be reset.

[0093] At time t16, the first reset switch cmp_az1 and the second reset switch cmp_az2 are turned off, and the third reset switch cmp_az3 and the fourth reset switch cmp_az4 are turned off. The low-gain image signal is amplified and inverted by amplifier U2 to generate a low-gain amplified image signal, and the low-gain amplified image signal is input to the inverting input terminal Vinn of comparator U1.

[0094] At time t18, the ramp voltage Vramp begins to decrease, and counter 142 begins to count downwards, obtaining the quantization result (third count result) of the low-gain amplified image signal.

[0095] At time t19, the quantization of the low-gain amplified image signal ends, and the ramp voltage Vramp begins to return to the reference state.

[0096] Between times t20 and t21, the reset signal rst is set to a high level, resulting in a low-gain reset signal. This low-gain reset signal is amplified and inverted by amplifier U2 to generate a low-gain amplified reset signal, which is then input to the inverting input Vinn of comparator U1.

[0097] At time t22, the ramp voltage Vramp begins to decrease, and counter 142 begins to count upwards, obtaining the difference between the low-gain amplified image signal and the low-gain amplified reset signal, which is the quantized value of the effective image signal under low gain.

[0098] At time t23, the quantization of the low-gain amplified reset signal ends, and the ramp voltage Vramp begins to return to the reference state.

[0099] At time t24, quantization ends, and the signals of the reset transistor RST and the selection switch colamp_en are reset, waiting for the next line of signals to arrive.

[0100] Among them, "overlapping" means that the two are equal and overlap.

[0101] In this embodiment of the invention, an amplifier circuit is connected to the pixel circuit of an image sensor. The pixel circuit sequentially outputs a high-gain reset signal, a high-gain image signal, a low-gain image signal, and a low-gain reset signal. The amplifier circuit amplifies and inverts the low-gain image signal and the low-gain reset signal to output an inverted low-gain amplified image signal and an inverted low-gain amplified reset signal. A switch selection circuit sequentially receives the high-gain reset signal, the high-gain image signal, and the inverted low-gain amplified image signal and the inverted low-gain amplified reset signal. Based on a first control signal, it sequentially outputs the high-gain reset signal and the high-gain image signal, and based on a second control signal, it sequentially outputs the inverted low-gain amplified image signal. The analog-to-digital converter (ADC) quantizes the high-gain reset signal and the high-gain image signal to obtain the quantized value of the effective image signal under high gain, and quantizes the inverted low-gain amplified image signal and the inverted low-gain amplified reset signal to obtain the quantized value of the effective image signal under low gain. Since the low-gain image signal is processed by the amplifier circuit, a single ADC can quantize the low-gain image signal and the high-gain image signal output from one pixel. This achieves a high dynamic range for the image sensor while saving hardware costs and reducing size. At the same time, the ADC has no waiting time during the quantization process, which improves the readout speed of the image signal.

[0102] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0103] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. An image sensor readout circuit, characterized by, The image sensor readout circuit comprises: an amplifier circuit connected with the pixel circuit of the image sensor, the pixel circuit being configured to sequentially output a high-gain reset signal, a high-gain image signal, a low-gain image signal and a low-gain reset signal; the amplifier circuit being configured to amplify and invert the low-gain image signal and the low-gain reset signal to output an inverted low-gain amplified image signal and an inverted low-gain amplified reset signal; a switch selection circuit connected with the pixel circuit and the amplifier circuit, configured to sequentially access the high-gain reset signal, the high-gain image signal and the inverted low-gain amplified image signal and the inverted low-gain amplified reset signal, and sequentially output the high-gain reset signal and the high-gain image signal according to a first control signal, and sequentially output the inverted low-gain amplified image signal and the inverted low-gain amplified reset signal according to a second control signal; an analog-to-digital conversion circuit connected with the switch selection circuit, configured to quantize the high-gain reset signal and the high-gain image signal to obtain an effective image signal quantization value under high gain, and quantize the inverted low-gain amplified image signal and the inverted low-gain amplified reset signal to obtain an effective image signal quantization value under low gain.

2. The image sensor readout circuit of claim 1, wherein, The analog-to-digital conversion circuit comprises a comparison circuit, a counter and a memory connected in sequence; The comparison circuit comprises a comparator, a positive input terminal of the comparator being connected with a ramp voltage, and a negative input terminal of the comparator being connected with the switch selection circuit.

3. The image sensor readout circuit of claim 2, wherein, When the analog-to-digital conversion circuit quantizes the high-gain reset signal, the comparison circuit is configured to compare the ramp voltage and the high-gain reset signal and output a first comparison signal; the counter is configured to count down when receiving the first comparison signal, and record a first count result when the state of the first comparison signal flips; When the analog-to-digital conversion circuit quantizes the high-gain image signal, the comparison circuit is configured to compare the ramp voltage and the high-gain image signal and output a second comparison signal; the counter is configured to count up from the first count result when receiving the second comparison signal, and output a second count result when the state of the second comparison signal flips, the second count result being a difference between a quantization result of the high-gain reset signal and a quantization result of the high-gain image signal; the memory is configured to store the second count result and take the second count result as the effective image signal quantization value under high gain; When the analog-to-digital conversion circuit quantizes the inverted low-gain amplified image signal, the comparison circuit is configured to compare the ramp voltage and the inverted low-gain amplified image signal and output a third comparison signal; the counter is configured to count down when receiving the third comparison signal, and record a third count result when the state of the third comparison signal flips. When the analog-to-digital conversion circuit quantizes the inverted low-gain amplified reset signal, the comparison circuit is configured to compare the ramp voltage and the inverted low-gain amplified reset signal and output a fourth comparison signal; the counter is configured to start counting up from the third counting result when the fourth comparison signal is received, and output a fourth counting result when the state of the fourth comparison signal is reversed, the fourth counting result being the difference between the quantization result of the inverted low-gain amplified image signal and the quantization result of the inverted low-gain amplified reset signal; and the memory is configured to store the fourth counting result and take the fourth counting result as the valid image signal quantization value under the low gain.

4. The image sensor readout circuit of claim 2, wherein, The comparison circuit comprises the comparator, a first capacitor, a second capacitor, a first clear switch and a second clear switch. The positive input end of the comparator and the first end of the first clear switch are connected to the first end of the first capacitor. The second end of the first capacitor is connected to the ramp voltage. The negative input end of the comparator and the first end of the second clear switch are connected to the first end of the second capacitor, and the second end of the second capacitor is connected to the switch selection circuit as an input end of the comparison circuit to sequentially connect the high-gain reset signal, the high-gain image signal, the inverted low-gain amplified image signal and the inverted low-gain amplified reset signal. The first positive output end of the comparator is connected to the second end of the first clear switch, the first negative output end of the comparator is connected to the second end of the second clear switch, and the output end of the comparator is connected to the counter as an output end of the comparison circuit to output the first comparison signal, the second comparison signal, the third comparison signal and the fourth comparison signal.

5. The image sensor readout circuit of claim 4, wherein, The first capacitor is a variable capacitor.

6. The image sensor readout circuit of claim 1, wherein, The switch selection circuit comprises a selection switch. The first input end of the selection switch is connected to the amplifier circuit as a first input end of the switch selection circuit to sequentially connect the inverted low-gain amplified image signal and the inverted low-gain amplified reset signal. The second input end of the selection switch is connected to the pixel circuit as a second input end of the switch selection circuit to sequentially connect the high-gain reset signal and the high-gain image signal. The output end of the selection switch is connected to the analog-to-digital conversion circuit as an output end of the switch selection circuit to sequentially output the high-gain reset signal, the high-gain image signal, the inverted low-gain amplified image signal and the inverted low-gain amplified reset signal.

7. The image sensor readout circuit of claim 5, wherein, The amplifier circuit comprises the amplifier, a third capacitor, a fourth capacitor, a fifth capacitor, a third clear switch and a fourth clear switch. The positive input end of the amplifier and the first end of the third clear switch are connected to the first end of the third capacitor, and the second end of the third capacitor is connected to a reference voltage. The negative input end of the amplifier is connected to the second end of the fourth capacitor, and the second end of the fourth capacitor is connected to the third clear switch as an input end of the amplifier circuit to sequentially connect the high-gain reset signal, the high-gain image signal, the inverted low-gain amplified image signal and the inverted low-gain amplified reset signal. The inverting input terminal of the amplifier, the first terminal of the fourth clear switch, and the first terminal of the fifth capacitor are connected to the first terminal of the fourth capacitor, and the second terminal of the fourth capacitor is used as the input terminal of the amplifier circuit and is connected to the pixel circuit and the switch selection circuit to access the low-gain image signal and the low-gain reset signal. The second terminal of the third clear switch is connected to the first non-inverting output terminal of the amplifier, and the second terminal of the fourth clear switch is connected to the first inverting output terminal of the amplifier. The second terminal of the fifth capacitor and the output terminal of the amplifier are used as the output terminal of the amplifier circuit to output the low-gain amplified image signal after inversion and the low-gain amplified reset signal after inversion.

8. The image sensor readout circuit of claim 7, wherein, The third capacitor and the fifth capacitor are adjustable.

9. The image sensor readout circuit of claim 2, wherein, The slope of the ramp voltage is adjustable.

10. An image sensor, characterized by The image sensor readout circuit comprises: a pixel circuit configured to sequentially output a high-gain reset signal, a high-gain image signal, a low-gain image signal, and a low-gain reset signal; and The image sensor readout circuit according to any one of claims 1 to 9.

11. An electronic device, comprising: The image sensor according to claim 10.

12. A method of operating a readout circuit for an image sensor as claimed in any one of claims 1-9, characterized by, The image sensor readout circuit comprises: inputting a first control signal to cause the switch selection circuit to sequentially output the high-gain reset signal and the high-gain image signal, and cause the analog-to-digital conversion circuit to quantize the high-gain reset signal and the high-gain image signal to obtain the valid image signal quantization value under high gain; inputting a second control signal to cause the switch selection circuit to sequentially output the low-gain amplified image signal after inversion and the low-gain amplified reset signal after inversion, and cause the analog-to-digital conversion circuit to quantize the low-gain amplified image signal after inversion and the low-gain amplified reset signal after inversion to obtain the valid image signal quantization value under low gain.

13. The method of operating a readout circuit for an image sensor as defined in claim 12, wherein, When the analog-to-digital conversion circuit comprises a comparison circuit, a counter, and a memory, the step of quantizing the high-gain reset signal, the high-gain image signal, the low-gain amplified image signal after inversion, and the low-gain amplified reset signal after inversion by the analog-to-digital conversion circuit comprises: the comparison circuit compares the ramp voltage with the high-gain reset signal and outputs a first comparison signal; the counter counts down when receiving the first comparison signal, and records a first count result when the state of the first comparison signal flips; the comparison circuit compares the ramp voltage with the high-gain image signal and outputs a second comparison signal; the counter counts up from the first count result when receiving the second comparison signal, and outputs a second count result when the state of the second comparison signal flips, the second count result being the difference between the quantization results of the high-gain reset signal and the high-gain image signal; the memory is configured to store the second count result and use the second count result as the valid image signal quantization value under high gain; the comparison circuit compares the low-gain amplified image signal after inversion with the ramp voltage and outputs a third comparison signal; The counter counts down when the third comparison signal is received, and records a third count result when the state of the third comparison signal flips; The comparison circuit compares the inverted low-gain amplified reset signal and the ramp voltage, and outputs a fourth comparison signal; The counter is configured to count up from the third count result when the fourth comparison signal is received, and outputs a fourth count result when the state of the fourth comparison signal flips, the fourth count result being a difference between the inverted low-gain amplified image signal and the inverted low-gain amplified reset signal quantization result; The memory is configured to store the fourth count result, and take the fourth count result as the low-gain valid image signal quantization value.

14. The method of operating a readout circuit for an image sensor as defined in claim 13, wherein, When the analog-to-digital conversion circuit includes the comparison circuit, the counter and the memory, before the analog-to-digital conversion circuit quantizes the high-gain reset signal and before the analog-to-digital conversion circuit quantizes the inverted low-gain amplified image signal, the analog-to-digital conversion circuit further includes: Clearing the comparison circuit.

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