semiconductor devices

Abstract

The present invention provides a technology that can improve the heat dissipation characteristics of a semiconductor device. The semiconductor device includes a heat sink, a layer component connected to the heat sink, a first semiconductor element, and a second semiconductor element. The first and second semiconductor elements are connected to the layer component on the side opposite to the heat sink, and are separated from each other by a gap. The heat sink includes a thick-walled portion and a thin-walled portion that is thinner than the thick-walled portion. The thin-walled portion is in contact with a groove provided on the surface of the heat sink opposite to the layer component, and overlaps with the gap when viewed from above.

Description

Technical Field

[0001] The present invention relates to semiconductor devices. Background Art

[0002] As a semiconductor device comprising multiple semiconductor elements, power modules are known in which the semiconductor elements are connected to a metal base for heat dissipation via an insulating substrate. For example, Patent Document 1 discloses a technique for suppressing thermal interference between semiconductor elements by providing grooves on the surface of the metal base facing the semiconductor elements.

[0003] Patent Document 1: International Publication No. 2013 / 141154 Summary of the Invention

[0004] Generally speaking, heat generated by semiconductor elements diffuses isotropically within components connected to the semiconductor elements, such as heat sinks. Specifically, heat generated by semiconductor elements is transferred and radiated at an angle of approximately 45 degrees relative to the main direction of heat transfer. In structures where semiconductor elements are placed close together to reduce the size of semiconductor devices, this isotropic heat transfer causes thermal interference beneath the semiconductor elements, where heat is superimposed. This thermal interference prevents efficient heat dissipation from the semiconductor elements.

[0005] The technology of Patent Document 1 has a problem that, although the grooves can prevent heat from each semiconductor element from being transferred to other semiconductor elements, thermal interference occurs as described above, resulting in poor heat dissipation characteristics of the semiconductor device.

[0006] The present invention has been made in view of the above-mentioned problems, and an object of the present invention is to provide a technology capable of improving the heat dissipation characteristics of a semiconductor device.

[0007] The semiconductor device according to the present invention comprises: a heat sink; a layer component connected to the heat sink; and a first semiconductor element and a second semiconductor element, which are connected to the layer component on the opposite side of the heat sink, and the first semiconductor element and the second semiconductor element are separated from each other by a gap. The heat sink includes: a thick-walled portion; and a thin-walled portion, which is connected to a groove provided on the surface of the heat sink on the opposite side of the layer component, the thin-walled portion overlapping the gap when viewed from above, and the thin-walled portion is thinner than the thick-walled portion.

[0008] Effects of the Invention

[0009] According to the present invention, the heat sink includes a thick portion and a thin portion. The thin portion is connected to a groove provided on the surface of the heat sink opposite the layer member. The thin portion overlaps the gap when viewed from above and is thinner than the thick portion. This structure can improve the heat dissipation characteristics of the semiconductor device.

[0010] The objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description and accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 It is a plan view showing the structure of the semiconductor device according to the first embodiment.

[0012] Figure 2 This is a cross-sectional view showing the structure of the semiconductor device according to the first embodiment.

[0013] Figure 3 It is a cross-sectional view showing the structure of a first related semiconductor device.

[0014] Figure 4 It is a cross-sectional view showing the structure of a second related semiconductor device.

[0015] Figure 5 It is a plan view showing the structure of a semiconductor device according to Modification 1 of Embodiment 1.

[0016] Figure 6 It is a plan view showing the structure of a semiconductor device according to a second modification of the first embodiment.

[0017] Figure 7 It is a plan view showing the structure of a semiconductor device according to Modification 3 of Embodiment 1.

[0018] Figure 8 This is a cross-sectional view showing the structure of a semiconductor device according to Modification 4 of Embodiment 1.

[0019] Figure 9 It is a plan view showing the structure of a semiconductor device according to the second embodiment.

[0020] Figure 10 It is a cross-sectional view showing the structure of a semiconductor device according to the second embodiment.

[0021] Figure 11 It is a plan view showing the structure of a semiconductor device according to Modification 1 of Embodiment 2.

[0022] Figure 12 This is a cross-sectional view showing the structure of a semiconductor device according to a second modification of the second embodiment. DETAILED DESCRIPTION

[0023] The following is a reference to the attached Figure 1The embodiments are described below. The features described in the following embodiments are examples, and not all features are required. In addition, in the description shown below, the same or similar reference numerals are used for the same structural elements in multiple embodiments, and the different structural elements are mainly described. In addition, in the description recorded below, specific positions and directions such as "up", "down", "left", "right", "front" or "back" do not necessarily have to be consistent with the directions in actual implementation. In addition, the semiconductor device described below is sometimes also referred to as a power module.

[0024] <Implementation Method 1>

[0025] Figure 1 is a plan view showing the structure of the semiconductor device according to the first embodiment. Figure 2 It is along Figure 1 Cross-sectional view of line A-A'.

[0026] The semiconductor device according to the first embodiment includes a first semiconductor element 101a, a second semiconductor element 101b, a layer member 102, and a heat dissipation member 104. Figure 2 As shown, the heat dissipation component 104 includes a heat dissipation plate 104 a and plate-shaped fins 104 b .

[0027] Layer member 102 is connected to heat sink 104a. In Embodiment 1, layer member 102 is connected to the upper surface of heat sink 104a, which is a flat surface. Furthermore, layer member 102 has substantially isotropic thermal conductivity, and heat sink 104a of heat sink member 104 also has substantially isotropic thermal conductivity.

[0028] also, Figure 2 The layer component 102 includes a conductive layer 102a and an insulating layer 102b, but is not limited thereto, and may include only the conductive layer 102a and the insulating layer 102b.

[0029] The first semiconductor element 101a and the second semiconductor element 101b are connected to the layer member 102 on the opposite side of the heat sink 104a and are separated from each other by the gap 103. Figure 2 In the example shown in FIG. 1 , the first semiconductor element 101 a and the second semiconductor element 101 b are connected to the conductive layer 102 a , and the insulating layer 102 b is connected between the conductive layer 102 a and the heat dissipation plate 104 a .

[0030] In addition, each of the first semiconductor element 101a and the second semiconductor element 101b includes at least one of, for example, an IGBT (Insulated Gate Bipolar Transistor), a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), a PND (PN junction Diode), an SBD (Schottky Barrier Diode), and a FWD (Free Wheeling Diode). Figure 2 In the example shown in FIG. 1 , the number of the first semiconductor elements 101 a is two and the number of the second semiconductor element 101 b is one, but the present invention is not limited thereto.

[0031] The first semiconductor element 101a and the second semiconductor element 101b can also be composed of wide bandgap semiconductors. The wide bandgap semiconductors mentioned here include, for example, silicon carbide (SiC), gallium nitride (GaN), and diamond. According to such a structure, the semiconductor device can operate stably at high temperatures and the SW speed can be increased. In addition, SiC can be used at a temperature higher than Si, so it is effective for chips (semiconductor elements) with a large amount of heat generated per unit area. On the other hand, the defect rate of the SiC crystal itself is higher than the defect rate of Si, making it difficult to achieve a large chip area. Therefore, in order to control large currents, multiple chips with appropriate areas are mostly connected in parallel. The details will be described later. According to this embodiment 1, the heat dissipation characteristics of the semiconductor device can be improved. Therefore, this embodiment 1 is effective for a structure in which multiple chips composed of SiC are arranged in parallel for parallel connection and the heat generated per unit area of ​​the chips is large.

[0032] In cross-section observation ( Figure 2 ), the heat sink 104a includes a thick-walled portion 104c and a thin-walled portion 104d thinner than the thick-walled portion 104c. Figure 2 In the example shown in FIG. 1 , the thin portion 104 d is in contact with a groove 104 e provided on the lower surface of the heat dissipation plate 104 a (the surface of the heat dissipation plate 104 a on the opposite side to the layer member 102 ).

[0033] The heat sink 104a is provided with plate-shaped fins 104b, or straight fins, protruding from the lower surface of the heat sink 104a. Furthermore, when the fins 104b are formed by forging (extrusion), it is preferable to pre-form a protrusion corresponding to the groove 104e in the die used to forge the fins 104b. With such a forging die, the groove 104e can be formed during the manufacture (forging) of the fins 104b, eliminating the need for a new step to form the groove 104e.

[0034] Looking down ( Figure 1), the thin-walled portion 104d and the groove portion 104e overlap with the gap 103. The groove portion 104e is provided only in the portion 121 ( Figure 3 ), the length of the groove portion 104e becomes shorter than the length of the fin 104b. In addition, the position and shape of the thin-walled portion 104d are substantially the same as those of the groove portion 104e.

[0035] Here, first and second semiconductor devices related to the semiconductor device according to the first embodiment (hereinafter referred to as “first and second related semiconductor devices”) will be described. Figure 3 as well as Figure 4 is a cross-sectional view showing the structure of the first related semiconductor device and the second related semiconductor device, Figure 2 The corresponding figure.

[0036] Figure 3 The structure of the first related semiconductor device and Figure 1 The structure of the semiconductor device according to the first embodiment is different in that the groove portion 104e is not provided on the lower surface of the heat dissipation plate 104a.

[0037] for Figure 3 In the first related semiconductor device, it is assumed that the heat generated by the first and second semiconductor elements 101a and 101b is isotropically diffused in the layer member 102 and the heat dissipation member 104. That is, it is assumed that the heat generated by the first and second semiconductor elements 101a and 101b is isotropically diffused in the layer member 102 and the heat dissipation member 104. Figure 3 The dotted line shows the situation where the heat is transferred in a diffuse manner at about 45 degrees relative to the main direction of heat flow. Figure 3 In the first related semiconductor device, heat interference occurs in the portion 121 of the heat dissipation member 104 below the gap 103, where heat from the first and second semiconductor elements 101a and 101b is superimposed. Therefore, there is a problem in that heat cannot be dissipated efficiently.

[0038] In order to solve such problems, Figure 4 As shown in the second related semiconductor device, by widening the gap 103 between the first and second semiconductor elements 101a and 101b, the Figure 3 However, according to such a structure, a new problem arises in that the size of the semiconductor device becomes larger.

[0039] Although not shown, in order to suppress heat transfer from one of the first and second semiconductor elements 101a and 101b to the other, a structure in which a groove is provided on the upper surface of the heat sink 104a in contact with the gap 103 is conceivable. However, in this structure, the groove is located Figure 2The upper side of the dotted line, that is, outside the range of isotropic heat transfer, cannot substantially affect the isotropic heat transfer and cannot substantially suppress the above-mentioned thermal interference.

[0040] On the other hand, according to the semiconductor device according to the first embodiment, since the groove portion 104e overlapping with the gap 103 in a plan view is provided on the lower surface of the heat sink 104a, the heat sink 104a includes the thin-walled portion 104d overlapping with the gap 103 in a plan view. With such a structure, even without widening the gap 103, it is possible to Figure 2 As shown by the dotted line, the thermal interference caused by the superposition of heat from the first and second semiconductor elements 101a and 101b is suppressed. Therefore, even without increasing the size of the semiconductor device, the heat dissipation characteristics of the semiconductor device can be improved. In addition, the side surfaces of the groove portion 104e are directly cooled by a cooling body (such as cooling water), thereby improving the heat dissipation characteristics of the semiconductor device.

[0041] Furthermore, according to Embodiment 1, the length of the groove portion 104e is shorter than the length of the fin 104b in a plan view. With such a structure, it is possible to suppress a decrease in the rigidity of the heat dissipation plate 104a.

[0042] In addition, the layer member 102 including the conductor layer 102a and the insulating layer 102b is preferably as follows Figure 1 According to such a structure, an increase in the number of parts and a deterioration in assemblability can be suppressed.

[0043] <Variation 1 of Implementation Example 1>

[0044] Figure 5 This is a top view showing the structure of a semiconductor device according to Modification 1 of Embodiment 1. In Modification 1, the semiconductor device is mounted on a water-cooling jacket 106. Water-cooling jacket 106 is provided with a cutout portion 107 for accommodating fins 104b and the cooling water, so that cooling water directly contacts fins 104b.

[0045] The inlet 110 of the water-cooling jacket 106 is connected to a groove 112a connected to the first side of the cutout 107. The outlet 111 of the water-cooling jacket 106 is connected to a groove 112b, which is connected to the second side of the cutout 107, opposite the first side. To prevent the cooling water in the cutout 107 from leaking to the outside, the heat sink 104a is fixed to the water-cooling jacket 106 with screws 109, with an O-ring 108 interposed between the two.

[0046] According to the water cooling jacket 106 described above, cooling water entering from the inlet 110 is distributed from the left fin 104b to the right fin 104b through the grooves 112a, flows between the plurality of fins 104b, is collected by the grooves 112b, and is discharged from the outlet 111. With this structure, the cooling of the fins 104b can be uniform.

[0047] <Variation 2 of Implementation 1>

[0048] Figure 6 This is a top view showing the structure of a semiconductor device according to Modification 2 of Embodiment 1. In Embodiment 1, the length of groove 104e is shorter than the length of fin 104b when viewed from above. However, in Modification 2, the length of groove 104e is equal to the length of fin 104b when viewed from above. In other words, groove 104e extends along the entire length of fin 104b. With this semiconductor device according to Modification 2, the contact area between the cooler and groove 104e is increased, thereby further improving the heat dissipation characteristics of the semiconductor device.

[0049] <Variation 3 of Implementation 1>

[0050] Figure 7 This is a top view showing the structure of a semiconductor device according to Modification 3 of Embodiment 1. In Embodiment 1, plate-shaped fins 104b protruding from the lower surface of heat sink 104a are provided on heat sink 104a. However, in Modification 3, needle-shaped fins 104f protruding from the lower surface of heat sink 104a are provided on heat sink 104a. With this semiconductor device according to Modification 3, increasing the density of needle-shaped fins 104f increases the area of ​​direct contact between needle-shaped fins 104f and water compared to plate-shaped fins 104b, thereby improving cooling efficiency.

[0051] <Variation 4 of Implementation 1>

[0052] Figure 8 This is a cross-sectional view showing the structure of a semiconductor device according to a fourth variation of the first embodiment. Here, the distance of gap 103 is L, the thickness of layer member 102 and thin-walled portion 104d as a whole is D, and the angle between the direction of heat diffusion in layer member 102 and thin-walled portion 104d as a whole and the out-of-plane direction of heat sink 104a is θ. In this case, in this fourth variation, L ≥ 2 × D × tanθ holds. That is, L / 2 ≥ D × tanθ or D ≤ L / (2 × tanθ) holds. This structure suppresses thermal interference caused by the superposition of heat from the first and second semiconductor elements 101a and 101b. Even if this equation does not hold, a semiconductor device having the structure of the first embodiment can still achieve a certain degree of thermal interference suppression.

[0053] <Implementation Method 2>

[0054] Figure 9 is a plan view showing the structure of a semiconductor device according to the second embodiment. Figure 10 It is along Figure 9 Cross-sectional view of line BB'.

[0055] The semiconductor device according to the second embodiment includes a first semiconductor element 101a, a second semiconductor element 101b, a layer member 102, and a heat sink 104, similar to the first embodiment. The heat sink 104 of the second embodiment is different from that of the first embodiment, so the structure of the heat sink 104 will be mainly described below.

[0056] The heat dissipation member 104 according to the second embodiment includes a heat dissipation plate 104a including a thick portion 104c and a thin portion 104d, and plate-shaped fins 104b.

[0057] The heat sink 104a includes not only the thick-walled portion 104c and the thin-walled portion 104d, but also a first anisotropic heat sink member 104g1 and a second anisotropic heat sink member 104g2. Hereinafter, the thin-walled portion 104d, which is arranged closer to the first semiconductor element 101a than semiconductor elements other than the first semiconductor element 101a, will be referred to as the thin-walled portion 104d corresponding to the first semiconductor element 101a. Similarly, the thin-walled portion 104d, which is arranged closer to the second semiconductor element 101b than semiconductor elements other than the second semiconductor element 101b, will be referred to as the thin-walled portion 104d corresponding to the second semiconductor element 101b.

[0058] The first anisotropic heat dissipation member 104g1 is embedded between the thin-walled portion 104d corresponding to the first semiconductor element 101a and the layer member 102. Figure 10 In the example, the second anisotropic heat dissipation member 104g2 is in contact with the insulating layer 102b below the first semiconductor element 101a. Similarly, the second anisotropic heat dissipation member 104g2 is embedded between the thin-walled portion 104d corresponding to the second semiconductor element 101b and the layer member 102. Figure 10 In the example of FIG, the second semiconductor element 101b is in contact with the insulating layer 102b below the second semiconductor element 101b.

[0059] The first anisotropic heat dissipation member 104g1 is Figure 10 The thermal conductivity in the transverse direction (in the plane of the heat sink 104a) is smaller than that of the first anisotropic heat sink 104g1. Figure 10The thermal conductivity in the longitudinal direction (outward direction of the heat sink 104a). Similarly, the second anisotropic heat sink 104g2 Figure 10 The thermal conductivity in the transverse direction (in the plane of the heat sink 104a) is smaller than that of the second anisotropic heat sink 104g2. Figure 10 The thermal conductivity in the longitudinal direction (outward direction of the heat dissipation plate 104a) is given by:

[0060] Furthermore, the first and second anisotropic heat dissipation members 104g1 and 104g2 use, for example, a graphite laminate. The graphite laminate has a low thermal conductivity in the first direction, but a high thermal conductivity in the second direction perpendicular to the first direction. Therefore, when the first and second anisotropic heat dissipation members 104g1 and 104g2 use a graphite laminate, the first direction can be set to Figure 10 Horizontal, set the second direction to Figure 10 The longitudinal and depth directions are sufficient.

[0061] In this embodiment 2, Figure 9 As shown, the outer periphery of the first anisotropic heat sink 104g1 is located outside the outer periphery of the first semiconductor element 101a. By making the first anisotropic heat sink 104g1 larger than the first semiconductor element 101a, heat isotropically diffused from the first semiconductor element 101a within the layer member 102 can be substantially transferred to the first anisotropic heat sink 104g1. Similarly, in this second embodiment, the outer periphery of the second anisotropic heat sink 104g2 is located outside the outer periphery of the second semiconductor element 101b.

[0062] According to the semiconductor device according to the second embodiment as described above, even without widening the gap 103, it is possible to Figure 10 As shown by the dotted line, thermal interference caused by the superposition of heat from the first and second semiconductor elements 101a and 101b is suppressed. Therefore, even without increasing the size of the semiconductor device, the heat dissipation characteristics of the semiconductor device can be improved.

[0063] <Variation 1 of Implementation Example 2>

[0064] Figure 11This is a top view showing the structure of a semiconductor device according to Modification 1 of Embodiment 2. In Embodiment 2, plate-shaped fins 104b protruding from the lower surface of heat sink 104a are provided on heat sink 104a. However, in Modification 1, needle-shaped fins 104f protruding from the lower surface of heat sink 104a are provided on heat sink 104a. With this semiconductor device according to Modification 1, increasing the density of needle-shaped fins 104f increases the area of ​​direct contact between needle-shaped fins 104f and water compared to plate-shaped fins 104b, thereby improving cooling efficiency.

[0065] <Variation 2 of Implementation Example 2>

[0066] Figure 12 This is a cross-sectional view showing the structure of a semiconductor device according to a second variation of the second embodiment. Here, let L be the distance of gap 103, let D be the combined thickness of layer member 102 and thin-walled portion 104d, and let θ be the angle between the direction of heat diffusion in layer member 102 and thin-walled portion 104d and the out-of-plane direction of heat sink 104a. Furthermore, let D1 be the total thickness from the top of layer member 102 to the bottom of thin-walled portion 104d, let D2 be the thickness of each of first and second anisotropic heat dissipating members 104g1 and 104g2, let D3 be the thickness of layer member 102, and let D4 be the thickness of thin-walled portion 104d. The equation D = D1 - D2 = D3 + D4 holds true.

[0067] In this case, in this second variation, L ≥ 2 × D × tanθ holds. That is, L ≥ 2 × (D1 - D2) × tanθ, L / 2 ≥ (D1 - D2) × tanθ, or D2 ≥ D1 - L / (2 × tanθ) holds. This structure suppresses thermal interference, where the heat from the first and second semiconductor elements 101a and 101b is superimposed. Even if this equation does not hold, a semiconductor device having the structure of the second embodiment can still achieve a certain degree of thermal interference suppression.

[0068] Furthermore, the embodiments and modifications can be freely combined, and the embodiments and modifications can be appropriately modified or omitted.

[0069] The above description is intended in all respects to be illustrative rather than restrictive, and it should be understood that numerous variations not shown in the examples are contemplated.

[0070] Description of the label

[0071] 101a: first semiconductor element, 101b: second semiconductor element, 102: layer component, 103: gap, 104a: heat sink, 104b: 104f: fins, 104c: thick-walled portion, 104d: thin-walled portion, 104e: groove portion, 104g1: first anisotropic heat dissipation component, 104g2: second anisotropic heat dissipation component.

Claims

1. A semiconductor device comprising: heat sink; a layer component connected to the heat sink; and a first semiconductor element and a second semiconductor element connected to the layer member on the side opposite to the heat sink, the first semiconductor element and the second semiconductor element being separated from each other by a gap; The heat sink comprises: Thick wall part; a thin-walled portion overlapping the gap when viewed from above and being thinner than the thick-walled portion; a first anisotropic heat dissipation member embedded between the thin-walled portion corresponding to the first semiconductor element and the layer member; as well as a second anisotropic heat dissipation member embedded between the thin-walled portion corresponding to the second semiconductor element and the layer member; The thermal conductivity of each of the first anisotropic heat dissipation member and the second anisotropic heat dissipation member in the in-plane direction of the heat dissipation plate is smaller than the thermal conductivity in the out-plane direction of the heat dissipation plate.

2. The semiconductor device according to claim 1, wherein The heat sink is provided with needle-shaped fins protruding from a surface of the heat sink opposite to the layer member.

3. The semiconductor device according to claim 1, wherein When the distance of the gap is L, the thickness of the layer member and the thin-walled portion is D, and the angle between the direction of heat diffusion in the layer member and the thin-walled portion and the out-of-plane direction of the heat dissipation plate is θ, L≥2×D×tanθ holds.

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