CAN transmitter with fast CANL loop and switch output cascode structure

Abstract

A controller area network (CAN) transmitter is provided. The CAN transmitter includes an output stage circuit including a CANH port and a CANL port, and an input stage circuit configured to receive an input signal. The input signal is configured to indicate whether the output stage circuit is to provide a dominant state or a recessive state. The CAN transmitter includes a cascode circuit configured to provide an output signal on the output stage circuit to provide the dominant state or the recessive state based on the input signal. The CAN transmitter includes a switching circuit configured to turn on and turn off the cascode circuit based on the input signal.

Description

[0001] Priority

[0002] This application claims priority to U.S. Provisional Patent Application No. 63 / 132,511, filed December 31, 2020, the contents of which are hereby incorporated in their entirety. TECHNICAL FIELD

[0003] The present disclosure relates to Controller Area Network (CAN) control, and in particular, to a CAN transmitter with a fast CANL control loop. BACKGROUND

[0004] CAN is defined in International Standards Organization (ISO) 11898 specification. ISO 11898 is a series of specifications, where ISO 11898-1 covers the data link layer and ISO 118980-2 and ISO 118980-3 cover the physical layer of CAN. CAN is a robust communication protocol. CAN nodes on the bus can detect errors in a received message and force the message to be destroyed and retransmitted. As a result, messages received by a node contain valid data. CAN frames require that each node acknowledge the message before it can be processed by the node. This acknowledgement can only be made after various error condition checks on the message are performed, such as a 15-bit Cyclic Redundancy Check (CRC). If a CAN node finds an error in the message, the message is destroyed and retransmitted.

[0005] The CAN specification defines three different error states for a CAN node, where each error state provides a different level of bus access to the CAN node. The error states limit a faulty node from shutting down the CAN bus.

[0006] CAN includes serial communication, where all nodes on the CAN bus attach to a common connection using the same bit rate. CAN is message-based, rather than address-based. As a result, messages are not transmitted from one node to another based on the address of the CAN node. Instead, a CAN node broadcasts its message to all nodes on the bus. It is up to the receiving node to determine if it should perform an operation on the message. One or more nodes can perform an operation on the same data. As a result, new nodes can be added to the CAN bus without having to update existing nodes with addressing information.

[0007] Due to the reliability of the data, CAN allows for distributed control throughout the network. This allows network designers to flexibly set up a consumer-producer network or a peer-to-peer network.

[0008] CAN network transmissions can be performed using a differential pair of transmission lines—CANH and CANL. CAN can specify two logical states: recessive and dominant. During a recessive logical state, CANH and CANL can be approximately the same voltage, or within a voltage tolerance range of each other. During a dominant logical state, CANH and CANL can be separated by a voltage difference VDiff. Figure 1 An exemplary differential bus timing diagram is shown in which CAN is used, including CANH, CANL, and VDiff.

[0009] In a recessive state (i.e., a logical ‘1’ on the input of a CAN transceiver or module), the differential voltage on CANH and CANL can be less than a minimum threshold. This minimum threshold can be determined by whether the state is on the input (where the threshold is 0.5V) or the state is on the output (where the threshold is 1.5V). In a dominant state (i.e., a logical ‘0’ on the input of a CAN transceiver or module), VDiff is greater than the minimum threshold. Dominant bits overdrive recessive bits on the bus to enable non-destructive bit- wise arbitration.

[0010] The inventors of examples of the present disclosure have found that some implementations of CAN transceivers can experience excessive jitter or other noise, particularly with respect to the output of the CANH and CANL signals. Further, the inventors of examples of the present disclosure have found that some implementations of CAN transceivers can experience such jitter in transitioning the output CAN signal from dominant to recessive, which is observable during the recessive pulse. Examples of the present disclosure can reduce such jitter by shorting the source of a cascode output in a CAN transceiver to a cascode bias voltage, thereby reducing the sensitivity of the output value to power transients. BRIEF DESCRIPTION OF DRAWINGS

[0011] Figure 1 is an illustration of exemplary CAN signaling.

[0012] Figure 2 is an illustration of an exemplary CAN network in accordance with examples of the present disclosure.

[0013] Figure 3 is an illustration of an exemplary CAN transceiver having a fast CANL control loop and a switch output cascode structure in accordance with examples of the present disclosure.

[0014] Figure 4 is a timing diagram of various signals, inputs, and outputs of a CAN transceiver in accordance with examples of the present disclosure. DETAILED DESCRIPTION

[0015] Figure 2is a diagram of an exemplary CAN network 100 according to examples of the present disclosure. The network 100 can include any suitable number and variety of CAN nodes 102. For example, the network 100 can include nodes 102A, 102B, 102C. The nodes 102 can be configured to communicate with each other over a CAN bus 116. The CAN bus 116 can be implemented with two wires. For example, the CAN bus 116 can include a CANH line 120 and a CANL line 118.

[0016] The nodes 102 can be implemented in any suitable manner, such as by a computer, a system on a chip, an application-specific integrated circuit, a field-programmable gate array, a server, or any suitable electronic device. Figure 2 An exemplary variation of a CAN node implementation is shown. For example, the CAN node 102A can be implemented with a microcontroller 104. The microcontroller 104 can be implemented by, for example, an 8-bit, 16-bit, or 32-bit PIC microcontroller from the assignee of the present disclosure. The microcontroller 104 can not include an integrated CAN module. Accordingly, the CAN node 102A can include a separately implemented CAN module 110A.

[0017] The CAN modules 110 in the network 100 can be configured to provide an interface between the CAN transceivers 112 and the rest of the CAN nodes 102. The CAN modules 110 and CAN transceivers 112 can be implemented by any suitable mechanism, such as by a library, a software stack, a function, an application, a driver, digital logic, digital circuitry, analog circuitry, instructions for execution by a processor, or any suitable combination thereof. The CAN modules 110 can make function calls to the CAN transceivers 112 to send and receive data, or otherwise execute the CAN protocol. The other elements of the CAN nodes 102 can in turn make function calls to the CAN modules 110. For example, software running on the microcontroller 110A can communicate with other nodes 102 by making function calls to the CAN module 110A, which in turn can make function calls to the CAN transceiver 112A. The CAN transceiver 112A can write data to or read data from other CAN nodes 102 over the CAN bus 116.

[0018] CAN node 102A can include a microcontroller 110A that does not include an integrated CAN module 110A. CAN node 102B can include a microcontroller 110B that includes an integrated CAN module 110B. CAN node 102C can be implemented as a CAN input / output (I / O) expander 108. CAN node 102C can provide I / O expansion for CAN network 100 without a microcontroller. CAN node 102C can include peripherals such as general IO, A2D, pulse width modulation, or other interfaces to emit periodic or event-based messages driven according to thresholds. CAN I / O expander 108 can be implemented by any suitable combination of analog circuitry, digital circuitry, or instructions for execution by a processor.

[0019] When implementing CAN network 100, many challenges can be encountered. For example, CAN system development can encounter electromagnetic compatibility (EMC) issues, such as electromagnetic interference (EMI) in an electromagnetic environment (EME). In CAN, differential communication must work despite EMI. Such digital communication can include operation even within a large common mode range of + / - 12V. Further, such digital communication can include operation with radio frequency (RF) power injected up to 36 dBm (40V peak). Further, CAN must work in an EME, such as a common mode emission of up to 55 dBpV (0.6 mV) at frequencies up to 20 Mhz, a common mode emission of up to 15 dBpV (6 pV) at a frequency of 75 MHz and a differential signal amplitude of 2V. Further, CAN L current and CAN H current can need to be matched to each other with very high precision at both DC and transients.

[0020] A given CAN node 102 can be slow or fast controlled to generate a CAN H signal or a CAN L signal at a transceiver. The "fast" or "slow" aspect can refer to the speed at which a control loop generates an appropriate dominant or recessive signal. In particular, the "fast" or "slow" aspect of CAN H control or CAN L control can refer to the slope of a signal change between a recessive state and a dominant state, or between a dominant state and a recessive state. The slope can also be referred to as a slew rate of a signal transition. Faster rise times and fall times can support higher bus rates and longer bus lengths in network 100.

[0021] Figure 3 A more detailed view of a CAN transceiver 300 is shown in accordance with examples of the present disclosure. Transceiver 300 can be implemented in part by a CAN controller 302, a CAN driver 304, and a CAN receiver 306. CAN controller 302 can be implemented by any suitable combination of analog circuitry, digital circuitry, or instructions for execution by a processor. CAN controller 302 can be implemented by a CAN controller integrated circuit (IC) or a CAN controller implemented in software. CAN controller 302 can be implemented by a CAN controller IC that is integrated with a microcontroller or a CAN controller IC that is implemented in software. Figure 2transceiver 112. The transceiver 300 can receive a signal 318 from other components (not shown) of the transceiver or the CAN module 110. The signal 318 can be a bit pattern of values representing a dominant state or a recessive state to be written to the CAN network 100. The output dominant signal or recessive signal can be written to the CANH pin 308 or the CANL pin 310. The CANH pin and the CANL pin 310 can be connected to the CANH line 118 and the CANL line 120, respectively. The transceiver 300 can be configured to perform faster rise times and fall times compared to other solutions to write the recessive state or the dominant state to the CANH pin 308 and the CANL pin 310. Further, in one example, the transceiver 300 can be configured to switch the CANH and CANL common-source common-gate output transistors therein to high resistance when transitioning to a recessive state. As explained in more detail below, this can be performed based on and in synchronization with the recessive signal to be transmitted. In another example, during a recessive phase of operation, the transceiver 300 can be configured to short the sources of the output CANH and CANL common-source common-gate output transistors to the bias voltage of the respective common-source common-gate transistors, thereby making the outputs high resistance and insensitive to transient voltages. During a dominant phase, the common-source common-gate output transistors can be reactivated based on and in synchronization with the dominant signal to be transmitted.

[0022] In the first stage, input stage circuit 398, the transceiver 300 can include a current source 320 connected to the signal 318. The signal 318 can be configured to drive the output of the current source 320 according to the received bit pattern. The current source 320 can be implemented in any suitable manner. In one example, the current source 320 can be a floating current source. The current source 320 can be a programmable or adjustable current source based on the input of the signal 318. The injected bit pattern can be provided from the current source 320 into a current mirror. The current mirror can include the replication stage 304 and the output stage 306.

[0023] A VCC 312 can be connected to the transceiver 300. A ground 314 can be connected to the transceiver 300. The VCC 312 can be connected to the source of a transistor 316. The transistor 316 can be a p-type metal-oxide-semiconductor (PMOS) transistor. The current source 320 can be connected to the drain of the transistor 316. The current source 320 can be connected to the source of another transistor 322. The transistor 322 can be an n-type metal-oxide-semiconductor (NMOS) transistor. Further, the current source 320 can be connected to the gate of the transistor 322. The drain of the transistor 322 can be connected to the ground 314.

[0024] The transceiver 300 can include a replica stage 304. The replica stage 304 can include a transistor 330 connected to a VCC 312. The transistor 330 can be a PMOS transistor. The transistor 330 can be connected at its source to the VCC 312. The gate of the transistor 330 can be connected to the gate of the transistor 316. The drain of the transistor 330 can be connected to a diode 354. The diode 354 can be connected to a resistor 350, which can be connected to another resistor 352. The resistor 352 can be connected to a diode 356. The diode 356 can be connected to the source of a transistor 332. The drain of the transistor 332 can be connected to a ground 314. The diodes 356, 354 can be freewheeling diodes. The gate of the transistor 332 can be connected to the gate of the transistor 322. The transistor 332 can be an NMOS transistor.

[0025] The transceiver 306 can include an output stage 306. The output stage 306 can include two output common-source common-gate circuits 388, 390. In one example, each of the common-source common-gate circuits 388, 390 can be implemented by MOS transistors as well as lateral double-diffused (LD) MOS transistors. For example, the common-source common-gate circuit 388 can include a PMOS transistor 366 and an LD PMOS transistor 370. The common-source common-gate circuit 390 can include an NMOS transistor 372 and an LD NMOS transistor 368. The transistors 370, 372 can be referred to as common-source common-gate transistors.

[0026] The transistor 366 can be connected at its source to the VCC 312. The transistor 366 can be connected at its gate to the gate of the transistor 330 and the gate of the transistor 316. The transistor 366 can be connected at its drain to the source of the transistor 370. The transistor 370 can be connected at its drain to a diode 340. The diode 340 can be connected to a CANH pin 308. A CANL pin 310 can be connected to a diode 342. The diode 342 can be connected to the source of the transistor 372. The drain of the transistor 372 can be connected to the source of the transistor 368. The gate of the transistor 368 can be connected to the gate of the transistor 332 and the gate of the transistor 322. The drain of the transistor 368 can be connected to the ground 314. The diodes 340, 342 can be freewheeling diodes. The diodes 340, 342 can be used for electrostatic discharge protection as well as reverse protection.

[0027] In one example, transceiver 306 may include control amplifier 328. The output of amplifier 328 may be connected to the gate of transistor 368. Furthermore, the output of amplifier 328 may be connected to the gates of transistors 322 and 332. Amplifier 328 may be implemented as, for example, a one-stage, two-stage, or three-stage operational amplifier. In another example, amplifier 328 may receive inputs from reference distributor 302 and from replication stage 304. For example, amplifier 328 may receive a negative input from reference distributor 302 and a positive input from replication stage 304, or vice versa.

[0028] Reference distributor 302 can be connected to VCC 312. Reference distributor 302 may include two resistors 324 and 326. Resistor 326 can be connected to ground 314. The values ​​of resistors 324 and 326 can be the same. Reference distributor 302 can provide a reference voltage to amplifier 328 from the node between resistors 324 and 326.

[0029] The input from replication stage 304 to amplifier 328 can be provided from the node between resistors 350 and 352. Resistors 350 and 352 can have the same value. Any suitable resistance value can be used in resistors 324, 326, 350, and 352. Reference distributor 302 can be a total of 110 ohms. Resistors 350 and 352 can be, for example, six times the value of the output CAN bus resistor. Such a CAN bus resistor can be, for example, 60 ohms.

[0030] Transceiver 300 may include a discharge stage 360. For example, switch 334 may be disposed between VCC 312 and the gates of transistors 366, 330, and 316. Switch 334 may be optional. As another example, switch 336 may be disposed between ground 314 and the gates of transistors 368, 332, and 322. Switch 336 may be optional because... Figure 3 The transistors in the circuit provide control to perform equivalent functions. Switches 334 and 336 can be driven by bit pattern 318. Hard switching can be performed using a current source. In contrast, switches 334 and 336 can be driven by bit pattern 318.

[0031] The replica stage 304 can be a fraction of the size or current of the output stage 306. The fraction can be, for example, 1 / 10 to 1 / 3 of the current of the output stage 306. In one example, 1 / 6 of the output state current can be used. The replica stage 304 can be configured to produce a replica signal. The replica signal can detect the difference in CANH and CANL current changes. The replica signal can be an estimate of the common mode signal applied to the CAN bus through the CANH pin 308 and the CANL pin 310. The replica signal can be provided to an amplifier 328. The amplifier 328 in turn can be configured to maintain the replica signal at a desired level. The desired level can be represented by the reference voltage provided by the reference divider 302. In particular, the amplifier 328 can be configured to maintain the replica signal by controlling the signal on the CANL pin 310. The replica signal generated by the replica stage 304 can be controlled by applying the output of the amplifier 328 to the gate of the transistor 332.

[0032] The replica stage 304 can be implanted as a reduced size (such as 1-30%) of the output stage 306. The replica stage 304 can include a model of the bus load on the CAN network 100. Such a model can be implemented by, for example, resistors 326, 330. The center taps of the resistors 326, 330 can be used to input or feedback to the amplifier 328. The amplifier 328 can control the gate voltage of the transistor 368. Thus, the transceiver 300 can use active feedforward to compensate and stabilize the control loop to generate the CANL pin 310 signal. The transceiver 300 can use a constant voltage such as 2.5V as a target for the replica voltage. The transceiver 300 can use a certain ratio such as 50% as a target for the replica voltage. This can be achieved by the reference divider 302.

[0033] The transceiver 300 can provide advantages over slower CANH control and CANL control. By using a replica stage 304 that includes Figure 3 The transceiver 300 can provide advantages over using hard switching to generate the CANH signal and the CANL signal with the control circuit of the amplifier 328 and its connections as shown. With no hard switching, high frequency emissions can be reduced. Other solutions can use a switch to switch between explicit and implicit generation of the signals for CANH and CANL.

[0034] During CANL control, slow CANH control can be disabled. In one example, only the CANL signal can be controlled (using cascode 390) and not both the NMOS and PMOS devices of cascodes 390, 388 through amplifier 328. This can be due to the fact that PMOS mirror operates slower than NMOS mirror. Thus, the capacitance of the NMOS transistor in cascode 390 is 1 / 3 of the capacitance of the PMOS transistor in cascode 388, which can result in faster control. In one example, the control loop can be biased at all times.

[0035] In one example, transceiver 300 can include a bypass switch stage 392. Bypass switch stage 392 can be connected to or be part of discharge stage 360. Bypass switch stage 392 can include two switch circuits 382, 384 connected in series between VCC 312 and ground 314. Further, switch circuits 382, 384 can be separated by diode 386. Further, the path formed by switch circuits 382, 384 can be selectively enabled by any suitable mechanism, such as through switches 362, 364. Switches 362, 364 can be configured to connect switch circuits 382, 384 to the power rails of VCC 312 and ground 314, thereby enabling operation of switch circuits 382, 384. Further, switches 362, 364 can be driven by signal 318.

[0036] Each of switch circuits 382, 384 can be implemented in any suitable manner. In one example, each of switch circuits 382, 384 can be implemented through a resistor in parallel with a switch. For example, switch circuit 382 can include resistor 374 connected across transistor 376. Switch circuit 384 can include resistor 378 connected across transistor 380. The resistance values of resistors 374, 378 can be closely matched.

[0037] Transistor 376 can be implemented in any suitable manner, such as through an NMOS transistor. Resistor 374 can be connected across the gate and drain terminals of transistor 376. The gate of resistor 374 and transistor 376 can be connected to switch 362. The body and drain of transistor 376 can be connected together. The source of transistor 376 can be connected to cascode 388. Specifically, the source of transistor 376 can be connected to the midpoint between transistor 366 and transistor 370. The drain of transistor 376 can be connected to cascode 388. Specifically, the drain of transistor 376 can be connected to the gate of transistor 370.

[0038] The transistor 380 can be implemented in any suitable manner, such as by a PMOS transistor. The resistor 378 can be connected across the gate and drain terminals of the transistor 380. The resistor 378 and the gate of the transistor 380 can be connected to the switch 364. The source and body of the transistor 380 can be connected together. The drain of the transistor 380 can be connected to the midpoint between the transistor 368 and the transistor 372. The source of the transistor 380 can be connected to the cascode circuit 390. In particular, the drain of the transistor 376 can be connected to the gate of the transistor 372.

[0039] The transceiver 300 can be configured to operate on the push-pull control current generated from the input of the signal 318 and the VCC 312, which energizes the two resistors 374, 378 to control the switch circuits 382, 384 to turn on and off the cascode circuits 388, 390. This can be performed by operating the switches 362, 364, which can act as controlled current sources. The switch 362 can cause current to be supplied and the switch 364 can cause current to be received. This can cause the symmetrical voltage drop across the resistors in the current path (e.g., the resistors 374, 378), thereby enabling the synchronous switching of the switch circuits 382, 384.

[0040] In one example, the switch circuits 382, 384 can be configured to switch the cascode transistors 370, 372, respectively, to a high input impedance. This can be performed during the recessive state. In particular, the switch circuits 382, 384 can be configured to switch the cascode transistors 370, 372 to an off state, thereby resulting in such a high input impedance. The switch circuits 382, 384 can be configured to switch the cascode transistors 370, 372 to an on state during the dominant state.

[0041] The switch circuits 382, 384 can be configured to switch the cascode transistors 370, 372 based on any suitable criteria. In another example, the switch circuits 382, 384 can be configured to switch the cascode circuits 388, 390 to a high resistance based on the signal 318 being driven to the recessive state in accordance with the output of the CANL 310 and the CANH 308.

[0042] The switch circuits 382, 384 can be configured to turn on and off the cascode transistors 370, 372 in any suitable manner. For example, during the recessive state, the switches 362, 364 can be closed, thereby energizing the resistors 374, 378. In this state, the resistors 374, 378 can be connected in series. The voltage drop across each resistor 374, 378 can be the same. Further, the voltage drop across each resistor 374, 378 can equal or exceed the necessary Vgd voltage at the respective gates of the transistors 376, 380 to activate such transistors 376, 380, which in turn can turn off the respective cascode circuits 388, 390, and in particular the respective transistors 370, 372. This can effectively short the respective cascode transistors 370, 372, thereby causing current to flow from the VCC 312 through the transistor 366, the transistor 376, the transistor 380, and the transistor 368 to ground, rather than to the CANH port 308 or the CANL port 310. This path can be a short for the cascode transistors 370, 372, thereby causing the output to the CANH port 308 and the CANL port 310 to have a high impedance that is insensitive to transient voltages.

[0043] During the dominant state, the switches 362, 364 can be open, thereby causing no voltage drop across the resistors 374, 378. The switch circuits 382, 384 can be open, thereby activating the transistors 370, 372 to allow the current signal to reach the CANH port 308 or the CANL port 310.

[0044] The CAN bus 116 can be connected to the transceiver 300 using a termination resistor (not shown). The termination resistor can be, for example, 60 ohms. If the resistor is energized, it can reflect Figure 1 the dominant state shown in FIG. 3B. Otherwise, the resistor can reflect the recessive state. Such a resistor can be placed between the terminal pins CANH and CANL.

[0045] Figure 4 is a graphical illustration of a timing diagram of various signals of the transceiver 300 showing operation of the transceiver 300 according to examples of the present disclosure. Shown are VCNH, VCNL, the difference between VCNH and VCNL, the voltage at the gate of the transistor 376 (Vg), the Vg of the transistor 370, the Vg of the transistor 372, the Vg of the transistor 380, the current flowing through the resistor 374 (Ir), and the current flowing through the switch 334 (I).

[0046] Examples of the present disclosure can include a CAN transmitter. The CAN transmitter can be included in any suitable environment or device, such as a microcontroller or a transceiver. Although referred to as a CAN transmitter, the CAN transmitter can be implemented with additional components to make a CAN transceiver.

[0047] The CAN transmitter can include an output stage circuit including a CANH port and a CANL port. The CANH port and the CANL port can be configured to provide an output signal to other CAN devices. The CAN transmitter can include an input stage circuit configured to receive an input signal. The input signal can be configured to indicate whether the output stage circuit is to provide a dominant state or a recessive state. The input signal can include, for example, a bit code or bit sequence, each bit indicating whether the output stage circuit is to provide a dominant state or a recessive state for a period of time or clock cycle. The CAN transmitter can include a first cascode circuit configured to provide the output signal on the output stage circuit to provide the dominant state or the recessive state based on the input signal. The CAN transmitter can include a first switch circuit configured to turn on and turn off the first cascode circuit based on the input signal.

[0048] In connection with any of the above examples, the first switch circuit can be configured to turn off the first cascode circuit to cause current to flow through the CAN transmitter and avoid outputting on the CANH port or the CANL port.

[0049] In connection with any of the above examples, the first switch circuit can include a resistor and a switch circuit transistor. The resistor can be configured to provide a voltage drop across a gate and a drain of the switch circuit transistor sufficient to turn on the switch circuit transistor based on the input signal. The switch circuit transistor can be configured to turn on or turn off the first cascode circuit.

[0050] In connection with any of the above examples, the switch circuit transistor, when turned on, can be configured to turn off the first cascode circuit.

[0051] In connection with any of the above examples, the CAN transmitter can further include an input switch configured to be controlled by the input signal and to provide power for the voltage drop of the resistor.

[0052] In connection with any of the above examples, the first switch circuit can be configured to turn on the first cascode circuit based on an indication from the input signal to provide a recessive state.

[0053] In connection with any of the above examples, the first switch circuit can be configured to turn off the first cascode circuit based on an indication from the input signal to provide a dominant state.

[0054] With any of the above examples, the first cascode circuit can include a first transistor and a second transistor. The first transistor can be configured to selectively provide input power to the second transistor and be selectively controlled by the input signal. The first switch circuit can be configured to turn off the second transistor to turn off the first cascode circuit.

[0055] With any of the above examples, the first switch circuit can be further configured to turn off the second transistor to cause current to flow through the CAN transmitter instead of the second transistor.

[0056] With any of the above examples, the CAN transmitter can further include a second cascode circuit configured to provide an output signal on an output stage circuit to provide a dominant state or a recessive state based on the input signal. The CAN transmitter can further include a second switch circuit configured to turn on and turn off the second cascode circuit based on the input signal.

[0057] With any of the above examples, the first switch circuit and the second switch circuit can be configured to, based on an indication of an output recessive state from the input signal, turn off the first cascode circuit and the second cascode circuit to short a source of the first cascode circuit and a source of the second cascode circuit.

[0058] With any of the above examples, the first switch circuit can be configured to, when the first cascode circuit is turned off, create a high input impedance to an output port of the first cascode circuit.

[0059] Those skilled in the art will understand that numerous modifications can be made to the disclosed examples, all without departing from the spirit and scope of the present disclosure, which is defined only by the claims appended hereto. The components of the above-described systems can be implemented in digital circuitry, analog circuitry, instructions for a processor, or any suitable combination thereof.

Claims

1. A controller area network (CAN) transmitter comprising: an output stage circuit including a CANH port and a CANL port; an input stage circuit receiving an input signal indicating whether the output stage circuit is to provide a dominant state or a recessive state; a first cascode circuit providing an output signal on the output stage circuit to provide a dominant state or a recessive state based on the input signal; a first switch circuit turning on and off the first cascode circuit based on the input signal; a second cascode circuit configured to provide an output signal on the output stage circuit to provide a dominant state or a recessive state based on the input signal; and a second switch circuit configured to turn on and off the second cascode circuit based on the input signal, wherein the first and second switch circuits turn off the first and second cascode circuits based on an indication from the input signal of an output recessive state to short a source of the first cascode circuit and a source of the second cascode circuit.

2. The CAN transmitter of claim 1, wherein the first switch circuit turns off the first cascode circuit to cause current to flow through the CAN transmitter and avoid outputting on the CANH port or the CANL port.

3. The CAN transmitter of claim 1, wherein the first switch circuit turns on the first cascode circuit based on an indication from the input signal of a dominant state being provided.

4. The CAN transmitter of claim 1, wherein the first switch circuit is configured to turn off the first cascode circuit based on an indication from the input signal of a recessive state being provided.

5. The CAN transmitter of claim 1, wherein: the first cascode circuit includes a first transistor and a second transistor; the first transistor selectively provides input power to the second transistor and is selectively controlled by the input signal; and the first switch circuit turns off the second transistor to turn off the first cascode circuit.

6. The CAN transmitter of claim 5, wherein the first switch circuit turns off the second transistor to cause current to flow through the CAN transmitter and not the second transistor.

7. The CAN transmitter of claim 1, wherein the first switch circuit creates a high input impedance to an output port of the first cascode circuit when the first cascode circuit is turned off.

8. A controller area network (CAN) transmitter comprising: an output stage circuit including a CANH port and a CANL port; an input stage circuit receiving an input signal indicating whether the output stage circuit is to provide a dominant state or a recessive state; an output stage circuit including a CANH port and a CANL port; a first cascode circuit providing an output signal on the output stage circuit to provide a dominant state or a recessive state based on the input signal; a first switch circuit turning on and off the first cascode circuit based on the input signal; wherein the first switch circuit includes a resistor and a switch circuit transistor; and based on the input signal, the resistor provides a voltage drop across the gate and the drain of the switch circuit transistor sufficient to turn on the switch circuit transistor.

9. The CAN transmitter of claim 8, wherein the switch circuit transistor, when turned on, turns off the first cascode circuit.

10. The CAN transmitter of claim 8, comprising an input switch controlled by the input signal and providing power for the voltage drop of the resistor.

11. The CAN transmitter of claim 8, wherein the first switch circuit turns on the first cascode circuit based on an indication from the input signal providing a dominant state.

12. The CAN transmitter of claim 8, wherein the first switch circuit is configured to turn off the first cascode circuit based on an indication from the input signal providing a recessive state.

13. The CAN transmitter of claim 8, wherein: the first cascode circuit includes a first transistor and a second transistor; the first transistor selectively provides input power to the second transistor and is selectively controlled by the input signal; and the first switch circuit turns off the second transistor to turn off the first cascode circuit.

14. The CAN transmitter of claim 13, wherein the first switch circuit turns off the second transistor to cause current to flow through the CAN transmitter instead of the second transistor.

15. The CAN transmitter of claim 8, wherein the first switch circuit, when the first cascode circuit is turned off, creates a high input impedance to an output port of the first cascode circuit.

16. A method of operating a Controller Area Network (CAN) transmitter, comprising: receiving an input signal at an input stage circuit, the input signal indicating whether an output stage circuit is to provide a dominant state or a recessive state in a CANH output and a CANL output from a CANH port and a CANL port; providing an output signal on the output stage circuit at a first cascode circuit to provide a dominant state or a recessive state based on the input signal; turning on and off the first cascode circuit based on the input signal at a first switch circuit, wherein the first switch circuit includes a resistor and a switch circuit transistor; and based on the input signal, providing a voltage drop across the gate and the drain of the switch circuit transistor of the first switch circuit by the resistor sufficient to turn on the switch circuit transistor.

17. The method of claim 16, comprising switching off the first cascode circuit to cause current to flow through the CAN transmitter and avoid outputting on the CANH port or the CANL port.

18. The method of claim 16, comprising switching off the first cascode circuit when the switching circuit transistor is turned on.

19. The method of claim 16, comprising controlling an input switch by the input signal and powering the voltage drop of the resistor by the input switch.

20. The method of claim 16, comprising turning on the first cascode circuit by the first switch based on an indication from the input signal to provide a recessive state.

21. The method of claim 16, comprising turning off the first cascode circuit by the first switch based on an indication from the input signal to provide a dominant state.

22. The method of claim 16, wherein the first cascode circuit comprises a first transistor and a second transistor, the method further comprising: selectively controlling the first transistor to selectively provide input power to the second transistor by the input signal; and turning off the second transistor to turn off the first cascode circuit by the first switch circuit.

23. The method of claim 22, comprising turning off the second transistor by the first switch circuit to cause current to flow through the CAN transmitter instead of the second transistor.

24. The method of claim 16, comprising generating a high input impedance to an output port of the first cascode circuit by the first switch circuit when the first cascode circuit is turned off.

25. A method of operating a Controller Area Network (CAN) transmitter, comprising: receiving an input signal at an input stage circuit, the input signal indicating whether an output stage circuit is to provide a dominant state or a recessive state in a CANH output and a CANL output from a CANH port and a CANL port; providing an output signal on the output stage circuit by a first cascode circuit to provide a dominant state or a recessive state based on the input signal; turning on and turning off the first cascode circuit based on the input signal by a first switch circuit; providing an output signal on the output stage circuit by a second cascode circuit to provide a dominant state or a recessive state based on the input signal; turning on and turning off the second cascode circuit based on the input signal by a second switch circuit, turning off the first cascode circuit and the second cascode circuit by the first switch circuit and the second switch circuit based on an indication from the input signal of an output recessive state to short a source of the first cascode circuit and a source of the second cascode circuit.

26. The method of claim 25, comprising generating a high input impedance to an output port of the first cascode circuit by the first switch circuit when the first cascode circuit is turned off.

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