Matrix processing system and method for a vector-oriented dsp chip

Abstract

This invention relates to a matrix processing system and method for vector DSP chips. The system includes a matrix storage space allocation module, a matrix loop parallel optimization module, a data memory access latency hiding module, and a data protection module. The matrix storage space allocation module sets a corresponding storage space allocation strategy for the matrix data to be processed, laying the groundwork for subsequent SIMD vectorized matrix operations. The matrix loop parallel optimization module allocates data registers for the inner loop processing of the matrix and schedules functional units isomorphic to the vector DSP to parallelize multiple loops within the matrix. The data memory access latency hiding module hides the memory access latency during matrix data processing within the data operation time slots, reducing performance loss caused by memory access during matrix processing and improving the parallelism of program execution. This invention fully utilizes the architectural advantages of DSP chips and leverages their computational performance to improve the parallelism and efficiency of matrix processing.

Description

Technical Field

[0001] This invention relates to the field of upper-layer software development for vector digital signal processor chips, and more specifically, to a matrix processing system and method for vector DSP chips. Background Technology

[0002] A Digital Signal Processor (DSP) is a specialized embedded microprocessor. As a microprocessor that emerged alongside digital signal processing technology, DSP chips are characterized by high processing speed, strong real-time performance, and powerful processing capabilities, thus occupying an important position in people's production and daily lives.

[0003] Algorithms commonly used in digital signal processing, such as matrix operations and fast Fourier transforms, share a fundamental characteristic: a high frequency of multiplication and accumulation operations. To address these operations in digital signal processing algorithms, DSPs incorporate hardware multiply-accumulate units and multiply-accumulate instructions within their cores to improve computational speed and meet the application requirements of these algorithms. With the continuous development of digital signals, the application areas of DSPs have become more extensive, and the demand for high-performance computing in these areas has become more urgent.

[0004] To improve the computational performance and efficiency of computationally intensive applications such as matrix processing, radar signal processing, fast Fourier transform, and digital image processing, traditional DSP architectures are constantly evolving, leading to the emergence of high-performance vector digital signal processors (DSPs). On-chip multi-core, reconfigurable array processing architectures, and streaming architectures are the main structures used in high-performance DSPs. These are further enhanced by incorporating numerous new technologies from related fields such as Very Long Instruction Word (VLIW), Single Instruction Multiple Data (SIMD), and Application Specific Instruction Set Processors (ASIPs). Currently, mainstream vector DSPs typically employ VLIW and SIMD technologies, and at the hardware level, they usually include multi-level memory structures, arithmetic units, registers, DMA, and other modules. Single Instruction Multiple Data (SIMD) effectively improves the peak performance of data computation and fully utilizes the parallelism of instructions and data; therefore, vector digital signal processors are gradually becoming the development trend of high-performance DSP processors.

[0005] Matrix processing is an important component of linear algebra and, as a data-intensive computation, plays a crucial role in high-performance computing. It is not only an important tool for evaluating microprocessor performance but also a core component of the standard mathematical function library.

[0006] With the rapid development of high-performance vector DSPs, porting matrix processing programs from traditional DSP chips to vector DSP chips cannot effectively utilize the multi-level memory structure, vector operation units, and registers, resulting in unsatisfactory computational performance and failing to fully leverage the architectural advantages of vector DSP chips. Existing methods suffer from the following technical problems: when porting matrix processing methods suitable for traditional DSP chips to vector DSP chips, the data operation process cannot be executed in a SIMD vectorized manner, the vector operation functional units and vector register resources of the vector DSP chip cannot be fully utilized, and the degree of instruction-level parallelism and data-level parallelism is insufficient, thus failing to fully utilize the computational capabilities of the vector DSP chip. Summary of the Invention

[0007] The technical problem to be solved by the present invention is to provide a matrix processing system and method for vector DSP chips, which can make full use of the architectural advantages of DSP chips, give full play to their computing performance, improve the parallelism and efficiency of matrix processing, and optimize the efficiency of matrix processing.

[0008] The technical solution adopted by the present invention to solve its technical problem is: to construct a matrix processing system for vector DSP chips, including a matrix storage space allocation module, a matrix cyclic parallel optimization module, a data memory access latency hiding module, and a data protection module;

[0009] The matrix storage space allocation module is used to set the corresponding storage space allocation strategy for the matrix data to be processed, laying the groundwork for subsequent matrix operations in a SIMD vectorized manner.

[0010] The matrix loop parallel optimization module allocates data registers for the inner loop processing of the matrix and schedules functional units that are isomorphic to the vector DSP to perform parallel processing on multiple loops in the inner layer of the matrix.

[0011] The data memory access latency hiding module is used to hide the memory access latency in the matrix data processing process within the data operation time slot, thereby reducing the performance loss caused by memory access during matrix processing and improving the parallelism of program execution.

[0012] The data protection module is used to prevent errors caused by data write-back during matrix data processing in a vector digital signal processor.

[0013] This invention also discloses a matrix processing method for vector DSP chips, comprising the following steps:

[0014] S1. Store the data to be processed: Set up an appropriate storage scheme for the matrix data to be processed according to the size of the matrix.

[0015] S2. Optimize the matrix data processing process in parallel loops: For the inner loop in the matrix operation process, K1 loops are executed by merging the allocation of registers and the scheduling of DSP functional units.

[0016] S3. Hiding data memory access latency: For matrix data processed in a loop, data memory access accounts for the majority of the latency consumed in global processing;

[0017] S4. Data protection: If matrix operations are processed row-by-row, and the size of the matrix is ​​not an integer multiple of the number of single instruction outputs of the vector digital signal processor, the write-back operation of the nth loop will partially overwrite the data to be processed in the (n+1)th loop, thus causing an error.

[0018] According to the above scheme, in step S1:

[0019] If the matrix to be processed satisfies max{Nrows,Ncols}<N, then all the data to be processed is placed in the scalar space. If Nrows*Ncols*sizeof(auto)≤VectorMemory.Size, then all the data to be processed is placed in the vector storage space.

[0020] According to the above scheme, Nrow is the number of rows of the matrix to be processed, Ncols is the number of columns of the matrix to be processed, N is the number of single instruction data outputs of the vector DSP processor, sizeof(auto) is the space size used to store a single piece of data to be processed, and VectorMemory.Size is the total space size of the vector memory.

[0021] According to the above scheme, in step S2, a corresponding vector register is allocated for each data in the K1th loop, and the isomorphic vector DSP hardware functional unit is scheduled to perform operations on the allocated registers to achieve the purpose of merging and executing the Kth loop, so as to reduce repeated memory access operations and improve the parallelism of program processing.

[0022] According to the above scheme, the value of K1 is determined according to the following formula:

[0023] K1=Min{FreeReg.num / CurrentReg.num, SpareALU.num}

[0024] Where FreeReg.num is the number of globally unused registers, CurrentReg.num is the number of registers used in this loop, and SpareALU.num is the number of isomorphic hardware functional units idle in the current clock cycle.

[0025] According to the above scheme, in step S3, the loop body is arranged at the assembly language level, and the clock cycle arrangement interval between two adjacent loops is set to be K2. Thus, the calculation instruction of the nth loop and the memory access of the (n+1)th loop are parallel during the matrix processing, and the calculation process of the matrix data in the (n+1)th loop does not need to wait for the memory access to be completed.

[0026] According to the above scheme, the value of K2 is determined according to the following formula:

[0027] K2=Max{ALU.num / ThisALU.num,LongestCMD.cycle,mem.cycle+1}

[0028] Where ALU.num is the number of homogeneous functional units in the vector DSP chip, ThisALU is the number of functional units used in a single loop, LongestCMD.cycle is the number of clock cycles used by the longest instruction in a single loop, and mem.cycle is the number of clock cycles for memory access instructions.

[0029] According to the above scheme, in step S4, before the data write-back operation of the nth loop, the data to be processed in the (n+1)th loop is stored in a register and written back before the data is processed. Alternatively, the data in the register can be processed directly and written back after the calculation is completed.

[0030] The matrix processing system and method for vector-oriented DSP chips according to the present invention have the following advantages:

[0031] This invention proposes a method for vector digital signal processing (DSP) chips. Based on the characteristics of matrix processing and the architecture of DSPs, a data storage scheme is developed to pave the way for parallel matrix operations using vectors. A cyclic parallel optimization scheme for matrix data processing is introduced to improve the parallelism of matrix processing and the utilization of vector DSP hardware resources. A data access latency hiding scheme is introduced to reduce performance loss caused by memory access during matrix processing and improve the parallelism of program execution. A data protection scheme is introduced to avoid data overwriting errors caused during the SIMD vectorized cyclic processing of matrices. By adopting these schemes, the matrix processing process is made more aligned with the architecture characteristics of DSPs, leveraging the computational performance advantages of DSPs and improving the degree and efficiency of instruction-level and data-level parallelism in matrix processing. Attached Figure Description

[0032] The present invention will be further described below with reference to the accompanying drawings and embodiments. In the accompanying drawings:

[0033] Figure 1 This is a schematic diagram illustrating the data memory access latency concealment of the matrix processing system and method for vector DSP chips according to the present invention;

[0034] Figure 2 This is a schematic diagram illustrating data protection for the matrix processing system and method for vector DSP chips according to the present invention. Detailed Implementation

[0035] To provide a clearer understanding of the technical features, objectives, and effects of the present invention, specific embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0036] like Figure 1-2 As shown, the matrix processing method for vector DSP chips of the present invention includes a matrix storage space allocation module, a matrix cyclic parallel optimization module, a data memory access latency hiding module, and a data protection module.

[0037] The matrix storage space allocation module sets the corresponding storage space allocation strategy for the matrix data to be processed, laying the groundwork for subsequent matrix operations in a SIMD vectorized manner; the matrix loop parallel optimization module allocates registers for the data processed in the inner loop of the matrix and schedules the functional units isomorphic to the vector DSP to perform parallel processing on multiple inner loops of the matrix; the data memory access latency hiding module hides the memory access latency in the matrix data processing process in the time slots of data operation, reducing the performance loss caused by memory access during matrix processing and improving the degree of parallelism of program execution; the data protection module is used to avoid errors caused by data write-back during matrix data processing in the vector digital signal processor.

[0038] The present invention also provides a matrix processing method for vector DSP chips, comprising the following steps: S1, storing the data to be processed: setting a corresponding storage scheme for the matrix data to be processed according to the size of the matrix;

[0039] If the matrix to be processed satisfies max{Nrows, Ncols} < N, then all data to be processed is placed in the scalar space. If Nrows * Ncols * sizeof(auto) ≤ VectorMemory.Size, then all data to be processed is placed in the vector memory space. Nrow is the number of rows in the matrix to be processed, Ncols is the number of columns in the matrix to be processed, N is the number of single instruction data outputs of the vector DSP processor, sizeof(auto) is the space size used to store a single piece of data to be processed, and VectorMemory.Size is the total space size of the vector memory.

[0040] S2. Optimize the matrix data processing process in parallel loops: For the inner loop in the matrix operation process, K1 loops are executed by merging the allocation of registers and the scheduling of DSP functional units.

[0041] For each data in the K1th loop, a corresponding vector register is allocated, and the isomorphic vector DSP hardware functional unit is scheduled to perform operations on the allocated registers, so as to merge the execution of K loops, reduce repeated memory access operations, and improve the parallelism of program processing.

[0042] The value of K1 is determined according to the following formula:

[0043] K1=Min{FreeReg.num / CurrentReg.num, SpareALU.num}

[0044] Where FreeReg.num is the number of globally unused registers, CurrentReg.num is the number of registers used in this loop, and SpareALU.num is the number of isomorphic hardware functional units idle in the current clock cycle.

[0045] S3. Hiding data memory access latency: For matrix data processed in a loop, data memory access accounts for the majority of the latency consumed in global processing;

[0046] The loop body is arranged at the assembly language level, and the clock cycle interval between two adjacent loops is set to be K2. Thus, the calculation instructions of the nth loop and the memory access of the (n+1)th loop are parallel during matrix processing, and the calculation process of the matrix data in the (n+1)th loop does not need to wait for the memory access to complete.

[0047] The value of K2 is determined according to the following formula:

[0048] K2=Max{ALU.num / ThisALU.num,LongestCMD.cycle,mem.cycle+1}

[0049] Where ALU.num is the number of homogeneous functional units in the vector DSP chip, ThisALU is the number of functional units used in a single loop, LongestCMD.cycle is the number of clock cycles used by the longest instruction in a single loop, and mem.cycle is the number of clock cycles for memory access instructions.

[0050] S4. Data protection: If matrix operations are processed row-by-row, and the size of the matrix is ​​not an integer multiple of the number of single instruction outputs of the vector digital signal processor, the write-back operation of the nth loop will partially overwrite the data to be processed in the (n+1)th loop, thus causing an error.

[0051] Before the data write-back operation in the nth loop, the data to be processed in the (n+1)th loop is stored in a register and written back before processing this part of the data. Alternatively, the data in the register can be processed directly and written back after the calculation is completed.

[0052] The embodiments of the present invention have been described above with reference to the accompanying drawings. However, the present invention is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of the present invention without departing from the spirit and scope of the claims. All of these forms are within the protection scope of the present invention.

Claims

1. A matrix processing system for vector DSP chips, characterized in that, It includes a matrix storage space allocation module, a matrix cyclic parallel optimization module, a data memory access latency hiding module, and a data protection module; The matrix storage space allocation module is used to set the corresponding storage space allocation strategy for the matrix data to be processed. If the matrix to be processed satisfies max{Nrows,Ncols}<N, then all the data to be processed is placed in the scalar space; if Nrows * Ncols * sizeof(auto) ≤ VectorMemory.Size, then all the data to be processed is placed in the vector storage space. Nrow is the number of rows in the matrix to be processed, Ncols is the number of columns in the matrix to be processed, N is the number of single instruction data outputs of the vector DSP processor, sizeof(auto) is the space size used to store a single piece of data to be processed, and VectorMemory.Size is the total space size of the vector memory. The matrix loop parallel optimization module allocates data registers for the inner loop processing of the matrix and schedules functional units that are isomorphic to the vector DSP to parallelize the multiple inner loops of the matrix. For the inner loop in the matrix operation process, the strategy of allocating registers and scheduling DSP functional units is used to execute K1 loops in a combined manner. For each data point in the K1th iteration, a corresponding vector register is allocated, and the isomorphic vector DSP hardware functional unit is scheduled to perform operations on the allocated registers. The value of K1 is determined according to the following formula: K1 = Min{FreeReg.num / CurrentReg.num, SpareALU.num} Where FreeReg.num is the number of globally unused registers, CurrentReg.num is the number of registers used in this loop, and SpareALU.num is the number of isomorphic hardware functional units idle in the current clock cycle; The data memory access latency hiding module is used to hide the memory access latency in the matrix data processing process within the data operation time slots; The loop body is arranged at the assembly language level, and the clock cycle interval between two adjacent loops is set to be K2. Thus, the calculation instructions of the nth loop and the memory access of the (n+1)th loop are parallel during matrix processing, and the calculation process of the matrix data in the (n+1)th loop does not need to wait for the memory access to complete. The value of K2 is determined according to the following formula: K2 = Max{ALU.num / ThisALU.num, LongestCMD.cycle, mem.cycle+1} Where ALU.num is the number of homogeneous functional units in the vector DSP chip, ThisALU is the number of functional units used in a single loop, LongestCMD.cycle is the number of clock cycles used by the longest instruction in a single loop, and mem.cycle is the number of clock cycles for a memory access instruction; The data protection module is used to prevent errors caused by data write-back during matrix data processing; Before the data write-back operation in the nth loop, the data to be processed in the (n+1)th loop is stored in a register and written back before processing this part of the data, or the data in the register is processed directly and written back after the calculation is completed.

2. A matrix processing method for vector DSP chips, characterized in that, Includes the following steps: S1. Store the data to be processed: Set up an appropriate storage scheme for the matrix data to be processed according to the size of the matrix. If the matrix to be processed satisfies max{Nrows,Ncols}<N, then all the data to be processed is placed in the scalar space; if Nrows * Ncols * sizeof(auto) ≤ VectorMemory.Size, then all the data to be processed is placed in the vector storage space. Nrow is the number of rows in the matrix to be processed, Ncols is the number of columns in the matrix to be processed, N is the number of single instruction data outputs of the vector DSP processor, sizeof(auto) is the space size used to store a single piece of data to be processed, and VectorMemory.Size is the total space size of the vector memory. S2. Optimize the matrix data processing process in parallel loops: For the inner loop in the matrix operation process, the strategy of allocating registers and scheduling DSP functional units is used to merge the execution of K1 loops; allocate a corresponding vector register for each data in the K1 loops, and schedule the isomorphic vector DSP hardware functional unit to perform operations on the allocated registers. The value of K1 is determined according to the following formula: K1 = Min{FreeReg.num / CurrentReg.num, SpareALU.num} Where FreeReg.num is the number of globally unused registers, CurrentReg.num is the number of registers used in this loop, and SpareALU.num is the number of isomorphic hardware functional units idle in the current clock cycle; S3. Data access latency is hidden; The loop body is arranged at the assembly language level, and the clock cycle interval between two adjacent loops is set to be K2. Thus, the calculation instructions of the nth loop and the memory access of the (n+1)th loop are parallel during matrix processing, and the calculation process of the matrix data in the (n+1)th loop does not need to wait for the memory access to complete. The value of K2 is determined according to the following formula: K2 = Max{ALU.num / ThisALU.num, LongestCMD.cycle, mem.cycle+1} Where ALU.num is the number of homogeneous functional units in the vector DSP chip, ThisALU is the number of functional units used in a single loop, LongestCMD.cycle is the number of clock cycles used by the longest instruction in a single loop, and mem.cycle is the number of clock cycles for a memory access instruction; S4. Protect the data; Before the data write-back operation in the nth loop, the data to be processed in the (n+1)th loop is stored in a register and written back before processing this part of the data, or the data in the register is processed directly and written back after the calculation is completed.

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