Memory device and method of manufacturing the same

Abstract

A memory device and a method of fabricating the same are disclosed. The memory device includes a semiconductor substrate, a plurality of bit line structures, a plurality of isolation structures, a storage node contact structure, and a plurality of first voids. The bit line structures, the isolation structures, and the storage node contact structure are disposed on the semiconductor substrate. Each bit line structure extends along a first direction, and the plurality of bit line structures are arranged along a second direction. The plurality of isolation structures are located between adjacent ones of the plurality of bit line structures, the storage node contact structure is located between two adjacent ones of the plurality of bit line structures, and the storage node contact structure is located between two adjacent ones of the plurality of isolation structures along the first direction. The storage node contact structure includes four corner portions, the plurality of first voids are disposed in the storage node contact structure, and the plurality of first voids are located in at least two of the four corner portions, respectively. In this way, the operational performance of the memory device and / or the production capacity of the method of fabricating the same can be improved.

Description

TECHNICAL FIELD

[0001] The present application relates to a memory device and a manufacturing method thereof, and more particularly, to a memory device including a storage node contact structure having voids and a manufacturing method thereof. BACKGROUND

[0002] A memory, such as a dynamic random access memory (DRAM), generally includes a storage capacitor for storing an electric charge representing storage information and a storage transistor electrically connected to the storage capacitor through a node contact structure. In response to product demand, the density of the storage unit needs to be continuously improved, which causes the difficulty and complexity of the related manufacturing process and design to increase, thereby increasing the production cost. Therefore, it is still necessary to improve the production efficiency and reduce the production cost through structural design and / or manufacturing process improvement. SUMMARY

[0003] The present application provides a memory device and a manufacturing method thereof, in which voids are formed in a storage node contact structure and located in at least two of four corner portions of the storage node contact structure, thereby reducing the negative impact of the voids on the storage node contact structure under the condition of improving the production capacity of the manufacturing method.

[0004] One embodiment of the present application provides a memory device including a semiconductor substrate, a plurality of bit line structures, a plurality of isolation structures, a storage node contact structure, and a plurality of first voids. The bit line structures, the isolation structures, and the storage node contact structure are disposed on the semiconductor substrate. Each bit line structure extends along a first direction, and the plurality of bit line structures are arranged along a second direction. The plurality of isolation structures are located between adjacent bit line structures, the storage node contact structure is located between two adjacent bit line structures, and the storage node contact structure is located between two adjacent isolation structures in the first direction. The storage node contact structure includes four corner portions, the plurality of first voids are disposed in the storage node contact structure, and the plurality of first voids are located in at least two of the four corner portions, respectively.

[0005] An embodiment of the present invention provides a method for manufacturing a memory device, comprising the following steps: forming a plurality of bit line structures on a semiconductor substrate, wherein each bit line structure extends along a first direction and the plurality of bit line structures are arranged along a second direction; forming a plurality of isolation structures on the semiconductor substrate, wherein the plurality of isolation structures are located between adjacent bits line structures; forming a memory node contact structure on the semiconductor substrate, wherein the memory node contact structure is located between two adjacent bits line structures and, in the first direction, between two adjacent isolation structures; and forming a plurality of first gaps in the memory node contact structure, wherein the memory node contact structure includes four corner portions and the plurality of first gaps are respectively located in at least two of the four corner portions. Attached Figure Description

[0006] Figure 1 This is a top view schematic diagram of a memory device according to an embodiment of the present invention.

[0007] Figure 2 This is a partially enlarged top view of a memory device according to an embodiment of the present invention.

[0008] Figure 3 This is a cross-sectional schematic diagram of a memory device according to an embodiment of the present invention.

[0009] Figure 4 This is another cross-sectional schematic diagram of a memory device according to an embodiment of the present invention.

[0010] Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 and Figure 12 This is a schematic diagram of a method for manufacturing a memory device according to an embodiment of the present invention, wherein... Figure 6 for Figure 5 A cross-sectional view along another direction under the same conditions. Figure 7 for Figure 5 A diagram illustrating the subsequent situation. Figure 8 for Figure 7 A diagram illustrating the subsequent situation. Figure 9 for Figure 8 A diagram illustrating the subsequent situation. Figure 10 for Figure 9 A cross-sectional view along another direction under the same conditions. Figure 11 for Figure 9 A diagram illustrating the subsequent situation. Figure 12 for Figure 10 A diagram illustrating the subsequent situation.

[0011] The reference numerals in the attached figures are explained as follows:

[0012] 10 semiconductor substrate

[0013] 12 trench isolation structure

[0014] 22 gate dielectric layer

[0015] 24 work function layer

[0016] 26 conductive layer

[0017] 28 cap layer

[0018] 32 mask layer

[0019] 34 mask layer

[0020] 36 mask layer

[0021] 40 conductive epitaxial material

[0022] 50 insulating material

[0023] 50S second sidewall structure

[0024] 60 conductive structure

[0025] 62 dielectric layer

[0026] 91 epitaxial growth process

[0027] 92 etch-back process

[0028] 101 memory device

[0029] 102 memory device

[0030] BC bit line contact structure

[0031] BL bit line structure

[0032] CL cap layer

[0033] CR corner portion

[0034] D1 first direction

[0035] D2 second direction

[0036] D3 vertical direction

[0037] IS isolation structure

[0038] RC recess

[0039] SC storage node contact structure

[0040] SP first sidewall structure

[0041] S1 spacer

[0042] S2 spacer

[0043] S3 spacer

[0044] TS top surface

[0045] V1 first void

[0046] V2 second void

[0047] WL word line structure DETAILED DESCRIPTION

[0048] In order to enable a person skilled in the art familiar with the present application to further understand the present application, several preferred embodiments of the present application are listed below, and the technical solutions of the present application and the effects to be achieved are described in detail with reference to the accompanying drawings. Those skilled in the art can replace, reorganize, mix the features in several different embodiments to complete other embodiments without departing from the spirit of the present application.

[0049] Please refer to Figures 1 to 4 . Figure 1 is a top view schematic diagram of a memory device 101 according to an embodiment of the present application, Figure 2 is a partial enlarged top view schematic diagram of the memory device according to the embodiment, Figure 3 is a cross-sectional schematic diagram of the memory device 101 according to the embodiment, and Figure 4 is another cross-sectional schematic diagram of the memory device 101 according to the embodiment. In some embodiments, Figure 3 may be regarded as a cross-sectional schematic diagram drawn along a longitudinal cross-sectional line (for example, a cross-sectional line parallel to the second direction D2 in Figure 1 may be regarded as a cross-sectional schematic diagram drawn along a transverse cross-sectional line (for example, a cross-sectional line parallel to the first direction D1 in Figure 4 may be regarded as a cross-sectional schematic diagram drawn along a transverse cross-sectional line (for example, a cross-sectional line parallel to the first direction D1 in Figure 1 may be regarded as a cross-sectional schematic diagram drawn along a transverse cross-sectional line (for example, a cross-sectional line parallel to the first direction D1 in Figures 1 to 4As shown, the memory device 101 includes a semiconductor substrate 10, a plurality of bit line structures BL, a plurality of isolation structures IS, a storage node contact structure SC, and a plurality of first voids VI. The bit line structures BL, the isolation structures IS, and the storage node contact structure SC are disposed on the semiconductor substrate 10. Each bit line structure BL extends along a first direction Dl, and the plurality of bit line structures BL are arranged in a repeating pattern along a second direction D2. In some embodiments, the second direction D2 can be substantially orthogonal to the first direction Dl, but the application is not limited thereto. The plurality of isolation structures IS are located between adjacent ones of the plurality of bit line structures BL, the storage node contact structure SC is located between adjacent ones of the plurality of bit line structures BL, and the storage node contact structure SC is located between adjacent ones of the plurality of isolation structures IS along the first direction Dl. The storage node contact structure SC includes four corner portions CR, the plurality of first voids VI are disposed in the storage node contact structure SC, and the plurality of first voids VI are located in at least two of the four corner portions CR, respectively. Since the first voids VI are located in the corner portions CR of the storage node contact structure SC without affecting the contact condition between the storage node contact structure SC and the semiconductor substrate 10 (e.g., source / drain regions formed in the semiconductor substrate 10, not shown), the voids can be allowed to be formed in the storage node contact structure SC under the condition that the function of the storage node contact structure SC is ensured, so that the storage node contact structure SC can be formed by using a faster fabrication process, and thus the production capacity (throughput) of the corresponding process equipment can be improved, the production capacity can be increased, and / or the production cost can be relatively reduced.

[0050] In some embodiments, as Figure 1As shown, the memory device 101 can include a plurality of storage node contact structures SC, and the plurality of storage node contact structures SC can be arranged in an array manner along a first direction Dl and a second direction D2, but the scope of the present application is not limited thereto. The plurality of storage node contact structures SC and the plurality of isolation structures IS can be alternately arranged along the first direction Dl, the plurality of storage node contact structures SC and the plurality of bit line structures BL can be alternately arranged along the second direction D2, and each isolation structure IS can be located between two adjacent storage node contact structures SC along the first direction Dl. Each corner portion CR of each storage node contact structure SC can be surrounded by one of two adjacent isolation structures IS corresponding to the storage node contact structure SC and one of two adjacent bit line structures BL corresponding to the storage node contact structure SC. In some embodiments, the first direction Dl and the second direction D2 can be regarded as horizontal directions, and a vertical direction D3 orthogonal to the first direction Dl and the second direction D2 can be regarded as a thickness direction of the semiconductor substrate 10. The semiconductor substrate 10 can have opposite upper and lower surfaces along the vertical direction D3, and the bit line structures BL, the isolation structures IS, and the storage node contact structures SC can be at least partially disposed on the upper surface. In this context, a position and / or a component that is relatively higher along the vertical direction D3 can be farther from the lower surface of the semiconductor substrate 10 along the vertical direction D3 than a position and / or a component that is relatively lower along the vertical direction D3, a lower portion or a bottom portion of a component can be closer to the lower surface of the semiconductor substrate 10 along the vertical direction D3 than an upper portion or a top portion of the component, a component above another component can be regarded as relatively farther from the lower surface of the semiconductor substrate 10 along the vertical direction D3, and a component below another component can be regarded as relatively closer to the lower surface of the semiconductor substrate 10 along the vertical direction D3. In addition, an upper surface of a particular component can include a topmost surface of the component along the vertical direction D3, and a lower surface of the particular component can include a bottommost surface of the component along the vertical direction D3.

[0051] In some embodiments, as Figure 3As shown, the semiconductor substrate 10 can include a silicon substrate, a silicon-on-insulator (SOI) substrate, a silicon germanium substrate, a silicon carbide substrate, or the like. In addition, in some embodiments, the memory device 101 can further include a plurality of trench isolation structures 12 disposed in the semiconductor substrate 10 to define a plurality of active regions in the semiconductor substrate 10, source / drain regions can be formed in the active regions, and the storage node contact structures SC can be disposed on and in contact with the source / drain regions to form electrical connections therewith. The trench isolation structures 12 can include a single layer or a plurality of layers of insulating material such as silicon nitride, silicon oxynitride, silicon carbon nitride, or the like. In addition, as shown, the memory device 101 can further include a plurality of word line structures WL, each of which can extend along a second direction D2, and the plurality of word line structures WL can be arranged in a repeating pattern along a first direction Dl. In some embodiments, the word line structures WL can be disposed in the semiconductor substrate 10 using a buried approach, and thus the word line structures WL can be considered buried word lines, but the application is not limited thereto. In addition, each of the word line structures WL can include a gate dielectric layer 22, a work function layer 24 disposed on the gate dielectric layer 22, a conductive layer 26 disposed on the work function layer 24, and a cap layer 28 disposed on the work function layer 24 and the conductive layer 26. The gate dielectric layer 22 can include a high-k dielectric material or the like. The high-k dielectric material can include hafnium oxide (HfO4), hafnium silicon oxide (HfSiO4), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al2O3), tantalum oxide (Ta2O5), zirconium oxide (ZrO2), or the like. The work function layer 24 can include titanium nitride, titanium carbide, tantalum nitride, tantalum carbide, tungsten carbide, titanium trialuminide, aluminum titanium nitride, or the like, the conductive layer 26 can include tungsten, aluminum, copper, titanium aluminide, titanium, or the like, and the cap layer 28 can include silicon nitride, silicon oxynitride, silicon carbon nitride, or the like. X In some embodiments, as shown, the memory device 101 can further include a plurality of word line structures WL, each of which can extend along a second direction D2, and the plurality of word line structures WL can be arranged in a repeating pattern along a first direction Dl. In some embodiments, the word line structures WL can be disposed in the semiconductor substrate 10 using a buried approach, and thus the word line structures WL can be considered buried word lines, but the application is not limited thereto. In addition, each of the word line structures WL can include a gate dielectric layer 22, a work function layer 24 disposed on the gate dielectric layer 22, a conductive layer 26 disposed on the work function layer 24, and a cap layer 28 disposed on the work function layer 24 and the conductive layer 26. The gate dielectric layer 22 can include a high-k dielectric material or the like. The high-k dielectric material can include hafnium oxide (HfO4), hafnium silicon oxide (HfSiO4), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al2O3), tantalum oxide (Ta2O5), zirconium oxide (ZrO2), or the like. The work function layer 24 can include titanium nitride, titanium carbide, tantalum nitride, tantalum carbide, tungsten carbide, titanium trialuminide, aluminum titanium nitride, or the like, the conductive layer 26 can include tungsten, aluminum, copper, titanium aluminide, titanium, or the like, and the cap layer 28 can include silicon nitride, silicon oxynitride, silicon carbon nitride, or the like.

[0052] In some embodiments, as shown, the memory device 101 can further include a plurality of word line structures WL, each of which can extend along a second direction D2, and the plurality of word line structures WL can be arranged in a repeating pattern along a first direction Dl. In some embodiments, the word line structures WL can be disposed in the semiconductor substrate 10 using a buried approach, and thus the word line structures WL can be considered buried word lines, but the application is not limited thereto. In addition, each of the word line structures WL can include a gate dielectric layer 22, a work function layer 24 disposed on the gate dielectric layer 22, a conductive layer 26 disposed on the work function layer 24, and a cap layer 28 disposed on the work function layer 24 and the conductive layer 26. The gate dielectric layer 22 can include a high-k dielectric material or the like. The high-k dielectric material can include hafnium oxide (HfO4), hafnium silicon oxide (HfSiO4), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al2O3), tantalum oxide (Ta2O5), zirconium oxide (ZrO2), or the like. The work function layer 24 can include titanium nitride, titanium carbide, tantalum nitride, tantalum carbide, tungsten carbide, titanium trialuminide, aluminum titanium nitride, or the like, the conductive layer 26 can include tungsten, aluminum, copper, titanium aluminide, titanium, or the like, and the cap layer 28 can include silicon nitride, silicon oxynitride, silicon carbon nitride, or the like. Figure 3 ​As shown, the memory device 101 can further include a plurality of first sidewall structures SP disposed on the semiconductor substrate 10, each first sidewall structure SP can be disposed on a sidewall of a corresponding bit line structure BL, and each first sidewall structure SP can be sandwiched between the corresponding bit line structure BL and the storage node contact structure SC in the second direction D2. In addition, each corner portion CR of each storage node contact structure SC can be in direct contact with one and / or both of two adjacent isolation structures IS and one of two adjacent first sidewall structures SP corresponding to the storage node contact structure SC, but the disclosure is not limited thereto. In some embodiments, the first sidewall structure SP can include a multi-layer structure formed of different insulating materials, but the disclosure is not limited thereto. For example, the first sidewall structure SP can include a spacer S1, a spacer S2, and a spacer S3 disposed sequentially outward from the sidewall of the bit line structure BL in the second direction D2, the spacers S1, S2, and S3 can be nitride insulating material, oxide insulating material, and nitride insulating material, respectively, or other combinations of the above materials, but the disclosure is not limited thereto. In some embodiments, the memory device 101 can further include a plurality of bit line contact structures BC and a plurality of cap layers CL, each bit line contact structure BC can be located between the semiconductor substrate 10 and a corresponding bit line structure BL in the vertical direction D3, and each cap layer CL can be located above a corresponding bit line structure BL in the vertical direction D3. The bit line contact structure BC can include a non-metallic conductive material, such as polysilicon, amorphous silicon, or other silicon-containing or non-silicon-containing non-metallic conductive material, the cap layer CL can include silicon nitride, silicon oxynitride, silicon carbon nitride, or other suitable insulating material, and the bit line structure BL can include a conductive layer (not shown) and a barrier layer (not shown) located between the conductive layer and the bit line contact structure BC. The conductive layer in the bit line structure BL can include aluminum, tungsten, copper, titanium aluminum alloy, or other suitable low resistivity metallic conductive material, and the barrier layer in the bit line structure BL can include titanium, tungsten silicide, tungsten nitride, or other suitable conductive barrier material. The bit line structure BL can be electrically connected to a source / drain region in the semiconductor substrate 10 through the bit line contact structure BC, the bit line structure BL and the storage node contact structure SC can be respectively electrically connected to different source / drain regions located in the same active region, and a storage capacitor structure (not shown) can be electrically connected to a corresponding source / drain region through the storage node contact structure SC. In some embodiments, the memory device 101 can further include a mask material (such as the mask layer 32, the mask layer 34, and the mask layer 36 shown in FIG. 1) disposed between the bit line contact structure BC and the semiconductor substrate 10 in the vertical direction D3 to form an electrical isolation effect between the bit line contact structure BC and the non-corresponding active region. Figure 4

[0053] In some embodiments, as shown in FIG. 1, the memory device 101 can further include a plurality of second sidewall structures SP' disposed on the semiconductor substrate 10, each second sidewall structure SP' can be disposed on a sidewall of a corresponding bit line structure BL, and each second sidewall structure SP' can be sandwiched between the corresponding bit line structure BL and the storage node contact structure SC in the second direction D2. In addition, each corner portion CR of each storage node contact structure SC can be in direct contact with one and / or both of two adjacent isolation structures IS and one of two adjacent second sidewall structures SP' corresponding to the storage node contact structure SC, but the disclosure is not limited thereto. In some embodiments, the second sidewall structure SP' can include a multi-layer structure formed of different insulating materials, but the disclosure is not limited thereto. For example, the second sidewall structure SP' can include a spacer S1', a spacer S2', and a spacer S3' disposed sequentially outward from the sidewall of the bit line structure BL in the second direction D2, the spacers S1', S2', and S3' can be nitride insulating material, oxide insulating material, and nitride insulating material, respectively, or other combinations of the above materials, but the disclosure is not limited thereto. In some embodiments, the memory device 101 can further include a plurality of bit line contact structures BC' and a plurality of cap layers CL', each bit line contact structure BC' can be located between the semiconductor substrate 10 and a corresponding bit line structure BL in the vertical direction D3, and each cap layer CL' can be located above a corresponding bit line structure BL in the vertical direction D3. The bit line contact structure BC' can include a non-metallic conductive material, such as polysilicon, amorphous silicon, or other silicon-containing or non-silicon-containing non-metallic conductive material, the cap layer CL' can include silicon nitride, silicon oxynitride, silicon carbon nitride, or other suitable insulating material, and the bit line structure BL can include a conductive layer (not shown) and a barrier layer (not shown) located between the conductive layer and the bit line contact structure BC'. The conductive layer in the bit line structure BL can include aluminum, tungsten, copper, titanium aluminum alloy, or other suitable low resistivity metallic conductive material, and the barrier layer in the bit line structure BL can include titanium, tungsten silicide, tungsten nitride, or other suitable conductive barrier material. The bit line structure BL can be electrically connected to a source / drain region in the semiconductor substrate 10 through the bit line contact structure BC', the bit line structure BL and the storage node contact structure SC can be respectively electrically connected to different source / drain regions located in the same active region, and a storage capacitor structure (not shown) can be electrically connected to a corresponding source / drain region through the storage node contact structure SC. In some embodiments, the memory device 101 can further include a mask material (such as the mask layer 32, the mask layer 34, and the mask layer 36 shown in FIG. 1) disposed between the bit line contact structure BC' and the semiconductor substrate 10 in the vertical direction D3 to form an electrical isolation effect between the bit line contact structure BC' and the non-corresponding active region. Figure 4 ​As shown, the isolation structures IS can comprise nitride insulating material or other suitable insulating material, and the storage node contact structure SC can comprise non-metallic conductive material, such as polysilicon, amorphous silicon, or other non-metallic conductive material with or without silicon. In some embodiments, the plurality of first voids VI can be respectively located in four corner portions CR of the storage node contact structure SC, and the plurality of first voids VI can be separated from each other without being directly connected to each other, so as to avoid the first voids VI being too large to affect the structural strength and / or conductive effect of the storage node contact structure SC. In addition, the first voids VI located in the corner portions CR can be in direct contact with one of the two adjacent isolation structures IS and / or one of the two adjacent first sidewall structures SP, but the disclosure is not limited thereto. In some embodiments, the memory device 101 can further comprise second voids V2, which are disposed in the storage node contact structure SC and separated from the first voids VI. The second voids V2 can be disposed in the storage node contact structure SC and away from the corner portions CR of the storage node contact structure SC, and neither the first voids VI nor the second voids V2 are directly connected to the semiconductor substrate 10 and / or the source / drain regions in the semiconductor substrate 10, thereby avoiding the voids affecting the contact condition of the storage node contact structure SC and the source / drain regions in the semiconductor substrate 10. In some embodiments, the first voids VI and the second voids V2 can respectively comprise air gaps or other types of void structures, and the second voids V2 can be larger than the first voids VI, but the disclosure is not limited thereto.

[0054] Referring to Figures 1 to 6 . Figure 5 With Figure 6 a manufacturing method of a memory device according to an embodiment of the disclosure, wherein Figure 5 may be regarded as Figure 3 a schematic diagram of a previous condition, and Figure 6 may be regarded as Figure 4 a schematic diagram of a previous condition. As Figures 1 to 4 shown, a manufacturing method of a memory device according to an embodiment of the disclosure comprises the following steps. A plurality of bit line structures BL is formed on a semiconductor substrate 10, each bit line structure BL extends along a first direction D1, and the plurality of bit line structures BL is arranged along a second direction D2. A plurality of isolation structures IS is formed on the semiconductor substrate 10, and the plurality of isolation structures IS is located between adjacent bit line structures BL. A storage node contact structure SC is formed on the semiconductor substrate 10, the storage node contact structure SC is located between two adjacent bit line structures BL, and the storage node contact structure SC is located between two adjacent isolation structures IS in the first direction D1. A plurality of first voids VI is located in the storage node contact structure SC, the storage node contact structure SC comprises four corner portions CR, and the plurality of first voids VI is respectively located in at least two of the four corner portions CR.

[0055] In some embodiments, the method of forming the storage node contact structure SC can include, but is not limited to, the following steps. As shown in Figure 5 Figure 6 After the formation of the bit line structures BL and the isolation structures IS, a portion of the semiconductor substrate 10 (e.g., a portion of the source / drain region in the semiconductor substrate 10) can be exposed by etching down in the region surrounded by the plurality of bit line structures BL and the plurality of isolation structures IS. Then, an epitaxial growth process 91 can be performed to form a conductive epitaxial material 40 on the semiconductor substrate 10. A portion of the conductive epitaxial material 40 can cover the bit line structures BL, the cap layer CL, the first sidewall structure SP, and the isolation structure IS in the vertical direction D3, and another portion of the conductive epitaxial material 40 can fill in the space surrounded by the plurality of bit line structures BL and the plurality of isolation structures IS. Then, a back-etching process can be performed on the conductive epitaxial material 40 to remove a portion of the conductive epitaxial material 40 while leaving a portion of the conductive epitaxial material 40 in the space surrounded by the plurality of bit line structures BL and the plurality of isolation structures IS, forming the storage node contact structure SC as shown in Figure 3 Figure 4 In some embodiments, the storage node contact structure SC shown in Figure 5 Figure 6 may be formed in the conductive epitaxial material 40 by the epitaxial growth process 91 described above in the

[0056] ​​​Different embodiments of the present application will be described below, and for simplicity of illustration, the following description will mainly focus on the different parts of each embodiment, and the same parts will not be repeated. In addition, the same components in each embodiment of the present application are denoted by the same reference numerals, so as to facilitate mutual comparison between each embodiment.

[0057] Please refer to Figures 5 to 12 . Figures 5 to 12 The manufacturing method of the memory device of another embodiment of the present application is shown in the following figures, wherein Figure 6 is a cross-sectional view along another direction under the condition of Figure 5 , and Figure 7 is a cross-sectional view along another direction under the condition of Figure 5 , and Figure 8 is a cross-sectional view along another direction under the condition of Figure 7 , and Figure 9 is a cross-sectional view along another direction under the condition of Figure 8 , and Figure 10 is a cross-sectional view along another direction under the condition of Figure 9 , and Figure 11 is a cross-sectional view along another direction under the condition of Figure 9 , and Figure 12 is a cross-sectional view along another direction under the condition of Figure 10 , and Figure 11 may be regarded as a cross-sectional view of the memory device 102 of another embodiment of the present application, and Figure 12 may be regarded as a cross-sectional view of the memory device 102 in another direction. As Figures 5 to 7 shown, after the epitaxial growth process 91 is performed to form the conductive epitaxial material 40, a back-etching process 92 can be performed on the conductive epitaxial material 40 to remove part of the conductive epitaxial material 40, and to retain part of the conductive epitaxial material 40 in the space surrounded by the plurality of bit line structures BL and the plurality of isolation structures IS, thereby forming a storage node contact structure SC. The first void V1 and the second void V2 can be formed in the conductive epitaxial material 40 by the epitaxial growth process 91, and at least part of the first void V1 and / or at least part of the second void V2 can be located in the storage node contact structure SC after the back-etching process 92. In some embodiments, part of the first void V1 can be located near the height at which the conductive epitaxial material 40 stops during the back-etching process 92, so that the first void V1 originally covered by the conductive epitaxial material 40 can be exposed by the back-etching process 92 to become a recess RC. In other words, at least one of the plurality of first voids V1 can become a recess RC extending downward from the upper surface TS of the storage node contact structure SC after the back-etching process 92, and the bottom of the recess RC can be lower than the upper surface TS of the storage node contact structure SC in the vertical direction D3.

[0058] Then, as Figures 8 to 10As shown, a second sidewall structure 50S can be formed on the storage node contact structure SC, and the second sidewall structure 50S can be formed on the sidewalls of two adjacent isolation structures IS and two adjacent bit line structures BL (e.g., on the sidewalls of two adjacent first sidewall structures SP). In some embodiments, an insulating material 50 can be conformally formed on the storage node contact structure SC, the first sidewall structure SP, the cap layer CL, and the isolation structure IS, and a re-etching process can be performed on the insulating material 50 to form the second sidewall structure 50S. In other words, the second sidewall structure 50S is the insulating material 50 that remains on the storage node contact structure SC after the re-etching process, and the insulating material 50 can include nitride (e.g., silicon nitride) or other suitable insulating material. In some embodiments, the insulating material 50 can fill the recess RC described above, and the second sidewall structure 50S can be partially located in the recess RC. The width of the recess RC can be less than or equal to the width of the second sidewall structure 50S, so that the recess RC can be completely filled by the second sidewall structure 50S, and the lower surface of the second sidewall structure 50S can not be level, e.g., the lower surface of the second sidewall structure 50S located in the recess RC can be lower than the lower surface of the second sidewall structure 50S located on the upper surface TS of the storage node contact structure SC in the vertical direction D3, and the bottom of the second sidewall structure 50S (e.g., the lower surface of the second sidewall structure 50S) can be lower than the top of the storage node contact structure SC (e.g., the upper surface TS) in the vertical direction D3. In addition, in some embodiments, the width of the recess RC (e.g., the length of the recess RC in the first direction D1 or in the second direction D2) can be greater than the width of the second sidewall structure 50S (e.g., the length of the second sidewall structure 50S in the first direction D1 or in the second direction D2), and the recess RC in this case is not completely filled by the second sidewall structure 50S.

[0059] As Figures 9 to 12As shown, after the second sidewall structure 50S is formed, the conductive structure 60 and the dielectric layer 62 can be formed. The conductive structure 60 can include aluminum, tungsten, copper, titanium-aluminum alloy, or other suitable low-resistivity conductive material, and the dielectric layer 62 can include oxide, nitride, or other suitable dielectric material. In some embodiments, the conductive structure 60 can include a single layer of conductive material or multiple layers of conductive material, such as a multi-layer conductive structure that can be stacked with cobalt silicide (CoSi), titanium, titanium nitride, tungsten, but the application is not limited thereto. The dielectric layer 62 can be formed on the isolation structure IS and the cap layer CL, and the conductive structure 60 can be formed on the storage node contact structure SC, the second sidewall structure 50S, and the cap layer CL. In the case where the width of the recess RC is greater than the width of the second sidewall structure 50S and the recess RC is not filled by the second sidewall structure 50S, the recess RC can be filled by at least two materials, such as the recess RC can be filled by a portion of the second sidewall structure 50S and a portion of the conductive structure 60, but the application is not limited thereto. In some embodiments, the storage node contact structure SC can be electrically connected to a storage capacitor structure (not shown), such as can be electrically connected to a lower plate of the storage capacitor structure, but the application is not limited thereto.

[0060] As shown in FIG. 1, the memory device 102 can include the second sidewall structure 50S, the conductive structure 60, and the dielectric layer 62 described above. In addition, the memory device 102 can include the recess RC extending downward from the upper surface TS of the storage node contact structure SC, and the recess RC can be formed by the first void V1, so the recess RC can be located in one of the four corner portions (such as the corner portion CR shown in FIG. 1) of the storage node contact structure SC. In some embodiments, the width of the recess RC can be less than or equal to the width of the second sidewall structure 50S, the second sidewall structure 50S can be disposed on the storage node contact structure SC and partially located in the recess RC, the recess RC can be completely filled by the second sidewall structure 50S, and thus the bottom of the second sidewall structure 50S can be lower than the top of the storage node contact structure SC in the vertical direction D3. In addition, in some embodiments, the width of the recess RC can be greater than the width of the second sidewall structure 50S, and thus the recess RC can be filled by at least two materials, such as the recess RC can be filled by a portion of the second sidewall structure 50S and a portion of the conductive structure 60. Figure 11 Figure 12 As shown, the memory device 102 can include the second sidewall structure 50S, the conductive structure 60, and the dielectric layer 62 described above. In addition, the memory device 102 can include the recess RC extending downward from the upper surface TS of the storage node contact structure SC, and the recess RC can be formed by the first void V1, so the recess RC can be located in one of the four corner portions (such as the corner portion CR shown in FIG. 1) of the storage node contact structure SC. In some embodiments, the width of the recess RC can be less than or equal to the width of the second sidewall structure 50S, the second sidewall structure 50S can be disposed on the storage node contact structure SC and partially located in the recess RC, the recess RC can be completely filled by the second sidewall structure 50S, and thus the bottom of the second sidewall structure 50S can be lower than the top of the storage node contact structure SC in the vertical direction D3. In addition, in some embodiments, the width of the recess RC can be greater than the width of the second sidewall structure 50S, and thus the recess RC can be filled by at least two materials, such as the recess RC can be filled by a portion of the second sidewall structure 50S and a portion of the conductive structure 60. Figure 1 Figure 2 As shown, the memory device 102 can include the second sidewall structure 50S, the conductive structure 60, and the dielectric layer 62 described above. In addition, the memory device 102 can include the recess RC extending downward from the upper surface TS of the storage node contact structure SC, and the recess RC can be formed by the first void V1, so the recess RC can be located in one of the four corner portions (such as the corner portion CR shown in FIG. 1) of the storage node contact structure SC. In some embodiments, the width of the recess RC can be less than or equal to the width of the second sidewall structure 50S, the second sidewall structure 50S can be disposed on the storage node contact structure SC and partially located in the recess RC, the recess RC can be completely filled by the second sidewall structure 50S, and thus the bottom of the second sidewall structure 50S can be lower than the top of the storage node contact structure SC in the vertical direction D3. In addition, in some embodiments, the width of the recess RC can be greater than the width of the second sidewall structure 50S, and thus the recess RC can be filled by at least two materials, such as the recess RC can be filled by a portion of the second sidewall structure 50S and a portion of the conductive structure 60.

[0061] In summary, in the memory device and the manufacturing method thereof, the void can be formed in the storage node contact structure and located in at least two of the four corner portions of the storage node contact structure, so as to reduce the negative impact of the void on the storage node contact structure while improving the production capacity of the manufacturing method.

[0062] ​​The above merely provides the preferred embodiments of the present application, and is not used to limit the present application. For those skilled in the art, the present application can have various modifications and changes. Any modifications, equivalent replacements, improvements, etc. made within the principles and technical scope of the present application shall fall into the scope of the present application.

Claims

1. A memory device, characterized in that, include: A semiconductor substrate, wherein the semiconductor substrate includes an active region isolated and defined by a plurality of trench isolation structures; Multiple bit line structures are disposed on the semiconductor substrate, wherein each bit line structure extends along a first direction and the multiple bit line structures are arranged along a second direction; Multiple isolation structures are disposed on the semiconductor substrate, wherein the multiple isolation structures are located between adjacent bit line structures; A memory node contact structure is disposed on the semiconductor substrate and located between two adjacent bit lines in the plurality of bit line structures, and the memory node contact structure is located between two adjacent isolation structures in the first direction, wherein the memory node contact structure includes four corner portions. as well as Multiple first gaps are provided in the storage node contact structure, wherein the multiple first gaps are located in at least two of the four corner portions.

2. The memory device as claimed in claim 1, characterized in that, The multiple first gaps are located in all four of the four corner portions.

3. The memory device as claimed in claim 1, characterized in that, These multiple first gaps are separated from each other.

4. The memory device as claimed in claim 1, characterized in that, Also includes: The second gap is located in the contact structure of the storage node and is separate from the plurality of first gaps.

5. The memory device as claimed in claim 4, characterized in that, The second gap is larger than each of the first gaps.

6. The memory device as claimed in claim 1, characterized in that, Each corner portion is surrounded by one of the two adjacent isolation structures and one of the two adjacent bit line structures.

7. The memory device as claimed in claim 1, characterized in that, Each corner portion is in direct contact with one of the two adjacent isolation structures, and each first gap is in direct contact with one of the two adjacent isolation structures.

8. The memory device as claimed in claim 1, characterized in that, Also includes: A recess extending downward from the upper surface of the storage node contact structure is located in one of the four corner portions; as well as A sidewall structure is disposed on the storage node contact structure and partially located in the recess, wherein the bottom of the sidewall structure is lower than the top of the storage node contact structure.

9. The memory device as claimed in claim 8, characterized in that, The width of the recess is greater than the width of the sidewall structure.

10. The memory device as claimed in claim 8, characterized in that, The depression is filled with at least two materials.

11. The memory device as claimed in claim 8, characterized in that, The lower surface of the sidewall structure is not at equal height.

12. A method for manufacturing a memory device, characterized in that, include: Multiple bit line structures are formed on a semiconductor substrate, wherein each bit line structure extends along a first direction and the multiple bit line structures are arranged along a second direction; Multiple isolation structures are formed on the semiconductor substrate, wherein the multiple isolation structures are located between adjacent bit line structures; as well as A memory node contact structure is formed on the semiconductor substrate. The memory node contact structure is located between two adjacent bit lines in the plurality of bit line structures, and the memory node contact structure is located between two adjacent isolation structures in the first direction. A plurality of first gaps are formed in the memory node contact structure. The memory node contact structure includes four corner portions, and the plurality of first gaps are located in at least two of the four corner portions.

13. The method of manufacturing a memory device as claimed in claim 12, characterized in that, The steps for forming the contact structure of this storage node include: An epitaxial growth process is performed to form a conductive epitaxial material on the semiconductor substrate, wherein the conductive epitaxial material fills a space surrounded by the plurality of bit line structures and the plurality of isolation structures, and the plurality of first gaps are formed during the epitaxial growth process; and The conductive epitaxial material is subjected to an etch-back process to form the contact structure of the memory node.

14. The method of manufacturing a memory device as claimed in claim 13, characterized in that, At least one of the plurality of first voids becomes a recess extending downward from the upper surface of the memory node contact structure after the etch-back process.

15. The method of manufacturing a memory device as claimed in claim 14, characterized in that, Also includes: A sidewall structure is formed on the storage node contact structure, wherein the sidewall structure is formed on the sidewalls of the two adjacent isolation structures and the two adjacent bit line structures, and the sidewall structure is partially located in the recess. The lower surface of the sidewall structure is not of equal height, and the bottom of the sidewall structure is lower than the top of the storage node contact structure.

16. The method of manufacturing a memory device as claimed in claim 15, characterized in that, Also includes: A conductive structure is formed on the storage node contact structure, wherein the recess is filled by a portion of the sidewall structure and a portion of the conductive structure.

17. The method of manufacturing a memory device as claimed in claim 13, characterized in that, The epitaxial growth process forms a second void in the conductive epitaxial material. The second void is located in the memory node contact structure after the etch-back process. The second void is separated from the plurality of first voids and is larger than each of the first voids.

18. The method of manufacturing a memory device as claimed in claim 12, characterized in that, The multiple first gaps are located in the four corner portions respectively, and the multiple first gaps are separated from each other.

19. The method of manufacturing a memory device as claimed in claim 12, characterized in that, Each corner portion is surrounded by one of the two adjacent isolation structures and one of the two adjacent bit line structures.

20. The method of manufacturing a memory device as claimed in claim 12, characterized in that, Each corner portion is in direct contact with one of the two adjacent isolation structures, and each first gap is in direct contact with one of the two adjacent isolation structures.

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