Quantum computer capable of mitigating stretch factor error

Abstract

Techniques are provided for quantum computer error mitigation. For example, one or more embodiments described herein can include a system that can include a memory that can store computer executable components. The system can also include a processor that is operatively coupled to the memory and that can execute the computer executable components stored in the memory. The computer executable components can include an error mitigation component that interpolates gate parameters associated with a target stretch factor from within a reference model that includes reference gate parameters for quantum gates calibrated at a plurality of reference stretch factors.

Description

Background Technology

[0001] This disclosure relates to using stretching factors to mitigate errors in quantum operations, and more specifically, to interpolating quantum gate parameters associated with a target stretching factor from a reference model calibrated at a plurality of reference stretching factors.

[0002] Quantum computers generate noise that degrades the precision of quantum operations. Error mitigation techniques can address this noise and improve the results of quantum computers. In conventional error mitigation techniques, several quantum operations are performed on a quantum circuit. During one or more quantum operation executions, the duration of the gates included in the quantum circuit can be stretched by a given factor, called the stretching factor. By stretching the gate duration, additional noise can be introduced into the quantum operation execution. Thus, the quantum computer can generate multiple result datasets, each with a corresponding amount of noise affected by the stretching factor used. The error-mitigated results can then be extrapolated from the multiple result datasets. However, new gate parameters must be defined and calibrated for each corresponding stretching factor used in the quantum operation execution. Calibrating the gate parameters for each stretching factor requires scientists to access the quantum computer hardware and can be quite time-consuming. Therefore, conventional error mitigation techniques are limited by calibration requirements.

[0003] Other conventional error mitigation techniques achieve this by replacing each two-qubit quantum gate in a quantum circuit with several copies of itself. For example, each two-qubit gate in a quantum circuit can be replaced by an odd number of two-qubit gates. However, these techniques neglect single-qubit gates and can correspond to long stretching factors that may not be suitable for quantum circuits approaching the coherence limit. Furthermore, an additional constraint on conventional error mitigation techniques is that the two sequential applications of two-qubit gates must constitute an identity operation. Summary of the Invention

[0004] The following overview is provided to offer a basic understanding of one or more embodiments of the invention. This overview is not intended to identify key or essential elements, or to depict any scope of a particular embodiment or any scope of the claims. Its sole purpose is to present concepts in a simplified form as a prelude to the more detailed description that follows. In one or more embodiments described herein, systems, computer-implemented methods, apparatuses, and / or computer program products that can facilitate the mitigation of stretching factor errors for quantum operations are described.

[0005] According to one embodiment, a system is provided. The system may include a memory capable of storing computer-executable components. The system may also include a processor operatively coupled to the memory and capable of executing the computer-executable components stored in the memory. The computer-executable components may include error mitigation components that can interpolate gate parameters associated with a target stretching factor from a reference model, which may include reference gate parameters for quantum gates used for calibration at multiple reference stretching factors. An advantage of this system is that a reference model can be employed to reduce calibration overhead.

[0006] In some examples, the system may include a model component that can define multiple reference stretching factors by determining the number of reference stretching factors within a stretching factor interval based on at least one of per-gate error determination and gate parameter determination. An advantage of such a system is that the reference model can include reference stretching factors associated with the dynamic region of quantum gate calibration.

[0007] According to one embodiment, a system is provided. The system may include a memory capable of storing computer-executable components. The system may also include a processor operatively coupled to the memory and capable of executing the computer-executable components stored in the memory. The computer-executable components may include a recommended component that can identify a stretching factor for error mitigation of the quantum circuit based on the gate count and qubit count of the quantum circuit. An advantage of this system is its ability to select the stretching factor expected to be most effective in promoting Richardson error mitigation.

[0008] In some examples, the recommended component can compare the gate count and qubit count of the quantum circuit to a reference table that includes a range of stretching factors associated with defined combinations of gate counts and qubit counts. An advantage of such a system is that the stretching factor can be recommended based on past executions of similar quantum circuits.

[0009] According to an embodiment, a computer-implemented method is provided. This computer-implemented method may include, via a system operatively coupled to a processor, interpolating gate parameters associated with a target stretching factor from a reference model, the reference model including reference gate parameters for calibrating quantum gates at a plurality of reference stretching factors. An advantage of this computer-implemented method is that it can determine the gate parameters for the target stretching factor without calibrating the quantum gates at the target stretching factor.

[0010] In some examples, this computer-implemented method may include determining, by the system, the number of reference stretching factors included within the stretching factor interval based on at least one of per-gate error determination and gate parameter determination. An advantage of this computer-implemented method is that it can generate a highly calibrated reference model at the reference stretching factor associated with the increased variation in the operation of the quantum gates.

[0011] According to another embodiment, a computer-implemented method is provided. This computer-implemented method may include a system operatively coupled to a processor recommending a stretching factor for error mitigation in a quantum circuit based on gate counts and qubit counts. An advantage of this method is that it enables a user to efficiently implement an error mitigation protocol with the desired stretching factor.

[0012] In some examples, the computer-implemented method may also include a randomized benchmark operation performed by the system to determine the maximum stretching factor associated with a set of quantum gates. Furthermore, the computer-implemented method may include the system monitoring the availability of one or more quantum gates from that set. An advantage of this approach is that the stretching factor can be adjusted and / or recommended to meet the capabilities of the quantum hardware (e.g., the recent operational capability of the quantum gates).

[0013] According to an embodiment, a computer program product for error mitigation in quantum computers is provided. The computer program product may include a computer-readable storage medium having program instructions. The program instructions can be executed by a processor to cause the processor to generate a range of stretching factors associated with quantum gates at a plurality of reference stretching factors. The program instructions can also cause the processor to receive stretching factors from the stretching factor range. Additionally, the program instructions can cause the processor to interpolate gate parameters associated with the stretching factors based on the plurality of reference stretching factors. One advantage of this computer program product is that it can reduce the calibration overhead of quantum computers.

[0014] In some examples, the program instructions can also enable the processor to identify a recommended stretching factor from a range of stretching factors based on the gate count and qubit count of a quantum circuit including quantum gates. An advantage of such a computer program product could be increased applicability of error mitigation. Attached Figure Description

[0015] The patent or application document contains at least one color drawing. A copy of the patent or application publication with color drawings will be provided by the official upon request and payment of the necessary fees.

[0016] Figure 1 A block diagram of an exemplary non-limiting system, according to one or more embodiments described herein, is shown that can help mitigate stretching factor errors for one or more quantum operations.

[0017] Figure 2 An illustration of an exemplary non-limiting graph according to one or more embodiments described herein is shown, which characterizes the change per Clifford error, which may affect the number of reference stretch factors used within a stretch factor interval.

[0018] Figure 3A An exemplary non-limiting graph according to one or more embodiments described herein is shown, which can characterize the variation of gate parameters that can affect the number of reference stretch factors used within the stretch factor interval.

[0019] Figure 3B An illustration of an exemplary non-limiting graph according to one or more embodiments described herein is shown, which characterizes the error per Clifford variation, which may affect the number of reference stretch factors used within a stretch factor interval.

[0020] Figure 4 A block diagram of an exemplary non-limiting system, according to one or more embodiments described herein, is shown, capable of determining and / or tracking the maximum stretching factor associated with one or more gates employed by a quantum computer.

[0021] Figure 5 A block diagram of an exemplary non-limiting system according to one or more embodiments described herein is shown, which can interpolate one or more gate parameters of a quantum gate calibrated under multiple reference stretching factors.

[0022] Figure 6 A diagram is shown of an exemplary non-limiting reference model according to one or more embodiments described herein, which may characterize one or more quantum gate parameters associated with a plurality of reference stretching factors.

[0023] Figure 7 The diagram illustrates a block diagram of an example non-limiting system capable of performing one or more quantum operations on one or more quantum computers based on one or more stretching factor scheduling tables, according to one or more embodiments described herein.

[0024] Figure 8 A block diagram of an example non-limiting system is shown, according to one or more embodiments described herein, capable of performing one or more error-mitigation extrapolations to generate error-mitigated results from one or more quantum operations.

[0025] Figure 9 An exemplary non-limiting graph is shown that can demonstrate the effectiveness of the Richardson error mitigation protocol according to one or more embodiments described herein.

[0026] Figure 10 The diagram illustrates an example non-limiting scheme of operation that can be employed by one or more systems to achieve extension factor error mitigation for quantum operations, according to one or more embodiments described herein.

[0027] Figure 11 This document describes a block diagram illustrating a non-limiting system of examples of stretch factor errors that can be recommended for implementation in one or more stretch factor mitigation according to one or more embodiments described herein.

[0028] Figure 12 The diagram illustrates an example non-limiting scheme of operation that can be employed by one or more systems to achieve extension factor error mitigation for quantum operations, according to one or more embodiments described herein.

[0029] Figure 13 The diagram illustrates an exemplary, non-limiting computer-implemented method for mitigating one or more stretching factor errors according to one or more embodiments described herein.

[0030] Figure 14 A cloud computing environment according to one or more embodiments described herein is depicted.

[0031] Figure 15 An abstract model layer is described according to one or more embodiments described herein.

[0032] Figure 16 A block diagram of an example, non-limiting operating environment is shown, which may facilitate the description of one or more embodiments herein. Detailed Implementation

[0033] The following detailed description is illustrative only and is not intended to limit the embodiments and / or their application or use. Furthermore, it is not intended to be construed as being bound by any express or implied information presented in the foregoing Background or Summary of the Invention or Detailed Description sections.

[0034] One or more embodiments will now be described with reference to the accompanying drawings, wherein the same reference numerals are always used to denote the same elements. In the following description, numerous specific details are set forth for purposes of explanation in order to provide a more thorough understanding of one or more embodiments. However, it will be apparent in various cases that one or more of the described embodiments may be practiced without these specific details.

[0035] Considering the problems with other implementations of quantum computing error mitigation, this disclosure can be implemented to generate solutions to one or more of these problems by interpolating quantum gate parameters from one or more reference models calibrated with respect to a reference stretching factor. Advantageously, one or more embodiments described herein can achieve error mitigation for the stretching factor interval with minimal calibration overhead. The various embodiments described herein enable the use of one or more desired stretching factors within a given range characterized by multiple reference stretching factors.

[0036] Various embodiments of the present invention are directed to computer processing systems, computer-implemented methods, apparatuses, and / or computer program products that facilitate efficient, effective, and autonomous (e.g., without direct human guidance) stretch pulse calibration and gate parameter interpolation. For example, in one or more embodiments described herein, multiple quantum gates can be calibrated with respect to a reference stretch factor to generate a reference model. Furthermore, various embodiments can interpolate gate parameters from the reference model with respect to a desired stretch factor. Additionally, one or more embodiments described herein can recommend one or more stretch factors for a given quantum circuit. Furthermore, one or more embodiments can adjust one or more selected stretch factors to enhance compatibility with the hardware of a given quantum computer.

[0037] Computer processing systems, computer-implemented methods, apparatuses, and / or computer program products employ hardware and / or software to solve inherently highly technical problems (e.g., quantum computing error mitigation) that are not abstract and cannot be performed as a set of mental actions by humans. For example, one or more individuals cannot generate a reference model for stretching factor interpolation and error mitigation.

[0038] Furthermore, one or more embodiments described herein can constitute a technical improvement over conventional error mitigation by interpolating quantum gate parameters from one or more reference models calibrated at multiple reference stretching factors. Additionally, the various embodiments described herein can demonstrate a technical improvement over conventional error mitigation techniques by recommending the stretching factor to be used based on the hardware characteristics of a given quantum circuit and / or a given quantum computer. Moreover, the various embodiments described herein can demonstrate a technical improvement over conventional error mitigation techniques by enabling the selection of one or more stretching factors within a given range while minimizing calibration overhead.

[0039] Furthermore, one or more embodiments described herein can be practically applied by mitigating errors in one or more quantum operations. For example, the various embodiments described herein can interpolate quantum gate parameters from a reference model; thereby enabling the selection of one or more desired stretching factors from a given range without being inhibited by limitations associated with calibrating the quantum gate. Additionally, one or more embodiments described herein can control recommended components to analyze a given quantum circuit and / or generate one or more recommended stretching factors to be used for error mitigation. Thus, one or more embodiments can enable a user to employ stretching factors compatible with the desired quantum circuit.

[0040] Figure 1 A block diagram of an exemplary, non-limiting system 100 that can facilitate the mitigation of errors in quantum computing is shown. For brevity, repeated descriptions of similar elements employed in other embodiments described herein are omitted. Aspects of systems (e.g., system 100, etc.), apparatuses, or processes in various embodiments of the invention may constitute one or more machine-executable components contained within one or more machines, for example, contained in one or more computer-readable media (or media) associated with one or more machines. When executed by one or more machines (e.g., computers, computing devices, virtual machines, etc.), such components enable the machines to perform the described operations.

[0041] like Figure 1 As shown, system 100 may include one or more servers 102, one or more networks 104, input devices 106, and / or a quantum computer 108. Server 102 may include error mitigation components 110. Error mitigation components 110 may also include communication components 112 and / or modeling components 114. Furthermore, server 102 may include or otherwise be associated with at least one memory 116. Server 102 may also include a system bus 118, which may be coupled to various components, such as, but not limited to, error mitigation components 110 and associated components, memory 116, and / or processor 120. Although in Figure 1 Server 102 is shown, but in other embodiments, multiple devices of various types can be connected. Figure 1 The features shown are associated with or include these features.

[0042] One or more networks 104 may include wired and wireless networks, including but not limited to cellular networks, wide area networks (WANs) (e.g., the Internet), or local area networks (LANs). For example, server 102 may communicate with one or more input devices 106 and / or quantum computer 108 (and vice versa) using virtually any desired wired or wireless technology, including, but not limited to, cellular, WAN, Wi-Fi, Wi-Max, WLAN, Bluetooth, and combinations thereof. Furthermore, although error mitigation component 110 may be provided on one or more servers 102 in the illustrated embodiment, it should be understood that the architecture of system 100 is not limited thereto. For example, error mitigation component 110 or one or more components of error mitigation component 110 may be located at another computer device, such as another server device, client device, or a combination thereof.

[0043] One or more input devices 106 may include one or more computerized devices, which may include, but are not limited to: personal computers, desktop computers, laptop computers, cellular phones (e.g., smartphones), computerized tablets (e.g., including processors), smartwatches, keyboards, touchscreens, mice, combinations thereof, etc. One or more input devices 106 may be used to input one or more quantum circuits and / or target stretching factors into system 100 to share the data with server 102 (e.g., via a direct connection and / or via one or more networks 104). For example, one or more input devices 106 may transmit data to communication component 112 (e.g., via a direct connection and / or via one or more networks 104). Additionally, one or more input devices 106 may include one or more displays that can present one or more outputs generated by system 100 to a user. For example, one or more displays may include, but are not limited to: cathode ray tube displays (“CRT”), light-emitting diode displays (“LED”), electroluminescent displays (“ELD”), plasma display panels (“PDP”), liquid crystal displays (“LCD”), organic light-emitting diode displays (“OLED”), combinations thereof, and / or the like.

[0044] In various embodiments, one or more input devices 106 and / or one or more networks 104 may be used to input one or more settings and / or commands into system 100. For example, in the various embodiments described herein, one or more input devices 106 may be used to operate and / or manipulate server 102 and / or associated components. Additionally, one or more input devices 106 may be used to display one or more outputs (e.g., displays, data, visualizations, etc.) generated by server 102 and / or associated components. Furthermore, in one or more embodiments, one or more input devices 106 may be included within and / or operatively coupled to a cloud computing environment.

[0045] In various embodiments, one or more quantum computers 108 may include quantum hardware devices that can utilize the laws of quantum mechanics (e.g., superposition and / or quantum entanglement) to assist computational processing (e.g., simultaneously satisfying the DiVincenzo criterion). In one or more embodiments, one or more quantum computers 108 may include a quantum data plane, a control processor plane, a control and measurement plane, and / or qubit technology.

[0046] In one or more embodiments, a quantum data plane may include one or more quantum circuits, the quantum circuits including physical qubits, structures for ensuring the positioning of the qubits, and / or support circuitry. The support circuitry may, for example, facilitate the measurement of the state of the qubits and / or the performance of gate operations on the qubits (e.g., for gate-based systems). In some embodiments, the support circuitry may include a wiring network that enables multiple qubits to interact with each other. Furthermore, the wiring network may facilitate the transmission of control signals via direct electrical connections and / or electromagnetic radiation (e.g., light, microwaves, and / or low-frequency signals). For example, the support circuitry may include one or more superconducting resonators operatively coupled to the one or more qubits. As described herein, the term "superconducting" can characterize a material exhibiting superconducting properties at or below a superconducting critical temperature, such as aluminum (e.g., a superconducting critical temperature of 1.2 Kelvin) or niobium (e.g., a superconducting critical temperature of 9.3 Kelvin). Additionally, those skilled in the art will recognize that other superconducting materials (e.g., hydride superconductors, such as lithium / magnesium hydride alloys) may be used in the various embodiments described herein.

[0047] In one or more embodiments, the control processor plane can identify and / or trigger a sequence of Hamiltonian functions for quantum gate operations and / or measurements, wherein the sequence executes a program for implementing a quantum algorithm (e.g., provided by a host processor such as server 102 and / or one or more input devices 106). For example, the control processor plane can translate compiled code into commands for controlling and measuring the plane. In one or more embodiments, the control processor plane can also execute one or more quantum error correction algorithms.

[0048] In one or more embodiments, the control and measurement plane can convert digital signals generated by the control processor plane into analog control signals to perform operations on one or more qubits in the quantum data plane, the digital signals describing the quantum operation to be performed. Furthermore, the control and measurement plane can convert one or more analog measurement outputs of the qubits in the data plane into classical binary data that can be shared with other components of system 100, such as error mitigation component 110, via, for example, the control processor plane.

[0049] Those skilled in the art will recognize that various qubit technologies can provide the basis for one or more qubits in one or more quantum computers 108. Two exemplary qubit technologies may include ion trap qubits and / or superconducting qubits. For example, in the case of quantum computer 108 utilizing ion trap qubits, the quantum data plane may include a plurality of ions used as qubits and one or more traps for holding these ions in specific locations. Furthermore, the control and measurement plane may include: a laser or microwave source pointing at one or more ions to affect the quantum state of the ions, a laser cooling the ions and / or enabling the measurement of the ions, and / or one or more photon detectors measuring the state of the ions. In another instance, superconducting qubits (e.g., such as superconducting quantum interference devices "SQUIDs") may be photolithographically defined electronic circuits that can be cooled to milliKelvin temperatures to exhibit quantized energy levels (e.g., quantized states due to electron charge or magnetic flux). Superconducting qubits may be based on Josephson junctions, such as transmon qubits and / or similar qubits. Furthermore, superconducting qubits may be compatible with microwave control electronics and may be used with gate-based technologies or integrated cryogenic control. Other exemplary qubit technologies may include, but are not limited to: photonic qubits, quantum dot qubits, gate-based neutral atom qubits, semiconductor qubits (e.g., optically gated or electrically gated), topological qubits, combinations thereof, and / or the like.

[0050] In various embodiments, one or more quantum computers 108 may include one or more quantum gates 122. The one or more quantum gates 122 may operatively couple multiple qubits of the one or more quantum computers 108. The one or more quantum computers 108 may perform one or more quantum operations by controlling the one or more quantum gates 122 according to one or more given quantum circuits. In various embodiments, the one or more quantum gates 122 may be any type of quantum gate 122 in which the pulse implementing the gate can be broadened. Examples of gate types that may be included within the one or more quantum gates 122 may include, but are not limited to: cross-resonant gates, single-qubit gates, multi-qubit gates, combinations thereof, etc.

[0051] In one or more embodiments, the communication component 112 may receive one or more Hamiltonian operators, quantum circuits, and / or target stretching factors from one or more input devices 106 (e.g., via direct electrical connections and / or through one or more networks 104) and share data with the respective associated components of the error mitigation component 110. Additionally, the communication component 112 may facilitate data sharing between the error mitigation component 110 and one or more quantum computers 108 and / or vice versa (e.g., via direct electrical connections and / or through one or more networks 104).

[0052] The time-dependent driver Hamiltonian function can be characterized by the following equation 1:

[0053] K(t)=∑ α J α (t)P α (1)

[0054] Among them, “∑ α "J" can represent the sum at index α, and "J" α " can represent "P" α "The time-related strength of associated interactions. Furthermore, when 'P'..." α When the Pauli operator is an N-qubit operator, it is affected by time-invariant noise "λ", and at time "c j The ratio of "T" drives " "E" that can be observed after the next evolution K The expected value of (λ)” is equivalent to the amplified noise intensity “c”. j Measurements under “λ”. Therefore, it is possible to compute (e.g., via one or more quantum computers 108) several different observables “c”. j "The associated observables, and E" K(λ) can be extrapolated back to the zero-noise limit “E*”. In different implementations, one or more quantum computers 108 may make a set of calibrated quantum gates available for each stretching factor employed, which may depend on one or more characteristics of the given quantum circuit employed for a given quantum operation (e.g., performing a given quantum algorithm).

[0055] In various embodiments, model component 114 can reduce the calibration overhead associated with achieving various stretching factors by generating one or more reference models, based on which gate parameters of a target stretching factor can be interpolated. For example, one or more reference models generated by model component 114 can correlate quantum gate parameters of one or more quantum computers 108 with their effects on unit-time evolution. In various embodiments, model component 114 can generate one or more reference models based on analytical considerations and / or empirical measurements. Example gate parameters that can be interpolated from one or more reference models may include, but are not limited to: the amplitude of a cross-resonant pulse, the phase of a cross-resonant pulse, the derivative removal (“DRAG”) value through an adiabatic pulse (e.g., the DRAG coefficient of a single-qubit pulse), the amplitude of a single-qubit pulse, combinations thereof, etc.

[0056] For example, the amplitude "Ω" of a cross-resonance pulse of duration "T" can be obtained by rotating ZX according to a third-order model based on the following Equation 2 (e.g., by θ). ZX =ω ZX (T characterization) related.

[0057]

[0058] Where “δ1” can represent the non-reduction property of a control qubit of the one or more quantum computers 108, “Δ” can represent a frequency difference between the control qubit and the target qubit of the one or more quantum computers 108, and / or “J” can represent a coupling strength between these qubits.

[0059] One or more reference models may consider a stretch factor that includes multiple reference stretch factors (e.g., by "c"). j ∈[c min c max The continuous intervals (represented by the reference stretching factor) are used to characterize the quantum gates 122 of the one or more quantum computers 108. In different embodiments, each of these reference stretching factors can be calibrated relative to each of them. Furthermore, the calibrated gate parameters can be plotted against the reference stretching factors within the one or more reference models. Thus, the model component 114 can apply one or more empirical fits to the plotted data to characterize the relationship between the parameter values ​​of each of the quantum gates 122 of the one or more quantum computers 108 and the reference stretching factors.

[0060] Figure 2 An exemplary non-limiting graph 200 according to one or more embodiments described herein is shown, depicting various empirical fits that model component 114 can use to generate one or more reference models characterizing the relationship between gate parameters and stretch factors. For brevity, repeated descriptions of similar elements employed in other embodiments described herein are omitted. In various embodiments, model component 114 can fit the magnitude parameter of a given value gate 122 to calibrated reference stretch factor data. Furthermore, as shown in graph 200, model component 114 can use polynomial and / or piecewise linear fitting to fit the angle and / or increment parameters of a given value gate 122 to calibrated reference stretch factor data. The reference model illustrated by graph 200 can account for calibration of stretch factor intervals ranging between 1 and 2.

[0061] like Figure 2 As shown, line 202 can represent an initial stretch factor calibration performed on quantum gate 122 (e.g., a cross-resonance gate). Line 204 can represent a subsequent second stretch factor calibration performed on quantum gate 122. Line 206 can represent a piecewise linear fit using the parameters generated by the initial stretch factor calibration. Line 208 can represent a piecewise linear fit using the parameters generated by the second stretch factor calibration. Line 210 can represent a polynomial fit using the parameters generated by the initial stretch factor calibration. Line 212 can represent a polynomial fit using the parameters generated by the second stretch factor calibration. In various embodiments, θ is utilized... ZX =ω ZX Fitting the amplitude parameter of T (e.g., inversely proportional to time) can be less sensitive than fitting other gate parameters such as phase and / or DRAG parameters.

[0062] In various embodiments, model component 114 may determine the stretching factor interval associated with each quantum gate based on one or more operational characteristics of the quantum gates 122 of one or more quantum computers 108. For example, model component 114 may determine the stretching factor interval such that a minimal amount of calibration overhead is required while still producing quantum gates 122 for error mitigation (e.g., for Richardson error mitigation). For example, model component 114 may determine the number and / or which stretching factors are used as reference stretching factors for a given quantum gate 122 based on the error per Clifford value and / or the variation in parameter values ​​for that quantum gate 122.

[0063] For example, model component 114 may define the number and / or value of reference stretching factors included within the stretching factor interval based on per-gate error (e.g., per Clifford error). For example, the number of reference stretching factors included within the stretching factor interval may increase with the amount of change determined per-gate error (e.g., per Clifford error) within the stretching factor interval. In another example, model component 114 may define the number and / or value of reference stretching factors included within the stretching factor interval based on gate parameters. For example, the number of reference stretching factors included within the stretching factor interval may increase with the amount of change determined by the gate parameters within the stretching factor interval.

[0064] Figure 3A -B illustrates exemplary non-limiting graphs 300 and / or 302 according to one or more embodiments described herein, which may be generated by model component 114 to characterize one or more operational characteristics of one or more quantum gates 122 and identify reference stretching factors. For brevity, repeated descriptions of similar elements employed in other embodiments described herein are omitted. In one or more embodiments, graphs 300 and / or 302 may be generated by model component 114 based on one or more analytical considerations of the quantum gates 122 of one or more quantum computers 108 (e.g., according to Equation 2). Figure 3A As shown, exemplary graph 300 can represent the amplitude of the cross-resonant pulse (e.g., in...). Figure 3A The parameter referred to as "amp_CR" in the reference model is considered the gate parameter of interest. Figure 3B As shown, model component 114 can generate exemplary graph 302 by first estimating how the error per Clifford value varies as a function of the stretching factor value. For example, model component 114 can perform a first estimation in which the error per Clifford is determined for a set of typically linearly spaced stretching factors within the stretching factor intervals. Next, model component 114 can select a reference stretching factor based on the amount of change between the error per Clifford values.

[0065] In region A of exemplary graphs 300 and 302, a given quantum gate 122 may experience a greater amount of change in gate parameter and / or per Clifford error than in region B. For example, the difference between the gate parameter value and / or per Clifford error from one reference point in region A to another may be greater than the difference between the gate parameter value and / or per Clifford error from one reference point in region B to another.

[0066] In various embodiments, model component 114 may define the number of reference stretch factors included in region A as greater than the number of reference stretch factors included in region B. For example, model component 114 may identify 5 reference stretch factors corresponding to region A and 3 reference stretch factors corresponding to region B. Figure 3A As shown. In another example, model component 114 can identify four reference stretch factors corresponding to region A and two reference stretch factors corresponding to region B, as shown. Figure 3B As shown. Therefore, the density of the reference stretch factor associated with region A can be greater than the density of the reference stretch factor associated with region B.

[0067] In one or more embodiments, the error mitigation component 110 may share a reference stretching factor value determined by the model component 114 with one or more data scientists via one or more input devices 106. This allows the data scientists to calibrate the quantum gates 122 of one or more quantum computers 108 for the reference stretching factor. As a result of the calibration, reference gate parameters associated with the reference stretching factor can be determined. For example, the reference gate parameters for a given quantum gate may be the gate parameters that implement the reference stretching factor according to the calibration. Furthermore, one or more input devices 106 may be used to input the reference gate parameters into system 100 and share them with the error mitigation component 110. According to the various embodiments described herein, the model component 114 may plot the relationship between the reference gate parameters and the reference stretching factor and generate one or more reference models using empirical fitting (e.g., piecewise linear fitting, polynomial fitting).

[0068] In one or more embodiments, the error mitigation component 110 may share the reference stretching factor value determined by the model component 114 with one or more input devices 106 and / or the quantum computer 108 to facilitate automatic calibration of one or more quantum gates 122. For example, the calibration may execute multiple calibration routines that perform operations of one or more quantum computers 108 to determine the values ​​of the gate parameters of the associated pulse. Each calibration routine may also return the accuracy associated with the gate parameters of the associated pulse, which is the calibration target. Therefore, the automatic calibration can determine whether it can execute the next calibration routine or whether the last calibration routine needs to be repeated.

[0069] Figure 4A diagram illustrating an example non-limiting system 100, including a gate resource component 402, a tracking component 404, and / or an adjustment component 406, according to one or more embodiments described herein, is shown. For brevity, repeated descriptions of similar elements employed in other embodiments described herein are omitted. In various embodiments, the gate resource component 402 may define one or more operational capabilities of one or more quantum gates 122 of the quantum computer 108. Similarly, the tracking component 404 may track the operational capabilities defined by the gate resource component 402 to identify whether one or more changes have occurred. Furthermore, the adjustment component 406 may modify one or more target stretching factors to accommodate the operational capabilities defined by the gate resource component 402 and tracked by the tracking component 404.

[0070] One or more quantum gates 122 of the quantum computer 108 (e.g., cross-resonant gates) can be initially optimized to have different gate lengths and gate errors. Therefore, the maximum stretching factor that can be used with the corresponding quantum gate can vary. For example, a first quantum gate 122 of the quantum computer 108 can successfully employ a maximum stretching factor of 2; while a second quantum gate 122 of the quantum computer 108 may fail with a stretching factor of 2.

[0071] In various embodiments, gate resource component 402 may generate one or more gate resource tables 408. For example, each quantum gate 122 of one or more quantum computers 108 may be represented in one or more gate resource tables 408. Furthermore, gate resource component 402 may populate gate resource tables 408 with minimum and maximum stretching factors that can be used with each quantum gate 122. For example, one or more gate resource tables 408 may represent each quantum gate 122 by corresponding identifiers (e.g., headers and / or numbers) and may list minimum and maximum stretching factor values ​​associated with each quantum gate 122. In different embodiments, the number, location, and / or composition of quantum gates 122 may be input into system 100 by one or more data scientists and / or computer programs familiar with quantum computer 108 via one or more input devices 106. In some embodiments, gate resource component 402 may retrieve data defining the number, location, and / or composition of quantum gates 122 from one or more quantum computers 108. In one or more embodiments, quantum gates 122 may be identified, for example, by a name and a stretching factor (e.g., the stretching factor may be incorporated into the name of quantum gate 122). For example, the names of exemplary quantum gates 122 may include, but are not limited to: CNOT_1.00 (e.g., where the stretching factor is 1.00), CNOT_1.50 (e.g., where the stretching factor is 1.50), and / or CNOT_2.00 (e.g., where the stretching factor is 2.00). In various embodiments, one or more gate resource tables 408 may be stored in one or more memories 116. In one or more embodiments, one or more gate resource tables 408 may be stored in a computer architecture outside of server 102. In some embodiments, one or more quantum gates 122 may be further grouped into multiple groups, referred to as families, within one or more gate resource tables 408 based on functionality within one or more quantum computers 108 and / or their proximity to each other.

[0072] The minimum and / or maximum stretching factors associated with quantum gate 122 can be calculated by gate resource component 402 based on one or more analytical considerations and / or one or more measurements. For example, in different embodiments, one or more input devices 106 can be used to input hardware characteristics of quantum gate 122 into system 100. Example hardware characteristics may include, but are not limited to: the material composition of quantum gate 122, the connectivity of quantum gate 122, the length of quantum gate 122, the fidelity fluctuation of quantum gate 122, combinations thereof, etc. For example, given the maximum stretching factor of quantum gate 122, a stretching factor value can be defined beyond which quantum gate 122 will be too unstable to be used, or will experience too much error to be used. Based on these hardware characteristics, gate resource component 402 can calculate the minimum and / or maximum stretching factors that can be used with the quantum gate based on a numerical model of the quantum system, using the hardware characteristics of one or more quantum computers 108. In another example, the quantum gate 122 can be operated using multiple increasing stretching factors to identify the minimum and / or maximum stretching factor values ​​that enable successful operation, wherein one or more quantum computers 108 may share the identified minimum and / or maximum stretching factors with the gate resource component 402 (e.g., via one or more networks 104).

[0073] In various embodiments, one or more quantum gates 122 may be susceptible to operational fluctuations. As a result of these fluctuations, the maximum stretch factor that the quantum gate 122 can employ may change over time. The tracking component 404 can track the operating conditions of one or more quantum gates 122 to ensure that the maximum stretch factor reflected in one or more gate resource tables 408 is up-to-date. For example, the tracking component 404 can execute one or more randomized benchmarking protocols to evaluate the capabilities of the quantum computer 108 hardware by estimating the average error rate measured under implementations of a sequence of randomized quantum gate operations. For example, the randomized benchmarks can be based on uniformly randomized Clifford operations. Additionally, quantum process tomography (“QPT”) and / or quantum gate set tomography (“GST”) (e.g., via the tracking component 404) can be implemented to determine the maximum stretch factor value (e.g., based on the fidelity of the quantum gate 122). With the randomized benchmarking protocol employed, multiple Clifford gate sequences can be created using a number of “m” Clifford gates. In any given sequence of Clifford gates of length m, 1 to m-1 Clifford gates can be randomly selected from the Clifford group. The last Clifford gate can be chosen such that the sequence of m Clifford gates constitutes an identity operation. The measurements at each length m can be averaged to create a curve showing the qubit count as a function of m.

[0074] In one or more embodiments, the tracking component 404 may periodically implement a randomized benchmarking protocol to verify the maximum stretch factor included in one or more gate resource tables 408. For example, the tracking component 404 may implement the randomized benchmarking protocol according to one or more schedules. For example, the tracking component 404 may implement the randomized benchmarking protocol daily, at daily intervals (e.g., every two days), weekly, and / or at another desired time interval. Furthermore, the randomized benchmarking schedule implemented by the tracking component 404 may vary among the quantum gates 122. For example, the quantum gate associated with the highest maximum stretch factor may be the gate with the most suspected gate variability, and therefore may be subjected to randomized benchmarking by the tracking component 404 more frequently than quantum gates associated with lower maximum stretch factors. For example, the quantum gate associated with the highest maximum stretch factor may be subjected to randomized benchmarking by the tracking component 404 on a daily basis; while the quantum gate associated with the lower maximum stretch factor may be subjected to randomized benchmarking by the tracking component 404 on a weekly basis. In various embodiments, the randomized benchmark scheduling implemented by the tracking component 404 can vary based on the amount of maintenance overhead budgeted for system 100 and / or quantum computer 108.

[0075] In one or more embodiments, the adjustment component 406 may refer to one or more gate resource tables 408 (e.g., gate resource tables generated by the gate resource component 402 and / or updated by the tracking component 404) to determine whether one or more target stretching factors should be modified to accommodate the available capacity of the quantum gates 122. For example, one or more input devices 106 may be employed to define one or more quantum circuits that will be executed by one or more quantum computers 108 during one or more quantum operations. In cases where error mitigation is employed to enhance the results of quantum operations, one or more input devices 106 may also be employed to define one or more target stretching factors to be utilized during error mitigation protocols.

[0076] The adjustment component 406 can analyze the received quantum circuit (e.g., received via one or more networks 104 and / or communication components 112) to identify which quantum gates 122 from one or more quantum computers 108 will operate during quantum operation. For example, the adjustment component 406 can associate the quantum gates 122 of the quantum computer 108 with the given quantum circuit based on the qubit connectivity established by these quantum gates and depicted by the quantum circuit. In another instance, each quantum gate 122 of a given quantum circuit must be executed by one or more quantum computers 108. If a given quantum circuit contains quantum gates 122 that are not natively supported by the quantum computer 108, those quantum gates 122 can be decomposed into natively supported quantum gates 122. For example, if a given quantum circuit depicts quantum gates 122 that are not supported by one or more quantum computers 108 due to finite qubit connectivity, swap gates (e.g., decomposed into gates supported by the quantum computer 108) can be inserted into the quantum circuit via the adjustment component 406. Thus, the adjustment unit 406 can identify the relevant quantum gate 122 for quantum operations and can refer to one or more gate resource tables 408 to identify the permissible range of stretch factors (e.g., as limited by the maximum stretch factor) that can be used with the relevant quantum gate 122. If one or more target stretch factors provided via input device 106 are within the permissible stretch factor range, the error mitigation unit 110 can continue to utilize the given target stretch factor to implement one or more error mitigation protocols described herein. If one or more stretch factors provided via input device 106 are outside the permissible stretch factor range, the adjustment unit 406 can change the value of the target stretch factor to one or more values ​​within the permissible range. For example, the adjustment unit 406 can change the value of one or more target stretch factors to a value within the permissible range that is closest to the initially provided value. In another instance, the adjustment unit 406 can change the value of one or more target stretch factors to a value within the center of the permissible range.

[0077] In various embodiments, one or more stretch factors within the permissible range may still be inoperable. Inoperable stretch factors within the permissible range can be reflected by performance benchmarks, such as high error per Clifford value. For example, an exemplary permissible stretch factor range could be 1.0 to 3.0. However, stretch factors of 2.1 to 2.3 may be inoperable due to poor fidelity (e.g., one or more calibration protocols may be ineffective for these stretch factors). Adjustment component 406 ensures that the target stretch factor is not within the range of 2.1 to 2.3.

[0078] Additionally, the adjustment component 406 can change the target stretching factor to meet one or more hardware constraints. For example, some quantum computer 108 hardware can only load pulses with a limited number of samples (e.g., only pulses that are multiples of 16 samples). The adjustment component 406 can choose to change the target stretching factor such that the pulses are multiples of the number defined for the quantum computer 108 hardware. For example, where the defined number is 16; if a pulse with a stretching factor of 2.1 has 168 samples, the adjustment component 406 can choose to use a target stretching factor of 2, such that the pulse has 160 samples (which is a multiple of 16).

[0079] To illustrate a non-limiting embodiment of how gate resource component 402, tracking component 404, and / or adjustment component 406 can be combined in operation, consider the following exemplary use case. A quantum gate 122 of one or more quantum computers 108 can be initially optimized such that a stretching factor ranging from greater than or equal to 1.0 to less than or equal to 2.0 can be successfully used in one or more error mitigation protocols. Gate resource component 402 can store the permissible stretching factor range (e.g., 1.0 to 2.0) associated with a unique identifier for quantum gate 122 within one or more gate resource tables 408. After initial optimization, quantum gate 122 may undergo one or more operational fluctuations, resulting in the permissible stretching factor range narrowing to a new range greater than or equal to 1.0 and less than or equal to 1.8. For example, qubit coherence times T1 and T2 may fluctuate in one or more quantum computers 108, which could adversely affect quantum gate 122 employing a large stretching factor. During a randomized benchmarking protocol executed by tracking component 404 according to one or more defined schedules, tracking component 404 can identify narrowed ranges and update one or more gate resource tables 408 accordingly. Before a quantum operation utilizing quantum gate 122 is performed by one or more quantum computers 108, adjustment component 406 can compare one or more target stretching factors associated with the quantum operation with a range of allowed stretching factors (e.g., 1.0 to 1.8) stored in one or more gate reference tables 408. If the target stretching factor is greater than 1.8, adjustment component 406 can change the value of the target stretching factor to 1.8 to satisfy the capacity of quantum gate 122.

[0080] Figure 5A diagram of an example non-limiting system 100, including an interpolation component 502, is shown according to one or more embodiments described herein. For brevity, repeated descriptions of similar elements employed in other embodiments described herein are omitted. In various embodiments, the interpolation component 502 may determine one or more quantum gate parameters (e.g., provided by one or more input devices 106 and / or modified by the adjustment component 406) based on one or more reference models generated by the modeling component 114, which can achieve a target stretching factor for a given quantum gate 122.

[0081] In one or more embodiments, interpolation component 502 may interpolate the gate parameters of a target stretch factor based on nearby reference gate parameters calibrated with respect to a reference stretch factor. As described herein, one or more reference models generated by model component 114 may plot the relationship between the reference stretch factor and the reference gate parameters (e.g., determined by one or more calibration protocols) and include an empirical fit to the plotted data. Interpolation component 502 may further interpolate the gate parameters based on the empirical fit of one or more target stretch factors. Thus, interpolation component 502 may interpolate gate parameters from the reference model for stretch factors that have not been otherwise calibrated (e.g., non-reference stretch factors).

[0082] Figure 6 A diagram is shown of an example non-limiting reference model 600 according to one or more embodiments described herein, which can depict gate parameter interpolation that can be performed by interpolation component 502. For brevity, repeated descriptions of similar elements used in other embodiments described herein are omitted. The exemplary reference model 600 may be generated by model component 114 according to various embodiments described herein.

[0083] like Figure 6 As shown, the exemplary reference model 600 can plot four reference stretch factors (e.g., by " "", "", "and" " indicates the AND gate parameter "p i The relationship curve is shown as follows: (e.g., the amplitude of the cross-resonance pulse). As described herein, the four reference stretching factors can be identified by model component 114 based on the severity of the error variation calculated per Clifford and / or the severity of the gate parameter variation (e.g., the density of reference stretching factors can increase with the slope of the empirical fit). Furthermore, the quantum gate can be calibrated at the reference stretching factors to determine the gate parameter values ​​associated with each reference stretching factor (e.g., reference gate parameters).

[0084] Therefore, the interpolation component 502 can interpolate the gate parameters associated with the target stretch factor by locating the position of the target stretch factor on the fitted model and referring to the gate parameter value corresponding to that position. For example, the target stretch factor " "The position on the empirical fit 602 of the calibrated reference stretch factor data can be determined by..." Figure 6 The asterisk (*) indicates the target stretch factor, as shown by the dashed line 604. "The relevant gate parameter values ​​can be interpolated from the empirical fit 602."

[0085] Figure 7 A diagram is shown of an example non-limiting system 100 including an execution component 702 according to one or more embodiments described herein. For brevity, repeated descriptions of similar elements employed in other embodiments described herein are omitted. In various embodiments, the execution component 702 can perform a quantum operation on one or more quantum computers 108 using one or more gate parameters interpolated from one or more reference models.

[0086] In one or more embodiments, one or more input devices 106 may be used to define one or more quantum circuits, which will be executed on one or more quantum computers 108 to perform a quantum operation. Additionally, the one or more input devices 106 may be used to define one or more target stretching factors to be used in one or more error mitigation protocols relating to the quantum operation. An interpolation unit 502 may interpolate one or more gate parameters to obtain the target stretching factor from one or more reference models. An execution unit 702 may execute the quantum circuit on one or more quantum computers 108 using the one or more interpolated gate parameters.

[0087] For example, execution unit 702 can execute the quantum circuit multiple times on one or more quantum computers 108 to generate result data. For each execution, execution unit 702 can utilize the corresponding interpolation gate parameters. Thus, each execution of the quantum circuit on one or more quantum computers 108 can generate result data associated with a corresponding stretching factor, and thereby incorporate the corresponding noise level. In various embodiments, execution unit 702 can send one or more execution commands to one or more quantum computers 108 via one or more networks 104. For example, execution unit 702 can generate one or more digital signals that depict the quantum circuit to be executed by the quantum computer 108 and / or the gate parameter values ​​to be adopted by the quantum computer 108 during execution.

[0088] Figure 8A diagram of a non-limiting system 100 further including mitigation component 802 is shown. For brevity, repeated descriptions of similar elements used in other embodiments described herein are omitted. In various embodiments, mitigation component 802 may implement one or more error mitigation protocols to remove noise from the resulting data. The error mitigation protocols implemented by mitigation component 802 may identify noise, such as that affected by varying stretching factors, based on differences between the resulting data generated by different executions of the quantum circuit. In one or more embodiments, mitigation component 802 may generate an error-mitigated result by extrapolating the resulting data obtained by execution component 702 to the zero-order noise limit using Richardson error mitigation or another extrapolation method.

[0089] Figure 9 Examples of non-limiting graphs illustrating the effectiveness of one or more error mitigation protocols implemented by mitigation component 802 according to one or more embodiments described herein are shown. For brevity, repeated descriptions of similar elements used in other embodiments described herein are omitted. Figure 9 The graph depicts the molecular hydrogen dissociation energy curve with Richardson error mitigation that can be generated by the error mitigation component 110. For example, Figure 9 The mitigation results depicted can be considered using a target stretching factor to account for a set of results performed on a cloud-based quantum computer 108: 1.00, 1.50, and 2.00. For example, the gate parameters of one or more quantum computers 108 for the target stretching factor are obtained by interpolation unit 502 by interpolating parameters from a reference stretching factor: 1.0, 1.26, 1.58, and 2.00. Figure 9 The results depicted show that the error-mitigated result data (e.g., indicated by triangles) is closer to the ideal result data (e.g., indicated by stars) than the execution performed with a stretch factor of 1.0.

[0090] Figure 10 A diagram illustrates an example non-limiting operational scheme 1000 that can facilitate one or more error mitigation protocols performed by error mitigation component 110 according to one or more embodiments described herein. For brevity, repeated descriptions of similar elements employed in other embodiments described herein are omitted. Operational scheme 1000 can depict exemplary, non-limiting paths of communication between error mitigation component 110 (e.g., and associated components of error mitigation component 110), one or more input devices 106, and / or one or more quantum computers 108. In various embodiments, Figure 10The communication and / or transmission of the data described herein can be performed via one or more networks 104, such as a cloud computing environment. For example, system 100 may employ a cloud computing environment to control one or more quantum computers 108.

[0091] At 1002, gate resource component 402 may share a stretch factor interval with one or more input devices 106. The stretch factor interval may be a range of stretch factors from which one or more target stretch factors can be selected to implement one or more error mitigation protocols described herein. In one or more embodiments, the stretch factor interval (e.g., characterized as "[c...)" is...) min ,c max The minimum stretching factor value (“c”) associated with quantum gate 122 and / or the family of quantum gate 122 can be used to determine the minimum stretching factor value (“c”). min ") and maximum stretch factor value ("c max The gate resource component 402 can define one or more gate resource tables 408 with respect to one or more quantum gates 122 and / or families of quantum gates 122 that can be used to perform quantum operations. The gate resource component 402 can define the minimum stretching factor value of the interval ("c"). min The term "" is defined as the minimum stretch factor value associated with quantum gate 122 and / or the family of quantum gates 122 (e.g., as defined in one or more gate resource tables 408). Furthermore, gate resource component 302 can specify the maximum stretch factor value of the interval ("c"). max The stretch factor interval is defined as the maximum stretch factor value associated with quantum gate 122 and / or the family of quantum gates 122 (e.g., as defined in one or more gate resource tables 408). Thus, this stretch factor interval can characterize the widest range of permissible stretch factors associated with one or more quantum gates 122 and / or the family of quantum gates 122 that can be used for operation.

[0092] According to one or more embodiments described herein, one or more input devices 106 may be used to select one or more stretching factor values ​​from a stretching factor interval as one or more target stretching factors for error mitigation. For example, one or more input devices 106 may be used to select multiple stretching factor values ​​within a stretching factor interval as target stretching factors. At 1004, one or more input devices 106 may share the selected target stretching factor with the error mitigation component 110 to facilitate the execution of one or more quantum operations. Additionally, at 1004, one or more input devices 106 may be used to define one or more quantum circuits, which may be executed using the selected target stretching factor to implement quantum operations.

[0093] In various embodiments, the adjustment component 406 may analyze the selected target stretching factor and / or one or more given quantum circuits. As described herein, the adjustment component 406 may identify relevant quantum gates 122 of one or more quantum computers 108 for performing the one or more given quantum circuits. For example, in cases where one or more quantum computers 108 include multiple quantum gates 122, the adjustment component 406 may identify quantum gates 122 that can be used for operation (e.g., quantum gates 122 that are not currently performing another quantum operation and / or are under operating conditions). Furthermore, the adjustment component 406 may identify one or more quantum gates 122 that satisfy the qubit connectivity described by one or more quantum circuits as relevant quantum gates 122 for a given quantum operation. For example, one or more given quantum circuits may describe the number of qubits coupled by quantum gates 122 and / or the type of coupling exhibited by quantum gates 122 (e.g., including logical conditions), wherein one or more of the relevant quantum gates 122 identified by the adjustment component 406 may satisfy the description of the quantum circuit. Furthermore, in one or more embodiments, the adjustment component 406 may also compare one or more target stretching factors with one or more updates of one or more associated quantum gates 122 (e.g., via updates via the tracking component 404).

[0094] If one or more target stretching factors are outside the allowed stretching factor range after the update of one or more associated quantum gates 122, adjustment component 406 can change the value of one or more target stretching factors to be within the allowed stretching factor range. For example, adjustment component 406 can add to or subtract from one or more target stretching factor values ​​the minimum amount required to move the target stretching factor value to the allowed range. At 1006, adjustment component 406 can share one or more target stretching factors (e.g., changed or unchanged) with interpolation component 502.

[0095] In various embodiments, interpolation component 502 can determine one or more quantum gate 122 parameters that can achieve one or more target stretching factors. For example, interpolation component 502 can use one or more reference models (e.g., generated by model component 114) to interpolate one or more quantum gate 122 parameters from one or more empirical fits. Thus, interpolation component 502 can interpolate one or more quantum gate 122 parameters from a model calibrated at multiple reference stretching factors. Advantageously, interpolating one or more quantum gate parameters 122 from a calibrated reference model enables interpolation component 502 to determine one or more quantum gate 122 parameters without calibrating one or more quantum computers 108 to a specific target stretching factor. At 1008, interpolation component 502 can share one or more interpolated quantum gate 122 parameters with execution component 702.

[0096] In some embodiments, interpolation component 502 may be included within one or more input devices 106. For example, at 1002, model component 114 may further share one or more interpolation functions with one or more input devices 106. For example, model component 114 may generate one or more interpolation functions based on one or more reference models. The one or more interpolation functions may characterize the empirical fit performed by model component 114. Thus, the one or more interpolation functions may input and output one or more quantum gate 122 parameters based on one or more target stretching factors. For example, the empirical fit of one or more reference models may characterize the relationship between gate parameters and stretching factors (e.g., as observed via calibration of one or more reference stretching factors), which may be expressed as one or more interpolation functions.

[0097] In one or more embodiments, execution unit 702 may generate one or more execution schedules based on one or more given quantum circuits, one or more target stretching factors, and / or one or more interpolated quantum gate 122 parameters. The one or more execution schedules may characterize the quantum circuits as a plurality of circuits, each associated with a corresponding target stretching factor. For example, in the case of defining two quantum circuits and three target stretching factors via one or more input devices 106, execution unit 702 may generate an execution schedule comprising six corresponding quantum circuits (e.g., three stretching factor-based variations for each quantum circuit). At 1010, execution unit 702 may send one or more command signals to one or more quantum computers 108 to execute a given quantum operation. For example, the one or more command signals may characterize the one or more execution schedules and associate the interpolated quantum gate 122 parameters for execution by the one or more quantum computers 108.

[0098] One or more quantum computers 108 can execute one or more quantum operations based on these command signals to generate a set of result data. For example, one or more quantum computers 108 can execute one or more given quantum circuits according to one or more execution schedules and thus according to one or more target stretching factors, using associated interpolation quantum gate 122 parameters. In various embodiments, one or more quantum computers 108 can generate a corresponding result dataset for each quantum circuit execution. For example, in the case where the execution schedule includes six quantum circuit executions (e.g., two quantum circuits, each with three variations corresponding to three target stretching factors, as described above), one or more quantum computers 108 can generate result data associated with each of the six executions. Furthermore, the result data of all six quantum circuit executions can constitute a result dataset associated with a given quantum operation.

[0099] In one or more embodiments, the resulting dataset may include labels specifying the context in which the data was generated. For example, these labels may describe the quantum circuits, target stretching factors, and / or quantum gate 122 parameters executed by one or more quantum computers 108 to implement the associated resulting data. For instance, in a case where a set of resulting data comprises six datasets, each dataset may include labels (e.g., header entries) describing the quantum circuits, target stretching factors, and / or quantum gate 122 parameters implemented in that dataset. At 1012, one or more quantum computers 108 may share the resulting dataset for a given quantum operation with one or more mitigation components 802.

[0100] In various embodiments, mitigation component 802 may implement one or more error mitigation protocols, such as the Richardson error mitigation protocol, to extrapolate the resulting dataset to the zero-noise limit. For example, mitigation component 802 may analyze the labels of the datasets to determine which datasets are associated with variations in the same quantum circuit and which target stretching factors are associated with each variation. For example, the individual datasets in the resulting dataset may characterize a given quantum circuit with varying noise levels based on the respective target stretching factors employed. Thus, mitigation component 802 may use the Richardson error mitigation technique to extrapolate the error-migrated results from the resulting dataset. At 1014, mitigation component 802 may share the error-migrated resulting data with one or more input devices 106.

[0101] Figure 11 A diagram of an example non-limiting system 100, including a recommendation component 1102, according to one or more embodiments described herein, is shown. For brevity, repeated descriptions of similar elements employed in other embodiments described herein are omitted. In various embodiments, the recommendation component 1102 may generate one or more recommended stretch factors for selection as a target stretch factor via one or more input devices 106.

[0102] In one or more embodiments, the recommendation component 1102 may generate one or more recommended stretching factors based on the count of quantum gates 122 (e.g., the total count of quantum gates 122 and / or the count of quantum gates 122 according to gate type, such as a one-qubit gate, a two-qubit gate, etc.) and / or the number of qubits in a given quantum circuit. For example, as the count of quantum gates 122 and / or qubits in a quantum circuit increases, the maximum recommended stretching factor for execution of the quantum circuit may decrease. For example, employing a large stretching factor value for a quantum circuit with multiple quantum gates 122 and / or qubits (e.g., a quantum circuit with high circuit depth) may result in an overwhelming amount of noise in the resulting data; thus prohibiting error mitigation protocols. For example, if the fidelity of the gates in the quantum circuit is below a given threshold (e.g., 50%), the quantum circuit may be considered too deep to be executed by one or more quantum computers 108. The recommendation component 1102 may analyze one or more given quantum circuits (e.g., defined via one or more input devices 106) to determine an optimal set of stretching factors that can maximize and / or otherwise enhance the effectiveness of one or more error mitigation protocols. For example, recommendation component 1102 can analyze (e.g., defined via one or more input devices 106) one or more given quantum circuits to determine the optimal set of stretching factors that can achieve the desired noise distribution within the resulting dataset used for quantum operations.

[0103] In various implementations, the recommended component 1102 can be calibrated and / or trained via multiple reference quantum operations executed on one or more quantum computers 108. For example, the quantum operations can be performed multiple times on one or more quantum computers 108 with a given stretching factor, wherein the quantum gate 122 count and / or qubit count can vary with each execution (e.g., thereby changing the depth of the quantum circuit). For example, a reference full-to-full connectivity quantum alternation operator transformation (“QAOA”) can be performed for multiple reference stretching factors using several different circuit depths “p” and several different qubit counts “N” (e.g., on one or more quantum computers 108 and / or simulators). The resulting dataset obtained by the execution can be defined as a recommended range of allowable stretching factors for a given quantum circuit graph (p, N). For example, an allowable stretching factor could be a stretching factor that ensures the Hellinger distance falls below a defined threshold.

[0104] Furthermore, the recommendation component 1102 can generate and / or populate one or more recommendation tables 1104 based on the execution of one or more benchmark calculations. For example... Figure 11As shown, one or more recommendation tables 1104 may be stored, for example, in one or more memories 116. For example, one or more recommendation tables 1104 may specify multiple quantum circuit profiles (p, N) (e.g., multiple quantum circuits having various combinations of gate counts and / or qubit counts, and thereby specifying various circuit depths). Recommendation component 1102 may populate one or more recommendation tables 1104 with a range of allowable stretching factors associated with each quantum circuit profile (p, N).

[0105] Recommendation component 1102 can compare one or more given quantum circuits (e.g., provided via one or more input devices 106) with one or more quantum circuit profiles of recommendation table 1104. When one or more quantum circuits have the same circuit depth as the quantum circuit profiles of recommendation table 1104 (e.g., the same combination of gate counts and qubit counts), recommendation component 1102 can identify the associated allowable stretching factor range as the recommended stretching factor range. When one or more given quantum circuits have a different circuit depth than the quantum circuit profiles (e.g., the same combination of gate counts and qubit counts), recommendation component 1102 can identify the allowable stretching factor range associated with the closest matching quantum circuit profile (e.g., the quantum circuit profile with the smallest deviation from the one or more given quantum circuits in the combination of quantum gates 122 and / or qubit counts).

[0106] In various embodiments, the recommendation component 1102 may share a recommended stretch factor range with one or more input devices 106 to select one or more target stretch factors (e.g., where one or more input devices 106 may be used to select a target stretch factor from the recommended stretch factor range). In one or more embodiments, the recommendation component 1102 may select one or more stretch factors as recommended target stretch factors from an associated allowable stretch factor range (e.g., the recommended target stretch factors may be linearly spaced between a value of 1.0 and the maximum stretch factor associated with a given quantum gate 122). Furthermore, the recommendation component 1102 may share one or more recommended stretch factors with one or more input devices 106 for approval via one or more input devices 106.

[0107] In one or more embodiments, the recommendation component 1102 may implement one or more heuristic methods to determine one or more recommended stretching factors. For example, the recommendation component 1102 may generate one or more recommended target stretching factors based on a count of the number of single-qubit quantum gates 122 and / or two-qubit quantum gates 122 depicted by a given quantum circuit and the error rate observed for the quantum gates 122 during calibration at one or more reference stretching factors.

[0108] Figure 12 An example non-limiting operational scheme 1200 is illustrated, which may facilitate the execution of one or more error mitigation protocols by error mitigation component 110 according to one or more embodiments described herein. For brevity, repeated descriptions of similar elements employed in other embodiments described herein are omitted. Operational scheme 1200 may depict exemplary, non-limiting paths of communication between error mitigation component 110 (e.g., and associated components of error mitigation component 110), one or more input devices 106, and / or one or more quantum computers 108. In various embodiments, Figure 12 The communication and / or transmission of the data described herein can be performed via one or more networks 104, such as a cloud computing environment. For example, system 100 may employ a cloud computing environment to control one or more quantum computers 108.

[0109] Compared to operation scheme 1000, operation scheme 1200 incorporates recommendation component 1102. For example, one or more input devices 106 may be used to define one or more quantum circuits for performing one or more quantum operations on one or more quantum computers 108. At 1202, the one or more input devices 106 may share one or more given quantum circuits with recommendation component 1202. Recommendation component 1102 may generate one or more recommendations, including but not limited to: multiple recommendation stretching factors, recommended stretching factor ranges, combinations thereof, and / or similar. For example, recommendation component 1102 may compare one or more given quantum circuits with one or more quantum circuit profiles stored in one or more recommendation tables 1004 according to various embodiments described herein.

[0110] At 1204, the recommendation component 1102 may share one or more recommendations with one or more input devices 106 for approval and / or selection. For example, according to the various embodiments described herein, one or more input devices 106 may be used to approve one or more recommended stretching factors as target stretching factors to be used in one or more error mitigation protocols. In another example, one or more input devices 106 may be used to select one or more target stretching factors from a range of recommended stretching factors.

[0111] Subsequently, operation scheme 1200 can implement steps 1006 and 1014 described herein with reference to operation scheme 1000. For example, one or more input devices 106 may share one or more target stretching factors with adjustment component 406 (e.g., which may include approved recommended stretching factors, stretching factors selected from a recommended range, and / or stretching factors defined independently of one or more recommendations generated by recommendation component 1102) to facilitate compatibility with the capabilities of one or more quantum gates 122 of quantum computer 108 performing one or more quantum operations. Subsequently, according to the different embodiments described herein, the one or more given quantum circuits can be executed on one or more quantum computers 108 with these target stretching factors. Furthermore, the resulting data generated by the execution on quantum computer 108 may be subject to one or more error mitigation protocols, such as Richardson error mitigation.

[0112] Figure 13 A flowchart illustrating an exemplary, non-limiting computer-implemented method 1300 according to one or more embodiments described herein, which can assist in performing one or more quantum operations on one or more quantum computers 108 and has error mitigation. For brevity, repeated descriptions of similar elements employed in other embodiments described herein are omitted.

[0113] At 1302, the computer-implemented method 1300 may include one or more reference models generated by a system 100 operatively coupled to a processor 120 (e.g., via model component 114), the one or more reference models including reference gate parameters for calibrating one or more quantum gates 122 at a plurality of reference stretching factors. At 1304, the computer-implemented method 1300 may include one or more quantum circuits received by the system 100 (e.g., via error mitigation component 110). For example, one or more input devices 106 may be used to define the one or more quantum circuits, which may depict how one or more quantum operations are performed on a quantum computer 108 (e.g., the number of qubits used, the number of quantum gates 122 used, the connectivity of qubits and / or quantum gates 122, the type of quantum gates 122 used, measurement operations, qubit reset operations, the number of times each quantum circuit is repeated to collect statistics, combinations thereof, and / or the like).

[0114] At 1306, the computer-implemented method 1300 may include one or more stretching factors recommended by system 100 based on qubit and / or gate counts of the quantum circuit (e.g., via recommendation component 1102) for error mitigation of the quantum circuit. For example, recommendation component 1102 may identify one or more recommended stretching factors and / or intervals of recommended stretching factors to be used with the quantum circuit, at least based on the circuit depth of the quantum circuit according to various embodiments described herein. Furthermore, the recommended stretching factors may be shared with one or more input devices 106 for selection and / or approval. At 1308, the computer-implemented method 1300 may include one or more target stretching factors received by system 100 (e.g., via error mitigation component 110) to be used with the quantum circuit to facilitate one or more error mitigation protocols. For example, one or more input devices 106 may be used to: select one or more recommended stretching factors as target stretching factors, select one or more target stretching factors from a range of recommended stretching factors, and / or define one or more non-recommended target stretching factors.

[0115] At 1310, the computer-implemented method 1300 may include adjusting (e.g., via adjustment unit 406) one or more target stretching factors by system 100 to satisfy one or more capabilities of one or more quantum gates 122 of a quantum circuit. For example, according to various embodiments described herein, the values ​​of one or more target stretching factors may be changed based on one or more fluctuations in the operational capabilities of one or more quantum gates 122. At 1312, the computer-implemented method 1300 may include interpolating (e.g., via interpolation unit 502) one or more quantum gate 122 parameters from one or more reference models for one or more target stretching factors by system 100. At 1314, the computer-implemented method 1300 may include generating (e.g., via execution unit 702) result data by system 100 by performing quantum operations on one or more quantum computers 108 according to one or more given quantum circuits, target stretching factors, and / or interpolated gate parameters. For example, execution unit 702 may generate one or more execution schedules according to various embodiments described herein to generate a set of result data associated with the execution of a quantum circuit having varying noise levels due to the changing target stretching factors. At 1316, the computer-implemented method 1300 may include generating (e.g., via mitigation component 802) an error mitigation result by system 100 by extrapolating the resulting data to the zero-order noise limit. For example, mitigation component 802 may implement the Richardson error mitigation protocol according to various embodiments described herein.

[0116] It should be understood that although this disclosure includes a detailed description of cloud computing, the implementation of the teachings set forth herein is not limited to a cloud computing environment. Rather, embodiments of the invention can be implemented in conjunction with any other type of computing environment now known or developed hereafter.

[0117] Cloud computing is a service delivery model for enabling convenient, on-demand network access to a shared pool of configurable computing resources (e.g., networks, network bandwidth, servers, processing, memory, storage, applications, virtual machines, and services) that can be rapidly provisioned and released with minimal management effort or interaction with service providers. This cloud model may include at least five features, at least three service models, and at least four deployment models.

[0118] The characteristics are as follows:

[0119] On-demand self-service: Cloud consumers can unilaterally and automatically provide computing power, such as server time and network storage, as needed, without requiring manual interaction with the service provider.

[0120] Wide Area Network (WAN) Access: Capabilities are available on the network and accessed through standard mechanisms that facilitate the use of heterogeneous thin or thick client platforms (e.g., mobile phones, laptops, and PDAs).

[0121] Resource pooling: A provider's computing resources are pooled to serve multiple consumers using a multi-tenant model, where different physical and virtual resources are dynamically allocated and reallocated based on demand. Location independence has significance because consumers typically do not control or know the exact location of the resources provided, but can specify the location at a higher level of abstraction (e.g., country, state, or data center).

[0122] Rapid Flexibility: In some cases, the ability to scale outwards and inwards quickly and flexibly can be provided. For consumers, the available capacity often appears unlimited and can be purchased in any quantity at any time.

[0123] Measurement services: Cloud systems automatically control and optimize resource usage by leveraging metering capabilities at a level of abstraction appropriate to the service type (e.g., storage, processing, bandwidth, and active user accounts). Resource usage can be monitored, controlled, and reported, providing transparency to both the providers and consumers of the services being utilized.

[0124] The service model is as follows:

[0125] Software as a Service (SaaS): The capability offered to consumers is the ability to use the provider's applications running on cloud infrastructure. Applications can be accessed from various client devices through thin client interfaces such as web browsers (e.g., web-based email). Consumers do not manage or control the underlying cloud infrastructure, including the network, servers, operating system, storage, or even individual application capabilities, with possible exceptions such as limited user-specific application configuration settings.

[0126] Platform as a Service (PaaS): This provides consumers with the ability to deploy consumer-created or acquired applications onto cloud infrastructure using programming languages ​​and tools supported by the provider. Consumers do not manage or control the underlying cloud infrastructure, including networks, servers, operating systems, or storage, but they have control over the deployed applications and the configuration of any application hosting environments.

[0127] Infrastructure as a Service (IaaS): This provides consumers with the capability to offer processing, storage, networking, and other basic computing resources that enable consumers to deploy and run arbitrary software, which may include operating systems and applications. Consumers do not manage or control the underlying cloud infrastructure, but they have control over the operating system, storage, deployed applications, and possibly limited control over selected networking components (e.g., host firewalls).

[0128] The deployment model is as follows:

[0129] Private cloud: Cloud infrastructure operated solely by an organization. It can be managed by the organization or a third party and can exist inside or outside a building.

[0130] Community cloud: Cloud infrastructure shared by several organizations and supporting a specific community with shared concerns (e.g., tasks, security requirements, policies, and compliance considerations). It can be managed by an organization or a third party and can exist on-site or off-site.

[0131] Public cloud: Cloud infrastructure available to the general public or large industrial groups and owned by organizations that sell cloud services.

[0132] Hybrid cloud: A cloud infrastructure is a combination of two or more clouds (private, community, or public) that remain a single entity but are bound together by standardized or proprietary technologies that enable data and applications to be ported together (e.g., cloud bursting for load balancing between clouds).

[0133] Cloud computing environments are service-oriented, focusing on statelessness, loose coupling, modularity, and semantic interoperability. At the heart of cloud computing is the infrastructure of a network of interconnected nodes.

[0134] Now for reference Figure 14The illustration depicts a cloud computing environment 1400. As shown, the cloud computing environment 1400 includes one or more cloud computing nodes 1402 to which local computing devices used by cloud consumers can communicate, such as personal digital assistants (PDAs) or cellular phones 1404, desktop computers 1406, laptop computers 1408, and / or automotive computer systems 1410. The nodes 1402 can communicate with each other. They can be physically or virtually grouped (not shown) in one or more networks, such as private clouds, community clouds, public clouds, or hybrid clouds, or combinations thereof, as described above. This allows the cloud computing environment 1400 to provide infrastructure, platform, and / or software as a service, without requiring cloud consumers to maintain resources on their local computing devices. It should be understood that... Figure 14 The types of computing devices 1404 and 1410 shown are intended to be illustrative only, and computing node 1402 and cloud computing environment 1400 can communicate with any type of computerized device on any type of network and / or network-addressable connection (e.g., using a web browser).

[0135] Now for reference Figure 15 This demonstrates the 1400 (cloud computing environment) Figure 14 This provides a set of functional abstraction layers. For brevity, repeated descriptions of similar elements used in other embodiments described herein are omitted. It should be understood beforehand that... Figure 15 The components, layers, and functions shown are for illustrative purposes only, and embodiments of the invention are not limited thereto. As described, the following layers and corresponding functions are provided.

[0136] The hardware and software layer 1502 includes hardware and software components. Examples of hardware components include: a host 1504; a server 1506 based on a RISC (Reduced Instruction Set Computer) architecture; a server 1508; a blade server 1510; a storage device 1512; and a networking component 1514. In some embodiments, the software components include network application server software 1516 and database software 1518.

[0137] The virtualization layer 1520 provides an abstraction layer from which the following examples of virtual entities can be provided: virtual server 1522; virtual storage 1524; virtual network 1526, including virtual private network; virtual application and operating system 1528; and virtual client 1530.

[0138] In one example, the management layer 1532 can provide the functionality described below. Resource provisioning 1534 provides dynamic procurement of computing resources and other resources used to perform tasks within the cloud computing environment. Metering and pricing 1536 provides cost tracking when utilizing resources in the cloud computing environment, as well as bills or invoices for consuming these resources. In one example, these resources may include application software licenses. Security provides authentication for cloud consumers and tasks, and protection for data and other resources. User portal 1538 provides access to the cloud computing environment for consumers and system administrators. Service level management 1540 provides cloud resource allocation and management to ensure the required service level is met. Service level agreement (SLA) planning and fulfillment 1542 provides pre-scheduling and procurement of cloud resources, where future needs are anticipated according to the SLA.

[0139] Workload layer 1544 provides examples of functionalities that can leverage a cloud computing environment. Examples of workloads and functionalities that can be provided from this layer include: mapping and navigation 1546; software development and lifecycle management 1548; virtual classroom education delivery 1550; data analysis and processing 1552; transaction processing 1554; and quantum computing 1556. Different embodiments of the invention can be found using references. Figure 14 and Figure 15 The cloud computing environment described herein is used to control one or more quantum computers 108 and / or execute one or more error mitigation protocols according to different implementations described herein.

[0140] This invention can be a system, method, and / or computer program product at any possible level of technical detail integration. A computer program product may include a computer-readable storage medium (or media) having computer-readable program instructions thereon for causing a processor to execute aspects of the invention. A computer-readable storage medium may be a tangible device capable of retaining and storing instructions used by an instruction execution device. A computer-readable storage medium may be, for example, but not limited to, electronic storage devices, magnetic storage devices, optical storage devices, electromagnetic storage devices, semiconductor storage devices, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of computer-readable storage media includes the following: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable optical disc read-only memory (CD-ROM), digital multifunction disc (DVD), memory sticks, floppy disks, mechanical encoding devices such as punch cards or recessed structures on which instructions are recorded, and any suitable combination of the foregoing. As used herein, computer-readable storage media should not be construed as transient signals themselves, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., optical pulses through fiber optic cables), or electrical signals transmitted through wires.

[0141] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to a suitable computing / processing device, or via a network, such as the Internet, a local area network (LAN), a wide area network (WAN), and / or a wireless network, to an external computer or external storage device. The network may include copper cables, optical fibers, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards them to a computer-readable storage medium within the respective computing / processing device.

[0142] Computer-readable program instructions used to perform the operations of this invention may be assembly instructions, instruction set architecture (ISA) instructions, machine-dependent instructions, microcode, firmware instructions, status setting data, integrated circuit configuration data, or source code or object code written in any combination of one or more programming languages ​​(including object-oriented programming languages ​​such as Smalltalk, C++, etc.) and procedural programming languages ​​(such as the "C" programming language or similar programming languages). The computer-readable program instructions may be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter case, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, to perform aspects of this invention, electronic circuits, including, for example, programmable logic circuits, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs), may execute computer-readable program instructions to personalize the electronic circuits by utilizing the status information of the computer-readable program instructions.

[0143] Various aspects of the present invention are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0144] These computer-readable program instructions may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions / actions specified in one or more blocks of a flowchart and / or block diagram. These computer-readable program instructions may also be stored in a computer-readable storage medium that can direct a computer, programmable data processing apparatus, and / or other devices to operate in a particular manner, such that the computer-readable storage medium in which the instructions are stored includes an article of writing comprising instructions for implementing aspects of the functions / actions specified in one or more blocks of a flowchart and / or block diagram.

[0145] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus or other device to produce a computer-implemented process, such that the instructions, which execute on the computer, other programmable apparatus or other device, perform the functions / actions specified in one or more boxes of a flowchart and / or block diagram.

[0146] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of instructions comprising one or more executable instructions for implementing a specified logical function. In some alternative embodiments, the functions indicated in the blocks may occur in a different order than indicated in the figures. For example, two blocks shown consecutively may actually be executed substantially simultaneously, or these blocks may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block illustrated in the block diagrams and / or flowcharts, and combinations of blocks illustrated in the block diagrams and / or flowcharts, may be implemented by a system based on dedicated hardware that performs the specified function or action or executes a combination of dedicated hardware and computer instructions.

[0147] To provide additional context for the various embodiments described herein, Figure 16 The following discussion is intended to provide a general description of a suitable computing environment 1600 in which various embodiments of the embodiments described herein may be implemented. Although the embodiments have been described above in the general context of computer-executable instructions that can run on one or more computers, those skilled in the art will recognize that the embodiments may also be implemented in combination with other program modules and / or as a combination of hardware and software.

[0148] Typically, program modules include routines, programs, components, data structures, etc., that perform specific tasks or implement specific abstract data types. Furthermore, those skilled in the art will understand that the methods of this invention can be implemented using other computer system configurations, including single-processor or multi-processor computer systems, minicomputers, mainframes, Internet of Things (“IoT”) devices, distributed computing systems, and personal computers, handheld computing devices, microprocessor-based or programmable consumer electronics, each of which can be operatively coupled to one or more associated devices.

[0149] The embodiments illustrated herein can also be practiced in a distributed computing environment, where certain tasks are performed by remote processing devices linked via a communication network. In a distributed computing environment, program modules can reside in both local and remote memory storage devices. For example, in one or more embodiments, computer executable components can be executed from memory that may include or consist of one or more distributed memory cells. As used herein, the terms "memory" and "memory cell" are interchangeable. Furthermore, one or more embodiments described herein can execute the code of computer executable components in a distributed manner, for example, by multiple processors working together or cooperating to execute code from one or more distributed memory cells. As used herein, the term "memory" can encompass a single memory or memory cell at one location or multiple memories or memory cells at one or more locations.

[0150] Computing devices typically include a variety of media, which may include computer-readable storage media, machine-readable storage media, and / or communication media, these two terms being used herein to distinguish themselves from each other. A computer-readable storage medium or a machine-readable storage medium can be any available storage medium accessible by a computer, and includes volatile and non-volatile media, removable and non-removable media. By way of example and not limitation, a computer-readable storage medium or a machine-readable storage medium may be implemented in conjunction with any method or technique used for storing information such as computer-readable or machine-readable instructions, program modules, structured data, or unstructured data.

[0151] Computer-readable storage media may include, but is not limited to, random access memory (“RAM”), read-only memory (“ROM”), electrically erasable programmable read-only memory (“EEPROM”), flash memory or other memory technologies, optical disc read-only memory (“CD ROM”), digital versatile disc (“DVD”), Blu-ray disc (“BD”) or other optical disc storage, magnetic tape cassettes, magnetic tape, disk storage or other magnetic storage devices, solid-state drives or other solid-state storage devices, or other tangible and / or non-transitory media that can be used to store desired information. In this regard, the terms “tangible” or “non-transitory” as used herein with respect to storage devices, memories, or computer-readable media shall be understood to exclude only the propagation of transient signals themselves as a modifier, and shall not waive the rights to all standard storage devices, memories, or computer-readable media that do not only propagate transient signals themselves.

[0152] Computer-readable storage media can be accessed by one or more local or remote computing devices, for example via access requests, queries or other data retrieval protocols, in order to perform various operations on the information stored on the media.

[0153] Communication media typically embody computer-readable instructions, data structures, program modules, or other structured or unstructured data in the form of data signals such as modulated data signals, such as carrier waves or other transmission mechanisms, and include any information transmission or delivery medium. The term "modulated data signal" or multiple signals refers to signals whose one or more characteristics are set or altered in a manner that encodes information in one or more signals. By way of example and not limitation, communication media include wired media, such as wired networks or direct-wire connections, and wireless media, such as acoustic, RF, infrared, and other wireless media.

[0154] Refer again Figure 16 An example environment 1600 for implementing embodiments of the aspects described herein includes a computer 1602, which includes a processing unit 1604, system memory 1606, and a system bus 1608. The system bus 1608 couples system components, including but not limited to system memory 1606, to the processing unit 1604. The processing unit 1604 can be any of a variety of commercially available processors. Dual-microprocessor and other multiprocessor architectures may also be used as the processing unit 1604.

[0155] System bus 1608 can be any of several bus architectures, which can also interconnect to memory buses (with or without memory controllers), peripheral buses, and local buses using any of the various commercially available bus architectures. System memory 1606 includes ROM 1610 and RAM 1612. The basic input / output system (“BIOS”) can be stored in non-volatile memory such as ROM, erasable programmable read-only memory (“EPROM”), EEPROM, etc., where the BIOS contains basic routines that help transfer information between components within computer 1602, such as during startup. RAM 1612 can also include high-speed RAM such as static RAM for caching data.

[0156] Computer 1602 further includes an internal hard disk drive (“HDD”) 1614 (e.g., EIDE, SATA), one or more external storage devices 1616 (e.g., floppy disk drive (“FDD”) 1616, memory stick or flash drive reader, memory card reader, etc.), and an optical disc drive 1620 (e.g., capable of reading from or writing to CD-ROMs, DVDs, BDs, etc.). Although the internal HDD 1614 is illustrated as being located within computer 1602, the internal HDD 1614 may also be configured for external use in a suitable chassis (not shown). Additionally, although not shown in environment 1600, a solid-state drive (“SSD”) may be used in addition to, or instead of, the HDD 1614. The HDD 1614, external storage device 1616, and optical disc drive 1620 may be connected to system bus 1608 via HDD interface 1624, external storage interface 1626, and optical disc drive interface 1628, respectively. The interface 1624 for external driver implementation may include at least one or both of Universal Serial Bus (“USB”) and Institute of Electrical and Electronics Engineers (“IEEE”) 1394 interface technologies. Other external driver connectivity technologies are within the scope of consideration for the embodiments described herein.

[0157] The drive and its associated computer-readable storage medium provide non-volatile storage of data, data structures, computer-executable instructions, etc. For computer 1602, the drive and storage medium accommodate storage of any data in a suitable digital format. Although the above description of computer-readable storage media refers to a corresponding type of storage device, those skilled in the art will understand that other types of computer-readable storage media, whether currently existing or developed in the future, may also be used in the example operating environment, and furthermore, any such storage medium may contain computer-executable instructions for performing the methods described herein.

[0158] Multiple program modules can be stored in the drive and RAM 1612, including an operating system 1630, one or more application programs 1632, other program modules 1634, and program data 1636. All or part of the operating system, application programs, modules, and / or data can also be cached in RAM 1612. The systems and methods described herein can be implemented using various commercially available operating systems or combinations of operating systems.

[0159] Computer 1602 may optionally include emulation technology. For example, a system hypervisor (not shown) or other intermediary may emulate a hardware environment for operating system 1630, and the emulated hardware may optionally be compatible with... Figure 16Unlike the hardware shown, in such an embodiment, the operating system 1630 may include one of a plurality of virtual machines (“VMs”) primarily residing at the computer 1602. Furthermore, the operating system 1630 may provide a runtime environment, such as a Java Runtime Environment (JVM) or a Java Runtime Environment (JVM) .NET Framework, for application 1632. A runtime environment is a consistent execution environment that allows application 1632 to run on any operating system that includes that runtime environment. Similarly, the operating system 1630 may support containers, and application 1632 may be in the form of a container, which is a lightweight, standalone, executable package that includes, for example, code, runtime, system tools, system libraries, and application setup.

[0160] Furthermore, computer 1602 can be enabled using a security module, such as a Trusted Processing Module (“TPM”). For example, with a TPM, the boot unit hashes the next boot unit at boot time and waits for the result to match a security value before loading the next boot unit. This process can occur at any layer of computer 1602’s code execution stack, for example, at the application execution level or at the operating system (“OS”) kernel level, thereby achieving security at any code execution level.

[0161] Users can input commands and information into computer 1602 through one or more wired / wireless input devices, such as keyboard 1638, touchscreen 1640, and pointing devices such as mouse 1642. Other input devices (not shown) may include microphones, infrared (“IR”) remote controls, radio frequency (“RF”) remote controls or other remote controls, joysticks, virtual reality controllers and / or virtual reality headsets, gaming pads, pointers, image input devices (e.g., cameras), gesture sensor input devices, visual motion sensor input devices, emotion or face detection devices, biometric input devices (e.g., fingerprint or iris scanners), etc. These and other input devices are typically connected to processing unit 1604 via input device interface 1644, which can be coupled to system bus 1608, but may also be connected via other interfaces such as parallel ports, IEEE 1394 serial ports, gaming ports, USB ports, IR interfaces, interfaces, etc.

[0162] The monitor 1646 or other types of display devices may also be connected to the system bus 1608 via an interface such as the video adapter 1648. In addition to the monitor 1646, the computer typically includes other peripheral output devices (not shown), such as speakers, printers, etc.

[0163] Computer 1602 can operate in a networked environment using logical connections to one or more remote computers (such as remote computer 1650) via wired and / or wireless communications. Remote computer 1650 can be a workstation, server computer, router, personal computer, portable computer, microprocessor-based entertainment device, peer-to-peer device, or other common network node, and typically includes many or all of the elements described relative to computer 1602, although only memory / storage device 1652 is shown for simplicity. The depicted logical connections include wired / wireless connections to a local area network (“LAN”) 1654 and / or larger networks, such as a wide area network (“WAN”) 1656. Such LAN and WAN networking environments are common in offices and companies and facilitate enterprise-wide computer networks such as intranets, all of which can connect to global communication networks such as the Internet.

[0164] When used in a LAN network environment, computer 1602 can connect to local area network 1654 via a wired and / or wireless communication network interface or adapter 1658. Adapter 1658 facilitates wired or wireless communication with LAN 1654, which may also include a wireless access point (“AP”) configured thereon for wireless communication with adapter 1658.

[0165] When used in a WAN network environment, computer 1602 may include modem 1660, or may be connected to a communication server on WAN 1656 via other means for establishing communication on WAN 1656, such as via the Internet. Modem 1660 may be built-in or external, and may be a wired or wireless device, and may be connected to system bus 1608 via input device interface 1644. In a networked environment, program modules described relative to computer 1602 or parts thereof may be stored in remote memory / storage device 1652. It is understood that the network connection shown is an example, and other means of establishing communication links between computers may be used.

[0166] When used in a LAN or WAN network environment, computer 1602 can access cloud storage systems or other network-based storage systems as a supplement to or replacement for external storage device 1616 as described above. Typically, the connection between computer 1602 and the cloud storage system can be established, for example, on LAN 1654 or WAN 1656 via adapter 1658 or modem 1660, respectively. When computer 1602 is connected to the associated cloud storage system, external storage interface 1626 can manage the storage provided by the cloud storage system with the help of adapter 1658 and / or modem 1660, just as it would manage other types of external storage. For example, external storage interface 1626 can be configured to provide access to cloud storage sources as if these sources were physically connected to computer 1602.

[0167] Computer 1602 can be used to communicate with any wireless device or entity operatively configured for wireless communication, such as printers, scanners, desktop and / or portable computers, portable data assistants, communication satellites, any device or location associated with a wirelessly detectable tag (e.g., a public telephone booth, newsstand, shelf, etc.), and telephones. This can include Wi-Fi and wireless technologies. Therefore, communication can be a predefined structure like a conventional network, or simply self-organizing communication between at least two devices.

[0168] The above description includes only examples of systems, computer program products, and computer-implemented methods. It is certainly impossible to describe every conceivable combination of components, products, and / or computer-implemented methods for the purpose of describing this disclosure; however, those skilled in the art will recognize that many further combinations and substitutions of this disclosure are possible. Furthermore, with regard to the use of the terms "comprising," "having," "possessing," etc., in the detailed description, claims, appendices, and drawings, these terms are intended to be inclusive in a similar manner to how the term "comprising" is interpreted when used as a transitional term in the claims. Various embodiments have been described for illustrative purposes but are not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein has been chosen to best explain the principles of the embodiments, their practical application, or improvements to existing technologies in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A system comprising: Memory, which stores executable components of a computer; as well as A processor operatively coupled to the memory and executing computer-executable components stored in the memory, wherein the computer-executable components include: An interpolation component that interpolates uncalibrated gate parameters for a quantum gate against a target stretch factor using a reference model, wherein the reference model includes reference gate parameters for the quantum gate calibrated at multiple reference stretch factors; and An execution unit that performs quantum operations via a quantum circuit using uncalibrated gate parameters to generate result data, wherein the quantum circuit includes the quantum gate.

2. The system according to claim 1, further comprising: The model component defines the plurality of reference stretching factors by determining the number of reference stretching factors within a stretching factor interval based on at least one of the gate error determination and gate parameter determination.

3. The system of claim 2, wherein the number of reference stretch factors within the stretch factor interval increases with the amount of change determined per gate error within the stretch factor interval.

4. The system of claim 3, wherein the number of reference stretch factors within the stretch factor interval increases with the number of changes in the determination of gate parameters within the stretch factor interval.

5. The system according to claim 2, further comprising: The mitigation component generates error mitigation results by extrapolating the resulting data to the zero-order noise limit.

6. The system according to any one of claims 1 to 5, further comprising: The recommended component identifies the target stretching factor based on the gate count and qubit count of the quantum circuit including the quantum gate.

7. A computer-implemented method, comprising: The system operatively coupled to the processor interpolates uncalibrated gate parameters for the quantum gate against a target stretching factor using a reference model, wherein the reference model includes reference gate parameters for the quantum gate calibrated at multiple reference stretching factors; and The system generates the resulting data by performing quantum operations via a quantum circuit using uncalibrated gate parameters, wherein the quantum circuit includes the quantum gate.

8. The computer-implemented method according to claim 7, further comprising: The system determines the number of reference stretch factors included in the stretch factor interval based on at least one of per-gate error determination and gate parameter determination.

9. The computer-implemented method of claim 8, wherein the number of reference stretch factors within the stretch factor interval increases with the number of changes in each gate error determination within the stretch factor interval, and further wherein the number of reference stretch factors within the stretch factor interval increases with the number of changes in the gate parameter determination within the stretch factor interval.

10. The computer-implemented method according to any one of claims 7 to 9, further comprising: The system generates error mitigation results by extrapolating the result data to the zero-order noise limit.

11. The computer-implemented method according to claim 10, further comprising: The system identifies the target stretching factor based on the gate count and qubit count of the quantum circuit including the quantum gate.

12. A computer program product for error mitigation in quantum computing, the computer program product comprising a computer-readable storage medium having program instructions embodied therein, the program instructions being executable by a processor to cause the processor to: The processor interpolates uncalibrated gate parameters for the quantum gate against a target stretching factor using a reference model, wherein the reference model includes reference gate parameters for the quantum gate calibrated at a plurality of reference stretching factors; and The processor generates the resulting data by performing quantum operations via a quantum circuit using uncalibrated gate parameters, wherein the quantum circuit includes the quantum gate.

13. The computer program product of claim 12, wherein the program instructions further cause the processor to: The processor defines the plurality of reference stretching factors by determining the number of reference stretching factors within a stretching factor interval based on at least one of per-gate error determination and gate parameter determination.

14. The computer program product according to claim 12 or 13, wherein, The program instructions also cause the processor to: The processor identifies the target stretching factor based on the gate count and qubit count of the quantum circuit including the quantum gate.

15. The computer program product of claim 14, wherein the program instructions further cause the processor to: The processor compares the gate count and the qubit count of the quantum circuit with a reference table that includes a range of stretching factors associated with a defined combination of gate counts and qubit counts.

16. The computer program product of claim 15, wherein the program instructions further cause the processor to: The processor generates the error mitigation result by extrapolating the result data to the zero-order noise limit.

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